BE840957A - Systeme de trairement des donnees constitue de plusieurs systemes partiels - Google Patents

Systeme de trairement des donnees constitue de plusieurs systemes partiels

Info

Publication number
BE840957A
BE840957A BE166330A BE166330A BE840957A BE 840957 A BE840957 A BE 840957A BE 166330 A BE166330 A BE 166330A BE 166330 A BE166330 A BE 166330A BE 840957 A BE840957 A BE 840957A
Authority
BE
Belgium
Prior art keywords
data processing
processing system
system consists
several partial
partial systems
Prior art date
Application number
BE166330A
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE19752517553 external-priority patent/DE2517553C3/de
Application filed filed Critical
Publication of BE840957A publication Critical patent/BE840957A/fr

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
    • G06F15/163—Interprocessor communication
    • G06F15/167—Interprocessor communication using a common memory, e.g. mailbox
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Multi Processors (AREA)
  • Information Transfer Systems (AREA)
  • Computer And Data Communications (AREA)
  • Logic Circuits (AREA)
  • Dram (AREA)
BE166330A 1975-04-21 1976-04-21 Systeme de trairement des donnees constitue de plusieurs systemes partiels BE840957A (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19752517553 DE2517553C3 (de) 1975-04-21 Datenverarbeitungssystem aus mehreren Teilsystemen

Publications (1)

Publication Number Publication Date
BE840957A true BE840957A (fr) 1976-10-21

Family

ID=5944546

Family Applications (1)

Application Number Title Priority Date Filing Date
BE166330A BE840957A (fr) 1975-04-21 1976-04-21 Systeme de trairement des donnees constitue de plusieurs systemes partiels

Country Status (12)

Country Link
US (1) US4133029A (fr)
JP (1) JPS51130133A (fr)
AT (1) AT346915B (fr)
AU (1) AU500780B2 (fr)
BE (1) BE840957A (fr)
CH (1) CH608902A5 (fr)
FR (1) FR2308983A1 (fr)
GB (1) GB1542136A (fr)
IT (1) IT1059164B (fr)
NL (1) NL7603797A (fr)
SE (1) SE405517B (fr)
ZA (1) ZA761804B (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4491907A (en) * 1980-12-15 1985-01-01 Texas Instruments Incorporated Plurality of processors sharing the memory, the arithmetic logic unit and control circuitry all on a single semiconductor chip
US5768623A (en) * 1995-09-19 1998-06-16 International Business Machines Corporation System and method for sharing multiple storage arrays by dedicating adapters as primary controller and secondary controller for arrays reside in different host computers
US10684797B2 (en) * 2018-08-31 2020-06-16 Micron Technology, Inc. Command-in-pipeline counter for a memory device

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3253262A (en) * 1960-12-30 1966-05-24 Bunker Ramo Data processing system
US3287705A (en) * 1963-03-07 1966-11-22 Rca Corp Computer system
US3302185A (en) * 1964-01-20 1967-01-31 Jr Andrew P Cox Flexible logic circuits for buffer memory
US3517174A (en) * 1965-11-16 1970-06-23 Ericsson Telefon Ab L M Method of localizing a fault in a system including at least two parallelly working computers
SE313849B (fr) * 1966-03-25 1969-08-25 Ericsson Telefon Ab L M
CH515557A (it) * 1969-06-21 1971-11-15 Olivetti & Co Spa Calcolatore elettronico
GB1268283A (en) * 1970-04-02 1972-03-29 Ibm Connect module
NL7007615A (fr) * 1970-05-27 1971-11-30
DE2027567A1 (de) * 1970-06-04 1971-12-09 Siemens Ag Speicher zur Zwischenspeicherung von Daten
US3678467A (en) * 1970-10-20 1972-07-18 Bell Telephone Labor Inc Multiprocessor with cooperative program execution
US3676861A (en) * 1970-12-30 1972-07-11 Honeywell Inf Systems Multiple mask registers for servicing interrupts in a multiprocessor system
NL7202501A (fr) * 1972-02-25 1973-08-28
GB1422952A (en) * 1972-06-03 1976-01-28 Plessey Co Ltd Data processing system fault diagnostic arrangements
US3964056A (en) * 1974-04-08 1976-06-15 International Standard Electric Corporation System for transferring data between central units and controlled units

Also Published As

Publication number Publication date
AU1241076A (en) 1977-09-29
IT1059164B (it) 1982-05-31
DE2517553B2 (de) 1977-02-24
DE2517553A1 (de) 1976-11-04
FR2308983A1 (fr) 1976-11-19
CH608902A5 (fr) 1979-01-31
GB1542136A (en) 1979-03-14
US4133029A (en) 1979-01-02
AT346915B (de) 1978-12-11
JPS51130133A (en) 1976-11-12
FR2308983B1 (fr) 1978-05-12
SE405517B (sv) 1978-12-11
ATA150876A (de) 1978-04-15
AU500780B2 (en) 1979-05-31
NL7603797A (nl) 1976-10-25
ZA761804B (en) 1977-03-30
SE7602904L (sv) 1976-10-22

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Legal Events

Date Code Title Description
RE Patent lapsed

Owner name: SIEMENS A.G.

Effective date: 19910430