BE1002405A4 - Systeme de microcalculateur a bus multiple avec arbitrage d'acces aux bus. - Google Patents
Systeme de microcalculateur a bus multiple avec arbitrage d'acces aux bus. Download PDFInfo
- Publication number
- BE1002405A4 BE1002405A4 BE8900435A BE8900435A BE1002405A4 BE 1002405 A4 BE1002405 A4 BE 1002405A4 BE 8900435 A BE8900435 A BE 8900435A BE 8900435 A BE8900435 A BE 8900435A BE 1002405 A4 BE1002405 A4 BE 1002405A4
- Authority
- BE
- Belgium
- Prior art keywords
- bus
- arbitration
- phase
- signal
- cpu unit
- Prior art date
Links
- 230000000977 initiatory effect Effects 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/70—Software maintenance or management
- G06F8/71—Version control; Configuration management
-
- G—PHYSICS
- G02—OPTICS
- G02B—OPTICAL ELEMENTS, SYSTEMS OR APPARATUS
- G02B27/00—Optical systems or apparatus not provided for by any of the groups G02B1/00 - G02B26/00, G02B30/00
- G02B27/28—Optical systems or apparatus not provided for by any of the groups G02B1/00 - G02B26/00, G02B30/00 for polarising
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03B—APPARATUS OR ARRANGEMENTS FOR TAKING PHOTOGRAPHS OR FOR PROJECTING OR VIEWING THEM; APPARATUS OR ARRANGEMENTS EMPLOYING ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ACCESSORIES THEREFOR
- G03B21/00—Projectors or projection-type viewers; Accessories therefor
- G03B21/54—Accessories
- G03B21/56—Projection screens
- G03B21/60—Projection screens characterised by the nature of the surface
- G03B21/604—Polarised screens
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
- G06F13/362—Handling requests for interconnection or transfer for access to common bus or bus system with centralised access control
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F8/00—Arrangements for software engineering
- G06F8/20—Software design
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Computer Security & Cryptography (AREA)
- Optics & Photonics (AREA)
- Bus Control (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Multi Processors (AREA)
- Information Transfer Systems (AREA)
Abstract
Un système de micro-calculateur à bus multiple comprend un sous système d'antémémoire et un superviseur d'arbitrage. Une unité CPU est prévu avec une source de signaux PREEMPT qui génère un signal de péemption dans des cycles CPU dépassant une durée spécifiée. Le signal de préemption peut s'appliquer à n'importe quel dispositif ayant accès au bus pour initier la fin de l'usage du bus. Lorsque ce dispositif signale sa fin d'usage du bus, le superviseur d'arbitrage change l'état d'un conducteur d'attribution d'arbitrage qui était en phase d'attribution, en phase d'arbitrage. Pendant la phase d'arbitrage, chacun des dispositifs (autres que l'unité CPU) coopère dans un mécanisme d'arbitrage d'usage du bus pendant la phase d'attribution suivante. D'autre part, l'unité CPU ayant revendiqué la préemption, répond à un signal indiquant l'amorçage de la phase d'arbitrage en accédant immédiatement au bus de système.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/198,895 US5129090A (en) | 1988-05-26 | 1988-05-26 | System bus preempt for 80386 when running in an 80386/82385 microcomputer system with arbitration |
Publications (1)
Publication Number | Publication Date |
---|---|
BE1002405A4 true BE1002405A4 (fr) | 1991-01-29 |
Family
ID=22735319
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
BE8900435A BE1002405A4 (fr) | 1988-05-26 | 1989-04-20 | Systeme de microcalculateur a bus multiple avec arbitrage d'acces aux bus. |
Country Status (23)
Country | Link |
---|---|
US (1) | US5129090A (fr) |
EP (1) | EP0343770B1 (fr) |
JP (1) | JPH0623970B2 (fr) |
CN (1) | CN1010808B (fr) |
AT (1) | ATE123162T1 (fr) |
AU (1) | AU611287B2 (fr) |
BE (1) | BE1002405A4 (fr) |
BR (1) | BR8902388A (fr) |
CA (1) | CA1317682C (fr) |
DE (2) | DE68922784T2 (fr) |
DK (1) | DK189889A (fr) |
ES (1) | ES2072895T3 (fr) |
FI (1) | FI96145C (fr) |
FR (1) | FR2632096B1 (fr) |
GB (1) | GB2219176A (fr) |
HK (1) | HK23696A (fr) |
IT (1) | IT1230191B (fr) |
MX (1) | MX171578B (fr) |
MY (1) | MY111733A (fr) |
NL (1) | NL8901282A (fr) |
NO (1) | NO176038C (fr) |
NZ (1) | NZ228785A (fr) |
SE (1) | SE8901306L (fr) |
Families Citing this family (53)
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US5034883A (en) * | 1987-05-01 | 1991-07-23 | Digital Equipment Corporation | Lockhead bus arbitration system with override of conditional access grants by bus cycle extensions for multicycle data transfers |
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FR2642246B1 (fr) * | 1988-12-30 | 1991-04-05 | Cit Alcatel | Procede de deblocage d'un systeme multiprocesseurs multibus |
CA2016348C (fr) * | 1989-05-10 | 2002-02-05 | Kenichi Asano | Systeme multiprocesseur de codage d'images variant avec le temps et processeur d'images |
US5293493A (en) * | 1989-10-27 | 1994-03-08 | International Business Machines Corporation | Preemption control for central processor with cache |
CA2038012A1 (fr) * | 1990-03-14 | 1991-09-15 | Hideki Shimizu | Laminage de supraconducteurs en couches d'oxyde, et procede de fabrication connexe |
US5086427A (en) * | 1990-04-09 | 1992-02-04 | Unisys Corporation | Clocked logic circuitry preventing double driving on shared data bus |
JP4733219B2 (ja) * | 1990-06-04 | 2011-07-27 | 株式会社日立製作所 | データ処理装置およびデータ処理方法 |
AU648309B2 (en) * | 1990-06-14 | 1994-04-21 | International Business Machines Corporation | Apparatus and method for assembly of direct access storage device with a personal computer |
EP0472274A1 (fr) * | 1990-08-24 | 1992-02-26 | International Business Machines Corporation | Appareil de traitement de données avec connecteurs pour composants de système |
GB9019022D0 (en) * | 1990-08-31 | 1990-10-17 | Ncr Co | Work station or similar data processing system including interfacing means to microchannel means |
GB9019001D0 (en) * | 1990-08-31 | 1990-10-17 | Ncr Co | Work station including a direct memory access controller and interfacing means to microchannel means |
GB9018993D0 (en) * | 1990-08-31 | 1990-10-17 | Ncr Co | Work station interfacing means having burst mode capability |
ATE137038T1 (de) * | 1990-08-31 | 1996-05-15 | Advanced Micro Devices Inc | Übertragungssteuerungssystem für einen rechner und peripheriegeräte |
US5218681A (en) * | 1990-08-31 | 1993-06-08 | Advanced Micro Devices, Inc. | Apparatus for controlling access to a data bus |
EP0473276B1 (fr) * | 1990-08-31 | 1996-12-18 | Advanced Micro Devices, Inc. | Appareil intégré de traitement numérique |
GB9018991D0 (en) * | 1990-08-31 | 1990-10-17 | Ncr Co | Work station with timing independant interface units |
JPH04141757A (ja) * | 1990-10-03 | 1992-05-15 | Fujitsu Ltd | バス制御方式 |
US5195089A (en) * | 1990-12-31 | 1993-03-16 | Sun Microsystems, Inc. | Apparatus and method for a synchronous, high speed, packet-switched bus |
US5249297A (en) * | 1991-04-29 | 1993-09-28 | Hewlett-Packard Company | Methods and apparatus for carrying out transactions in a computer system |
US5537600A (en) * | 1991-05-28 | 1996-07-16 | International Business Machines Corporation | Personal computer with alternate system controller |
EP0516323A1 (fr) * | 1991-05-28 | 1992-12-02 | International Business Machines Corporation | Systèmes d'ordinateur personnel |
US5392417A (en) * | 1991-06-05 | 1995-02-21 | Intel Corporation | Processor cycle tracking in a controller for two-way set associative cache |
CA2067599A1 (fr) * | 1991-06-10 | 1992-12-11 | Bruce Alan Smith | Ordinateur personnel a connecteur pour bus maitre auxiliaire |
US5255373A (en) * | 1991-08-07 | 1993-10-19 | Hewlett-Packard Company | Decreasing average time to access a computer bus by eliminating arbitration delay when the bus is idle |
US5630163A (en) * | 1991-08-09 | 1997-05-13 | Vadem Corporation | Computer having a single bus supporting multiple bus architectures operating with different bus parameters |
US5581731A (en) * | 1991-08-30 | 1996-12-03 | King; Edward C. | Method and apparatus for managing video data for faster access by selectively caching video data |
CA2068010C (fr) * | 1991-08-30 | 1996-10-22 | Robert Chih-Tsin Eng | Methode de gestion des debits de donnees transmises par salves utilisant un bus maitre auxiliaire pour systemes informatiques a architecture a double bus |
US5430860A (en) * | 1991-09-17 | 1995-07-04 | International Business Machines Inc. | Mechanism for efficiently releasing memory lock, after allowing completion of current atomic sequence |
JPH05210977A (ja) * | 1991-10-15 | 1993-08-20 | Internatl Business Mach Corp <Ibm> | メモリ・リフレッシュ制御装置 |
US5301282A (en) * | 1991-10-15 | 1994-04-05 | International Business Machines Corp. | Controlling bus allocation using arbitration hold |
US5371872A (en) * | 1991-10-28 | 1994-12-06 | International Business Machines Corporation | Method and apparatus for controlling operation of a cache memory during an interrupt |
US5237695A (en) * | 1991-11-01 | 1993-08-17 | Hewlett-Packard Company | Bus contention resolution method for network devices on a computer network having network segments connected by an interconnection medium over an extended distance |
US5548762A (en) * | 1992-01-30 | 1996-08-20 | Digital Equipment Corporation | Implementation efficient interrupt select mechanism |
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US5420985A (en) * | 1992-07-28 | 1995-05-30 | Texas Instruments Inc. | Bus arbiter system and method utilizing hardware and software which is capable of operation in distributed mode or central mode |
US5471585A (en) * | 1992-09-17 | 1995-11-28 | International Business Machines Corp. | Personal computer system with input/output controller having serial/parallel ports and a feedback line indicating readiness of the ports |
JP3057934B2 (ja) * | 1992-10-30 | 2000-07-04 | 日本電気株式会社 | 共有バス調停機構 |
US5699540A (en) * | 1992-11-16 | 1997-12-16 | Intel Corporation | Pseudo-concurrent access to a cached shared resource |
US5500946A (en) * | 1992-11-25 | 1996-03-19 | Texas Instruments Incorporated | Integrated dual bus controller |
CA2116826C (fr) * | 1993-03-11 | 1998-11-24 | Timothy J. Sullivan | Systeme de traitement de donnees utilisant un bus d'adresses et un bus de donnees asynchrones non multiplexes |
US5528765A (en) * | 1993-03-15 | 1996-06-18 | R. C. Baker & Associates Ltd. | SCSI bus extension system for controlling individual arbitration on interlinked SCSI bus segments |
JP3474646B2 (ja) * | 1994-09-01 | 2003-12-08 | 富士通株式会社 | 入出力制御装置及び入出力制御方法 |
KR0155269B1 (ko) * | 1995-01-16 | 1998-11-16 | 김광호 | 버스 중재방법 및 그 장치 |
US5692211A (en) * | 1995-09-11 | 1997-11-25 | Advanced Micro Devices, Inc. | Computer system and method having a dedicated multimedia engine and including separate command and data paths |
US5845097A (en) * | 1996-06-03 | 1998-12-01 | Samsung Electronics Co., Ltd. | Bus recovery apparatus and method of recovery in a multi-master bus system |
US6560712B1 (en) * | 1999-11-16 | 2003-05-06 | Motorola, Inc. | Bus arbitration in low power system |
US6842813B1 (en) | 2000-06-12 | 2005-01-11 | Intel Corporation | Method and apparatus for single wire signaling of request types in a computer system having a point to point half duplex interconnect |
US6877052B1 (en) * | 2000-09-29 | 2005-04-05 | Intel Corporation | System and method for improved half-duplex bus performance |
US7007122B2 (en) * | 2002-11-27 | 2006-02-28 | Lsi Logic Corporation | Method for pre-emptive arbitration |
US7107375B2 (en) * | 2003-05-13 | 2006-09-12 | Lsi Logic Corporation | Method for improving selection performance by using an arbitration elimination scheme in a SCSI topology |
DE602004019990D1 (de) * | 2004-08-30 | 2009-04-23 | Magima Digital Information Co | Verfahren und system zum datentransfer |
DE102008000031B4 (de) * | 2008-01-10 | 2014-07-10 | Koenig & Bauer Aktiengesellschaft | Verfahren zur Kontrolle einer Anordnung von an Formzylindern einer Druckmaschine angeordneten Druckformen |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0066766A2 (fr) * | 1981-06-05 | 1982-12-15 | International Business Machines Corporation | Dispositif de contrôle d'entrée-sortie avec une antémémoire dynamiquement réglable |
US4414624A (en) * | 1980-11-19 | 1983-11-08 | The United States Of America As Represented By The Secretary Of The Navy | Multiple-microcomputer processing |
EP0192366A2 (fr) * | 1985-02-05 | 1986-08-27 | Digital Equipment Corporation | Appareil et procédé d'amélioration de performances de système-bus dans un système de traitement de données |
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-
1988
- 1988-05-26 US US07/198,895 patent/US5129090A/en not_active Expired - Fee Related
-
1989
- 1989-03-03 AT AT89302162T patent/ATE123162T1/de not_active IP Right Cessation
- 1989-03-03 EP EP89302162A patent/EP0343770B1/fr not_active Expired - Lifetime
- 1989-03-03 GB GB8904919A patent/GB2219176A/en not_active Withdrawn
- 1989-03-03 DE DE68922784T patent/DE68922784T2/de not_active Expired - Fee Related
- 1989-03-03 ES ES89302162T patent/ES2072895T3/es not_active Expired - Lifetime
- 1989-03-25 DE DE3909948A patent/DE3909948A1/de active Granted
- 1989-04-10 JP JP1088194A patent/JPH0623970B2/ja not_active Expired - Lifetime
- 1989-04-11 SE SE8901306A patent/SE8901306L/ not_active Application Discontinuation
- 1989-04-11 FR FR898905077A patent/FR2632096B1/fr not_active Expired - Fee Related
- 1989-04-14 FI FI891786A patent/FI96145C/fi not_active IP Right Cessation
- 1989-04-18 NO NO891585A patent/NO176038C/no unknown
- 1989-04-18 NZ NZ228785A patent/NZ228785A/en unknown
- 1989-04-19 DK DK189889A patent/DK189889A/da not_active Application Discontinuation
- 1989-04-20 BE BE8900435A patent/BE1002405A4/fr not_active IP Right Cessation
- 1989-04-25 CN CN88108702A patent/CN1010808B/zh not_active Expired
- 1989-04-26 CA CA000597890A patent/CA1317682C/fr not_active Expired - Fee Related
- 1989-04-26 MY MYPI89000548A patent/MY111733A/en unknown
- 1989-05-05 AU AU34097/89A patent/AU611287B2/en not_active Ceased
- 1989-05-23 NL NL8901282A patent/NL8901282A/nl not_active Application Discontinuation
- 1989-05-24 IT IT8920626A patent/IT1230191B/it active
- 1989-05-24 BR BR898902388A patent/BR8902388A/pt unknown
- 1989-05-26 MX MX016199A patent/MX171578B/es unknown
-
1996
- 1996-02-08 HK HK23696A patent/HK23696A/xx not_active IP Right Cessation
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4414624A (en) * | 1980-11-19 | 1983-11-08 | The United States Of America As Represented By The Secretary Of The Navy | Multiple-microcomputer processing |
EP0066766A2 (fr) * | 1981-06-05 | 1982-12-15 | International Business Machines Corporation | Dispositif de contrôle d'entrée-sortie avec une antémémoire dynamiquement réglable |
EP0192366A2 (fr) * | 1985-02-05 | 1986-08-27 | Digital Equipment Corporation | Appareil et procédé d'amélioration de performances de système-bus dans un système de traitement de données |
Non-Patent Citations (3)
Title |
---|
COMPUTER DESIGN, vol. 23, no. 13, novembre 1984, pages 133-138; W. MAYBERRY et al.: "Cache boosts multiprocessor performance" * |
ELECTRONICS INTERNATIONAL, vol. 56, no. 19, septembre 1983, pages 155-158, New York, US; M. BARON: "Stopping system memory and bus from putting the squeeze on fast CPUs" * |
NEW ELECTRONICS, vol. 20, no. 7, 31 mars 1987, pages 30-33, London, GB; "Extending 80386 performance" * |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
RE | Patent lapsed |
Owner name: INTERNATIONAL BUSINESS MACHINES CORP. Effective date: 19960430 |