AU766759B2 - Image cache system and method - Google Patents

Description

S&F Ref: 546920

AUSTRALIA

PATENTS ACT 1990 COMPLETE SPECIFICATION FOR A STANDARD PATENT

ORIGINAL

Name and Address of Applicant: Actual Inventor(s): Address for Service: Canon Kabushiki Kaisha 30-2, Shimomaruko 3-chome, Ohta-ku Tokyo 146 Japan Yu-Ling Chen Spruson Ferguson St Martins Tower,Level 31 Market Street Sydney NSW 2000 Image Cache System and Method Invention Title: ASSOCIATED PROVISIONAL APPLICATION DETAILS [33] Country [31] Applic. No(s) AU PQ6970 [32] Application Date 18 Apr 2000 The following statement is a full description of this invention, including the best method of performing it known to me/us:- Documents received on': 29 AR 2001 Batch Ne. 5815c 4, -1- IMAGE CACHE SYSTEM AND METHOD Technical Field of the Invention The present invention relates to an image cache system and method for caching one or more digital images.

Background Cache memories are simply high-speed buffer memories that are placed between a processor and a main memory. When a memory access to main memory is to be performed, a request for an address is presented to the cache memory. A tag portion of the cache memory, along with associated cache controller logic, determines whether or not a data portion of the cache contains the data associated with that requested address. If the cache memory contains that particular data, the cache memory delivers the data, else it signals a cache miss.

Cache memory is typically implemented using an associative memory. The cache eeeo* memory includes the tag portion and the data portion. The tag portion includes a plurality of entries, each entry being paired with a corresponding entry in the data memory. When a requested tag the address) is presented to the tag memory, a determination is made whether or not the cache contains data corresponding to that tag. Each entry of the tag memory includes a memory to store a particular tag and a comparator to compare that tag S"with the requested tag. A "hit" is generated by an entry x when tag x equals the requested tag. When a "hit" is noted, line X in the data memory will be accessed. When none of the entries produces a hit, a "miss" is signaled.

A cache generally follows the following sequence of steps in its operation. First, the cache memory is presented with an address. A search is made in the cache tag memory for the address. If an address is found, a cache "hit" is indicated. Upon a cache "hit", the corresponding line of information of the data memory is sent to the processor.

Moreover, the validity of line is updated. Once the associated line from the data memory 546920.doc is accessed, the requested bytes within that line are selected. These selected bytes are sent to the processor.

If, after a search of the tag memory, none of the tag entries matches the address, a cache "miss" is generated. The address is sent to main memory. A line from main memory is accessed. This line is stored in the data memory of the cache, and certain requested bytes are selected from this line and sent to the processor. Upon a "miss", the cache system also selects an existing cache entry for replacement if the cache is currently full. After a replacement policy determined, the received line from the main memory is then stored into the predetermined line in the cache.

10 In most image applications, an image data cache is often implemented to reduce the memory latency. Although the image data cache does provide a significant performance improvement, the performance penalty on cache miss is still significant and unavoidable.

Summary of the Invention It is an object of the present invention to substantially overcome, or at least ameliorate, one or more disadvantages of existing arrangements.

According to a first aspect of the invention, there is provided an image cache system for caching one or more digital images, the image cache system comprising: a o cache memory having a plurality of memory groups for storing pixels of said one or more digital images, wherein during first cycles one or more first said groups function as a cache and one or more second said groups function as a pre-fetch cache, and during second cycles said one or more first groups function as said pre-fetch cache and said one or more second groups function as said cache; and a cache controller for pre-fetching predicted pixels of said one or more digital images and storing said predicted pixels in said pre-fetch cache during each of said first and second cycles, wherein said predicted pixels of said one or more digital images are those said pixels in raster order immediately following said pixels of the corresponding said one or more digital images stored in said cache.

546920.doc -3- According to a second aspect of the invention, there is provided a method of caching one or more digital images, the method comprising the steps of: storing pixels of said one or more digital images in a plurality of memory groups of a cache memory, wherein during first cycles one or more first said groups function as a cache and one or more second said groups function as a pre-fetch cache, and during second cycles said one or more first groups function as said pre-fetch cache and said one or more second groups function as said cache; and pre-fetching predicted pixels of said one or more digital images and storing said predicted pixels in said pre-fetch cache during each of said first and second cycles, wherein said predicted pixels of said one or more digital images are those said pixels in raster order immediately following said pixels of the corresponding said one or more digital images stored in said cache.

Brief Description of the Drawings A number of preferred embodiments of the present invention will now be described with reference to the drawings, in which: Fig. 1 is a schematic diagram of an image cache system; Fig. 2 is a schematic diagram of the memory organisation of the cache memory of the image cache system of Fig. 1; Fig. 3 illustrates the pre-fetch operation of the image cache system of Fig. 1 in an S"one non-interpolated bit map image mode and pre-fetch sub-mode; Fig. 4 shows a Table listing the initial address tags for the different modes of the image cache system of Fig. 1; Fig. 5 shows a Table listing the conditions for pre-fetch in the different modes of the image cache system of Fig. 1; Fig. 6 shows a Table listing the different modes of the image cache system of Fig. 1 Fig. 7 illustrates the state transitions of the image cache system of Fig. 1; and Fig. 8 shows a Table listing the state transitions illustrated in Fig. 4.

Detailed Description including Best Mode 546920.doc Where reference is made in any one or more of the accompanying drawings to steps and/or features, which have the same reference numerals, those steps and/or features have for the purposes of this description the same function(s) or operation(s), unless the contrary intention appears.

Fig. 1 is a schematic diagram of an image cache system in accordance with the preferred embodiment. The image cache system 100 comprises a cache controller module 102, an address tag module 104, a cache memory module 106, a pipeline controller module 108, a data alignment module 110, and a bit alignment module 112.

i The image cache system 100 and the processor (not shown) may be integrated onto an 10 o l integrated circuit chip. However, the image cache system 100 and processor (not shown) may be formed on separate chips as well.

i Preferably, the image cache system 100 can operate in any one of four different modes. In a first mode, the image cache system 100 is able to cache one non-interpolated ••ooe bit map image. In a second mode, the image cache system 100 is able to cache two noninterpolated bit map images. In a third mode, the image cache system 100 is able to cache one interpolated bit map image. In a fourth mode, the image cache system 100 is disabled.

S

o Further, the image cache system 100 can operate in any one of two sub-modes for each one of the above mentioned enabled modes. In a first sub-mode, the image cache system 100 pre-fetches the image data to avoid a likely cache miss in the future. In a second sub-mode, the pre-fetching operation is disabled.

Preferably, each bit map image has a header containing a first set of cache data settings including a programmable cache enable bit, a pre-fetch enable bit, and data indicating the bit map type of the image. The cache enable bit indicates whether the image is to be cached or not and can be set by the processor (not shown). The pre-fetch enable bit indicates whether or not the image is to be pre-fetched. This first set of cache data settings together with a second set of cache data settings are supplied 150 to the 546920.doc image cache system 100 by a processor (not shown). These second set of cache data settings include an interpolated bit, and a global cache disable bit. The interpolated bit indicates whether the image is to be interpolated or non-interpolated. The global cache disable bit when set overrides the cache enable bit of any of the image(s) so that no images are cached. The bit map number bit indicates whether one or two bit map images are to be cached. These first and second sets of cache data settings together enable the control of the mode and sub-mode operations of the image cache system 100.

As mentioned above, preferably the image cache system 100 only caches up to two non-interpolated or one interpolated bit maps. This restriction is due to the large costs 10 involved in large sized cache memories. Further bit map requests for caching more than two non-interpolated or one interpolated bit map images will be treated by the image •cache system 100 as non-cacheable no matter whether the cache enable bit is set or not.

However, the image cache system 100 can be modified to cache any number of bit map images (non-interpolated and/or interpolated) by expanding the size of the cache memory, without departing from the spirit and the scope of the invention.

A brief overview of the operation of the image cache system 100 will now be described. First, a processor (not shown) supplies to the pipeline controller module 108 the first and second set of cache data settings 150, which supplies them 136 to the cache controller module 102, the data alignment module 110, and the bit alignment module 112.

The cache controller module 102 determines the mode and sub-mode of operation of the image cache system 100 in accordance with these cache data settings. The cache controller module 102 in turn supplies a cache mode signal 126 to the address tag module 104 indicating the determined current mode and sub-mode of operation of the image cache system 100.

Next, a processor (not shown) presents the address tag module 104, which has two address inputs, with one or two bit addresses (Aoo, Aoo(l) and Ao 0 or Aoo and Ao depending upon the current mode of operation of the image cache system 100. The bit 546920.doc map image data is accessed by these bit address(es), each referencing a starting bit of a pixel of the image data stored in the cache memory module 106 or in the main memory (not shown). The processor (not shown) presents one address A 0 0 to one input of the address tag module 104 when the image cache system 100 is in the one non-interpolated mode. During the two non-interpolated mode, the processor (not shown) presents an address A 00 oo to the input A 0 0 of the address tag module 104. In the latter mode, the address input A 00 oo references either the current active pixel (in raster scan order) of the first bit map image or the second bit map image. The cache controller module 102 has an internal bit map image counter, which it uses to keep track of the current bit map image being addressed. The internal counter is reset by a special bit sent (not shown) by the processor. Also, the processor (not shown) presents two addresses to inputs Aoo and Alo of the address tag module 104 when the image cache system 100 is in the interpolated mode. In the latter mode, the address input A 00 oo references the current active pixel (in raster scan order) and the next pixel, and the address input A 1 0 references the pixel at one scanline below the current active pixel and the next pixel. The A 10 address is used only for interpolated bit map image, where each pixel requires 4 neighbouring pixels for interpolation. The image data is accessed by a bit address, which references a starting bit of a pixel in the bit stream of the image data.

Prior to searching, the cache memory 106 sends to the address tag module 104 a 20 signal 124 indicating that the words in the cache memory 106 are valid and are ready for accessing. A search is then made by the address tag module 104 of a tag memory within S "the address tag module 104 for the word address(es) of address(es) (Aoo Aoo(1) and Aoo(2), or A 00 oo and A 10 o If the word address(es) of address(es) (Aoo Aoo(1) and Aoo(2), or A 00 oo and A 10 are found a hit_check signal 128 is supplied by the address tag module 104 to the cache controller module 102 indicating a cache "hit". The word address(es) S (ignoring the least significant 6 bits) of addresses (Aoo Aoo(1) and Aoo(2), or Aoo and Alo are indirectly used for accessing the words from cache memory module 106, while the 546920.doc byte and bit address(es) of address(es) (Aoo Aoo(1) and Aoo(2), or Aoo and Aio are directly used by the data alignment module 110 and the bit alignment module 112 respectively. The address tag module 104 checks whether the word address(es) (Aoo Aoo(1) and Aoo(2), or Aoo and Alo) (ignoring the least significant 6 bits) are present in tag memory. If the word address(es) (Aoo Aoo(1) and Aoo(2), or Aoo and Alo) are found, the address tag module 104 generates a corresponding read address for the cache memory 106, which supplies the corresponding words 140 stored in the cache memory 106 to the data alignment module 110. In addition, the byte addresses 130 of the input address(es) (Aoo Aoo(l) and Aoo(2), or Aoo and Alo) are supplied to the data alignment module 110 I 0 404* 10 for selecting and aligning the addressed bytes of words 140 supplied by the cache memory module 106. Furthermore, the bit addresses 132 of the address(es) (Aoo Aoo(1) and Aoo(2), or Aoo and Aio) are supplied to the bit alignment module 112 for selecting and aligning the addressed bits of the selected bytes 142 supplied by the data alignment q@9* module 110 into one or more pixels. These pixels are then sent 144 to the processor (not shown).

If, after a search of the tag memory within the address tag module 104, none of tag o entries matches the word address(es) of the address(es) (Aoo Aoo(1) and Aoo(2), or Aoo Sand A 1 0 a hit_check signal 128 is sent to the cache controller module 102 indicating that 4.

so a cache "miss" is generated. When a cache "miss" happens, the cache controller module 102 sends a signal 134 to the pipeline controller module 108 stalling the output of the image cache system 100. The cache controller module 102 then requests 152 word(s) including the requested word(s) from the main memory (not shown) and fills 140 the whole cache memory module 106 with these word(s).

Turning now to Fig. 2, there is shown a schematic diagram of the memory organisation of the cache memory module 106 of the image cache system of Fig. 1. The cache memory of module 106 is divided into four groups, named A, B, C and D, and each group has four 64-bit words. Each 64-bit word has an associated bit within the cache 546920.doc memory of module 106 indicating the validity of the data of the associated word.

Preferably, each group of the cache memory module 106 has only one associated word address tag stored in a tag address register in the address tag module 104. As the addresses of the four words stored in a group are in sequential order, then the address tag module 104 need only check the one associated word address tag for that group in order to determine if the requested word address is in the cache memory module 106.

The cache memory module 106 can accommodate various types of bit map images in non-interpolated mode and interpolated mode. The cache memory module 106 also can hold data of more than 1 bit map image at the same time.

10 Turning now to Fig. 3, there is illustrated the pre-fetch operation of the image cache system of Fig. 1 in the one non-interpolated bit map image mode and pre-fetch sub-mode.

In this mode, the groups A and B of the cache memory 106 are grouped together to form a group AB of eight 64 bit-words and the groups C and D are grouped together to form a 0: group CD of eight 64 bit-words. In order to reduce memory latency for cache misses, the groups (AB, CD) of the cache memory module 106 operate in pairs with one group active 0. 0.and the other group functioning as pre-fetch cache. The cache controller module 102 00 0. fetches predicted pixels using memory free cycles.

These predicted pixels are based on the following insight. Given that image data in most instances is linearly stored in memory in raster order, it is possible to predict when 0. 0.o the next cache miss is likely to happen and therefore pre-fetch the predicted image data to avoid the likely cache miss in the future. The most likely cache miss address is likely to occur on the word right after the cached word. Namely, the most likely cache miss is likely to occur on the next pixel in the raster order. The image data can then be prefetched and stored in the cache memory module 106, in such a manner that the next pixel in the raster order after the current pixel presently being addressed is always in cache memory.

546920.doc Returning to Fig. 3, the method of pre-fetching will now be explained in more detail. When a cache miss does happen, the pipeline controller module 108 will stall. A 16-words burst read will then be initiated by the cache controller module 102 from the main memory (not shown) to fill 302 the whole cache memory module 106. The cache memory module is filled with pixel data in the same raster order as the main memory (not shown) and commencing with the currently addressed pixel. The pipeline controller module 108 will resume once the requested words are present in cache memory module 106. The cache memory module 106 will simultaneously continue to fill until the cache memory module 106 is full. The processor (not shown) then sends the addresses of the pixels in raster order one after another to the image cache system 100 for accessing the :0•000 corresponding words in the cache memory, if present. After the first half of the words of the cache memory group AB) have been accessed the image cache system 100 enters O oO a first cycle of pre-fetching 304. During this cycle 304, the cache controller module 102 will start another 8-words burst read to fill the stale cache (group AB). These 8-words are "000 15 read from those words in main memory, which immediately follow the words read in the previous cycle 302 in raster order. Also, during this cycle 304, the previously fetched words of group CD are active and can be addressed. After the second half of the words of the cache memory (group CD) have been accessed, the image cache system 100 enters a o :*second cycle ofpre-fetching 306. During this cycle 306, the cache controller module 102 will start another 8-words burst read to fill the stale cache (group CD). The latter 8-words are read from those words in main memory, which immediately follow the words read in the previous cycle 304 in raster order. Also, during this cycle 306, the previously fetched words (group AB) are now active and can be addressed. The pre-fetching will then keep on going between cycles 304 and 306 until a cache miss happens. This pre-fetch method can efficiently avoid subsequent cache miss penalty, when the bit map image is linearly stored in the memory in raster order, as the next pixel in the raster order after the current pixel presently being addressed is always in cache memory.

546920.doc A similar pre-fetching method can be applied in the two non-interpolated bit map images mode and the one interpolated mode with some modifications. During the two non-interpolated mode, groups A and B operate in pair (one being the pre-fetch group, the other being the active group) for the first bit map while groups C and D operate in pair (one being the pre-fetch group, the other being the active group) for the second bit map.

In the latter mode, the active group and pre-fetch group are reduced to 4 cache words each. The one interpolated mode operates in similar way as the two non-interpolated bit map images mode except group C and D use A 10 as address. Namely, groups C and D store the pixels from the next scanline, which are immediately below the pixels stored in groups A and B.

In some special cases (eg. a rotated image) the image data are not linearly stored in the main memory (not shown) in raster order and as a result the presence of cache will S waste the memory bandwidth, eg. pre-fetching unnecessary image data. Preferably, the processor (not shown) enables by way of software the pre-fetch enable bit where the 15 image data is linearly stored in the main memory (not shown), otherwise it is disabled. In these special cases (eg. a rotated image), the image data can still be cached (but not prefetched).. The cache controller module 102 is able to read the pre-fetch bit of the cache data settings 136 and operate in the appropriate pre-fetch sub-mode or pre-fetch disabled sub-mode.

In this way, the image cache system 100 can efficiently pre-fetch the image data and give the highest image data throughput when the image is linearly stored in the memory. It also provides a programmable configuration to disable the cache or pre-fetch function to avoid wasting memory cycles for some special cases, where the image data are not linearly stored in the memory in raster order.

Turning now to Fig. 4, there is shown a Table listing the initial address tags for the different modes of the image cache system of Fig. 1. This table shows the initial state of the tag addresses AddrA, AddrB, AddrC, and AddrD) for the first words in the 546920.doc -11groups B, C, and D) respectively after a cache fill for the one non-interpolated bit map image mode, two non-interpolated bit map images mode, and the one interpolated bit map image mode. The role of the group in each pair will swap when half of the cache memory becomes stale.

In the one non-interpolated bit map image mode, groups A and B, C and D are grouped together as group AB and CD respectively. In the initial state of this mode, the tag address AddrA stores the word address of A 00 corresponding to the first word in the group AB stored in the cache memory module 106. The tag address AddrC stores the predicted word address corresponding to the first word in the group CD in the cache i 10 memory module 106. The predicted address Addr C) is offset from the address Aoo 00 by :••°•eight words. The remaining words in groups AB and CD of the cache memory module 106 are stored sequentially so that the pixel data is linearly stored in cache memory in raster order.

In the initial state of the two non-interpolated mode, the tag addresses AddrA and o00o AddrC store the word addresses of A 00 and A 00 corresponding to the first words of the groups A and C respectively stored in cache memory module 106. The bit ::::addresses Aoo and Aoo respectively reference pixel data within the first and second bitmap images respectively. These bit addresses Aoo and Aoo of the two bitmap images are generally independent of each other. The predicted word addresses (AddrB and Addr D) are offset from the word addresses of A 0 0 and A 00 respectively by four words. The remaining words in groups A and B of the cache memory module 106 are stored sequentially so that the pixel data of the first bitmap image is linearly stored in cache memory in raster order. Similarly, the remaining words in groups C and D are also stored linearly for the second bitmap image.

In the initial state of the one interpolated mode, the tag addresses AddrA and Addr_C store the word addresses of A 00 and Ao 10 corresponding to the first words of the groups A and C respectively stored in cache memory module 106. The bit address Ajo 546920.doc -12references pixel data of the bitmap image that lies in the next scan line immediately below the pixel data referenced by the bit address A 00 The processor (not shown) determines the bit address A 10 by determining the length of the scan line of the bitmap image and adding an offset to A 00 The predicted word addresses (AddrB and AddrD) are offset from the word addresses of A 00 and A 1 0 respectively by four words. The remaining words in groups A and B of the cache memory module 106 are stored sequentially in cache memory in raster order. Similarly, the remaining words in groups C and D are also stored sequentially in cache memory in raster order.

The cache controller module 102 performs a pre-fetching operation in response to signals received from the address tag module 104. The manner in which the address tag module 104 and cache controller module 102 implement the pre-fetching is dependent on the mode of operation of the image cache system 100. Namely, the actual operation of the pre-fetching sub-mode differs depending upon whether the image cache system 100 is operating in the one non-interpolated mode, two non-interpolated mode, or a one interpolated mode.

During the one non-interpolated mode, the address tag module 104 generates the following signals which are used by the cache controller 102 during the pre-fetching operation. The address tag module 104 generates a stale signal for each group indicating whether or not the pixel data within each group is active (ie currently being read) or 20 inactive (ie previously read). The address tag module 104 achieves this by checking S°whether the current bit address A 00 less the first tag word address of any one of groups SA,B,C, or D is equal to or greater than the number of words in a group eg. 4) and if so will generate a stale signal for that group (eg bstale TRUE indicating the pixel data within the group is inactive. The address tag module 104 also generates a hit signal for each group indicating whether or not the requested pixel data corresponding to the .current bit address Aoo 00 falls entirely in that group (eg chit TRUE(l)). The stale signal S• and the hit signal, from each cache group, are then sent 128 by the address tag module S•546920.doc -13- 104 to the cache controller module 102, which signals are then decoded according to the current cache mode. The cache controller module 102 then determines by logic circuitry if a pre-fetch condition occurs utilising the stale and hit signals and if so will then start a pre-fetch cycle.

The address tag module 104, during the two non-interpolated bit map images mode and the one interpolated mode generates the same signals but with some modifications.

These modifications are described below.

In the two non-interpolated mode, the address tag module 104 checks whether the current bit address Aoo 00 of the first bitmap image less the first tag word address of any 10 one of groups A or B is equal to or greater than the number of words in a group eg. 4) and if so will generate a stale signal for that group (eg astale TRUE indicating the pixel data within the group is inactive. In addition, the address tag module 104 checks 000whether the current bit address A 00 of the second bitmap image less the first tag word address of any one of groups C or D is equal to or greater than the number of words in a group eg. 4) and if so will generate a stale signal for that group (eg c_stale TRUE indicating the pixel data within the group is inactive.

In the one interpolated mode, the address tag module 104 checks whether the current bit address Aoo 00 less the first tag word address of any one of the groups A or B is equal to or greater than the number of words in a group eg. 4) and if so will generate a stale signal for that group (eg a_stale TRUE indicating the pixel data within the group is inactive. In addition, the address tag module 104 checks whether the current bit address A 10 less the first tag word address of any one of groups C or D is equal to or greater than the number of words in a group eg. 4) and if so will generate a stale signal for that group (eg c_stale TRUE indicating the pixel data within the group is inactive.

546920.doc 14- As mentioned above, the cache controller module 102 determines by logic circuitry if a pre-fetch condition occurs utilising the stale and hit signals and if so will then start a pre-fetch cycle.

Turning now to Fig. 5 there is shown a Table listing the conditions for the start of pre-fetch cycle in each cache mode. During an one non-interpolated mode, the cache controller module 102 first determines whether the bitmap image is pre-fetchable, that is if the pre-fetch attribute bit has been enabled. In the further event that the cache controller module 102 then receives a stale signal (b_stale TRUE(1)) and a hit signal (c_hit TRUE(l)) from the address tag generator 104, the cache controller module 102 10 will initiate a pre-fetch cycle pre-fetching words from main memory for group AB. The **chit TRUE(l1) signal indicates that the word associated with the current word address

A

0 0 is found in group C and thus group C is currently active. The b_stale TRUE(l) signal indicates that the words in group B (and thus group AB) are previous in raster order to those in group C (and thus group CD) and are thus inactive. The cache controller module 102 can then initiate a pre-fetch cycle pre-fetching words from main memory for group AB. In the event that the cache controller module 102 receives a stale signal (d_stale TRUE(1)) and a hit signal (ahit TRUE(1)) from the address tag generator 104 the cache controller module 102 will initiate a pre-fetch cycle pre-fetching words o. from main memory for group CD. The a_hit TRUE(1) signal indicates that the word associated with the current word address A 00 is found in group A and thus group A is currently active. The d_stale TRUE(1) signal indicates that the words in group D (and thus group CD) are previous in raster order to those in group A (and thus group AB) and are thus inactive. The cache controller module 102 can then initiate a pre-fetch cycle prefetching words from main memory for group CD. The cache controller module 104, during the two non-interpolated bit map images mode and the one interpolated bit map image mode performs similar pre-fetching operations with some modifications, as can be seen from the Table shown in Fig. 546920.doc Returning to Fig. 1, the operation of image cache system 100 will be described in further detail. As mentioned above, the image cache system 100 can operate in any one of four modes: a one non-interpolated bit map image mode, a two non-interpolated bit map image mode, a one non-interpolated bit map image mode, and a disabled mode. In the latter mode, the cache controller module 102 determines from the data cache settings that cache enable bit is disabled and sends a stall signal 134 to the pipeline controller 108 and the requests are directed to the main memory (not shown). In this way, the image cache memory module is bypassed.

As mentioned previously, the host processor presents the bit addresses (Aoo A00oo(1) and Aoo(2), or A 00 and A 1 0 to the address tag module 104. Each of these bit addresses corresponds to pixel data that may be found in a single word or two words depending on the format of the bit map image. The image cache system 100 is capable of handling bit map image formats having the following number of bits per pixel (1,8,24,32). The bits required for a pixel can cross a 64-bit word boundary and thus the address tag module 104 performs cross word checking. The address tag module 104 takes the bit addresses and performs cache hit checking on each group B, C, or A hit signal for a group is generated if the pixel data corresponding to the current bit address falls in that group.

The address tag module 104 generates the following types of hit signals hit0 the most significant byte falls in this group.

S 20 hitl all bits fall in this group.

hit3 the least significant byte falls in this group.

S •The hit0 and hit3 signals are only generated where the addressed pixel data crosses the boundary of adjacent groups in the cache memory. On the other hand, the hitl signal is only generated where the addressed pixel data falls entirely within the group. It is the S 25 latter hitl signal, which is used for the controlling of the pre-fetch operation (eg chit TRUE The address tag module 104 also checks the data is valid given that the tag addresses are updated before the data is actually written into the cache memory.

546920.d 546920.doc The cache controller module 102 decodes the hit check status from each group as per the current cache mode. Once cache miss happens, stall 134 is signalled by the cache controller 102 and cache fill 140 will take place. Cache Fill 140 is initiated by the cache control module 102 as a result of cache miss or pre-fetch. Cache write control and address 138 are sent to the cache memory module 106 and the corresponding tags in the address tag module 104 are updated accordingly. In the cache miss case, tags are updated using the word address presented by Aoo 00 or Al 0 while in pre-fetch case, tags are updated using the predicted address. In the start of cache fill cycle the valid bits of the group, which is to be filled, are cleared and then set when the corresponding word is written.

:i lo This mechanism will ensure the coherency between the address tag module 104 and the cache memory module 102.

For a cache miss cycle, in the one non-interpolated bit map image (nonintl) mode, the whole cache is reloaded. In the two non-interpolated bit map images mode (nonint2) mode, either the first half or the second half of cache is reloaded depending on cache miss S 15 happens on the first bit map or the second. In the one interpolated bit map image mode (intl) mode, if cache miss happens on A 00 the first half cache is reloaded otherwise the second half is reloaded.

Preferably, the cache memory is partitioned into 2 parts and indirectly indexed by 2 separate addresses. The cache memory is indexed by the word address(es) generated by the address tag module 104 corresponding to the bit address(es) (Aoo, Aoo(1) and Aoo(2), or A 00 oo and A 10 During the non-intl mode, the first part bank_ab and the second part bank_cd are indirectly indexed by the bit address A 00 During the non-int2 mode, the first part, bank_ab, is indirectly indexed by the bit address of Aoo and the second part bank_cd, is indirectly indexed by the bit address of A 00 oo During the intl mode, the first part, bank_ab, is indirectly indexed by the bit address of A 00 oo and the second part, bank_cd, is indirectly indexed by the bit address of A l o 546920.doc -17- Preferably, each part of the cache memory outputs 2 consecutive words. As mentioned earlier, the bits required for a pixel may cross a 64-bit word boundary and thus in this instance two consecutive words are required. The cache memory, by always outputting two consecutive words simplifies the implementation of the image cache system 100. Preferably, each bank functions as a circular buffer. If the index is 1, then word 1 and word 2 are output. If the index is 7, then word 7 and word 0 are output.

Preferably, the cache controller module 102 may make memory requests of 1, 2, 4, 8 or 16 words burst read. The 1 or 2 words burst read is made by the cache controller module 102 during the processing of a non-cacheable bit map only. The cache controller 10 module 102 bypasses the cache memory 106 and feeds the words directly to the data o.• alignment module 110. If the non-cacheable bit map is interpolated, 2 consecutive requests will be sent for the current pixel and the pixel one line below. The returned data is latched in the data alignment module 110.

•The accessed words of the cache memory module 106 are sent to the data alignment module 110 and bit alignment module 112. The required bits of the pixel(s) are extracted in 2 steps byte alignment by the data alignment module 110 and bit alignment by the bit oo° alignment module 112. The data alignment module 110 selects the requested bytes within the accessed words using the byte address(es) 122 supplied by the address tag module 104. The bit alignment module 112 selects the requested bits in the bytes supplied by the data alignment module 110 using the bit address(es) 132 to obtain the requested pixels, which are then sent 144 to the host processor (not shown).

The cache controller module 102 has a state machine (not shown) recording the status of the current operational mode of the image cache system 100 and for the controlling the state transitions between the different modes.

Turning now to Fig. 6, there is shown a Table listing the enabled modes of the state machine. As mentioned earlier, the image cache system 100 can operate in one non- 546920.doc -18interpolated bitmap image mode (non-intl); a two non-interpolated bitmap images mode (non-int2); and a one interpolated bitmap image mode (intl).

Turning now to Fig. 7, there is shown the state transitions of the image cache system of Fig. 1. The state machine will transit to another state depending on the current state and the type of the new requested bit map (cacheable or not and interpolated or not).

The cache controller module 102 determines from the data cache settings if a new requested bit map is cacheable if the following condition is satisfied: a global cache disable bit is not set; and the cache disable bit in the newly requested bit map is not set; and 10 the number of active bit maps in the cache is smaller than the threshold (2 non-interpolated and I interpolated bit map).

For example, an active non-interpolated bit map in the cache will make the second interpolated bit map non-cacheable.

These state transitions will now be described with reference to Fig. 7 and the Table shown in Fig. 8. When the state machine is presently in the non-intl mode (default mode) and there is no active non-interpolated bitmap in the cache and the newly requested bitmap is a cacheable interpolated bitmap, the state machine will transition to the intl mode (Condition When the state machine is presently in the intl mode, and o there is no active interpolated bitmap in the cache and the incoming bitmap is a cacheable non-interpolated bitmap, the state machine will transition to the non-intl mode once a cache miss happens (Condition When the state machine is presently in the non-intl mode and a second cacheable non-interpolated bitmap is encountered while there is one active non-interpolated bitmap in the cache, the state machine will transition to the nonint2 mode once there is a cache miss (Condition When the state machine is presently in the non-int2 mode, and a cache miss occurs on the incoming bitmap and there is less than two active bitmaps in the cache, the state machine transitions to the non-intl mode (Condition When the state machine is in the non-int2 mode, and the incoming bitmap 546920.doc -19is a cacheable interpolated bitmap, the state machine transitions to the intl mode. The host processor may reset the state machine at any time. All address tags of the address tag module 104 and validity bit in each cache word of the cache memory module are cleared after reset.

Industrial Applicability It is apparent from the above that the embodiment(s) of the invention are applicable to the computer graphics and related industries.

The foregoing describes some embodiments of the present invention, and modifications and/or changes can be made thereto without departing from the scope and spirit of the invention, the embodiment(s) being illustrative and not restrictive.

In the context of this specification, the word "comprising" means "including i principally but not necessarily solely" or "having" or "including" and not "consisting only of'. Variations of the word comprising, such as "comprise" and "comprises" have corresponding meanings.

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0o o 546920.doc

Claims (10)

1. An image cache system for caching one or more digital images, the image cache system comprising: a cache memory having a plurality of memory groups for storing pixels of said one or more digital images, wherein during first cycles one or more first said groups function as a cache and one or more second said groups funetion as a pre-fetch cache, and during second cycles said one or more first groups function as said pre-fetch cache and said one or more second groups function as said cache;.and 10 a cache controller for pre-fetching predicted pixels of said one or more digital images and storing said predicted pixels in said pre-fetch cache during each of said first So and second cycles, wherein said predicted pixels of said one or more digital images are those said pixels in raster order immediately follovwing said pixels of the corresponding said one or more digital images stored in said cache.

2. An image cache system as claimed in claim 1, wherein said image cache system is adapted to cache one said digital image,; and said image cache system comprises: said cache memory having two memory groups for storing pixels of said digital image, wherein during first cycles one first said group functions as a cache and one second said group functions as a pre-fetch cache, and during second cycles said first group functions as said pre-fetch cache and said second group functions as said cache; and said cache controller adapted for pre-fetching predicted pixels of said digital image and storing said predicted pixels in said pre-fetch cache during each of said first and second cycles, wherein said predicted pixels of said digital image are those said pixels in raster order immediately following said pixels of said digital image stored in said cache.

546920.doc -21

3. An image cache system as claimed in claim 1, wherein said image cache system is adapted to cache two said digital images, and said image cache system comprises: said cache memory having four memory groups for storing pixels of said two digital images, wherein a first and second said group store pixels of a first one of said two digital images and a third and fourth said group store pixels of a second one of said two digital images, and wherein during first cycles said first and third groups function as a first and second cache respectively and said second and fourth groups function as a first and second pre-fetch cache respectively, and during second cycles said first and third groups function as said first and second pre-fetch cache respectively and said second and fourth 10 groups function as said first and second cache respectively; and °*o*0 said cache controller being adapted for pre-fetching predicted pixels of said first o digital image and storing said predicted pixels in said first pre-fetch cache during each of said first and second cycles, wherein said predicted pixels of said first digital image are those said pixels in raster order immediately following said pixels of the first digital S image stored in said first cache, and being adapted for pre-fetching predicted pixels of said second digital image and storing said predicted pixels in said second pre-fetch cache o during each of said first and second cycles, wherein said predicted pixels of said second see* digital image are those said pixels in raster order immediately following said pixels of the ooO0* second digital image stored in said second cache. o S

4. An image cache system as claimed in claim 1, wherein said image cache system is adapted to cache one digital image, and said image cache system comprises: said cache memory having four memory groups for storing pixels of said one digital image, wherein a first and second said group store a number of pixels of a first scan line of said digital image and a third and fourth said group store a number of pixels of a second scan line of said digital image immediately below said pixels of the first scan line, and wherein during first cycles said first and third groups function as a first and second 546920.doc -22- cache respectively and said second and fourth groups function as a first and second pre- fetch cache respectively, and during second cycles said first and third groups function as said first and second pre-fetch cache respectively and said second and fourth groups function as said first and second cache respectively; and said cache controller being adapted for pre-fetching predicted pixels of a said first scan line and storing said predicted pixels in said first pre-fetch cache during each of said first and second cycles, wherein said predicted pixels of said first scan line are those said pixels in raster order immediately following said pixels of the first scan line stored in said first cache, and being adapted for pre-fetching predicted pixels of said second scan line 10 and storing said predicted pixels in said second pre-fetch cache during each of said first and second cycles, wherein said predicted pixels of said second scan line are those said oo.ooi pixels in raster order immediately following said pixels of the second scan line stored in said second cache.

5. An image cache system as claimed in claim 1, wherein the image cache system is *able to operate in any one of a plurality of operating modes.

6. An image cache system as claimed in claim 5, wherein the image cache system in one said operating mode is adapted to cache one said digital image.

7. An image cache system as claimed in claim 5, wherein the image cache system in one said operating mode is adapted to cache two said digital images.

8. An image cache system as claimed in claim 5, wherein the image cache system in one said operating mode is adapted to cache a number of pixels of a first scan line of one said digital image and a number of pixels of a second scan line of said digital image immediately below said pixels of the first scan line. 546920.doc -23-

9. An image cache system as claimed in claim 1, wherein the image cache system is adapted to handle digital images of different formats.

10. An image cache system as claimed in claim 1, wherein said image cache system further comprises: an address tag module for storing addresses of pixels stored in the cache memory and for generating hit signals and stale signals for each said group of the cache memory, wherein a hit signal for a said group indicates whether or not a requested address falls 10 entirely in that said group, and a stale signal for a said group indicates whether or not the requested address less a first address of said group is equal to or greater than a ooooo 0. predetermined number. 000:11. An image cache system as claimed in claim 10, wherein the cache controller determines if a pre-fetch condition occurs utilising the stale and hit signals and if so the o e cache controller starts said first or second cycle. o. 12. An image cache system as claimed in claim 1, wherein said one or more digital images each comprise a cache enable bit and said cache controller when said cache enable bit is disabled bypasses said cache memory and directly addresses main memory. 13. An image cache system as claimed in claim 1 or 12, wherein said one or more digital images each comprise a pre-fetch enable bit, and said cache controller when said pre-fetch enable bit is enabled performs said pre-fetching and when said pre-fetch enable bit is disabled does not perform said pre-fetching. 546920.doc -24- 14. An image cache system as claimed in claim 13, wherein software on a processor is capable of setting the cache enable bit and the pre-fetch enable bit of each said digital image dependent upon the nature of the digital image. 15. An image cache system as claimed in claim 1, wherein said cache controller is adapted to automatically decide a further digital image is cacheable or not dependent upon a current mode of the image cache system. 16. An image cache system as claimed in claim 1, wherein the cache memory .oo.oi 10 comprises four said groups of memory each consisting of four words of 64 bits. o• 17. A method of caching one or more digital images, the method comprising the steps of: •storing pixels of said one or more digital images in a plurality of memory groups of a cache memory, wherein during first cycles one or more first said groups function as a cache and one or more second said groups function as a pre-fetch cache, and during second cycles said one or more first groups function as said pre-fetch cache and said one or more second groups function as said cache; and pre-fetching predicted pixels of said one or more digital images and storing said predicted pixels in said pre-fetch cache during each of said first and second cycles, wherein said predicted pixels of said one or more digital images are those said pixels in raster order immediately following said pixels of the corresponding said one or more digital images stored in said cache. 18. A method as claimed in claim 17, wherein said method is adapted to cache one said digital image, and said storing step comprises: 546920.doc storing pixels of said digital image in two said memory groups of said cache memory, wherein during first cycles one first said group functions as a cache and one second said group functions as a pre-fetch cache, and during second cycles said first group functions as said pre-fetch cache and said second group functions as said cache; and said pre-fetching step comprises: pre-fetching predicted pixels of said digital image and storing said predicted pixels in said pre-fetch cache during each of said first and second cycles, wherein said predicted pixels of said digital image are those said pixels in raster order immediately following said pixels of said digital image stored in said cache. eeeee oe S19. A method as claimed in claim 17, wherein said method is adapted to cache two said °digital images, and said storing step comprises: storing pixels of said two digital images in four said memory groups of said cache •memory, wherein a first and second said group store pixels of a first one of said two digital images and a third and fourth said group store pixels of a second one of said two digital images, and wherein during first cycles said first and third groups function as a first and second cache respectively and said second and fourth groups function as a first S-and second pre-fetch cache respectively, and during second cycles said first and third .i groups function as said first and second pre-fetch cache respectively and said second and fourth groups function as said first and second cache respectively; and said pre-fetching step comprising: pre-fetching predicted pixels of said first digital image and storing said predicted pixels in said first pre-fetch cache during each of said first and second cycles, wherein said predicted pixels of said first digital image are those said pixels in raster order immediately following said pixels of the first digital image stored in said first cache, and pre-fetching predicted pixels of said second digital image and storing said predicted pixels in said second pre-fetch cache during each of said first and second cycles, wherein 546920.doc -26- said predicted pixels of said second digital image are those said pixels in raster order immediately following said pixels of the second digital image stored in said second cache. A method as claimed in claim 17, wherein said method is adapted to cache one digital image, and said storing step comprising: storing pixels of said one digital image in four said memory groups of said cache memory, wherein a first and second said group store a number of pixels of a first scan line of said digital image and a third and fourth said group store a number of pixels of a second scan line of said digital image immediately below said pixels of the first scan line, 10 and wherein during first cycles said first and third groups function as a first and second cache respectively and said second and fourth groups function as a first and second pre- ooo.oi S" fetch cache respectively, and during second cycles said first and third groups function as o said first and second pre-fetch cache respectively and said second and fourth groups function as said first and second cache respectively; and pre-fetching predicted pixels of a said first scan line and storing said predicted pixels in said first pre-fetch cache during each of said first and second cycles, wherein said predicted pixels of said first scan line are those said pixels in raster order immediately following said pixels of the first scan line stored in said first cache, and pre- fetching predicted pixels of said second scan line and storing said predicted pixels in said second pre-fetch cache during each of said first and second cycles, wherein said predicted pixels of said second scan line are those said pixels in raster order immediately following said pixels of the second scan line stored in said second cache. 21. A method as claimed as claimed in claim 17, wherein the method of caching is able to operate in any one of a plurality of operating modes. 546920.doc d -27- 22. A method as claimed in claim 21, wherein the method in one said operating mode is adapted to cache one said digital image. 23. A method as claimed in claim 21, wherein the method in one said operating mode is adapted to cache two said digital images. 24. A method as claimed in claim 21, wherein the method in one said operating mode is adapted to cache a number of pixels of a first scan line of one said digital image and a number of pixels of a second scan line of said digital image immediately below said pixels of the first scan line. 25. A method as claimed in claim 17, wherein the method is adapted to handle digital images of different formats. ooooo 00o 15 26. A method as claimed in claim 17, wherein the pre-fetching step further comprises the sub-steps of: generating hit signals and stale signals for each said group of the cache memory, wherein a hit signal for a said group indicates whether or not a requested address falls S.i entirely in that said group, and a stale signal for a said group indicates whether or not the requested address less a first address of said group is equal to or greater than a predetermined number. 27. A method as claimed in claim 26, wherein the pre-fetching step further comprises the sub-steps of: determining if a pre-fetch condition occurs utilising the stale and hit signals and if so starting said first or second cycle. 546920.doc -28- 28. An image cache system substantially as described herein with reference to the accompanying drawings. 29. A method of caching one or more digital images, the method substantially as described herein with reference to the accompanying drawings. DATED this Twenty Seventh Day of March 2001 CANON KABUSHIKI KAISHA 10 Patent Attorneys for the Applicant SPRUSON FERGUSON 546920.doc