AU736780B2 - Method for providing delays independent of switch size in a crossbar switch with speedup - Google Patents

Description

-1- METHOD FOR PROVIDING DELAYS INDEPENDENT OF SWITCH SIZE IN A CROSSBAR SWITCH WITH SPEEDUP FIELD OF THE INVENTION The present invention relates generally to variable and fixed size packet switches, and more particularly, to an apparatus and method for scheduling packet cell inputs through such packet switches.

BACKGROUND OF THE INVENTION In the field of Integrated Services Networks, the importance of maintaining Quality of Service (QoS) for individual traffic streams (or flows) is 15 generally recognized. Thus, such capability continues to be the subject of much research and development. Of particular interest is the delay experienced by an i individual packet or cell. Good delay performance must be provided to all flows abiding to their service contract negotiated at connection setup, even in the presence of other potentially misbehaved flows. Many different methods have been developed to provide such performance in non-blocking switch architectures such as output buffered or shared memory switches. Several algorithms providing a wide range of delay guarantees for non-blocking e architectures have been disclosed in the literature.

Typically, output-buffered or shared memory non-blocking architectures require the existence of high-speed memory. For example, an output-buffered switch requires that the speed of memory at each output must be equal to the total speed of all inputs. Unfortunately, the rate of the increase in memory speed available with current technology has not kept pace with the rapid growth in demand for providing large-scale integrated services networks. Because there is a growing demand for large switches with total input capacity on the order of tens and hundreds of Gb/s, building an output buffered switch at this speed has become a daunting task given the present state of technology.

Similar issues arise with shared memory switches as well.

W:Amade\GABNODEL%23174c.doc -2- Thus, there exists a present need in the art to provide adequate delay performance to guaranteed flows while utilizing the scalability of a crossbar architecture with speedup independent of switch size.

SUMMARY OF THE INVENTION According to one aspect of the present invention there is provided a method of providing delay performance independent of switch size in an inputbuffered switch with a speedup S of greater than two having input channels and output channels for transferring cells therebetween, including the steps of: providing to each of the input channels per-output-channel queues for buffering cells awaiting transfer to the output channels, each per-output-channel queue being associated with a respective input channel and output channel, and having an assigned rate and an ideal service associated therewith; providing an arbiter for controlling the transmission of buffered cells from input channels to output channel, the arbiter having a rate controller for scheduling at a given cell slot the queues in the input channels, the rate 'controller being capable of guaranteeing to each queue an amount of actual service that is within fixed bounds from the ideal service of the queue, the fixed bounds each being equal to one cell; for each per-output-channel queue, maintaining a pair of state variables including a first and a second the state variable, the first state variable corresponding to an ideal beginning time of the next cell of the per-output queue and the second state variable corresponding to an ideal finishing time of transmission of the next cell of the per-output queue; :initializing the first and second state variables, the first state variable being equal to one and the second state variable being equal to one divided by the assigned rate; initializing an arbiter clock counter for counting switch phases to zero; providing a set-match set and a set_queues set; initializing the set-match set to include an empty set and the set-queues set to include all said pairs of state variables; running the rate controller to select from the set queues set one of the pairs having the smallest eligible finish time first and, for the selected pair, W:Vnarie\GABNODEL\23174c.doc -3updating the first state variable with the ideal finish time and second state variable with the ideal beginning time plus one divided by the assigned rate; adding the selected pair to the set-match set; removing from the set_queues set those pairs corresponding to the same input channel and output channel as the selected pair; determining whether or not the set_queues set is empty; if the set_queues set is determined to be empty, then notifying the input channels of the per-output-channel queues corresponding to those pairs added to the set-match set, incrementing the counter by one and returning to the step of initializing the set-match and setqueues sets; and if the set_queues is determined to be not empty, then returning to the step of running the rate controller.

According to a further aspect of the present invention there is provided a switching method for transferring data between input ports and output ports, 15 including: providing input channels including the input ports for receiving data into the apparatus and output channels including the output ports for transmitting .o oo S:data from the apparatus; providing, for each said input channel, per-output-channel queues for buffering data units awaiting transfer to said output channels, each said peroutput-channel queue being associated with at least one said output channel and having an assigned rate and an ideal service associated therewith; providing an arbiter for controlling transfer of said buffered data units between said input channels and said output channels, said arbiter including a *oo S 25 rate controller for scheduling the transfer and guaranteeing to each said peroutput-channel queue an amount of actual service within fixed bounds from the ideal service; maintaining, for each said per-output-channel queue, a first state variable and a second the state variable, said first state variable corresponding to an ideal begin time of a next data unit of said per-output queue and said second state variable corresponding to an ideal finish time of transmission of the next data unit of said per-output queue; and a3rie\GABNODEL\23174.doc -4selecting for transfer by said rate controller, based on said state variables, said data unit buffered in one of said per-output queues having the smallest eligible finish time.

According to a still further aspect of the present invention there is provided a data switching apparatus for transferring data between input ports and output ports, including: input channels including the input ports for receiving data into the apparatus and output channels including the output ports for transmitting data from the apparatus; each said input channel including per-output-channel queues for buffering data units awaiting transfer to said output channels, each said peroutput-channel queue being associated with at least one said output channel and having an assigned rate and an ideal service associated therewith; an arbiter for controlling transfer of buffered data units between said S 15 input channels and said output channels, said arbiter including a rate controller constructed and arranged to schedule the transfer and guarantee to each said per-output-channel queue an amount of actual service within fixed bounds from the ideal service; said rate controller arranged to maintain, for each said per-outputchannel queue, a first state variable and a second the state variable, said first state variable corresponding to an ideal begin time of a next data unit of said per-output queue and said second state variable corresponding to an ideal finish time of transmission of the next data unit of said per-output queue; and ~said rate controller arranged to select for transfer, based on said state variables, said data unit buffered in one of said per-output queues having the smallest eligible finish time.

The present invention may provide per cell/packet delay independent of the switch size comparable to delay guarantees associated with non-blocking output-buffered architectures, while utilizing the scalability of a crossbar. It may allow arbitrary assignment of rates (as long as the rates are feasible in the sense that the sum of all rates does not exceed the total available bandwidth at any input or any output). Additionally, it may allow the flexibility to quickly admit new flows and change the rate assignment of existing flows. Moreover, it ensures protection of well-behaved flows against misbehaved flows.

W:\marie\GABNODEL\23174c.doc More specifically, simulations indicate that such a system may be capable of providing delays comparable to those of an output buffered switch, with any speedup of greater than or equal to two, and the delays observed are independent of switch size.

While the invention is primarily related to providing per-packet/cell delays to guaranteed flows, it can be used in conjunction with best-effort traffic as well.

If best effort traffic is present, it is assumed that the invention as described herein is run at an absolute priority over any scheduling algorithm for best effort traffic.

BRIEF DESCRIPTION OF THE DRAWINGS Preferred embodiment of the present invention will now be described with reference to the accompanying drawings, wherein:

S

i* o S **e W:\marie\GABNODEL\23174c.doc WO 99/35792 PCT/US99/00684 -6- FIG. 1 is block diagram depicting an input-buffered crossbar switch capable of utilizing per-output-channel queue scheduling and arbitration schemes in accordance with the present invention; and FIG. 2 is a flow diagram illustrating a queue scheduling and arbitration scheme for providing delays independent of the switch size in accordance with the present invention.

DESCRIPTION OF THE PREFERRED

EMBODIMENTS

Referring to FIG. 1, with like reference numerals identifying like elements, there is shown an input-buffered crossbar switch 10 implementing a crossbar arbitration scheme in accordance with the present invention. As illustrated in FIG. 1, the underlying architecture of the inputbuffered crossbar switch 10 is represented as an n x m crossbar. Here, is the number of input channels i (I i n) 12 and is the number of output channelsj (I <j m) 14. Each input channel has one or more input ports 16, each of which corresponds to a physical input link 18.

Similarly, the output channels each have one or more output ports 20, each corresponding to a physical output link 22. The input channels 12 are connected to the output channels 14 by way of a crossbar unit 24. It will be understood by those skilled in the art that the crossbar unit as depicted in FIG. 1 includes a crossbar switch fabric of known construction, the details of which have been omitted for purposes of simplification. It is the crossbar switch fabric that is responsible for transferring cells between input and output channels.

In the embodiment shown, the total capacity of all input channels and all output channels is assumed to be the same, although the capacity of individual links may be different.

Hereinafter, the capacity of a single channel is denoted by rc. The speed of the switch fabric, denoted by rsw, is assumed to be S times faster than the speed of any channel. In general, the switch and the channel clocks are not assumed to be synchronized. The speedup values may be arbitrary (and not necessarily integer) values in the range of 1 <S n. It is further assumed that the switch operates in phases of duration T_sw defined as the time needed to transmit a unit of data at speed r_sw. Such phases are referred to as matching phases. In this disclosure, a unit of data shall be referred to as a cell. Accordingly, a switch can move at most one cell from each input channel and at most one cell to each output channel at each matching phase. Therefore, on average, a switch with speedup S can move S cells from each input channel and S cells to each output channel. At S=n, the switch is equivalent to the output buffered switch.

WO 99/35792 PCT/US99/00684 -7- Although not shown in FIG. 1, packets received on a given input link 18 are typically buffered at the input ports. Also, each flow to which the received packets correspond may be allocated a separate buffer or queue at the input channel. These "per-flow" queues may be located in an area of central memory within the input channel. Alternatively, flow queues may be located in a memory in the input ports associated with the input channel. When the packets received from the input links are of variable length, they are fragmented into fixed-size cells. If the packets arriving at the switch all have a fixed length, a cell in ATM networks, no fragmentation is required. In packet switching networks, where arriving packets are of different sizes, the implementation is free to choose the size of the cell as is convenient. The tradeoff in l0 the choice of this size is that the smaller the cell, the better delays can be provided, but the faster the arbitration must be (and therefore the more expensive the switch). In addition, small cell size causes larger fragmentation overhead. Upon arrival and after possible fragmentation, cells are mapped to a corresponding flow (based on various classifiers: source address, destination address, protocol type, etc.). Once mapped, the cells are placed in the appropriate "per-flow" queue.

Associated with each guaranteed flow is some rate rf which is typically established at connection setup time via RSVP). Rates assigned to guaranteed flows can also be changed during a renegotiation of service parameters as allowed by the current RSVP specification. It is assumed that the rate assignment is feasible, the sum of the rates of all flows at each input port channel does not exceed the capacity of this input port channel, and the sum of rates of all flows across all input ports destined to a particular output port does not exceed the capacity of that output port. If the sum of port capacities equals the channel capacity as assumed here, the feasibility of rates across all input and output ports implies the feasibility of rates across all input and output channels. Included in the rate rjf assigned to the flow is any overhead associated with packet fragmentation and re-assembly. The actual data rate negotiated at connection setup may therefore be lower. For networks with fixed packet size, such as ATM, however, no segmentation and re-assembly is required. Thus, no overhead is present.

As shown in FIG. 1, each input channel i 12 has m virtual output queues (VOQs) or peroutput-channel queues 26 (also referred to as per-output or virtual output queues), denoted by Q(ij), 1 <j m, one for each output channelj 14. In the embodiment shown in FIG. 1, the input channel maintains a single flow-level scheduler SJf(i) 28, which needs to schedule only a single flow per cell time. Once scheduler Sf(i) schedules some flowf, it adds the index of this WO 99/35792 PCT/US99/00684 -8flowf (or, alternatively, the head of the line (HOL) cell of flowj) to the tail of queue Q(i,j).

Thus, depending on the implementation, Q(ij) may contain either cells or pointers to cells of individual flows. Any known QoS-capable scheduler, such as those described above, can be used for the Sfscheduler.

In another variation, each input channel could maintain one flow-level scheduler Sf(ij) for each output. When the input channel i needs to transmit a cell to a given outputj, it invokes scheduler Sf(ij) to determine which flow destined to j should be chosen. Unlike the option described above, in which scheduler SJf(i) can run at link speed, the flow-level schedulers Sf(i,j) must be capable of choosing up to S cells per cell time as it is possible that this input may need to send a cell to the same output in all S matching phases of the current cell slot. Inyetanother approach, the input can run m parallel Sfschedulers, one per output. Each of these schedulers may schedule 1 <k S cells per cell time. When a flow is scheduled by Sf an index to this flow is added to Q(ij).

Also included in the input-buffered crossbar switch 10 is an arbiter 30 as shown in FIG.

1. It is the arbiter's responsibility to determine which of the input channels should be able to transmit a cell to particular output channels, cells from which per-output-channel queues should be transmitted. It is assumed that arbiter 24 operates in matching phases. The duration of each phase is equal to the duration of the channel cell slot divided by the speedup S. The goal of the arbiter is to compute a maximal (conflict-free) match between the input and output channels so that at most one cell leaves any input channel and at most one cell enters any output channel during a single matching phase. Although the term "maximal match" (or, alternatively, "maximal matching") is well understood by those skilled in the art, a definition may be had with reference to papers by N. McKeown et al. and Stiliadis et al., cited above, as well as U.S. Patent No. 5,517,495 to Lund et al.

As explained above, during each of its matching phases, the arbiter decides which input can send a cell to which output by computing a maximal matching between all inputs and all outputs. The algorithm used to compute the maximal match is described in detail in paragraphs to follow. Once the matching is completed, the arbiter notifies each input of the output to which it can send a cell by sending to the input channel the index of the per-output queue from which the cell is to be transmitted. The input channel then picks a cell to send to that output channel and the cell is transmitted to the output channel. As shown in FIG. 1, the arbiter 30 maintains -9for each input/output pair ij, a pair of variables (b_ilj, f_ij) denoted as A (ij) 32. How the arbiter utilizes these input/output pairs will be described in detail later with reference to FIG. 2.

When an input channel 12 receives from the arbiter 30 the index of the Q(i,i) corresponding to the output channel 14 for the current matching phase, it forwards the HOL cell of Q(ij) (or, alternatively, the cell pointed to by the HOL pointer in Q(ij) to the output channel j. If Q(ij) is empty that is, there is no cell of a guaranteed flow in the queue, then a cell of a lower-priority service destined to the same output is sent instead. If there is no best effort traffic at this input matching phase, then no cell is sent.

Although not shown in FIG. 1, a cell forwarded by an input channel i to an output channel j is added to a queue maintained by the output channel. A variety of queuing disciplines can be used, such as FIFO, per-input-port, or per flow. If the queue is not a simple FIFO, each output has an additional scheduler, shown in FIG. 1 as output scheduler So 34. This output scheduler determines the order in which cells are transmitted onto the output link from the output channel.

It is assumed that any required reassembly occurs before So is used, so that So schedules 15 packets rather than cells.

Any known QoS-capable scheduler such as those mentioned above can be used for the schedule S_o.

t Since each scheduler Sf, So operates independently of the other, the delay of an individual cell in the switch is the sum of the delay of this cell under its input and output 20 schedulers Sfand S-o, plus the delay due to the potential arbitration conflicts. The delay of a °go* packet segmented in cells is comprised of the delay experienced by its last cell plus the segmentation and re-assembly delays.

Still referring to FIG. 1, it can now be appreciated that, with respect to each input channel, to: °each of the queues Q(ij) contains cells (or pointers to cells) which have already been scheduled by Sfbut which have not yet been transmitted to their destination output channel with which the VOQ is associated due to arbitration conflicts. The present invention undertakes the task of determining the sequence of transmissions between input channels and output channels satisfying the crossbar constraint that only one cell can leave an input channel and enter an output channel per phase in such a way that the arbitration delay is bounded for each cell awaiting its transmission at the input channel.

Now referring to FIG. 2, there is illustrated the actions of the arbiter with respect to TAheduling the per-output-channel queues 40 in accordance with the present invention. As previously indicated, the arbiter maintains a pair of variables (b_ij, f_ij) or A(ij) for each input/output pair ij. These variables b_ij andfij will be referred to as starting time and finish time, respectively. The starting time is the ideal beginning time of transmission of the next cell of the queue with which the input/output pair is associated. The finish time is the ideal finishing S time of transmission of the next cell of the queue with which the input/output pair is associated.

At initial step 42, the arbiter obtains for each input/output pair ij the rate r_i,j, which is the sum of the assigned rates of all flows going from input i to output. Also, in the same step, variables bij andf_ij are initialized (to zero and 1/r_ij, respectively) and a count value time is set to zero.

As further illustrated in FIG. 2, at each matching phase the arbiter computes the maximal match as follows. In step 44, the arbiter initializes a Set_Match set to an empty set and a SetQueues set to all A(ij). Now referring to step 46 in FIG. 2, the arbiter selects the pair A(ij) having the smallest finish timefij among all eligible pairs, where eligible pairs are defined as those whose starting time b_ij is at or before the current time. In step 48, the arbiter adds the pair selected in step 46 to SetMatch, updates the variables such that b_ij=f_ij andf_ij=f_ij+l/r_i,j S 15 as indicated in step 50 and, in step 52, removes from set SetQueues all pairs corresponding to 0: t.i the input and/or output of the A(ij) selected in step 46. If there are any pairs remaining in S SetQueues (step 54), the arbiter returns to step 46 and performs the next iteration of the matching process. Otherwise, the matching is complete. Instep 56, for each A(ij) in the match, the arbiter informs the input i to send to all outputj. As can be seen, the A(ij) in the match 20 correspond to the per-output-channel queues Q(ij) from which a cell should be transmitted in the ooo° current matching phase. The arbiter then proceeds to the next matching phase, incrementing count time by one (step 58) and updating the rates r_ij as necessary (step 60) before returning to step 44.

S.In an alternative input-buffered switch algorithm described in a co-pending application which runs a separate version of the rate controller per input and performs arbitration using the scheduling times of the rate controllers, the delay bound is a function of the size of the switch the number of input/channels). In contrast, the arbiter of the present invention runs a single rate controller across all queues regardless of the input or output channels to which they correspond and uses finish times (rather than scheduled times) as described above. Also, in the above-referenced co-pending application, the input rate controllers which schedule per-output queues at each input are oblivious to potential arbitration conflicts. The arbitration conflicts are pz resolved at the arbiter using timestamps of the scheduling times of the input rate controllers.

WO 99/35792 PCT/US99/00684 -11- Here, in the present invention, the rate controller which is run in the arbiter uses ideal start and finish times of all input/output pairs directly and explicitly resolves arbitration conflicts as part of the operation of the rate controller. Hence, the advantage of the present invention is that the observed delays are independent of the size of the switch and depends only on the rate of the flow. However, in the present invention the rate controller must operate at the faster speed of the switch fabric whereas the input channel rate-controllers in the co-pending application need to operate at a slower channel speed. Likewise, the size of the input to the rate-controller in the present invention is nxm, whereas in the co-pending invention the input to each of the ratecontrollers is only nm. As a result, the implementation of the co-pending invention may be less expensive, especially at high speeds.

While the disclosed input-buffered switch and scheduling method has been particularly shown and described with reference to the preferred embodiments, it will be understood by those skilled in the art that various modifications in form and detail may be made therein without departing from the scope and spirit of the invention as set forth by the claims. Accordingly, modifications such as those suggested above, but not limited thereto, are to be considered within the scope of the claims.

Claims (18)

1. 2. The method of claim 1 further including providing to each of the output channels a queue arranged to receive cells.
2. 3. The method of claim 1 or 2 wherein said cells are ATM cells. A switching method for transferring data between input ports and output ports, including: providing input channels including the input ports for receiving data into °the apparatus and output channels including the output ports for transmitting 20 data from the apparatus; 99*g providing, for each said input channel, per-output-channel queues for buffering data units awaiting transfer to said output channels, each said per- eoutput-channel queue being associated with at least one said output channel and having an assigned rate and an ideal service associated therewith; 999999 providing an arbiter for controlling transfer of said buffered data units S° between said input channels and said output channels, said arbiter including a rate controller for scheduling the transfer and guaranteeing to each said per- output-channel queue an amount of actual service within fixed bounds from the ideal service; maintaining, for each said per-output-channel queue, a first state variable and a second state variable, said first state variable corresponding to an ideal begin time of a next data unit of said per-output queue and said second state variable corresponding to an ideal finish time of transmission of the next data unit of said per-output queue; and W:made\GABNODEL23174c.doc -14- selecting for transfer by said rate controller, based on said state variables, said data unit buffered in one of said per-output queues having the smallest eligible finish time.
3. 5. The switching method of claim 4, wherein said selecting for transfer includes: initializing the first and second state variables forming a pair of state variables, the first state variable being equal to one and the second state variable being equal to one divided by the assigned rate; initializing an arbiter clock counter for counting switch phases to zero; providing a set-match set and a set_queues set; initializing the set-match set to include an empty set and the setqueues set to include all said pairs of state variables; running the rate controller to select from the set_queues set one of the pairs having the smallest eligible finish time first and, for the selected pair, updating the first state variable with the ideal finish time and second state i variable with the ideal begin time plus one divided by the assigned rate; adding the selected pair to the set-match set; ~removing from the set_queues set those pairs corresponding to the same 20 input channel and output channel as the selected pair; determining whether or not the set queues set is empty; if the set_queues set is determined to be empty, then notifying the input o channels of the per-output-channel queues corresponding to those pairs added to the set-match set, incrementing the counter by one and returning to the step of initializing the set-match and setqueues sets; and S• if the set_queues is determined to be not empty, then returning to the step of running the rate controller.
4. 6. The switching method of claim 4 or 5 wherein said data units buffered in said per-output-channel queues are pointers to data stored in a shared memory.
5. 7. The switching method of claim 4, 5 or 6 wherein said data units are fixed length cells. W:made\GABNODELV3174c.doc
6. 8. The switching method of claim 7 wherein said cells are ATM cells.
7. 9. The data switching apparatus of any one of claims 4 to 8 wherein said data transferred between input ports and output ports are a variable length packets and said method including fragmenting, in said input channel, said variable length packets into said data units to be buffered in said per-output- channel queues, and assembling, in said output channel, said fragmented data units to form said variable length packets.
8. 10. A data switching apparatus for transferring data between input ports and output ports, including: input channels including the input ports for receiving data into the apparatus and output channels including the output ports for transmitting data from the apparatus; 5 each said input channel including per-output-channel queues for buffering data units awaiting transfer to said output channels, each said per- i output-channel queue being associated with at least one said output channel and having an assigned rate and an ideal service associated therewith; an arbiter for controlling transfer of buffered data units between said 20 input channels and said output channels, said arbiter including a rate controller constructed and arranged to schedule the transfer and guarantee to each said per-output-channel queue an amount of actual service within fixed bounds from the ideal service; said rate controller arranged to maintain, for each said per-output- channel queue, a first state variable and a second the state variable, said first S"state variable corresponding to an ideal begin time of a next data unit of said per-output queue and said second state variable corresponding to an ideal finish time of transmission of the next data unit of said per-output queue; and said rate controller arranged to select for transfer, based on said state variables, said data unit buffered in one of said per-output queues having the smallest eligible finish time.
9. 11. The data switching apparatus of claim 10 wherein said rate controller is further arranged to use a set-match set and a set_queues set, said set-match W:AmarIe\GABNODEL\23 74c.doc -16- set being first initialized to include an empty set and said set-queues set to include all pairs of said state variables; said rate controller being further arranged to select from said set_queues set one of the pairs having the smallest eligible finish time first and, for the selected pair, update said first state variable with the ideal finish time and second state variable with the ideal begin time plus one divided by the assigned rate, add the selected pair to said set- match set, and remove from said set queues set those pairs corresponding to a same one of said input and output channels as the selected pair.
10. 12. The data switching apparatus of claim 10 wherein said input channel further includes one flow-level scheduler arranged to schedule said data units for storing in said per-output queues.
11. 13. The data switching apparatus of claim 12 wherein said flow-level 15 scheduler is a QoS capable scheduler. i 14. The data switching apparatus of any one of claims 10 to 13 wherein said input channel further includes several flow-level schedulers. 20 15. The data switching apparatus of claim 12, 13 or 14 wherein said output channel further includes one output scheduler arranged to schedule said data go•• units. •r o Vo
12. 16. The data switching apparatus of claim 15 wherein said output scheduler S* 25 is a QoS capable scheduler. V
13. 17. The data switching apparatus of claim 15 wherein said output channel further includes output buffers.
14. 18. The data switching apparatus of any one of claims 10 to 17 wherein said data units stored in said queues are pointers to data stored in a shared memory. W;Xmarde\GABNODEL23174c.doc -17-
15. 19. The data switching apparatus of any one of claims 10 to 18 wherein said data units are fixed length cells. The data switching apparatus of claim 19 wherein said cells are ATM cells.
16. 21. The data switching apparatus of any one of claims 10 to 20 wherein said data transferred between input ports and output ports are a variable length packets.
17. 22. The data switching apparatus of claim 21 wherein said input channel further includes a fragmentation circuitry, and said output channel further includes an assembly circuitry.
18. 23. A method of providing delay performance independent of switch size in an input buffered switch substantially as herein described with reference to the •accompanying drawings. :24. A switching method for transferring data between input ports and output 20 ports substantially as herein described with reference to the accompanying drawings. •g o So .o 25. A data switching apparatus for transferring data between input ports and output ports substantially as herein described with reference to the S.. accompanying drawings. 0 DATED: 31 August, 2000 PHILLIPS ORMONDE FITZPATRICK Attorneys for: CABLETRON SYSTEMS, INC. 3174C.doc