AU658029B2 - Pulse driver - Google Patents

Description

P/100/011 28/5/9J1 Regulation 3.2

AUSTRALIA

Patents Act 1990 a.

ORIGINAL

COMPLETE SPECIFICATION STANDARD PATENT a. I a.

a. a a a. a a. a Ia. a *a*a .ILea.

Invention Title., "PULSE DRIVER" The following statement Is a full description of this Invention, including the best method of performing It known to us:- This invention relates to a pulse driver designed as a customer design analog circuit manufactured on the basis of a rrefabricated array of transistors and resistors.

For custome, design integrated analog circuits which are needed in small quantities, but which should not be very expensive, there are preferably used so-called "low cost analog arrays" for which the customer may choose within certain limits the wiring for a number of elements (transistors and resistors) implemented thereon. Arrays of this kind are not very expensive, but they use transistors of rather low cut-off frequency which transistors may not be driven into saturation for different reasons.

In a 2/34 Mbit/s MUX/DEMUX circuit there are multiplexed 16 usual PCM highways each of 2 Mbit/s (exactly 2.048 Mbit/s) to a 34 Mbit/s multiplex signal and this signal is demultiplexed to 1 6 PCM highways, respectively. For the transmission at the 2 Mbit/s side there is often used a standardised HDB3-coded signal. Said signal is a symmetrical signal with respect to the zero line which is especially adapted for the transmission over symmetrical anes as its DC component may be made exactly zero for a given number of transmitted bits so that the use of transformers is possible to isolate the source and the drain of the 2 Mbit/s signal galvanically fro-r each other.

At the 2 Mbit/s side of the MUX/DEMUX circuit there is needed a receiving and transmitting circuit, respectively, for each incoming and outgoing line, respectively. As the signals received are not free of distortions the receiving circuit has to be an analog 0 20 circuit. For reasons of space economy it may be desirable to have the receiving and the transmitting circuits of a pair of lines within the same integrated circuit so that the transmitting circuit processing as a pulse driver exclusively digital signals has to be an analog circuit too. A digital circuit would also be more expensive as its cut-off frequency had to be rather high to fulfil the rather strict requirements for the generation 25 of the HDB3-coded line signal.

In a pulse driver used for the generation of the HDB3-coded line signal there are admitted time delays between input and output in the range of nanoseconds only. In order to achieve time delays of this range in spite of the low cut-off frequency of the transistors used there are needed special circuitry means. At the sanr:' time the circuit should have a power consumption as small as possible in order to avoid problems with heat dissipation in the case where all 16 transmitting and receiving circuits of said MUX/DEMUX circuit are arranged on the same printed circuit board.

It is therefore an object of the present invention to provide a pulse driver of the above kind which allows the required small time delays between input and output to be achieved in spite of the use of a relatively "slow" technology and which has in addition a low power consumption.

According to the invention there is provided a pulse driver of the aforementioned type, comprising two input transistors the emitter terminals of which are commonly connected via a first resistor with a voltage source, the input transistors being interconnected in such a manner that for two signals applied to input terminals each being connected to the base terminal of the respective input transistor there results an AND-operation for signals of the same polarity, by comprising a third transistor the base terminal of which is directly connected with the emitter terminals of the input tr ,sistors and the collector terminal of which is directly connected with the voltage source, and by comprising an output transistor the base terminal of which is connected via a fourth transistor connected as a diode and a second resistor with the emitter terminal of the third transistor and via a leakage resistor with ground, the emitter terminal of which is directly connected with ground and the collector terminal of which is connected via an extenal load resistor with the voltage source.

The invention will be best understood from the following description of an embodiment taken in conjunction with the accompanying drawing in which: n Figure 1 shows the basic circuit diagram of the pulse driver according to the invention; Figure 2 shows a block diagram of an application of pulse drivers according to S 20 Figure 1 for the generation of a HDB3 line signal; Figure 3 shows signal riagrams at several points of the circuit of Figure 2; Figure 4 shows the di8 Nm of Figure 2 with additionally indicated voltages; Figure 5 shows the diagram of a modification of a part of the circuit according to Figure 1; and 25 Figure 6 shows the diagram of a modification of a part of the circuit according to Figure rigure 1 shows the basic circuit diagram of the pulse driver according to the inve It comprises a first input I1 for a first, preferably pulsed input signal which is applied to the base terminal of a first transistor Qj, a second input 12 for a second input signal, eg. a clock signal, which is applied to the base terminal of a second transistor Q 2 and nn output 0 connected with the collector terminal of a seventh transistor Q7 whereby the output signal can be taken from a load resistor indicated by dashed lines.

Further there are provided transistors Q3 QO and resistors R 1

R

3 the meaning of which will be explained in the following description of the mode of operation of the pulse former.

The input transistors Q, and Q 2 perform an AND operation for positive input signals. When one of the two inputs is maintained at OV then the transistors Q. Q7 are blocked. In this case the power consumption is determined only by resistor R 1 the value of which may be rather high in response to the circuit capacitances, ie. in the range of some kOhms The output O is externally connected with the power supply via the load resistor RL and is in this case at If a positive voltage of 4 5 Volts is applied to both of the inputs transistor Q 3 becomes conductive via resistor R, and delivers the base current for transistor Q 7 via resistor R 2 and transistor 04 connected as a diode. Therefore transistor Q7 becomes .0 conductive and brings the output voltage from 5V to OV.

In the initial condu.cting phase the base current of transistor Q7 is limited only by resistors R 2 and R 3 the lastnamed resistor shunts a portion of the current flowing through R 2 to ground. This rather large base current results in a correspondingly quick decrease of the output voltage.

As soon as the output voltage has fallen to the base voltage of transistor Q 7 the transistor 05 connected as a diode starts to conduct. The transistors Q, and Q 0 form a current mirror circuit so that transistor Q is also conductive. As soon as transistor aQ is conductive the current through esistor R 3 becomes larger and therewith the base voltage of transistor Q3 smaller so that the current through R 3 is decreasing.

20 If further positive voltages are applied to the two inputs there results a base current for transistor Q 7 which is just sufficient to maintain the output voltage at the value of the base voltage of transistor Q7. The current through resistor R 2 and thus the collector current through transistor 03 is composed of the current through resistor R 3 of the base current through transistor Q7 and of the shunt current to transistor Q5. Due to 25 the current mirror circuit QG/QG the last mentioned current is substantially equal to the S collector current through transistor Q0 which is partly determining the voltage drop across resistor R, and which is small with respect to the current through resistor R 3 The resistor R3 causes the positive charge stored in the base of transistor Q7 to be discharged in a sufficiently quick manner when one of the input signals goes to 0.

Therefore the resistor R 3 must have a rather low value which mainly determines the complete power consumption, In spite of the use of transistors of low cut-off frequency it is possible to achieve time delays of 5 10 ns between output and input. The slopes of the output signal are sufficiently steep and the amplitude of the output signal is substantially independent of the load. The requirements with respect to a low power consumption are fulfilled, Figure 2 shows a block diagram of an application of two pulse drivers according to Figure 1 for the generation of a HDB3 line signal in 2 Mbit/s PCM transmission systems. The two pulse drivers 21 and 22 represented as blocks correspond to the circuit of Figure 1, ie. each one comprises two inputs 1 and an output 0, To the input I1 of pulse driver 21 there is applied a signal MA (mark pulse A) and to the input I1 of pulse driver 22 there is applied a signal MB (mark pulse B) whereas the remaining two inputs 12 of the pulse drivers 21 and 22 receive in common eg. a clock signal CP. The outputs 0 of the two pulse drivers are each connected via a resistor R with the ends of the primary winding of an output transformer 23 to the middle of which the supply voltage 5V is applied. The secondary winding of the transformer 23 is connected with a not shown transmission line, eg. with a symmetrical line with an impedance of 120 !D.

As it can be seen from Figure 3 that the signals MA and MB are digital signals which are processed by a circuit (not shown) for the generation of a HDB3 signal in such a manner that a signal MA indicates that a positive pulse of the HDB3 signal has i to be produced whereas a signal MB indicates that a negative pulse of the HDB3 signal has to be produced. This circuit processes said signals in such a manner that the HDB3 signal is DC-free over a given time. Due to the already mentioned AND operation of the two inputs of each pulse driver the clock signal CP determines the time duration and the 20 position of the individual pulses of the line signal LS. It would also be 3ossible to process the signals MA and MB in such a manner that their time duration and position would correspond to the line signal. In this case a positive DC signal at the corresponding inputs would be sufficient instead of the clock signal CP, Figure 4 shows the voltages at the output sides of the pulse drivers 21 and 22 2E5 with active pulse driver 21 and passive pulse driver 22. As the outputs of the two S pulse drivers are coupled over the output transformer 23 the output voltage of the passive pulse driver is raised by the voltage u, induced in the primary winding over the supply voltage U, to a voltage U, u,.

Figure 5 shows a modification of that portion of the circuit of Figure 1 being at the right hand side of the vertical separation line whereas the left hand portion remains unchanged and is therefore not shown. Said modification is used in the case where the raised voltage mentioned in connection with Figure 4 does exceed the admissible baseemitter reverse voltage of transistors Q and Qc,, respectively, of the respective passive pulse driver. By the insertion of a diode or a transistor Q 8 connected as a diode the admissible reverse voltage can be doubled. In order to maintain the lower output voltage of the respective active pulse driver unchanged a transistor Q 9 connected as a diode is inserted in series with transistor Q 4 If an increased variation of the output voltage amplitude is admissible transistor Q 9 could be replaced by a correspondingly chosen resistor.

Figure 6 shows a modification of the circuit according to Figure 5 in the case where the control of the output voltage with conducting transistor Q7 tends to be instable due to time delays and a simultaneoulsly high loop gain. In this case the loop gain is reduced correspondingly by the insertion of resistors R4 and The value of these resistors can be relatively low so that due to the rather low currents through said resistor there results no substantial shift of the controlled output voltage of the conducting transistor Q7.

The present circuit, owing to the use of so-called "low cost analog arrays", realises a low cost pulse driver fulfilling the requirements with respect to the time delay between input and output, to the edge steepness of the output signal and to the insensitiveness against changes of the load impedance. It is especially useful for the generation of a HDB3-coded line signal on a symmetrical line, but it is not limited to said code and said kind of line.

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Claims (11)

1. A pulse driver comprising two input transistors the emitter terminals of which are commonly connected vo C rirst resistor with a voltage source, the input transistors being interconnected in such a manner that for two signals applied to input terminals each being connected to the base terminal of the respective input transistor there results an AND-operation for signals of the same polarity, a third transistor the base terminal of which is directly connected with the emitter terminals of the input transistors and the collector terminal of which is directly connected with the voltage source, and an output transistor the base terminal of which is connected via a fourth transistor connected as a diode and a second resistor with the emitter terminal of the third transistor and via a third resistor to ground, the emitter terminal of said output transistor being directly connected to ground and the collector terminal of said transistor is connected via an oo external load resistor with said voltage source, wherein the collector terminal of the output transistor being fed back via a fifth transistor connected as a diode to the 15 collector terminal of said fourth transistor and via the emitter-collector path of a sixth transistor connected as a current mirror to said fifth transistor to the emitter terminals of the input transistors, the arrangement being such that when the output transistor starts to conduct its base current is limited only by said second and third resistors in order to achieve a quick voltage decrease over the collector-emitter path of the output transistor, and wherein in the steady state condition the base current of the output transistor is reduced by the feedback over the fifth and sixth transistors to such an amount that it is just sufficient to maintain the output voltage at the level of the base voltage of the t output transistor, and that said leakage resistor has a low value to discharge at the transition to the blocked condition the charge stored in the base of the output transistor in a sufficiently quick manner.

2. A pulse driver as claimed in claim 1, wherein the supply voltage is positive with respect to ground, the input transistors being PNP-transistors and the remaining transistors being NPN-transistors.

3 A pulse driver as claimed in claim 1 or claim 2, implemented as a customer design analog circuit based on a low-cost analog array.

4. A line driver arrangement of two pulse drivers as claimed in any one of the preceding claims for the generation of a HDB3-coded line signal, wherein one input of each pulse driver is provided for a mark pulse signal and the other input of each pulse driver is provided for a common enabling signal, the outputs of the two puise drivers "35 being connected via current limiting resistors with the ends of the primary winding of an r f 4 T F.'i output transformer to the middle of which the supply voltage of the output transistors of the two pulse drivers is applied and the secondary winding of which is connected with a transmission line.

A line driver arrangement as claimed in claim 4, wherein into the feedback connections from the respective collector terminals of the output transistors of the two pulse drivers there is inserted an eighth transistor connected as a diode to ensure that the sum voltage U, up resulting from the supply voltage U, and the voltage up induced in the primary winding of the pulse driver being inactive at that moment is smaller than the admissible base-emitter reverse voltages of the fifth transistor and sixth transistor I, and the eighth transistor, and that to compensate for the voltage drop across the eighth transistor a ninth transistor is connected in series with said fourth transistor so that the voltage across the collector-emitter path of the conducting output transistor is equal to that resulting without said eighth and ninth transistors connected as diodes,

6. A line driver arrangement as claimed in claim 4, wherein into the feedback 15 connections from the respective collector terminals of the output transistors of the two to. pulse drivers there is inserted an eighth transistor connected as a diode to ensure that the sum voltage U, up resulting from the supply voltage U, and the voltage up induced in the primary winding of the pulse driver being inactive at that moment is smaller than the admissible base-emitter reverse voltages of the fifth transistor and sixth transistor, 20 and the eighth transistor, and that to compensate for the voltage drop across the eighth transistor an additional resistor of a predetermined value is connected in series with said fourth transistor so that the voltage across the collector-emitter path of the conducting output transistor is about equal to that resulting without said eighth resistor and said additional resistor,

7. A line driver arrangement as claimed in claim 5 or 6, wherein said enabling signal is a DC signal if said mark pulse signals correspond to the conditions of the line signal with respect to their time position and duration,

8, A line driver r.'rangement as claimed in claim 5 or 6, wherein said enabling signal is a clock signal which determines the time position and the duration of the output signal of the pulse drivers in accordance with the requirements of the line signal with the aid of said AND operation of the inputs of the pulse drivers.

9. A pulse driver substantially as herein doscriued with reference to Figure 1 of the accompanying drawings.

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11. A line driver arrangement substantially as herein described with reference to Figure 2 6 of the accompanying drawings. DATED THIS EIGHTH DAY OF DECEMBER 1994 ALCATEL N. V. 6* 0* 6S S S. S S S SS SS S. S So SS S S S *0 S S S S. S S SS*SS* 5* S S S S S S S ABSTRACT A low cost pulse driver with a low mean power consumption for the generation of a line signal. The pulse driver is realised as a customer design analog circuit based on a so-called "low cost analog array". In order to achieve switching delays in the range of nanoseconds in spite of the rather low cut-off frequency of the transistors of this array the output transistor (Q 7 is controlled in the initial conducting phase with a high base current. In the steady state phase the base current is reduced by a feedback circuit (Q4 Q 6 to such an extent that the output transistor remains still conductive so that there results a low mean power consumption. In the cut-off phase a rather low leakage resistor (R 3 provides for a quick removal of the charge stored in the base of the output transistor. The circuit is especially adapted for the generation of a HDB3-coded line signal at the output side of a 34/2 Mbit/s demultiplexer. FIGURE 1. a 4, O 4* 44 t e a 1