AU6503000A - Pll noise smoothing using dual-modulus interleaving - Google Patents

Pll noise smoothing using dual-modulus interleaving

Info

Publication number
AU6503000A
AU6503000A AU65030/00A AU6503000A AU6503000A AU 6503000 A AU6503000 A AU 6503000A AU 65030/00 A AU65030/00 A AU 65030/00A AU 6503000 A AU6503000 A AU 6503000A AU 6503000 A AU6503000 A AU 6503000A
Authority
AU
Australia
Prior art keywords
dual
noise smoothing
pll noise
interleaving
modulus
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU65030/00A
Inventor
Earl W. Mccune
Brian Sander
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tropian Inc
Original Assignee
Tropian Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tropian Inc filed Critical Tropian Inc
Publication of AU6503000A publication Critical patent/AU6503000A/en
Abandoned legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08Details of the phase-locked loop
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K23/00Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/64Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two
    • H03K23/66Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses
    • H03K23/667Pulse counters comprising counting chains; Frequency dividers comprising counting chains with a base or radix other than a power of two with a variable counting base, e.g. by presetting or by adding or suppressing pulses by switching the base during a counting cycle
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • H03L7/06Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H03L7/193Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number the frequency divider/counter comprising a commutable pre-divider, e.g. a two modulus divider
AU65030/00A 1999-07-29 2000-07-31 Pll noise smoothing using dual-modulus interleaving Abandoned AU6503000A (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US36267099A 1999-07-29 1999-07-29
US09362670 1999-07-29
PCT/US2000/020749 WO2001010028A1 (en) 1999-07-29 2000-07-31 Pll noise smoothing using dual-modulus interleaving

Publications (1)

Publication Number Publication Date
AU6503000A true AU6503000A (en) 2001-02-19

Family

ID=23427049

Family Applications (1)

Application Number Title Priority Date Filing Date
AU65030/00A Abandoned AU6503000A (en) 1999-07-29 2000-07-31 Pll noise smoothing using dual-modulus interleaving

Country Status (6)

Country Link
EP (1) EP1201034A1 (en)
JP (1) JP2003506909A (en)
KR (1) KR20020019582A (en)
CN (2) CN1207845C (en)
AU (1) AU6503000A (en)
WO (1) WO2001010028A1 (en)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101436860B (en) * 2007-11-15 2011-03-30 天钰科技股份有限公司 Phase-locked loop circuit and corresponding frequency translation method
GB2533557A (en) * 2014-12-16 2016-06-29 Nordic Semiconductor Asa Frequency divider
CN111478696B (en) * 2020-05-07 2024-05-31 上海磐启微电子有限公司 Control method of four-mode prescaler and four-mode prescaler applying same

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3521288A1 (en) * 1985-06-13 1986-12-18 Siemens AG, 1000 Berlin und 8000 München Arrangement for digital division of an input cycle
FR2716053B1 (en) * 1994-02-09 1996-04-26 Sat Method for generating a specific frequency by dividing a reference frequency.

Also Published As

Publication number Publication date
JP2003506909A (en) 2003-02-18
CN1667955A (en) 2005-09-14
EP1201034A1 (en) 2002-05-02
CN1207845C (en) 2005-06-22
KR20020019582A (en) 2002-03-12
CN1371549A (en) 2002-09-25
WO2001010028A1 (en) 2001-02-08

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase