AU631153B2 - Clock synchronization - Google Patents

Description

OPI DATE 10/07/90 APPLN. I D 45262 89 PT AOJP DATE 09/08/90 PCT NUMBER PCT/AU89,/00'492 INTERNATIONAL APPLICATION PUBLISHED UNDER THE 'PATENT COOPERATION TREATY (PCT) (51) International Patent Classification 4 (11) International Publication Number: WO 90/P7147 G04G 7/00, G04C I11/00 IAl (43) International Publicption D14te: S28 June 1990 (28,06.90) (21) International Application Num (22) international F'iling Date: ber: PCT/AU89/00492 17 November 1989 (17.11.89) 19 December 1988 (19.12.88) AU (74) Agent: O'CO NNO R, Patent Depa rtment, Standard Telephones and Cables Pty. Limited, 2512280 Botany Road, Alexandria, NSW 2015 (AU).

(81) Designated States: AU, GB, JP, KR, US.

Published With international search report.

With amended claims, 631 (71Jtplicaiit (for AU on~v): STANDA-D-T-ET*IHON-ES ~7-D-C-A-BL-E-s--L-~ITTED [AU/AU]; 252-280 c tany Road, Alexandria, NSW 2015 (AU).

(71) Applicant (for GB JP KR only): ALCATEL N.V, tNL/NL]; Strawvinskvlaan 341!, NL-1077 XX Amsterdam (NL).

(72) Inventoi-s; and lnventorsi'Applicants (for US only) STANBURY, Evan, John 8 Myers Street, Lakemba, NSW 2195 JEREMY, Peter, Grant [AU/AU]; 100 Metropolitan Road, Enimore, NSW 2042 (AU).

(54)Title: CLOCK SYNCH RONIZATION t (57) Abstract A method of adjusting the pulse rate of a local clock by generating a first pulse train at a first predetermined rate, dividing the pulse train by a divisor to produce a second pulse train. The value of the divisor is selected 5, 6) so that the rate of the second pulse train is adjusted within a predetermined range.

90/07147 PCT/AU89/00492 Clock synchronization Technical Field This invention relates to a method of and apparatus for adjusting the pulse rate of a local clock to a desired pulse rate. The invention is particularly though not exclusively useful in an arrangement where the clock is incorporated in a remote station associated with a central control station such as, for example, an energy management system, and must be locked into the time of day within a set tolerance and where any clock synchronizing pulse transmitted from the control station to synchronize the local is subjected to random delays in the control station or the transmission medium.

Background Art In a known energy management system used to record consumption of electricity at consumers' premises, electronic registers are used to record the amount of electricity consumed during a number of different tariff rate periods per day. Thus there may be a high tariff rate register, a medium tariff rate register and a low tariff rate register and a time of day clock determines whether consumption occurs during a peak period, a normal period or a low cost period so the meter registrations are recorded in the appropriate register. It is thus necessary for the time of day clocks at each consumer's meter to be accurately locked into the time of day within a set tolerance of e.g. one minute.

In a system where a central computer can monitor the meters at each consumer's premises over the consumer's line, a time signal may be transmitted from the central computer at regular intervals, eg. once a day.

However, the transmission process has an inherent random delay while accessing the subscribers' energy management terminals (EMT). This delay may be of the order of 30 seconds between when the central computer transmits the time signal and when it is received by the EfTs.

2 There will thus usually be a difference between the time registered by the EMT's time of day clock and the clock synchronizing signal received from the central computer due to drift in the EMT clock and due to the random transmission delay. Both the drift and the delay are unknown parameters but a maximum drift will usually be specied in the tolerances for the EMT. This may be, e.g. 0.04s per minutes (40 per day).

A further complication may be added if the requirements of the electricity supply authority require that the time intervals for the consumption pL-'1ds be within a giver tolerance. In the US the electricity metering standard ANSI C12.13 requires an accuracy of 15 minutes 0.9 seconds.

This latter requirement means that the EMT clock cannot automatically be reset in synchronism with the received clock synchronization signal because such a time step may exceed the permissible tolerance.

It is an object of the present invention to provide a method of and an apparatus for adjusting the pulse rate of a local clock to obtain a more accurate time signal therefrom in the absence of an accurate clock synchronization signal.

It is a further object of the present invention to provide a method of and an apparatus for adjusting the pulse rate of a local clock to obtain a more accurate time signal therefrom when using a clock synchronization signal for synchronizing 20 said local clock transmitted from a remote station via a communication link which introduces random delays to the transmission of the synchronization signal.

Summary of the Invention According to the invention there is provided a a method of producing a composite clock signal approxirnating a standard clock signal within a given tolerance 25 linit over a period of time, the method comprising providing at least one slow clock signal having a clock rate slightly slower than the standard clock signal by a first difference frequency and at least one fast clock signal having a clock rate slightly faster than the standard clock signal by a second difference frequency, and applying the fast clock signal as the composite clock signal for a first portion of the 30 period of time approximately determined by the ratio of the first difference frequency divided by a divisor being the sum of the first and second difference frequencies, and applying the slow clock signal as the composite clock signal for the remainder of the time period, the method being repeated in successive time periods.

r3 3 Preferably the period of time is chosen so that the difference between the standard clock signal and the composite clock signal remains within the tolerance limit.

In a refinement of the invention the remainder of the time period and the first portion of the time period are broken up into shorter mutually interleaved intervals.

The slow clock signal may be produced by dividing a supply clock signal by a first dSvisor and the fast clock signal is produced by dividing the supply clock signal by a second divisor.

The method of producing a clock signal may include a method of reducing the difference between the time indicated by a local clock signal derived from a local oscillator and the time indicated by a clock synchronization signal, the method including dividing the local oscillator output in a divider having a variable divider ratio, comparing the time indicated by the local clock signal with the time indicated by the synchronization signal to derive a time difference and using the time difference to vary the divider ratio from the ratio determined by any of the previously defined methods such that the average pulse rate of the divided local oscillator output over a predetermined interval of time is adjusted by an amount not greater than a predetermined rate of adjustment of the local clock signal so as to reduce 20 ths said difference over time, the divider ratio being restored to the ratio determined by any of the methods previously defined.

.The adjustment is achieved by setting the loca! clock pulse rate to a pulse rate slightly shorter or longer than its nominal pulse rate. This may be done on a continuous basis or intermittently for a short period at regular intervals until the de- 25 sired degree of synchronization is achieved, It may be continued until the whole difference is nominally eliminated or until a set portion, e.g. 75% of the tolerance S: limit is eliminated.

In the case of the energy management system where there is a set tolerance on the accuracy of the metering periods t;,en the rate of adjustment must also be 30 kept within this limit, so the nominal accuracy of the EMT clock sets the lower limit of the rate of adjustment and the allowable tolerance on metering periods sets the upper limit.

The synchronization signal may be transmitted over a telephone line.

According to another aspect of the invention there is provided a clock signal -Snerator generating a composite clock signal which approximates a standard clock signal within a given tolerance limit over a period of time, the generator comprising a source of clock signals applied to controllable divider means, the divider means being capable of producing at least one slow clock signal having a clock rate slightly slower than the standard clock signal by a first difference frequency, the divider means also being capabale of producing at least one fast clock signal having a clock rate slightly faster than the standard clock signal by a second difference frequency and control means causing the fast clock signal to be applied to the output of the generator for a first portion of the tinie period approximately determined by a ratio of the first difference frequency divided by a divisor being the sum of the first and second difference frequencies, and applying the slow clock signal to the output of the generator for the remainder of the time period, the control means causing the composite signal to be applied to the output of the generator in successive periods of time.

Preferably, the divider ratio is restored when only a position of said difference is eliminated.

Preferably, if the differnce is greater than a predetermined magnitude the4 line difference is eliminated immediately.

Brief Description of Drawings In order that the invention may be readily carried into effect, embodiments 20 thereof will now be described in relation to the drawings, in which: Fig. 1 shows a block diagram of a first embodiment of the present invention for deriving a more accurate time of day from a less than accurate source of synchronization.

Fig. 2 shows a block diagram of a second embodiment of the present in- 25 vention for achieving a desired degree of synchronization between a local clock and a clock synchronization signal.

Best Mode of Carrying out the Invention Referring to Fig. 1, the arrangement comprises a local clock 1 comprising crystal unit 2, a selectable divisor in the form of a circulating register 3 whose length is varied by gates 4, 5 and 6 tapping some of the register's register elemerits. Periodic pulses from register 3 drive counter 7 whose content is the time of day. Pulses from register 3 are also coupled into microprocessor 8 which is programmed to select the desired register length via gates 4, 5 and 6. By periodically switching between gates 4, 5 and 6 at a rate determined by a ratio register ia 9, the microprocessor can alternately select pulse rates which are slightly faster

S*

5 ii i 4.1 and slightly slower than the required pulse rate. By selecting the period of time at each rate, a more accurate long-term pulse rate can be produced .9 .9 9 0 0 9 9 9**9 9* 99 9 9 9 9. 9 9* 99 0 999* 9 9* 99&9 9* 90 9 9 9 9 99 9 99 9 9 WO 90/07147 PCT/A U89/00492 than could be produced by selecting just one of the available gate taps on register 3.

Should the frequency of crystal unit 2 drift over time due to, for example, ageing, the contents of ratio register 9 may be varied by control means to cancel the drift. Such an arrangement will now be described in relation to Fig. 2 which shows an arrangement similar to that described in relation to Fig.. 1 except for the inclusion of a comparator means 10 arranged to compare a clock synchronization signal transmitted from a remote control station (not shown) on link 11. The difference between the local clock and the clock synchronization signal derived in comparator means is stored in register 8 and read by microprocessor 8. The length of register 3 is thereby varied by gates 4, 5 and 6. The gate 5 sets the nominal length, then a shorter circulating period can be achieved by switching gates 5 and 6 off and switching on gate 4. Similarly, a longer period can be achieved by switching gates 4 and 5 off and switching gate 6 on. The periodic pulses from register 3 drive counter 7 whose output is the time of day clock.

When a difference between the clock synchronization signal and the time of day clock is registered, microprocessor 8 can switch the register 3 to the longer or shorter mode, that is, gate 4 or gate 6 for a period sufficient to bring the clock within the desired degree of synchronism to reduce the error indicated in register 8. This may be done for a continuous period or at short intervals. When the difference between the clock synchronization signal and the time of day clock exceeds a predetermined value, microprocessor 8 sets the'local time of day at counter 7 to that of the incoming clock synchronization signal.

The time difference between the nominal period set by gate 5 and the shorter or longer periods set by gates 4 and 6 can be proportionally greater than the accuracy set by the control station authority if the intermittent correction mode is used.

I~ ;BC- WO 90/07147 PCT/AU89/00492 -6- If the difference is greater than a given amount, for example, due to a power failure or the start of daylight saving, then the microprocessor 8 can set the time of day clock counter 7 in synchronism with the clock synchronization signal in a single step.

While the present invention has been described with regard to many particulars, it is understood that equivalents may be readily substituted without departing from the scope of the invention.

~il

Claims (15)

1. A metLhd of producing a composite clock signal approximating a standard clock signal within a given tolerance limit over a period of time, the method comprising providing at least one slow clock signal having a clock rate slightly slower than the standard clock signal by a first dif- ference frequency and at least one fast clock signal having a clock rate slightly faster than the standard clock signal by a second difference fre- quency, and applying the fast clock signal as the composite clock signal for a first portion of the period of time approximately deterdmined by the ratio of the first difference frequency divided by a divisor being the sum of the first and second difference frequencies, ;nd applying the slow clock signal as the composite clock signal for the remainder of the time period, the method being repeated in successive time periods.

2. A method as claimed in claim 1 wherein the period of time is chosen so that the difference between the standard clock signal and the composite clock signal remains within the tolerance limit.

3. A method as claimed in claim 1 or claim 2 wherein the remainder of the time period and the first portion of' the time period are broken up into shorter mutually interleaved intervals.

4. A method as claimed in any one of claims 1 to 3 wherein the slow clock signal is produced by diviaing a supply clock signal by a first divi- sor and the fast clock signal is produced by dividing the supply clock sig- nal by a decond divisor. A clock signal generator generating a composite clock signal which approximates a standard clock signal within a given tolerance limit over a period of time, the generator comprising a source of clock signals applied to controllable divider means, the divider means being capable of producing at least one slow clock signal having a clock rate slightly slower than the standard clock signal by a first difference frequency, the divider means ,also being capable of producing at least one fast clock signal havitg a N. RECEIVED o 7 NV' 1990 PCT/AU a 9 /0 0 4 9 -8- clock rate slightly faster than the standard clock signal by a second dif- ference frequency and control means causing the fast clock signal to be ap- plied to the output nf the generator for a first portion of the time period approximately dete imined by the ratio of the first difference frequency di- vided by a divi -l being the sum of the first and second difference fre- quencies, and applying the slow clock signal to the output of the generator for the remainder of the time period, the control means causing the compos- ite signal to be applied to the output of the generator in successive peri- ods of time.

6. A method of producing a composite clock signal as claimed in any ore of claims 1 to 4, including a method of reducing the difference between the time indicated by a local clock signal derived from a local oscillator and the time indicated by a clock synchrolization signal, the method including dividing the local oscillator output in a divider having a variable divider ratio, comparing the time indicated by the local clock signal with the time indicated by the synchronization signal to derive a time difference and us- ing the time difference to vary the divider ratio from the ratio determined by the method of any one of claims 1 to 4 such that the average pulse rate of the divided local oscillator output over a predetermined interval of time is adjusted by an amount not greater than a predetermined rate of ad- justment of the local clock signal so as to reduce the said difference over time, the divider ratio being restored to the ratio determined by the method of any one of claims 1 to 4 when che said difference is substan- tially eliminated.

7. A method as claimed in claim 6, Including the step of comparing by the time indicated clock synchronization signal with the time of the local clock and calculating a time difference signal, the time difference signal being used to adjust said divided local oscillator output within a prede- termined range. iUBSTTUTE SWET L RECEIVED iV 199 PcTr/ a 0 0 4 9 2

8. A method as claimed in claim 6 or 7, wherein the method of any one of claims 1 to 4 is restored when only a portion of the time difference is eliminated.

9. A method ea claimed in any one of claims 6 to 8, wherein if said dif- ference is greater than a predetermined magnitude, the time difference is eliminated imnediately, A method as claimed in any one of claims 6 to 9, wherein said clock synchronization signal is transmitted from a remote source at regular or irregular intervals.

11. A method as claimed in any one of claims 6 to 10, wherein said local clock is incorporated in a terminal at a customer's premises, said terminal associated with an energy management terminal.

12. A method as claimed in claim 11 as dependent on claim 10, wherein said clock synchronization signal is transmitted from a remote control station associated with the energy management system.

13. A method as claimed in claim 12, wherein said synchronization signal is transmitted over a telephone line.

14. An arrangement for carrying out the method as claimed in any one of claim 6 to 13, comprising a pulse generator means for generating a first pulse train at a first predetermined rate, the said generator means being operatively associated with a selectable divisor means such that a second pulse train is produced therefrom, the value of said divisor being selected so that the rate of said second pulse train is adjusted within a predeter- mined range, said selectable division means comprises a pulse divider means operatively coupled to a, control means, said control means determining the rate of said second pulse train, the second pulse train constituting the divided local oscillator output. An arrangement as claimed in claim 14, wherein said control means is a microprocessor. I-SST ITU7T E SIMPT 1 Sm RECEIVED u N 190. 10 PCT/A 8 9 0 0 4 9 2

16. An arrangement as claimed in claim 15, including comparator means for comparing a clock synchronization signal with the time of the local clock and calculating the time difference signal, said time difference signal be- ing used to adjust said second pulse train within a predetermined range.

17. An arrangement substantially as herein described with reference to Figures 1 to 2 of the aLcompanying drawings.

18. An arrangement as claimed in any one of claims 14 to incorporated in a terminal at a consumer's premises, said terminal associated with an energy management system. 19, A method of adjusting the pu',se rate of a local clock, substantially as herein described with reference to Figures 1 or 2 of the accompanying drawings. LSBSTITUTE SHELZ