AU630900B2 - A telephone subset arrangement - Google Patents

Description

I i I OPI DATE 01/08/90 AOJP DATE 30/08/90 APPLN I D 45214 89

PCT

PCT NUMBER PCT/AU89/00493 INTERNATIONAL APPLICATION PUBLISHED UNDER THE PATENT COOPERATION TREATY (PCT) (51) International Patent Classification 4 Interna'onJ Pblic, ion ber: WO 90/07835 H04M 19/08 Al (43) inter t ial li tii ly 1990 (12.07.90) (21) International Application Number: PCT/AU89/00493 (81) Designated States: AU, US.

International Filing Date: 17 November 1989 (17.11.89) Published With internationot search report.

Priority data: PJ 2096 23 December 1988 (23.12.88) AU (71) Applicant (for AU only):- STA-NDA-RD-TELEPHONES

S

AND-GA-BLES-PTY-LIMITED [AU/AU]; 252-280 Bo- 7 tany Road, Alexandria, NSW 2015 (72) Inve~tor; and Inventor/Applicant (for US only) FOX, Ronald, Christo-" pher, Shaw [AU/AU]; Flat 4/89 Gilderthorpe Avenue, Randwick, NSW 2031 0 (74) Agent: O'CONNOR, Patent Department, Standard Telephones and Cables Pty. Limited, 252-280 Botany Road, Alexandria, NSW 2015 (AU).

(54) Title: A TEILEPHONE SUBSET ARRANGEMENT (57) Abstract A telephone circuit subset arrangement in which the base/emitter junction of a switching transistor (TRI) coupling an internal battery (BI) to the dialler chip's power terminals (VDD, VSS) is shunted by hook-switch signal contacts (HS) when the subset is brought into the off-hook mode, thereby turning the switching transistor off and disconnecting the battery, The circuit is so arranged that upon the switching transistor turning off, three auxiliary switching transistors (TR3, TR4 and TR5) turn on and operate the subset's line switch to connect line current to the dialler chip's power terminals A network of resistors (Rl, R2 and R3) associated with the switching transistor (TRI) ensure that on the one hand sufficient current is available to turn on the auxiliary switching transistors, and on the other hand limit the current to a magnitude which does not cause excessive battery discharge while the subset is off-hook.

A Telephone Subset Arrangement Technical Field This invention relates to telephone subsets and in particular to low voltage telephone subsets incorporation a dialler chip and an electronic lin switch.

The electronic line switch fulfils a number of functions including the hookswitch function, that is, the line switch acts as a hook-switch when a hook-switch control signal is selectively applied to the line switch, a hook-switch control signal being generated when the user brings the subset into the off-hook mode. This control signal may be provided by a ten number repetory tone/pulse dialler chip or a microprocessor.

In a subset provided with a dialler chip and a conventional mechanical hookswitch, the dialler chip is provided with its operating power from current derived from the exchange battery and drawn over the exchange line through the hookswitch. As soon as the subset is brought into the off-hook mode the hook-svVitch contacts operate and adequate operatinq voltage is extended to the dialler chip which is then able to function.

In the case of a subset provided with an electronic line switch, however, when such a subset is initially connected to the exchange line, or reconnected after subsequently being un-plugged, the dialler chip is without power because its 20 power source is cut off by the line switch which it controls. Consequently the dialler chip cannot function and the line switch cannot be signalled.

Background Art A known method by which the dialler chip of such a subset is provided with 25power is described in the specification of Australian Patent No. 606397. This specification disclosed an arrangement wherein a storage capacitor provides a current source for the dialler chip. The arrangement is such that initially, with the capacitor discharged, upon connexion of the subset's line terminals to the exchange line, current flows via c circuit to cause a i* i WO 90/07835 PCT/AU89/00493 2 first transistor to switch on thereby rendering the subset's electronic line switch conducting. The capacitor is charged via the operated line switch until the voltage level across the capacitor reaches the minimum operation voltage of the dialler chip. A control circuit then switches off the first transistor and hence the line switch.

This known arrangement, however, is not satisfactory for providing power to the dialler chip in a low voltage phone, and particularly low voltage phones in parallel, because of the low voltage at the phone line terminals.

Another known arrangement for providing power to the dialler chip is a bleed circuit around the line switch to bleed sufficient current from the exchange line in the on-hook mode. With low voltage subsets, particularly parallel low voltage subsets, the bleed cu.rrent required to power the dialler chips would exceed the allowable on-hook current allowed by some telecommunication authorities.

A solution to the problem of providing power to the dialler chip in, the on-hook mode is to provide the power with a dry cell. An undesirable feature of this solution, however, is the necessity to replace the cell when its capacity falls due to discharge. If the discharge is kept to a minirum, the cell life will be greatly extended.

It is therefore an object of the present invention to provide a dry cell switching arrangement for disconnecting a dry cell providing power to the dialler chip of a subset when the subset is in the off-hook mode.

Summary of the Invention The inventive concept of the present invention is to provide a switching arrangement to disconnect a dry cell providing power to the subset's dialler chip during the "off-hook" mode, the arrangement using minimal power.

According to the invention there is provided a telephone subset circult arrangement comprising first and second line terminal means for reripspectively connecting to conductors of an exchange line, a transmission circuit means coupled to said line terminal means, a line switch means whose line switching element comprises a conductive path of a first controllable semiconductor switch means having a control element coupled to a first output of a control means operatively coupled to the transmission circuit means, said line switching element being serially in the subset circuit's loop current circuit, said control means having power terminal means fo" applying energizing power to enable said control means, wherein energy from a battery means associated with said subset is connected to said power terminal means via a conductive path of a second controllable semiconductor switch means whe, 'he subset is in the onhook mode, and wherein when the subset is in tne off-hook mode, hook-switch means render said second controllable semiconductor switch means nonconducting thereby disconnecting said battery means from said power terminal means, and rendering a third controllable semiconductor switch means conducting, said third controllable semiconductor means applying signal means to hookswitch signal input means of said control means, said control means thereupon producing a line switch signal to render said line switching element conducting, said power terminal means being thereby coupled via the transmission circuit means to said first and second line terminal means.

In order that the invention can be readily understood, an embodiment tl ereof will now be described in relation to the figure of the drawing.

Referring to the drawing there is shown a schematic circuit of part of a low voltage telephone subset. The circuit comprises a ten number repetory tone/pulse dialler chip 1 having a dial pulse output DP, a power terminal VDD, a common 25 voltage rail terminal VSS and a hook switch input HS; an electronic line switch 2 S.. serially connected between the L1 line terminal (not shown) and the transmission circuit and the ine switch control transistor TR6; a lithium 3V dry cell B1; a hook switch signal contact HS; a storage capacitor C1 connected across VDD and

*V.

USS; the positive terminal of battery B1 is connected to the emitter element of 30 transistor TRI whose base element is connected to the common voltage rail via three serially connected resistors R1, R2 and R3; the collector element of a PNP transistor TR1 is connected to the base element of an NPN transistor TR2 whose emitter is connected to VDD of dialler chip 1; the junction of resistor R2 and R3 is connected to the base element of an NPN transistor TR3 whose collector is connected to the base element of a PNP transistor TR4 via resistor R5; the col- 'i 7 r II I 1 e lector of PNP transistor TR4 is connected to the base element of an NPN transistor via resistor R6; the collector of transistor TR5 is connected to NIS of dialler chip 1; the emitter and base of transistor TR4 are coupled via resistor ,Z4; the emitter and base of transistor of transistor TR5 are coupled via resistor R7, signal contact HS is connected across the positive terminal of battery B1 and the junction of resistors R1 and R2; VSS is coupled to the L2 terminal (not shown) of the subset.

In operation, in the on-hook mode, the hook switch signal contacts HS are open and transistor TR1 is turned on by current provided by battery B1 through its emitter/base junction and resistors R1, R2, R3. Transistor TR2 is turned on by current from battery B1 via the emitter/collector junction of transistor TR2. The collector/emitter junction of transistor TR2 connects the positive terminal of battery B1 to the VDD terminal of dialler chip 1 to maintain the chip's memory. In this condition the dialler chip typically draws 1.0 UA. Storage capacitor C1 is quickly charged by current drawn from battery B1 via the collector/emitter junction of transistor TR2. The charge on C1 maintains the chip's memory during impulse dialling.

When the subset is placed in the off-hook mode, signal contacts HS close and effectively shunt transistor TR1 and resistor R1. Transistor TR1 and TR2 turn off.

20 The current through resistors R2 and R3 increases causing transistor TR3 to now turn on, which in turn causes transistors TR4 and TR5 to turn on. When transistor i: TR5 turns on terminal HS of dialler chip 1 is rendered LOW, this causes terminal DP to go HIGH. Terminal DP is connected to the base element of line switch control transistor TR6 which is turned on by the changed condition on terminal DP.

25 Transistor TR6 renders line switch 2 conducting and dialler chip 1 is now powered by current from the exchange line via the line switch and the transmission circuit.

The values of resistors R2 and R3 must be such that on the one hand sufficient current must be available to turn on transistor TR3, and on the other hand limit the current to a magnitude which does not cause excessive battery discharge.

30 Typically, this current should be approximately 1.0 UA.

Resistor R4 ensures that transistor TR4 is held off while transistor TR3 is off.

Resistor R7 ensures that transistor TR5 is held off while transistor TR4 is off.

While the present invention has been described with regard to many particulars it is understood that equivalents may be readily substituted without departing from the scope of the invention, -I

Claims (6)

1. A telephone subset circuit arrangernent comprising first and second line terminal means for respectively connecting to conductors of an exchange line, a transmission circuit means coupled to said line terminal means, a line switch means whose line switching element comprises a concuctive pEth of a first con- trollable semiconductor switch means having a control element coupled to a first output of a control means operatively coupled to the transmission circuit means, said line switching element being serially in the subset circuit's loop current cir- cuit, said control means having power terminal means for applying energizing power to enable said control means, wherein energy from a battery means asso- ciated with said subset is connected to said power terminal means via a conductive path of a second controllable semiconductor switch means when the subset is in the on-hook mode, and wherein when the subset is in the off-hook mode, hook-switch means render said second controllable semiconductor switch means non-conducting thereby disconnecting said battery means from said power terminal means, and rendering a third controllable semiconductor switch means conducting, said third controllable semiconductor means applying signal means to hook-switch signal input means of said control means, said control means thereupon producing a line switch signal to render said line switching element S 20 conducting, said power terminal means being thereby coupled via the trans- mission circuit means to said first and second li-e terminal means.

2. An arrangement as claimed in claim 1, wherein said second controllable semiconductor switch means comprises a complementary configuration of a first and a second transistor, the conductive path of the said first transistor connecting 25 energy from said battery means to said power terminal means upon being ren- dered conducting by said second transistor by current flowing from said battery means connected across a circuit which includes a t I r WO 90/07835 PCT/AU89/00493 junction of said second transistor and a resistance means in series there- with.

3. An arrangement as claimed in claim 2, wherein when the said subset is in the off-hook mode said hook switch means short circuits said junction of said second transistor and a predetermined part of the resistance means, whereby said second semiconductor switching means is rendered non- conducting and, moreover, the current in said circuit increases by a prede- termined magnitude to render said third semiconductor switch means conducting.

4. An arrangement as claimed in claim 3, wherein said resistance means comprises at least a first resistance, a second resistance and a third re- sistance in series, the distal end of the first resistance being connected to the control element of said second transistor and the distal end of said third resistance being connected to a pole of said battery means, the junc- tion of the first resistor and the second resistor being connected to a terminal of said hook-switch means, and the junction of the second resist- ance and the third resistance being coupled to the control element of the third controllable semiconductor switch means.

An arrangement as claimed in any one of the preceding claims, wherein a capacitive storage means is connected across said power terminal means.

6. A telephone subset circuit arrangement substantially as herein de- scribed with reference to the figure of the drawing.