AU620127B2 - A real-time signal processing circuit - Google Patents

Description

I r OPI DATE 05/02/90 APPLN. ID 39643 I 89 AOJP DATE 22 /03/a P N E CT 7 89/00294 INTERNATIONAL APPLICATION PUBLISHED NDER TE PATENT COOPERATION TREATY (PCT) (51) International Patent Classification 4 (11) Intrnational Publication Number: WO 90/00849 H4N 967 A (43) International Publication Date: 25 January 1990 (25.01.90) (21) International Application Number: PCT/AU89/00294 (81) Designated States: AT (European patent), AU, BE (European patent), CH (European patent), DE (European patent), (22) International Filing Date: 7 July 1989 (07.07.89) FI, FR (European patent), GB (European patent), IT (European patent), JP, KR, LU (European patent), NL (European patent), SE (European patent), US.

Priority data: PI 9209/88 8 July 1988 (08.07.88) AU Published With international search report.

(71) Applicant (for all designated States except US): COMMON- WEALTH SCIENTIFIC AND INDUSTRIAL RE- SEARCH ORGANISATION [AU/AU]; Limestone Avenue, Campbell, ACT 2601 (AU).

(72) Inventors; and Inventors/Applicants (for US only) WARD, John, Victor [AU/AU]; 58 Andrew Crescent, Croydon, VIC 3136 MCNAMEE, Robert, Charles [AU/AU]; 16 Griffiths Road, Upwey, VIC 3158 (AU).

(74) Agents: WEBBER, David, Brian et al.; Davies Collison, I Little Collins Street, Melbourne, VIC 3000 (AU).

(54)Title: A REAL-TIME SIGNAL PROCESSING CIRCUIT (57) Abstract A real-time signal processing circuit 70, 80, 150) which includes means (12, 14, 16, 18, 20) for receiving input signals generated by a scanning device and means (10) for obtaining a synchronising signal and a first blanking signal from the receiving means (12, 14, 16, 18, 20). The circuit has an input stage and a processing stage which selectively generates colour output signals from the input signals, each colour output signal being derived from one or a combination of the input signals. The circuit also has an output stage for including a blanking output signal in the colour output signals in response to the first blanking signal and outputting the colour signals and the synchronising signal.

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WO 90/00849 PCY/AU89/00294 "A REAL-TIME SIGNAL PROCESSING CIRCUIT" The present invention relates to a real-time signal processing circuit which is particularly, but not exclusively, adapted for processing signalls received from a scanning device so as to produce signals for driving a colour monitor.

A scanning device, such as a scanning electron microscope or a television camera, on scanning an object produces a number of signals which relate to characteristics of the object, together with synchronising and blanking signals. The synchronising signals are issued at the beginning of each line scanned and the blanking signals issue at the end of each line scanned. Vertical synchronising and blanking signals issue at the beginning and end, respectively, of each field scanned. The scan which the scanning device performs is known as a raster L p 1- I; WO 90/00849 PCr/AU89/00294' scan. In particular, with respect to a scanning electron microscope, signals can be generated by detectors relating to the detection of secondary electrons generated from the scanned object and backscattered electrons both pursuant to the incidence of a scanning beam of the electron microscope on the surface of the object. As discussed in the specification of Australian Patent No. 549,193 it is desirable to provide means which processes, in real-time, the signals produced by the detectors of a scanning electron microscope so that the processed signals may be used in directly driving a colour monitor. Thus characteristics of the scanned object at a particular location thereon can be rapidly determined using the display produced on the colour monitor by the processed signals, which are representative of the characteristics. Also it is desirable to provide real-time processing means which enables the signals used to drive the colour I monitor to each be derived from one or more of the signals generated by a scanning device.

In accordance with the present invention there is provided a real-time signal processing circuit comprising: means for receiving input signals generated by a scanning device; means for obtaining a synchronising signal and a first blanking signal from said receiving means; means for olctivoly generating colour 1 output signals from said input signals, each colour output signal being derived from one or a combination of said input signals; and means for including a blanking output signal i Ii

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\l 1 1 1 1 a% 1 1 1 1 1 1 1 1 1 11 1 i i 1 1 1 WO 90/00849 PCT/AU89/00294 in said colour output signals in response to said first blanking signal and outputting said colour output signals and said synchronising signal.

Preferably the said circuit includes means for respectively adjusting the level of said colour output signals.

Preferably said adjusting means is adapted to alter the DC voltage level of said colour output signals. Preferably said adjusting means is also adapted to separately adjust a gain applied to said colour output signals.

Preferably said input signals include characterising signals which represent respective characteristics of a scanned subject and each colour output signal includes a selected percentage of said characterising signals and also preferably said inverted characterising signals.

Preferably said generating means includes means for inverting said characterising signals and varying the gain of the characterising signals and of the inverted characterising signals.

Preferably said generatinc' means is adapted such that said selected percentage is variable with respect to each colour output signal.

Preferably said obtaining means includes sync separator means for generating said synchronising signal from said input signals and blanking generator means for generating said firt-t blanking signal from said synchronising signal.

14C- VS/ WO 90/00849: PCT/AU89/00294' predetermined period of time which is equivalent to the period of time which the characterising signals are delayed by the signal processing circuit before being outputted in a representative form as the colour output signals.

The obtajing means may also include means for delaying the first blanking signal by a second predetermined period of time which is equivalent to the period of time which the characterising signals are delayed before being inputted in a representative form as the colour output signals to said blanking signal including means.

Preferably said blanking output signal is said -ir gt- blanking signal.

Preferably said scanning device is a scanning electron microscope.

Preferably said colour output signals and said synchronising signals are outputted to a colour monitor which includes RGB inputs to which the colour output signals are applied, respectively.

Preferred embodiments of the present invention will now be described, by way of example only, with reference to the accompanying drawings, in which: Figure 1 is a block diagram of a first preferred embodiment of a signal processing circuit; Si i iW i i 3 90/00849 PCT/AU89/00294 Figure 2 is preferred embodiment Figure 3 is preferred embodiment Figure 4 is generator circuit of Figure 5 is preferred embodiment a block diagram of a second of a signal processing circuit; a block diagram of a third of a signal processing circuit; a block diagram of a sync the processing circuit; and a block diagram of a fourth of a signal processing circuit.

A real-time signal processing circuit 2, as shown in Figure 1, comprises an input stage 4, a processing stage 6, an output stage 8 and a synchronising and blanking processing stage 10. At the input stage 4 provision is made for receiving up to three different characterising signals on input lines 12, 14 and 16 and for receiving a signal from which a synchronising signal may be extracted nn a synchronising input line 18 and a blanking signal on a blanking input line 20. The signals received on the input lines 12, 14, 16, 18 and 20 are to be obtained from the outputs of a scanning device pursuant to the scanning of a subject thereby. The characterising signals received on the input lines 12, 14 and 16 would each represent characteristics of the scanned subject. On being inputted on the lines 12, 14 and 16 the signals are buffered by respective unity gain amplifiers 22 and are outputted so as to appear across two respective low impedance potentiometers 24 and 26. Each amplifier 22 has sufficient output power so as to drive!a respective pair of potentiometers 24 and 26, which are connected in parallel and each has one terminal connected to a respective output of an amplifier 22 whilst another terminal is connected to ground. Tl,'e wipers of the

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WO 90/00849 pCr/AU89/00294 6 potentiometers 24 and 26 are each connected to the input of an amplifier, the wiper oZ one potentiometer 24 of each pair being connected to a respective non-inverting amplifier 28 and the wiper of the other potentiometer 26 of the pair being connected to a respective inverting amplifier 30. The output of each amplifier 28 and 30 is connected to a respective input 32 of a switching circuit 34. The potentiometers 24 and 26 may be adjusted as desired and are used to control the voltage levels of the signals received on the input lines 12, 14 and 16 before being inputted to the amplifiers 28 and The amplifiers 28 and 30 amplify the attenuated signals received from the potentiometers 24 and 26 according to gains which are preset as desired. The potentiometers 24 and 26 may be adjusted independently with respect to one another, and similarly, the gains of the amplifiers 28 and 30 may be adjusted independently with respect to one another. Hence, the input stage 4 provides inverted and non-inverted forms of the signals inputted on the lines 12, 14 and 16, the voltage levels of which are adjusted as desired, at respective inputs 32 of the switching circuit 34.

The switching circuit 34 has three sets 36 of output lines which terminate at a respective i summing node 38. Each set 36 comprises three output lines 39. The three summing nodes 38 are each connected to an input of a unity gain amplifier The processing stage 6 is configured so as to enable a user of the processing circuit 2 to output any one of the signals received on inputs 32 to a selected output line 39. Each node 38 may therefore have one, i i1 WO 90/00849 PCT/AU89/00294 7 two or three of the signals received on the inputs 32 incident thereon, and any signals received at summing node 38 are added on being inputted to the respective i amplifier 40. For example, the signal received on the input line 12 may be outputted unchanged on one output line 39 to a summing node 38, an inverted form of the signal received on line 14 may be outputted to another summing node 38 and the signal received on line 14 and the signal received on line 16 may both j be outputted to a third summing node 38 so as to combine the signals. Alternatively, the three signals received on the lines 12, 14 and 16 may be added together at one summing node 38, the inverted forms of the signals may be added together at another summing node 38 and one of the signals may be i outputted to the third summing node 38. The switching circuit 34 may be constructed in a number of ways, one of which would be to employ an array of multiplexers which enable the input lines 32 to be selectively switched to the sets 36 of output lines 39 as described above. Connected to each summing node 38 is also the output of a respective saturation control circuit 42. The saturation control circuits 42 are configured so as to apply a DC offset voltage, as required, to the summing node 38 so as to adjust the DC level of the signal inputted to the amplifiers As the signals applied to the inputs of the three amplifiers 40 are eventually used to drive the RGB inputs of a colour monitor, the saturation control circuit 42 provide the user of the circuit 2 with a means for adjusting the saturation intensity of each primary colour displayed on the monitor, the intensity of the colours being determined by the three signals applied to the RGB inputs.

'rU K, WO 90/00849 PC/AU89/00294 8 The outputs of the amplifiers 40 are each connected to an output line 43, 44 and 46, respectively, via a blanking switch 48. The output lines 43, 44 and 46 are connected, in use, to the Red, Green, and Blue inputs, respectively, of an RGB colour monitor. The blanking switches 48 each apply a blanking signal to the signals outputted from the amplifiers 40 by placing the output lines 43, 44 and 46 connected thereto in a low state for a predetermined period of time in response to a further blanking signal received on the inputs 50 of the blanking switches 48. The further blanking signal is derived from the blanking signal inputted on the blanking input line 20. The signal received on the line 20 is first inputted to a pulse shaping circuit 52 which removes unwanted transients and improves distinction between the high and low s;tates of the signal inputted thereto. The output of the pulse shaping circuit 52 is then applied to a delay circuit 54, which delays the signal received on the line by a predetermined period of time. The predetermined period of time corresponds to the delay incurred by the signals received on the input lines 12, 14 and 16 in being processed by the input and processing stages 4 and 6 before being outputted to the blanking switches 48 in a representative form, according to the processing affected by the input and processing stages 4 and 6. This ensures that the blanking 4signal received at the inputs 50 remains in synchronism with the characterising signals after they have been processed by the input stage 4, the processing stage 6 and the output amplifiers 40 and inputted to the switches 48, and allows the characterising signals to be directly outputted I> WO 90/00849 PCT/AU89/00294 in a representative form as colour output signals on the output lines 43, 44 and 46 so as to drive the RGB inputs of a colour monitor, thereby enabling the processing circuit 2 to perform as a real-time processor. Similarly, the synchronising signal received on the synchronising input 18 is delayed by a second predetermined period of time by a second delay circuit 56 before being outputted to a synchronising input of the colour monitor on a synchronising output line 58. This ensures that the synchronising signal remains in synchronism with the characterising signals outputted in a representative form on output lines 43, 44 and 46. The second predetermined period of time by which the synchronising signal is delayed corresponds to the delay which is incurred by the characterising signals received on the input 12, 14 and 16 in being processed by the input, processing and output stages 4, 6 and 8 before being outputted as the representative colour output signals. As the synchronising signal received on the synchronising input line 18 may also include video information, the signal is applied first to a sync separator circuit which removes the video information and outputs only a synchronising signal to the second delay circuit 56.

The signal processing circuit 2 is Sparticularly advantageous for use with a scanning electron microscope. In one mode of use one input line 12 is connected to the output of a broad energy band electron detector and another input line 14 is connected to a backscattered electron detector. The broad energy band detector detects predominantly WO 90/00849 PCT/AU89/00294 secondary electrons and backscattered electrons emitted from a scanned subject. The input and output stages 4 and 6 are then set so that the broad energy band electron signal is applied directly to the Red output line 43, the backscattered electron signal is applied directly to the Green output line 44 and a signal produced by subtracting the backscattered electron signal from the broad energy band electron signal is outputted on the Blue output line 46. This provides the user viewing the colour monitor with a display which enables the user to instantaneously differentiate between the areas of secondary and backscattered electron emission from a scanned subject. Distinguishing between the areas is facilitated by applying the difference signal, which is representative of secondary electron emission from the scanned subject, to the Blue input of the colour monitor. The display may then be adjusted as desired by adjusting the saturation control circuits 42 so as to alter the dominance of particular colours or altering the potentiometers 24 and 26 or amplifiers 28 and 30 of the input stage 4 so as to adjust the level of the inputted signals. This enables particular characteristics or elements of the scanned subject, as represented by respective colours, to be highlighted on the display. Another mode of use would involve connecting one of the input lines 12 to i a detector of the microscope which detects electrons in a broad energy band, a second input line 14 to a detector which detects backscattered electrons and a third input line 16 to a detector which detects electrons in a high energy band, which falls within the broad energy band, and then passing the signals directly to the Red, Green and Blue output lines 43, f 1 1 WO 90/00849 PCT/AU89/00294 44, and 46, respectively.

A real-time signal processing circuit 70, as shown in Figure 2, performs the same function as the previously described processing circuit 2 but enables more flexibility with respect to determining the contribution of a signal inputted on one of the input lines 12, 14 or 16 in forming a colour output signal. The switching circuit 34 of the processing stage 6 is replaced by a potentiometer array 72 and the potentiometers 24 and 26 of the input stage 4 are removed so that each output of the input amplifiers 22 is connected directly to the respective non-inverting amplifier 28 and inverting amplifier The outputs 32 of the amplifiers 28 and 30 are each connected to three low impedance potentiometers I 74, 76 and 78. The potentiometers 74, 76 and 78-are connected in parallel between each respective output 32 and ground. The wipers of the first potentiometers 74 are connected via resistors to one summing node 38, and similiarly, the wipers of the second potentiometers 76 are connected to a second summing node 38 and the wipers of the third potentiometers 78 are connected to a third summing node 38. The signals on each of the outputs 32 can therefore be applied to a summing node 38 and the contribution which one of the signals makes to forming a respective colour output signal is determined by the position of the wiper of the potentiometer 74, 76 or 78 connected to the node 38 and the output line 32 of the signal. Thus, the percentage contribution of the signals on the outputs 32 can be varied for each summing node 38. This is distinct from the processing circuit 2 of Figure 1 WO 90/00849 PCT/AU89/00294 12 where the outputs 32 can only be selectively switched to the summing nodes 38.

The processing circuit 70 also does not require the use of the delay circuits 56 and 54. The delay signals experience in passing through the input, processing and output stages 4, 6 and 8 is reduced to approximately 20ns by using high frequency, high slew rate operational amplifiers for each of the amplifiers 22, 28, 30 and 40 in the circuit 70. The input buffer amplifiers 22 are LM733H amplif.iers, the amplifiers 28 and 30 connected to the potentiometer array 72 and the output amplifiers 40 are LH0032 amplifiers The blanking switches 48 are 74HC4066 cmos analog switches. The delay induced in the colour output signals with respect to the synchronising signal on line 58 and the blanking signal on the input 50 produces an offset in the F picture generated on the RGB monitor, but the offset is virtually unnoticeable and does not seriously degrade the quality of the picture.

A further real-time signal processing circuit 80, as shown in Figure 3, performs essentially the same function as and has similar components to the previously described signal processing circuits 2 and 70, however, the circuit includes a potentiometer array 82 having a reduced number of potentiometers, and derives the synchronising output signal and the blanking signal inputted to the switches 48 in a different mannex. I The circuit 80 also includes means for monitoring and adjusting the signal level of the output signals on the output lines 43, 44 and 46.

''i s 1 l I 'ii WO 90/00849 PCI/AU89/00294 13 The number of potentiometers 74, 76 and 78 employed in the array 82 is half the number of potentiometers 74, 76 and 78 employed in the array 72 j illustrated in Figure 2. As a user obtains minimal advantage from applying an inverted version of one of the input signals together with a non-inverted version of the same input signal to a summing node 38, a single potentiometer 74, 76 or 78 is provided to couple a respective input signal to a respective summing node 38. A switch 94, 96 or 98 is included to selectively connect the potentiometer 74, 76, or 78 to the output of the respective non-inverting amplifier 28 or the respective inverting amplifier 30 associated with the input signal. The first potentiometers 74 connected to the first summing node 38 all have respective first switches 94 connected to a first terminal thereof and the other terminal of the potentiometers 74 is connected to ground. The first switches 94 have two switching contacts connected respectively to the outputs of respective non-inverting and inverting amplifiers 28 and 30 and the first terminals of the potentiometers 74 may be switched between the contacts. Similarly, the second and third potentiometers 76 and 78 are connected to respective second and third switches 96 and 98 which each have two switching contacts connected respectively to respective non-inverting and inverting amplifiers 28 and 30, as shown in Figure 3. Thus if an inverted version of the first input signal applied to the first input line 12 is to be passed to the second summing node 38, the second switch 96 associated with the first input line 12 is switched so as to connect Y. A real-time signal processing circuit 70, 80, 150) which includes means (12, 14, 16, 18, 20) for receiving input signals generated by a scanning device and means (10) for obtaining a synchronising signal and a first blanking signal from the receiving means (12, 14, 16, 18, 20). The circuit has an input stage and a processing stage,(6) which selectively generates colour output signals from the input signals, each colour output signal being derived from one or a combination of the input signals. The circuit also has an output stage for including a blanking output signal in the colour output signals in response to the first blanking signal and outputting the colour signals and the synchronising signal, 7 1 WO 90/00849 PCT/AU89/00294" i 14 the respective second potentiometer 76 to the output i of the inverting amplifier 30 which receives the first input signal. The wiper of the second potentiometer 76 may then be adjusted to select the level of the inverted input signal which is to be applied to the second summing node 38.

The signal processing circuit 80 does not require a blanking input on line 20 or an externally derived synchronising input on line 18 in order to derive the synchronising output signal and the blanking signal applied to the blanking switches 48.

This is particularly advantageous as most scanning devices, such as scanning electron microscopes, do not provide easily accessible blanking and synchronising outputs on the housing of the devices.

A blanking input signal, in particular, normally has to be obtained by dismantling the scanning device and locating an appropriate contact node in the electrical hardware of the device.

In the signal processing circuit 80 the input line 18 of the sync separator is connected to the output of the buffer amplifier 22 connected to the first input line 12. The sync separator 60 of the processing circuit 80 is configured to remove the video information from a composite video signal received on input line 18 and retain only the synchronising signal included in the composite video signal. The synchronising signal is then outputted on the synchronising output line 58. All that is required is to ensure a composite video signal is applied to the first input line 12.

1 1 1 1 1 1 1 11 1 1 1 1 c t WO 90/008 49 PCT/AU89/00294 The blanking signal to be applied to the inputs 50 of the blanking switches 48 is generated by a sync generator circuit 100 connected between the synchronising output line 58 and the inputs 50. The i generator circuit i00, as shown in Figure 4, includes a SAA043 universal sync generator chip 110, marketed by Philips Industries Ltd, an oscillator 112 and a Varactor diode 114. The synchronising signal outputted on line 58 by the sync separator 60 is Sinputted to the chip 110 at an external composite sync input 116 of the chip 110. In response to the synchronising signal the chip 110 adjusts the level of a DC signal outputted on a phase detector output 118 of the chip 110. The DC signal is applied to the Varactor diode 114, which in turn adjusts the level of a DC signal applied to a timing input 120 of the oscillator 112. The oscillator 112 has an output line 122 which is connected to an oscillator input 124 of the chip 110. The frequency of the signal outputted on the oscillator output 122 is determined by the level of the ignal inputted to the timing input 120. The frequency of the outputted signal governs the timing of the chip 110 and consequently governs the timing of the blanking signal outputted on a composite blanking output 126 of the chip 110.

The blanking output 126 is connected to the input of the blanking switches 48. The oscillator 112 is therefore locked to the synchronising signal inputted on line 58 and, accordingly, the timing for generation of appropriate vertical and horizontal blanking signals on the blanking output 126 is determined on the basis of the synchronising signal.

Preferably the oscillator 112 is locked to the frequency of the horizontal synchronising pulses of the synchronising signal.

iy' *Q "N I L k WO 90/00849 pCT/AU89/00294I 16 The chip 110 is adapted to monitor and count the vertical and horizontal synchronising pulses received on the input 116 to determine the type of blanking pulses to be placed on the blanking output 126. By counting these synchronising pulses and monitoring the period therebetween the chip 110 is able to determine whether the synchronising pulses relate to an odd or even field of a raster scan and adjust the blanking pulses outputted accordingly.

The signal processing circuit 80 further includes three monitoring units 130 which are connected respectively to the output lines 43, 44 and 46. The monitoring units 130 monitor the level of the output signals on the lines 43, 44, and 46 and provide a display which is representative of the l levels of each signal to a user. The amplifiers connected between the summing nodes 38 and the blanking switches 48 are provided with adjustable gains so that a user may view the display, or displays, and adjust the levels of the output signals by adjusting the gain of the respective output amplifier 40. It is particularly desirable to ensure the level of each output signal is maintained below a predetermined threshold level when the output lines 43, 44 and 46 are connected to the RGB inputs of a PAL encoder. If the level of an output signal i| exceeds the threshold level the colour of the picture produced by the output of the encoder will be distorted.

i-C blanking signal from said synchronising signal.

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I WO! 4 )0/00849 PCT/AU89/00294 17 A fourth real-time signal processing circuit 150, as shown in Figure 5, is the same as the third signal processing circuit 80 described above except the fourth circuit 150 includes a different potentiometer array 152. The array 152 does not require the use of the switches 94, 96 and 98 as the potentiometers 74, 76 and 78 are centre-tapped potentiometers, ie the centre of the resistor of each potentiometer 74, 76, and 78 is connected to ground.

The outputs of each pair of non-inverting and inverting amplifiers 28 and 30 have three respective potentiometers 74, 76 and 78 connected therebetween.

The wipers of each potentiometer 74, 76, and 78 are therefore able to move betweeen a positive and negative range of levels of the signal inputted to the respective input line 12, 14 or 16 associated therewith.

The input stages 4 of the second, third and fourth processing circuits 70, 80, and 150 have been described as including a non-inverting buffer amplifier 22 for each input line 12, 14 and 16 having its output connected to respective non-inverting and inverting amplifiers 28 and 30, which provide non-inverted and inverted versions of the respective input signal. An alternative approach is to configure the buffer amplifiers 22 so they provide an inverted and a non-inverted output in respect of each input signal. The inverted and non-inverted outputs are then applied to the potentiometer arrays 72, 82 and 152 via non-inverting amplifiers 28 and 30, which are preferably LH0002 amplifiers.

1 1 1 1 L I L i i 1 1 1 11 1 VA 44 WO 90/00849 PC /AU89/00294 18 While all of the signal processing circuits 2, 70, 80 and 150 are particularly useful for processing the signals generated by a scanning electron microscope and television cameras, the processing circuits may be used for processing any i video or colour signals which have been generated by a raster scan. For example, a video signal may be stored digitally in a digital memory circuit, outputted to a digital to analog converter and applied to one of the processing circuits.

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Claims (11)

1. A real-time signal processing circuit comprising: means for receiving input signals generated by a scanning device; means for obtaining a synchronising signal and a blanking signal from said receiving means; means for generating colour output signals from said input signals, each colour output signal being derived from one or a combination of said input signals; and means for including a blanking output signal in said colour output signals in 10 response to said blanking signal and outputting said colour output signals and said synchronising signal.

2. A processing circuit as claimed in claim 1, wherein said input signals include characterising signals which represent respective characteristics of a scanned subject and each colour output signal includes a selected percentage of said characterising signals.

3. A processing circuit as claimed in claim 2, wherein said generating means includes means for inverting said characterising signals and varying the gain of the 20 characterising signals and of the inverted characterising signals.

4. A processing circuit as claimed in claim 3, wherein each colour output signal includes a selected percentage of said characterising signals and said inverted characterising signals. A processing circuit as claimed in claim 4, wherein said generating means is adapted such that said selected percentage is variable with respect to each colour output signal.

6. A processing circuit as claimed in claim 5, wherein said inverting and varying means includes a plurality of non-inverting and inverting amplifier stages each adapted to receive a respective one of said characterising signals, and a potentiometer 4 4/ NT 0' 91 125,dbwspe.037,csiro,19 j ULIL&4-=ri P.'I.:LCI UjQL .V-LLAJ UV -ILTZ 13L3 ±lLYjJUL. M 20 array connected to said stages, and having a plurality of potentiometers, for each stage, adapted to receive and adjust the percentage of the respective characterising signal and/or inverted characterising signal outputted by the stage, each one of said potentiometers being connected to a respective one of a plurality of summing nodes, j said colour output signals thereby appearing, in use, at said summing nodes.

7. A processing circuit as claimed in any one of the preceding claims, wherein said obtaining means includes sync separator means for generating said synchronising signal from said input signals and blanking generator means for generating said blanking signal from said synchronising signal.

8. A processing circuit as claimed in claim 7, wherein timing of said blanking generator means is locked to said synchronising signal. *o 15 9. A processing circuit as claimed in any one of claims 1 to 6, wherein said obtaining means includes means for delaying the synchronising signal by a first predetermined period of time which is equivalent to the period of time which the characterising signals are delayed by the signal processing circuit before being outputted in a representative form as the colour output signals.

10. A processing circuit as claimed in claim 9, wherein said obtaining means includes means for delaying said blanking signal by a second predetermined period of time which is equivalent to the period of time which the characterising signals are delayed before being inputted in a representative form as the colour output signals to i said blanking signal including means.

11. A processing circuit as claimed in any one of claims 1 to 10, wherein said input signals include a blanking input signal and said obtaining means includes means for pulse shaping said blanking input signal to generate said blanking signal.

12. A processing circuit as claimed in any one of the preceding claims, further >AL/ comprising means for respectively adjusting the level of said colour output signals. 911125,dbwspc.037,coir,20 /V (.L1dLaUL1e-it.L11Y ZlyXIL.LD LU U U.

21- 13. A processing circuit as claimed in claim 12, wherein said adjusting means is adapted to alter the DC voltage level of said colour output signals. 14. A processing circuit as claimed in claim 12, or 13, wherein said adjusting means is adapted to adjust a gain applied to said colour output signals. A processing circuit as claimed in any one of the preceding claims, wherein said blanking output signal is said blanking signal. 16. A processing circuit as claimed in any one of the preceding claims, wherein said blanking signal including means comprises blanking switch means which switches output lines between said colour output signals and a low state in response to said blanking signal. 17. A processing circuit as claimed in any one of the preceding claims wherein said scanning device is a scanning electron microscope. 18. A processing circuit as claimed in any one of the preceding claims, wherein said colour output signals and said synchronising signals are outputted to a colour monitor which includes RGB inputs to which the colour output signals are applied, respectively. 19. A processing circuit substantially as hereinbefore described with reference to S* the accompanying drawings. DATED this 25th day of November, 1991 COMMONWEALTH SCIENTIFIC AND INDUSTRIAL RESEARCH ORGANISATION By its Patent Attorneys DAVIES COLLISON CAVE i V