AU608690B2 - Method and apparatus for decoding error correction code - Google Patents

Description

5845/3 S F Rf: 85487 S F Ref: 85487 FORM COMMONWEALTH OF AUSTRALIA PATENTS ACT 1952 COMPLETE SPECIFICATION

(ORIGINAL)

FOR OFFICE USE: Class This document contains the amunedments made utlndr Section 49 and is correct for printing.

Int Class S Complete Specification Lodged: Accepted: Published: Priority: SRelated Art: Name and Address of Applicant; 1t Sony Corporation 7-35, Kitashinagawa 6-Chome Shinagawa-Ku Tokyo

JAPAN

Spruson Ferguson, Patent Attorneys Level 33 St Martins Tower, 31 Market Street Sydney, New South Wales, 2000, Australia °Address for Service: Complete Specification for the invention entitled: Method and Apparatus for Decoding Error Correction Code The following statement is a full description of this invention, including the best method of performing it known to me/us '1G 0©^110:2/ "5' 1 5845/4 JTA:73 W r

SPECIFICATION

TITLE OF THE INVENTION METHOD AND APPARATUS FOR DECODING ERROR CORRECTION CODE TECHNICAL FIELD This invention relates to a method and an apparatus for decoding error correction code.

The present application is a divisional application proceeding under S51 of the Australian Patents Act based on parent Australian patent application no.37812/85 to the same 0 of #0 applicant.

00 BACKGROUND ART a 0 S* oProduct code are well known such that information ,0 s° ymbols are arranged in two-dimensional form, error correcttion code ae encoded for each row and column on the twcdimensional arrangement so that each information symbol is included in two error correction code series. In decodIng the product code, error correction code is decoded for each row by employing of the decode information. The decode information is called a pointer.

In the conventional method, since each information symbol is associated with a pointer, it is required that the total number of pointers is at least equal to the number of the information symbols.

Further, in the case where erasure correction is made by employing the pointers, since the pointer are read out from a pointer memory and the error values is calculated every row, there exists a problem in that the number of processing steps such as memory accesses, calculations and 1 'PATEN 0FF1, A.C.

so on Inevitably increases.

On the other hand, in the case where complicated codes such as 'CH codes are employed as error correction codes, since the operations for obtaining error values become Inevitably complicated, there exists a problem 1n that a great number of program steps are required in the case where the calculation are implemented by hardware.

According to one aspect of the present Invention there is provided a method for decoding error correction code in which respective first error correction codes of k l (where n, denotes the code length) are encoded for every ki information symbols arranged in respective columns of a two dimensional arrangement of X k 2 and respective second error correctioni codes of (n 2 k 2 (where n 2 denotes the code length) are encoded for every k 2 Information symbols arranged in respective rows of the two dimensional arrangement, the method comprising the steps of:

S

l receiving at least the respective first error correction codes; first decoding the respective first error correction codes; generating respective first pointers for indicating error detection or correction status of respective first error correction codes; storing the respective first pointers in memory means having a capacity of at least n 2 bits; rsecond decoding the respective second error correction codes by implementing an erasure correction for each code series of the respective second error correction codes by employing the respective first pointers and by Implementing a part of calculation for obtaining error value only once for each code series of the respective second error correction codes upon the erasure error correction; and outputting the information symbols, fit According to another aspect of the present Invention there is provided an apparatus for decoding error correction code in which respective first error correc:ion codes of k l (where n I denotes the code length) are encoded for every k 1 information symbols arranged in respective columns a two dimensional arrangement of X k 2 and respective second error correction codes of (n 2 k 2 (where n 2 denotes the code length) are encoded for every k 2 information symbols arranged in respective rows of the two dimensional arrangement, the apparatus comp Ising: 4IJi. receiving means for receiving at least the respective first error correction codes; first decoding means connected to said receiving means and for first decoding the respective first error correction codes and for generating respective first pointers for indicating error detection or correction status of respective first error correction codes; first memory means connected to said first decoding means and having a capacity of at least n 2 bits for storing the respective first pointers; second decoding means connected to said first decoding means and said first memory means and for second decoding the respective second error correction codes by implementing an erasure correction for each code series of the respective second error correction codes by implementing the respective first pointers and by implementing a part of calculation for obtaining error value only once for each code series of the respective second error correction codes upon the erasure error correction; and output means for deriving the information symbols.

°According to a further aspect of the present invention there is provided an apparatus for decoding error corre"tion code in which respective first error correction codes of (n 1 kI) (where n, denotes the code length) are encoded for every k I information symbols arranged in respective columns a two dimensional arrangement of X k 2 and respective second error correction codes of (n 2 k 2 (where n 2 denotes the code length) are encoded for e-'ry k 2 information symbols arranged in respective rows of the two dimensional arrangement, the apparatus comprising: receiving and output means for receiving at least the respective first error correction codes and for deriving the information symbols; decoding means connected to said re,:eiving and output means and for first decoding the respective first error correction codes and for generating respective first pointers for indicating error detection or 30 correction status of respective first error correction codes and for second decoding the respective second error correction codes by Implementing an erasure correction for each code series of the respective second error correction codes by employing the respective first pointers; and memory means connected to said decoding means and having a capacity of at least n 2 bits for storing the respective first pointers; characterized In that said second decoding includes a step of calculations for obtaining error values of erasure symbols by an algebraic expression consisting of a first term to be a common value and a second term to be "14-3 r, ^-i individually Independent values with respect to the erasure error corrections of the respective second error correction codes and said decoding means implements a first calculation of the first term only once corresponding to each of the respective first pointers, stores the result of the first calculation of the first term and implements each of the calculations for obtaining error values corresponding to the respective second error correction codes by each of second calculations of the second term and by using the stored result of the first calculation.

4.

**c 4,

I

I1 1 4r 12 *r I I. 4 3a S 4 BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic block diagram showing an encoder according to an embodiment of the present invention.

Fig. 2 is a schematic diagram for assistance in explaining the operation of an embodiment of the present invention.

Fig. 3 is a schematic block diagram showing a decoder according to one embodiment of this inventic:n.

Fig. 4 is a block diagram showing an embodiment of this invention.

e Fig. 5 is a block diagram showing an essential portion of an embodiment of this invention.

4 f Fig. 6 is a block diagram showing an.construction of an embodiment for use with this invention.

Fig. 7 is a block diagram for assistance in explaining a processing circuit of Fig. 6.

BEST MODE FOR CARRYING OUT THE INVENTION I An embodiment of the present invention will be described, referring to the drawings. Fig. 1 shows a structure of an encoder for product code. The reference numeral 1 denotes an input terminal, the reference numeral 2 denotes a C 2 (the second error correction code) parity generatoi. The input data from the input terminal 1 are supplied to the C 2 parity generator 2 and one input terminal of a selector 3, and the C 2 parity data formed by the C 2 parity generator 2 are supplied to the other input terminal of the selector 3. The selector 3 repeats k I times the operations for selecting (n 2 k 2 parity data after k 2 information symbols are 5 selected. During this operation, the information symbols and the i parity data are stored in a RAM (Random Access Memory) 4 in sequence under control of an address controller The data read out from the RAM 4 are supplied to a C 1 (the first error correction code) parity generator 6 and one input terminal of a selector 7 and the C 1 parity data formed by the C 1 parity generator 6 are supplied to the other input terminal of the selector 7. The selector 7 selects ((n 1 k

I

x k 2

C

1 parity data of after having selected (k I x n 2 symbols including the C 2 parity data. The digital data derived from an outoput terminal 8 of the selector 7 are transmitted or recorded on a magnetic tape (not shown) with a magnetic head, for instance.. In this case, it is possible to write again the encoded output once into the RAM 4 and to read out it in different sequence for recording.

I t t t t Fig. 2 shows an configuration of code formed by the encoder as described above. The information symbols are arranged in two dimension of (k I x k 2 The k 2 information symbols in every lateral direction, that is, in every row of the two-dimensional arrangement are subjected to encoding process for the C 2 code. The k I information symbols in every vertical direction, that is, in every column are subjected to encoding process for the C 1 code. The

C

2 parity data are also encoded into the C 1 code. The C 1 code is, for instance, (n 1 k

I

Reed-Solomon code, by which it is possible to correct errors of up to (n 1 kl)/2 symbols.

The general method of decoding the Reed-Solomon code will be described.

i _li i i 6 The hamming distance of the k) Reed-Solomon code (n denotes the code length and k denotes the number of information symbols) on a Galois Field GF(2 .can be expressed as (d n k 1) and the generator polynomial can be expressed as d-2 II (x If the received words are (r 0 rl, 2, rn-l i=O the syndrome can be obtained by operating the following expression: n-1 Sj r i 00' (j 0, d-2) (1) i=0 It An error location polynomial 6(z) and an error evaluation ,o polynomial 0(z) are obtained by employing the syndrome Sj. As to S this method, Euclid's mutual division method, Varlay-Camp's method, Peterson's method and so on have been proposed.

By solving 6(z) 0, the error location X can be obtained.

For this purpose, Chien search is employed.

t Then, the error value Yi can be obtained on the basis of the error location X i and the error evaluation polynomial The above calculations in the decoding steps are explained with the error location as X i (i 1, 2, e e denotes the number of errors), and the error value as Yi. Since the Reed-Solomon code is a liniear code, the syndrome can be expressed as: e S 7 i X 3 (j 1, 2, d-2) (2) i=l if the syndrome is expressed by a polynomial as: -7 d-2 S(z) E]S. zj (3) j=0 a following expression is obtained: e d-2 il j=0 e z (mod zdl (4) ~'If the error location polynomial and the error evaluation *polynomial are defined as e 6 r(z) M (1 X. z) #tit, j=l z) 4(z) S(z) (6) tt then Wt~z can be expressed as e Y e i j=1 e Y. 1 (U Xi Z) (mod. zdl (7) The error value Y. can be obtained by substituting xJ into z and by transforming the expression as follows: (1 U~ X j' (8) i (X i L 8 As an exsample, (32, 24) Reed-solomon code having roots of

CO

0 to U7 will be explained. Since this code is it is possible to correct errors of up to 4 symbols. If the error locations of the 4 symbols are X 1 to X 4 and the error values are Y1 to Y41 the syndrome is obtained from following expression.

4 s L Yi (j 0 to 3) i=l Namely, S O is as follows among 4 syndromes: 4 S Y i=l Once the error values Y 2 1 Y 3 can be obtained, the remaining S. error value Y is obtained as follows without implementing complicated calculations: Y 4 SO -Y 2 3 In coOdes on GF(2m), a subtraction is equivalent to an addition of i" (mod. 2) Fig. 3 shows a configuration of the encode:, of this embodiment. In Fig. 3, the reproduced data are supplied from an input terminal designated by the reference numeral 11 and to a C 1 decoder 12. In the C decoder 12, the decoding of the C 1 code is performed. All errors of up to (n I ki)/2 symbols are corrected in the C 1 decoding. In the case, however, where the number of errors in a single series of C 1 code is more than or equal to a S-kl)/2 the C 1 pointers of this series is set to the -9 Al ~1 r -9other pointers are set to In Figs. 2 and 3, the reference numeral 13 denotes a pointer memory for storing the pointers of the C 1 code, which has n 2 bits. The output of the C 1 decoder 12 is stored temporarily in a RAM 14 in sequence under the control of an address controller The output read out from the RAM 14 are supplied to a C 2 decoder 16 to be subjected to the decoding of the C 2 code. The C 2 S decoder 16 is supplied with the C 1 pointer from the pointer memory 13. Since the C 1 pointer is common to the all of K1 series of C 2 S code, it is possible to decode the C 2 code in accordance with the same procedure in each series. The C 2 decoder 16 corrects errors of up to (n 2 symbols and generate three kinds of pointers in the C 2 code which is stored in a pointer memory 17.

When error correction is perfomed by the C 2 decoder 16, the

C

2 pointers with respect to the series is set to When error correction can not be performed by the C 2 decoder 16 and the C 1 pointers are copied because of its high reliability, the C 2 pointers is set to When error correction can not be performed by the C 2 decoder 16 and all symbols are determined to be erroneous symbols because of low reliability of the C 1 pointer, the C 2 pointers are set to "2 Therefore, the C 2 pointers have 2 bits and the pointer memory 17 has 2K 1 bits.

These pointer memories 13 and 17 are disposed separately from the RAM 14 for storing information symbols and parity data in decoding or disposed in common with the RAM 14 by using a part of memory regions of the RAM 14.

Without being limited to 1 bit, the C 1 pointer may have 2 bits or more. Further, it is possible to implement the error correction code processing of C 2 code for the C 1 parity, while providing a C2 pointer memory of (2n l bits.

The output data of the C 2 decoder 16 are supplied to an interpolation circuit 18 to conceal error in the symbols which have not been corrected. The interpolation circuit 18 performs the mean value interpolation, for instance. The interpolation circuit 18 is controlled by a control circuit 19 which is supplied with the C 1 pointers and the C 2 pointers from the pointer memories 13 and 17. The output data of the interpolation circuit 18 are :I derived at an output terminal 20. The control circuit 19 determines by every information symbol whether interpolation is necessary on the basis of the c, pointer' and c 2 pointer. In S t Fig. 2, There exist all the combinations of Cl pointers designated as 13' and C pointers designated as 17'.

When the C2 pointer is irrespective of the fact that the C1 pointer is or the interpolation circuit 18 does not work, When the C2 pointer is and the C 1 pointer is since it is determined that the information symbol has no error, no interpolation is done. When the C 2 pointer is and the C, pointer is since it is determined that it is erroneous symbol, the interpolation operation is performed. Further when the C 2 pointer is irrespective of the fact that the C, pointer is or since it is determined that it is erroneous symbol, the Interpolation operation is performed.

ii i 11 Th- teliability of the C 1 pointers is evaluated by the C 2 decoder. For instance, provided that up to 2 symbol errors can be corrected by the C 2 code, if correction by the C 2 code can not be performed in spite of the fact that only one C 1 pointer is it is determined that the reliability of the C 1 pointer is low because the above is abnormal. Even if errors are not corrected by the C 2 code, it is possible to eliminate the necessity of interpolation by providing three kinds 0, 1, 2 of the C 2 pointers and by discriminating the copies of C 1 pointers from all errors.

In the above mentioned C 2 decoder 16, when the C 1 pointers are copied, the erasure corrfetion is made where the number of the C 1 pointers is less than or equal to (n 2 k2) and when the erasure correction is made, the C 2 pointer is set to As described above, the decod-ing of the Reed-Solomon code is performed by calculation of the error location polynomial d(z) and S the c.ror evaluation polynomial 0(z) every row and by employing syndrome obtained by n 2 symbols in each row. In the case of erasure correction, since the locations where the C 1 pointers are are detrmined a5 the error locations, it is possible to obtain the error value Yi from the error location X i and the error evaluation polynomial That is to say, by substituting Xi in place of z, Yi can be obtained as follows as in expression Y, a i a 1n Xj x l) (where i l, 2, 3, s denotes the number of symbols) i_ ii i 12 In the abov expression, the term of denominator can be determined by only th. )r locations. For instance, provided that the error locations shown by the C 1 pointer are Xl, X 2

X

3 the terms of denominator of the -xpressions for obtaining the error values Y1' Y2' Y are 2-1 -1 Denominator of Y1 (1 X 2

X

1 (1 X 1 Denominator of Y2 (1 X 1 X (1 X 2 X Denominator of Y3 (1 X 1 X 2 (1 X 3 X 1) S Here, the pointers stored in the pointer memory 13 are the same in the all of K 1 series of the C 2 code. Therfore, it is sufficient to 1 2 implement the calculation of term of denominator in the above expression to obtain error value only once with respect to the k series.

Fig. 4 shows the configuration of an error correcting decoder for use with the above mentioned C decoder and C 2 decoder.

The received data are supplied to an input terminal designated by the reference nurneral 21 and supplied to a delay circuit 22 and a syndrome generating circuit 23. The syndromes formed by the *0 to syndrome generating circuit 23 are supplied to an error location and error value calculating circuit 24. The error data from the error location and error value calculating circuit 24 are supplied to an exclusive OR gate 25 and added to the received data from the delay circuit 22 in (mod. The received data from the delay circuit 22 and the error corrected data from the exclusive OR gate are supplied to a selector 26. The selector 26 is controlled by the error location data. At the error locations, the output of the p-- Ili;- 13 exclusive OR gate 25 is selected by the selctor 26 to be derived at an output terminal 27 in place of the received data.

In the case of an audio PCM signal recording and reproducing apparatus, the reproduced data are once written in a RAM. By use of the data read out from the RAM, the syndrome is generated and on the basis of which the error locations and the error values are calculated. Fig. 5 shows a part of the error location and error value calculating circuit 24. In Fig. 5, the reference numeral 28 denotes a data bus through which data and syndrome and so on are transfered.

In Fig. 5, the reference numeral 29 denotes a syndrome register in which the syndrome S O is stored through the data bus 28, a bus buffer 30 and an exclusive OR gate 31. the syndrome S

O

b O4 has m bits in the case of Reed-Solomon code on GF(2m). The .o syndrome S O from the syndrome register 29 is supplied to the exclusive OR gate 31 and the bus buffer 32.

When the syndrome S O is stored in the syndrome register 29, the obtained error values Yi, Y21 Y 3 are supplied to the exclusive OR gate 31 in sequence from the data burs 28 through the bus buffer Therefore, the output of the exclusive OR gate 31 is (S 0 eY 1 (S0 Y 1

Y

2 and (S O e Y 1

Y

2

Y

3

Y

4 The error value Y is left in the syndrome register 29. The error value Y is outputted o M4 to the data bus 28 through the bus buffer 32 to be employed for error correction.

F Pig. 6 shows another example of hardware for decoding in an e A erasure corrction. A main RAM 35 is connected to the data bus 28 A 4

C

i 14 through a writing register 33 and a reading register 34. The syndrome register 29, a working RAM 36 and an operation logic circuit 37 are provided to the data bus 28.

The erasure correction by Reed-Solomon code can be concluded by solving the following n-order liniear simultaneous equations in the same way as in expression n S, X Yk S(9) k=l where, 0 to d 2 n Number of erasure X Location of kth S3 Syndrome Y Magnitude of error in the erasure of kth d Minimum distance of code Here, n, Xk, SV, are known, Yk is unknown.

To solve the above equation, the following method has been conventionally adopted: if n A(z) I (i Xi Z) i=l 1 Azrd-1 f ca Sz)(z) z) d. z L; Yi can be obtained as in expression as follows: Y (X1) i (1 -X jii In this method, however, if the number of actual calculation steps is counted when d 9 and n 8, for instance.

9*4* 1 Expansion of A(z) Number of multiplications 1 2 7 28 Number of additions 1 2 7 28 (ii) Previous calculations for obtaining the denominator of 8 Y. and Y I (1 X. Xi) j=i J i=l Number of reciprocals 1 x 8 8 Number of multiplications (7 6) x 8 104 Number of additions 7 x 8 56 (iii) Calculations for obtaining S(z) mod. Z C t, Number of multiplications 1 2 7 28 Number of additions 1 2 7 28 (iv) Calculations for obtaining 0W(X Number of reciprocals 1 x 8 8 Number of multiplications 7 x 8 56 Number of additions 7 x 8 =56 Calculations for obtaining Y.

W h Number of division 1 x 8 8 When these calculations need each one step, the number of steps is 408 in total.

In the circuit shown in Fig. 6, the roots of expression (9) ei are calculated by:

J:

r n-l (Xk X) (11) j=0 k V IIU L- -1)1 L" U c -3- 16 lli I I 1 where Anij Coefficient of Z j of L (z Xk)] k =1 Any integer more than or equal to 0 which satisfies d n 1 That is to say, in order to implement erasure correction, 1 0, i n are substituted into the expression (11) as follows: n-1 n-1 Y A S Ir (X X) n nj k=1 n j=0 k this calculation, Y is obtained and Y X 9 is added to each n n n 4 .syndrome S as follows: S S Y X v n n where 9 0 to n-2 **Since the data at the location X are correct, the syndrome n icludes erasures. Therefore, by reducing n by 1, Yn- can be obtained: *arrt n-2 -n-2 Y A. I (X X S n-1 n-1,n-1,j j k=1 k nj=0 By th-is calculation, Yn-1 is obtained and Yn-1 Xn is added to *each syndrome S as follows: 9 S e- S Yn-i Xnwhere 0 to n-3 By repeating the above, the last remaining erasure Y1 can be obtained as Y1 0= 0 17 As explained above, an erasure correction can be implemented.

In this case, the actual number of operation steps is counted in the same way as in the conventional method, provided that d 9 and n 8.

Expansion of Annj Number of multiplications 1 2 6 21 Number of additions 1 2 6 21 (ii) Previous calculations for obtaining the denominator of n-1 Y IIn Ii (Xk X n where it is sufficient to k=l obtain only 13 to II8 since II2 X 1 2 331" SNumber of multiplicatiohs 1 2 6 21 Number of additions 1 2 6 21 (iii) Calculations for obtaining the numerator of Y *Number of multiplications 7 6 1 28 C t t Number of additions 7 6 1 28 (iv) Calculations for obtaining Yn, since Y SO Number of divisions 7 t t I S S V Yn X Number of multiplications 6 5 21 Number of additions 7 6 1 28 The number of the above calculations steps is 202 in total.

Therefore, in the case of expression it is possible to S i reduce the number of calculation steps to 50% of the conventional Scase in the expression Further, in the case where the above mentioned correction code is a product code, provided that 30 symbols are arranged in xI^ -18 the vertical direction, 128 symbols are arranged in the lateral direction, the C 1 code is formed to the vertical direction, and the C 2 code is formed to the lateral direction, the erasure corresponds to the location of the C 1 pointers, and the location Xk (k=l to n) is the same in all the C 2 code series. This means n-l that it is possible to previously calculate Ann j and I (xk Xn) k=l in expression without calculating these terms every the C 2 decoding. That is to say, in this example, the above calculation is implemented only once while the C 2 decoding is performed times.

S t Therefore, in the number of the above calculation steps, since the number of the calculations of and (ii) is only once every 30 times of C 2 decoding, provided that the number of steps I of and (ii) is 90/30 3, the total number of steps is 115.

compared with that in the conventional method, where the number of steps in and (ii) is 224/3 74.7 and the total number of tt steps is 191.5, it is possible to reduce the number of steps by Sabout Accordingly, the method as above described has advantages S. such that it is possible to markedly reduce the number of calculation steps, processing time, hardware load for processing o, and so on as compared with the conventional method.

Additionaly, although the above calculations are performed I* 4 by employing the operation logic 37, in the case where, for example, S S) X Yi is obtained, a concept as shown in Fig. 7 is adopted. In Fig. 7, the reference numerals 38, 39, 1I PNPW 19 denote registers, the reference numeral 41 denotes an adder, the reference numeral 42 denotes a multiplier, the reference numeral 43 denotes a selector, which are all built in the operation logic 37. In this circuit, [11 S 0 is set to the register 38, Yi is set to the register is set to the register 40, respectively through the data bus 28 from the syndrome register 29 and the working RAM 36 and so on. S 0 Yi is outputted from the adder 41 to the data bus 28.

The content of the multiplier 42, X. Y. is set (feedbacked) to the register 39 through the selector 43, and S 1 is set to the register 38 from the data bus 28. Therefore, S 1 X. Y.

9 1 1 is outputted from the adder 41 to the data bus 28.

(31 Further, the content of the multiplier 42, X.2 Y. is feedbacked to the xegister 39 through the selector 43, and S 2 is 2 set to the register 38 from the data bus 28. Therefore, S2 X 2 Yi is outputted from the adder 41 to the data bus 28.

141 By repeating the above steps, S3 X3 Y, S4 X 4

Y,

are obtained sequentially, and supplied to the syndrome register 29 through the data bus 28 so as to' rewrite each value.

The calculation are implemented as described above.

In the above explanation, although all of Xl to X are assumed as erasures, in the case wher.e X 1 to Xn 1 are erasures and X is an error, it is possible to correct the symbols. In this S n case, thb number of unknown quantity are of Y1 to Y and x X can be obtained by using the above Ann j as follows: U Annj S jie~ n n-i112 Annj S j=0 Therefore, the unknown quantity are Y 1to Y n and thereafter, these unknown quantity can be obtained in the same way as in the erasure correction.

For instance, in the case where d 9 (6 erasures 1 error) in product coder Ill Check' locations of the erasures XX x 6 L23 Obtain and store A here 21 symbols in total of v~ 221 331 *~221 X 2 1 332 A 221

X

2 1

A

7 7 6 obtain and store 5 symbols in total of ni (Xk Xn k =1 (n 2 to 6).

The above processings are mnad~e once for each 30 times.

14] Calcul~ate syndromes S 0 to S.

£52 obtain X 7 by an expression as follows: 6 -77 j' j=0 t6) Obtain Y 7 by the following expression and feedback the syndrome Y 7 X 7 i i 21 6 n-1 Y7 A77j Sj) I (Xk X 7 k=l j=0 Thereafter, Y 6 to Y1 S 0 are sequentially obtained.

Although a case where expression is used is shown in this example, the operation is the same if 140.

As described above, it is possible to implement the correction of errors including erasures and one error. In this case, the number of calculation steps can be reduced as in the erasure correction described above.

The proof of the above expressions (11) and (12) will be I, described hereinafter: ,f [Lemma] If n n(z) nI (z Xk) n i k=l k i -nij [Ani(z the following expression is cleary obtained: n-1 ni j II (z Xk)' k=l k i [Theorem 1] The n-order linear simultaneous equations: n S X Yk k=l 0 to n-1 Yi is unknown quantity) has the roots as: 'ZOajo Ut? ST Ux pul? 0.nse 1 xol TX;x[ wooqj 5u~n-4p~qns 4q XPT:3aT wpT q' (4oo.7,1) (0 TT I

U

(x X) li X T Ut 1:-u (T 4JVTTOJO

S

t

I

*II 1*

II

It

I

ii ,t 1 1*

I

I I 1 4 1# Tt=

TLC

T

L=*

X X) -I X) T-x u Ul (X X) III ~x XJ 2 U u u

T~

(x X) LI1 X) LI

U

I-U

IT

(X 1 ~Tu U I )I PTS q6T (goold) Tc NXu TT7 (X X) LI/xSVL

I-U

23 n-i SAnnj sj+ +I n n-i 2 nn+j S+ j=0 (Proof) From Corollary 1, n-1 Yn n (X k n Right side Left side n-1 n Xn (Xk Xn) Therefore, it is understood from Theorem 1 that errors can be corrected in the erasure correction by use of any of Si to S S 2 to Sn+ 1 Sd--n to Sd among the series of SQ to Sn-I.

S That is, n continuous syndromes are necessary for n erasures correction, the remaining syndromes are usable for checking, so that n d-1.

Further, to obtain X from the theorem 2, total n+1 syndromes of Si to Sn+i are necessary, so that A d-2. In this case, the number of erasures is n-1 d-3. The remaining syndromes can be used for checking as in the above case.

In the conventional method, the pointer areas are required for the total number of data n 2 corrsponding to the error t correction code. According to the present invention, however it is 'possible to reduce the number of pointers to (nA 2n 1 and further to reduce the capacity of the memory required in decoding further, according to the present invention, it is possible to reduce the number of steps for writing or reading the pointers.

N-

1 A*"i I i; i: 24 Further, according to the present invention, in thecase where the erasure correction in the C 2 decoding is implemented by the use of pointers formed by the C 1 decoding, since the pattern of the pointers with respect to each series of C 2 code is common and a part of the operations to obtain error value become common, it is possible to implement the operation only once. Therefore it is possible to markedly reduce the number of processing steps in decoding and to realize a high-speed in decoding operation.

Furthermore, according to the present invention, without J necessity to obtain the whole error values in accordance with to, complicated error evaluation polynomial in obtaining a plurality of error values, it is possible to obtained one of the error values by a simple construction and to reduce the number of the i processing steps.

Moreover, according to the present invention, it is possible to markedly reduce the number of calculation steps in erasure ocorrection, 4* *4 t

Claims (5)

1. A method for decoding error correction code In which respective first error correction codes of k l (where n, denotes the code length) are encoded for every k, information symbols arranged in respective columns of a two dimensional arrangement of (k I X k 2 and respective second error correction codes of (n 2 k 2 (where n 2 denotes the code length) are encoded for every k 2 information symbols arranged in respective rows of the two dimensional arrangement, the method comprising the steps of: receiving at least the respective first error correction codes; first decoding the respective first error correction codes; generating respective first pointers for indicating error detection r or correction status of respective first error correction codes; storing the respective first pointers in memory means having a '$4f15 capacity of at least n 2 bits; ,second decoding the respective second error correction codes by Implementing an erasure correction for each code series of the respective second error correction codes by employing the respective first pointers and by implementing a part of calculation for obtaining error value only once for each code series of the respective second error correction codes upon the erasure error correction; and outputting the information symbols.

2. A method according to claim I, wherein the step of second decoding includes a step of calculations for obtaining error values of erasure symbols by an algebraic expression consisting of a first term to be a common value and a second term to be individually independent values with respect to the erasure error corrections of the respective second error correction codes and the step of calculations for obtaining error values Includes implementing a first calculation of the first term only once corrc(ponding to each of the respective first pointers; storing the result of the first calculation of the first term; and implementing each of the calculations for obtaining error values corresponding to the respective second error correction codes by each of second calculations of the second term and by using the stored result of the first calculation.

3. An apparatus for decoding error correction code in which respective first error correction codes of (n I (where n, denotes the code length) are encoded for every k I information symbols arranged In respective columns a two dimensional arranqement of (ki X k 2 and 25 respective second error correction codes of (n 2 k 2 (where n 2 denotes the code length) are encoded for every k 2 information symbols arranged in respective rows of the two dimensional arrangement, the apparatus comprising: receiving means for receiving at least the respective fir(t error correction codes; first decoding means connected to said receiving means and for first decoding the respective first error correction codes and for generating respective first pointers for indicating error detection or correction status of respective first error correction codes; first memory means connected to said first decoding means and having a capacity of at least n 2 bits for storing the respective first pointers; second decoding means connected to said first decoding means and said first memory means and for second decoding the respective second error correction codes by implementing an erasure correction for each code series of the respective second error correction codes by Implementing the respective first pointers and by Implementing a part of calculation for obtaining error value only once for each code series of the respective second error correction codes upon the erasure error correction; and output means for deriving the information symbols.

4. An apparatus according to claim 3, wherein the second decoding includes a step of calculations for obtaining error values of erasure symbols by an algebraic expression consisting of a first term to be a common value and a second term to be Individually independent values with respect to the erasure error corrections of the respective second error correction codes and said second decoding means Implementes a first calculation of the first term only once corresponding to each of the respective first pointers, has store means for storing the result of the first calculation of the first term and Implementes each of the 30 calculations for obtaining error values corresponding to the respective second error correction codes by each of second calculations of the second term and by using the stored result of the first calculation, An apparatus for decoding error correction c ode in which respective first error correction codes of (n 1 kI) (where n I denotes t the code length) are encoded for every kI information symbols arranged in respective columns a two dimensional arrangement of (k I X k 2 and respective second error correction codes of (n 2 k 2 (where n 2 denotes the code length) are encoded for every k 2 information symbols A P- LPt 26 l- rrr-, lr i i rm~ arranged In respective rows of the two dimensional arrangement, the apparatus comprising: receiving and output means for receiving at least the respective first error correction codes and for deriving the information symbols; decoding means connected to said receiving and output means and for first decoding the respective first error correction codes and for generating respective first pointers for indicating error detection or correction status of respective first error correction codes and for second decoding the respective second error correction codes by implementing an erasure correction for each code series of the respective second error correction codes by employing the respective first pointers; and memory means connected to said decoding means and having a capacity of at least n 2 bits for storing the respective first pointers; characterized in that said second decoding includes a step of calculations for obtaining error values of erasure symbols by an algebraic expression consisting of a first term to be a common value and a second term to be 4 individually independent values with respect to the erasure error corrections of the respective second error correction codes and said decoding means implements a first calculation of the first term only once corresponding to each of the respective first pointers, stores the result of the first calculation o( the first term and implements each of the tll calculations for obtaining error values corresponding to the respective 4t4P ,It4 second error correction codes by each of second calculations of the second term and by using the stored result of the first calculation. 14,125 6. A method for decoding error correction code as claimed in claims 1 or 2 and as hereinbefore particularly described with reference to what is shown in the accompanying drawings.

7. An apparatus for decoding error correction code as claimed in any one of claims 3 to 5 and as hereinbefore particularly described with reference to what is shown in the accompanying drawings. DATED this TWENTIETH day of AUGUST 1990 Sony Corporation Patent Attorneys for the Applicant SPRUSON FERGUSON 27