AU3246589A - Apparatus and method for accessing data stored in a page mode memory - Google Patents
Apparatus and method for accessing data stored in a page mode memoryInfo
- Publication number
- AU3246589A AU3246589A AU32465/89A AU3246589A AU3246589A AU 3246589 A AU3246589 A AU 3246589A AU 32465/89 A AU32465/89 A AU 32465/89A AU 3246589 A AU3246589 A AU 3246589A AU 3246589 A AU3246589 A AU 3246589A
- Authority
- AU
- Australia
- Prior art keywords
- data stored
- accessing data
- page mode
- mode memory
- memory
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
- G11C7/106—Data output latches
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/1018—Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
- G11C7/1021—Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
- G11C7/1024—Extended data output [EDO] mode, i.e. keeping output buffer enabled during an extended period of time
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1015—Read-write modes for single port memories, i.e. having either a random port or a serial port
- G11C7/103—Read-write modes for single port memories, i.e. having either a random port or a serial port using serially addressed read-write data registers
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US19872188A | 1988-05-26 | 1988-05-26 | |
US198721 | 1994-02-18 |
Publications (2)
Publication Number | Publication Date |
---|---|
AU3246589A true AU3246589A (en) | 1989-11-30 |
AU611275B2 AU611275B2 (en) | 1991-06-06 |
Family
ID=22734526
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU32465/89A Ceased AU611275B2 (en) | 1988-05-26 | 1989-04-05 | Apparatus and method for accessing data stored in a page mode memory |
Country Status (2)
Country | Link |
---|---|
AU (1) | AU611275B2 (en) |
FR (1) | FR2632094A1 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5692148A (en) * | 1994-04-11 | 1997-11-25 | Intel Corporation | Method and apparatus for improving system memory cost/performance using extended data out (EDO)DRAM and split column addresses |
FR2997732A1 (en) | 2012-11-08 | 2014-05-09 | Valeo Equip Electr Moteur | THERMAL MOTOR STARTER PROVIDED WITH SHEAR ABSORPTION DEVICE |
FR3004496B1 (en) | 2013-04-15 | 2017-08-11 | Valeo Equip Electr Moteur | CROWN WITH INSERT FOR SPEED REDUCER OF A THERMAL MOTOR STARTER AND CORRESPONDING SPEED REDUCER ASSEMBLY. |
-
1989
- 1989-04-05 AU AU32465/89A patent/AU611275B2/en not_active Ceased
- 1989-04-11 FR FR8905075A patent/FR2632094A1/en not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
FR2632094A1 (en) | 1989-12-01 |
AU611275B2 (en) | 1991-06-06 |
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