AU2159095A - Method and apparatus for distributing clock signals with minimal skew - Google Patents
Method and apparatus for distributing clock signals with minimal skewInfo
- Publication number
- AU2159095A AU2159095A AU21590/95A AU2159095A AU2159095A AU 2159095 A AU2159095 A AU 2159095A AU 21590/95 A AU21590/95 A AU 21590/95A AU 2159095 A AU2159095 A AU 2159095A AU 2159095 A AU2159095 A AU 2159095A
- Authority
- AU
- Australia
- Prior art keywords
- clock signals
- distributing clock
- minimal skew
- skew
- minimal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
- G06F13/4077—Precharging or discharging
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Dc Digital Transmission (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US24766694A | 1994-05-23 | 1994-05-23 | |
PCT/US1995/003165 WO1995032549A1 (en) | 1994-05-23 | 1995-03-14 | Method and apparatus for distributing clock signals with minimal skew |
US247666 | 1999-02-10 |
Publications (1)
Publication Number | Publication Date |
---|---|
AU2159095A true AU2159095A (en) | 1995-12-18 |
Family
ID=22935833
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU21590/95A Abandoned AU2159095A (en) | 1994-05-23 | 1995-03-14 | Method and apparatus for distributing clock signals with minimal skew |
Country Status (2)
Country | Link |
---|---|
AU (1) | AU2159095A (en) |
WO (1) | WO1995032549A1 (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5923611A (en) * | 1996-12-20 | 1999-07-13 | Micron Technology, Inc. | Memory having a plurality of external clock signal inputs |
US5852378A (en) * | 1997-02-11 | 1998-12-22 | Micron Technology, Inc. | Low-skew differential signal converter |
US6104209A (en) | 1998-08-27 | 2000-08-15 | Micron Technology, Inc. | Low skew differential receiver with disable feature |
US6212482B1 (en) | 1998-03-06 | 2001-04-03 | Micron Technology, Inc. | Circuit and method for specifying performance parameters in integrated circuits |
US6433605B1 (en) * | 2000-02-03 | 2002-08-13 | Hewlett-Packard Company | Low wiring skew clock network with current mode buffer |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4947113A (en) * | 1989-03-31 | 1990-08-07 | Hewlett-Packard Company | Driver circuit for providing pulses having clean edges |
-
1995
- 1995-03-14 AU AU21590/95A patent/AU2159095A/en not_active Abandoned
- 1995-03-14 WO PCT/US1995/003165 patent/WO1995032549A1/en active Application Filing
Also Published As
Publication number | Publication date |
---|---|
WO1995032549A1 (en) | 1995-11-30 |
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