AU2013205395B1 - Method of constraining a safe operating area locus for a power semiconductor device - Google Patents
Method of constraining a safe operating area locus for a power semiconductor device Download PDFInfo
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- AU2013205395B1 AU2013205395B1 AU2013205395A AU2013205395A AU2013205395B1 AU 2013205395 B1 AU2013205395 B1 AU 2013205395B1 AU 2013205395 A AU2013205395 A AU 2013205395A AU 2013205395 A AU2013205395 A AU 2013205395A AU 2013205395 B1 AU2013205395 B1 AU 2013205395B1
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 59
- 238000000034 method Methods 0.000 title claims abstract description 23
- 238000005259 measurement Methods 0.000 claims abstract description 23
- 230000001939 inductive effect Effects 0.000 description 10
- 238000010521 absorption reaction Methods 0.000 description 5
- 238000007493 shaping process Methods 0.000 description 4
- 239000007858 starting material Substances 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 230000005669 field effect Effects 0.000 description 2
- 229910044991 metal oxide Inorganic materials 0.000 description 2
- 150000004706 metal oxides Chemical class 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 239000005022 packaging material Substances 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 230000004913 activation Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/08—Modifications for protecting switching circuit against overcurrent or overvoltage
- H03K17/082—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit
- H03K17/0822—Modifications for protecting switching circuit against overcurrent or overvoltage by feedback from the output to the control circuit in field-effect transistor switches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Electronic Switches (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Emergency Protection Circuit Devices (AREA)
Abstract
A method of constraining a Safe Operating Area (SOA) locus for a power semiconductor device during operation of the power semiconductor device placed between a power source and a load, the method including: taking a voltage measurement across the load (VLOAD); selecting a scalar for scaling the voltage measurement taken across the load (VLOAD); and constructing a control voltage for controlling the power semiconductor device with a control circuit according to the voltage measurement taken across the load (VLOAD) multiplied by the scalar so as to constrain an output voltage of the power semiconductor. <filename>
Description
1 Title of Invention METHOD OF CONSTRAINING A SAFE OPERATING AREA LOCUS FOR A POWER SEMICONDUCTOR DEVICE Technical Field [0001] The present invention relates to a method and circuit for constraining a Safe Operating Area (SOA) locus for a power semiconductor device during operation of the power semiconductor device placed between a power source and a load. The present invention has particular, but not exclusive application, in constraining a SOA locus for an N-Channel Enhancement-Mode Power MOSFET in a high-side configuration between the power source and the load by constructing a control voltage for controlling the power MOSFET so as to constrain an output voltage of the power MOSFET. Background of Invention [0002] A power semiconductor device, such as a power metal oxide semi conductor field effect transistor (MOSFET), is typically used to switch ON and OFF electric power to an inductive load in, for example, automotive control and pulse-width modulation motor control applications. The power MOSFET has a gate electrode for controlling the power MOSFET, a drain electrode connected to the electric power source and a source electrode connected to the load. During operation, when the power MOSFET is switched OFF to switch the load OFF, inductive energy stored in the inductive load can cause the source voltage of the power MOSFET to fall below the ground potential. In some cases, the drain-source voltage of the power MOSFET increases until it exceeds a drain-source avalanche voltage leading to conduction in an internal parasitic antiparallel diode of the power MOSFET which can cause avalanche induced failure of the power MOSFET. Accordingly, efforts have been made to protect a power semiconductor device from avalanche induced failure and to operate the power MOSFET in a constrained Safe Operating Area (SOA). The SOA represents the maximum voltage and current conditions over which any such power semiconductor device can operate without causing self-damage to the device. C:\pof\ord\SPCN-969363.docx 2 [0003] In one existing example of an effort to prolong the longevity of a power MOSFET, the rate of change of the drain-source voltage is controlled by a secondary gate drive circuit via a MOSFET "miller capacitance". The secondary gate drive is achieved by selecting a high impedance primary gate drive circuit for the power MOSFET which interacts with the MOSFET inbuilt "miller capacitance". Nonetheless, in this example of "gate shaping", however, the MOSFET Safe Operating Area (SOA) locus is only constrained in certain situations and this technique is not robust against parameter variation. [0004] In another example, the secondary gate drive circuit is derived from the drain-source voltage and the inductive load is clamped with a clamping control circuit. However, in this example, the "clamping" MOSFET SOA locus does not yield a minimum peak power when used with typical loads. Indeed, the peak power is only minimised in extreme cases of operation. [0005] Figure 1 shows these abovementioned existing examples of constraining a SOA for a power semiconductor device graphically. Figure 1 also shows a graph 10 of a maximum rated forward bias Safe Operating Area (SOA) locus 12 for a power semiconductor device, such as a power MOSFET, with drain-source voltage (Vds) on the x-axis and drain current (lo) on the y-axis of the graph 10. The SOA locus 12 represents the maximum simultaneous drain-source voltage and drain current that the power MOSFET can handle safely with, for instance, a maximum peak junction temperature and a case temperature of 25'C. [0006] A power semiconductor device can be used to switch both clamped and unclamped inductive loads as per the abovementioned existing examples. For unclamped inductive loads, the stored inductive energy that is dissipated in the power MOSFET during avalanche must be less than the rated energy absorption limit of the power MOSFET. Also, the maximum simultaneous drain-source voltage and drain current that the power MOSFET can handle must be adjusted for different operating conditions such as case temperature. Thus, it can be seen a "gate shaping" SOA locus 16 using the above described existing method constrains the SOA locus 12 of the power MOSFET. For clamped loads, such as the above described existing example, it can be seen from Figure 1 that a "clamping" SOA locus 14 also constrains the SOA locus 12 of the power MOSFET but peak power is only minimised in extreme C:\pof\ord\SPCN-969363.docx 3 cases of operation where, for instance, battery voltage increases towards the MOSFET maximum drain-source voltage. It can also be seen that power is constrained using the "gate shaping" method over a greater range of operating conditions than the "clamping" method. Nonetheless, peak power, when drain current and drain-source voltage is at peak levels, is not significantly constrained. [0007] Also, it can be seen from both "clamping" 14 and "gate shaping" 16 loci of Figure 1 that the drain current (Id) is constrained to the initial drain current (Id(initial)) 18 and when there is no drain current across the power MOSFET the drain-source voltage is the source voltage (e.g. battery voltage) (Vbat) 20. Nonetheless, there exists a need to further constrain a SOA for a power semiconductor device across, for example, a greater range of operating conditions to better protect it from peak loads and avalanche induced failure. [0008] The discussion of the background to the invention herein is included to explain the invention. This is not to be taken as an admission that the referenced existing examples were published, known or part of the common general knowledge at the priority date of this application. Summary of Invention [0009] According to one aspect of the present invention, there is provided a method of constraining a Safe Operating Area (SOA) locus for a power semiconductor device during operation of the power semiconductor device placed between a power source and a load, the method including: taking a voltage measurement across the load (VLOAD); selecting a scalar for scaling the voltage measurement taken across the load (VLOAD); and constructing a control voltage for controlling the power semiconductor device with a control circuit according to the voltage measurement taken across the load (VLOAD) multiplied by the scalar so as to constrain an output voltage of the power semiconductor. C:\pof\ord\SPCN-969363.docx 4 [0010] Preferably, the power semiconductor device is a power metal oxide semi conductor field effect transistor (MOSFET) that is used to switch loads in, for instance, automotive starter motor control applications. Indeed, the power semiconductor device is, preferably, an N-Channel Enhancement-Mode Power MOSFET in a high side configuration between the power source and an inductive load such as a starter motor. The control voltage of the power MOSFET thus constrains the output voltage of the power MOSFET so as to constrain the SOA of the power MOSFET to maximise its lifetime. That is, the number of switching cycles before significant degradation occurs to the power MOSFET is maximised by minimising instances of avalanche stress on the power MOSFET and minimising the peak power produced and/or total energy absorption of the power MOSFET. As such, the SOA is constrained so as to minimally utilise the SOA of the power MOSFET. [0011] It will be appreciated by those persons skilled in the art that the power semiconductor device includes devices such as the power MOSFET, as well as a bipolar junction transistor (BJT), thyristor and an insulated-gate bipolar transistor (IGBT). [0012] In an embodiment, the method further includes selecting a first impedance
(R
1 ) in the control circuit between an output electrode of the power semiconductor device and a control electrode of the power semiconductor device and selecting a second impedance (R 2 ) in the control circuit between an output of the load and the control electrode of the power semiconductor device to form the scalar. [0013] Preferably, the scalar is: -1
(R
2 1 + ) [0014] In another embodiment, the method further includes offsetting the control voltage for the control circuit by adding an offset to the control voltage. In the embodiment, the control circuit further incudes a non-linear element (D1) placed between the load and the control electrode of the power semiconductor device and the offset includes a voltage measurement taken across the non-linear element (Vo 1 ) multiplied by the scalar. C:\pof\ord\SPCN-969363.docx 5 [0015] Accordingly, in the embodiment, the control voltage is: VLOAD
-(R
21 +1)+ VD1-
RJ
1 +i) [0016] With reference to the power MOSFET embodiment, the control voltage is the gate-source voltage (Vgs) of the power MOSFET. The control electrode is the gate electrode of the power MOSFET and the output electrode is the source electrode of the power MOSFET. Also, as will be appreciated, an input electrode of the power semiconductor device, connected to the power source (e.g. battery), is a drain electrode of the power MOSFET. [0017] According to another aspect of the invention, there is provided a control circuit for constraining a Safe Operating Area (SOA) locus for a power semiconductor device during operation of the power semiconductor device placed between a power source and a load, the control circuit including: a first resistor having a first impedance (R 1 ) between an output of the power semiconductor device and a control electrode of the power semiconductor device; and a second resistor having a second impedance (R 2 ) between an output of the load and the control electrode of the power semiconductor device, wherein the first and second impedances form a scalar for scaling a voltage measurement taken across the load (VLOAD), and wherein the control circuit constructs a control voltage for controlling the power semiconductor device according to the voltage measurement taken across the load (VLOAD) multiplied by the scalar so as to constrain an output voltage of the power semiconductor. [0018] Again, with reference to the power MOSFET embodiment, the above control circuit provides a high degree of robustness against erroneous activation by, for example, power supply transients to the power MOSFET. This is achieved by the control circuit having a lack of drain-gate coupling. Also, the constrained SOA locus of the embodiments of the invention is selected, via selection of the first and second C:\pof\ord\SPCN-969363. doc 6 impedances (R 1 & R 2 ), so that the lowest peak power can be achieved for any given power supply input voltage. Also, as will be appreciated, the SOA locus is selected via a selection of R 1 & R2 as a trade-off between peak power dissipation and total energy absorption of the power MOSFET. The reduction in peak power leads to minimisation of physical strain of the semiconductor die and packaging materials of the power MOSFET. Also, the reduction in total energy absorption leads to minimising peak temperatures experienced by the semiconductor die and packaging materials and thus increased lifetime of the power MOSFET. Brief Description of Drawings [0019] Embodiments of the invention will now be described with reference to the attached drawings, in which: [0020] Figure 1 is a graph of a maximum rated forward bias Safe Operating Area (SOA) locus for a power semiconductor device, showing examples of prior art efforts to constrain the SOA locus to protect the power semiconductor device; [0021] Figure 2 is a further graph of the maximum rated forward bias Safe Operating Area (SOA) locus for a power semiconductor device of Figure 1 showing a constrained SOA locus according to an embodiment of the present invention; [0022] Figure 3 is a schematic diagram depicting at least a control circuit for a power MOSFET according to an embodiment of the present invention; [0023] Figure 4 is a further schematic diagram depicting a control circuit for a power MOSFET according to an embodiment of the present invention; and [0024] Figure 5 is a graph depicting drain current and gate-source voltage of a power MOSFET during switching of the power MOSFET according to an embodiment of the present invention. Detailed Description [0025] Referring now to Figure 2, the maximum rated forward bias Safe Operating Area (SOA) locus 12 for a power semiconductor device is shown in graph 22. As described above, the SOA locus 12 represents the maximum simultaneous drain source voltage and drain current that a power MOSFET can handle safely. In an C:\pof\ord\SPCN-969363. doc 7 embodiment of the present invention, the SOA locus 12 is an N-Channel Enhancement-Mode Power MOSFET in a high-side configuration between a power source and a load is constrained to a constrained SOA locus 24. It will be appreciated by those persons skilled in the art that the graph 22 could depict SOA loci for other devices, such as BJTs. Nonetheless, it can be seen that the drain-source voltage of the power MOSFET is constrained and peak power produced and total energy absorption of the power MOSFET is constrained to minimally utilise the SOA of the power MOSFET. [0026] The constrained SOA locus 24 is produced according to the above described method. That is, during operation of the power MOSFET, the method includes taking a voltage measurement across the load (VLOAD), selecting a scalar for scaling the voltage measurement taken across the load (VLOAD), and constructing a control voltage for controlling the power MOSFET with a control circuit, as shown in Figures 3 and 4, according to the voltage measurement taken across the load (VLOAD) multiplied by the scalar so as to constrain an output voltage of the power MOSFET. In Figure 3, a switching circuit 26 for switching a load 28 ON and OFF is provided. As described, the load is a starter motor for a vehicle which is switched with a power MOSFET 30. [0027] The operation of the power MOSFET 30 is controlled by a control circuit 34, which is configured to control supply of electrical power from a battery 32 to the load 28 as well as constraining the SOA locus of the power MOSFET 30 to the constrained SOA locus shown in Figure 2 as described above. Also, in the embodiment shown in Figure 3, the control circuit 34 includes a switch for disenabling the function of constraining the SOA locus of the power MOSFET 30 in certain circumstances. Nonetheless, when enabled, the voltage measurement taken across the load (VLOAD) during operation of the power MOSFET 30 is scaled to construct the control voltage for the power MOSFET 30. The output voltage from the power MOSFET is subtracted from the voltage across the load (VLOAD) and then scaled by a scalar, as described, to construct the control voltage. Thus, the output voltage of the power MOSFET 30 is constrained by a closed loop control circuit. [0028] Figure 4 shows a switching circuit 36 with a control circuit for constraining a SOA locus in further detail than Figure 3. The power MOSFET 1 of the embodiment C:\pof\ord\SPCN-969363.docx 8 shown in Figure 4 is an N-Channel Enhancement-Mode Power MOSFET 1 in a high side configuration between a supply voltage source 4 and an inductive load 5. The N Channel Enhancement-Mode Power MOSFET 1 has a primary gate drive circuit 2 including a DC power supply for providing voltage to switch the MOSFET 1 ON and OFF. It will be appreciated by those persons skilled in the art that the power MOSFET is switched ON when the gate-source voltage exceeds a threshold voltage (VTH) and switched OFF when the gate-source voltage is less than the threshold voltage. Also, when the power MOSFET is switched OFF, inductive energy stored in the load 5 can cause the source voltage of the power MOSFET 1 to fall below the ground potential sufficiently far to induce MOSFET avalanche mode, causing avalanche induced failure of the power MOSFET 1 if the SOA of the power MOSFET 1 is not optimally constrained. The switching circuit 26 thus includes an anti avalanche control circuit 3 for constraining the SOA of the power MOSFET 1. [0029] The operation of the power MOSFET 1 of Figure 4 is now explained with respect to Figure 5. The primary gate drive circuit 2 is switched ON and OFF between CLOSED and OPEN states 38. For example, the MOSFET can be switched at 20Hz and takes 1 microsecond to switch between states. During this time, there is a switching power loss as the MOSFET drain current rises and falls. Accordingly, the MOSFET drain current (Id) 40 passed from drain to source of the power MOSFET 1 is switched ON and rises over time to its maximum value after the primary gate drive circuit 2 is CLOSED and falls over time to zero after the primary gate drive circuit 2 is OPENED. The MOSFET gate-source voltage (Vgs) 42 shows the control voltage controlling the power MOSFET 1 when the primary gate drive circuit 2 is switched both ON and OFF. That is, while the primary gate drive circuit 2 is switched ON, the power MOSFET 1 is in the saturation mode and is controlled by the primary gate drive circuit 2. When the primary gate drive circuit 2 is switched OFF, the power MOSFET 1 enters the linear mode and is controlled by the avalanche control circuit 3. [0030] The anti-avalanche control circuit 3 includes a first resistor (R 1 ) having a first impedance and being placed between the source electrode of the power MOSFET 1 and the gate electrode of the power MOSFET 1. The circuit 3 also includes a second resistor (R 2 ) having a second impedance and being placed between the output of the load 5 and the gate electrode of the power MOSFET 1. As described, the first and second impedances form a scalar for scaling the voltage C:\pof\ord\SPCN-969363. doc 9 measurement taken across the load (VLOAD). In this way, the control circuit 3 can construct a control voltage for controlling the power MOSFET 1 according to the scaled voltage measurement taken across the load 5. Also, the impedances are selected so as to constrain the output voltage of the power MOSFET 1. [0031] Furthermore, the control circuit 3 includes a non-linear element in the form of a diode (D1) and the control voltage is offset by adding an offset to the scaled control voltage. In the embodiment, the offset includes a voltage measurement taken across the diode (D1) multiplied by the scalar so that the control voltage, which is the voltage between the gate and source electrodes of the power MOSFET is: Vos = VLOAD-
(R
2
R
1 + 1 + VD1
-(R
2
R
1 + 1) [0032] Typical parameters for the switching circuit 36 include a battery supply voltage of 12V (Vbat = 12V) and an initial drain current of the power MOSFET 1 of 20A (Id(initial) = 20A). For the power MOSFET 1, the resistance between the source and the drain electrodes of the power MOSFET 1 when it is turn ON is 5mQ (Rds = 5mQ), the minimum gate threshold voltage required between the gate and source electrodes of the power MOSFET 1 to turn it ON is 4V (VTH = 4V), and the transconductance of the power MOSFET 1 is 100AN (gm = 100A/V). [0033] For the power MOSFET 1, as shown in Figure 4, controlled by the anti avalanche control circuit 3 when it is operating in the linear region: Vos = VTH + Id 1/gm - Equation 1 [0034] In the embodiment: I1 = Vg'R1 [0035] Accordingly, in steady state with gate drive switch of the primary gate drive circuit 2 OPEN: I1 = 12 V = 0V - VD1 2
.R
2 = OV - VD1 Vgs-RzR1 C:\pof\ord\SPCN-969363. docx 10 VS V - Vs = -VD1 gs- R2gR1 os = D1 gs- (R2/R1 +1) - Equation 2 [0036] So, substituting equations 1 and 2: V =VLOAD -VD1 s- Vg(R2 R + 1) Vs =VLOAD/ RzR1 + 1 + VD1 -/RzR1 +1 [0037] It can therefore be seen from the equations that the control voltage for the power MOSFET 1 (Vgs) constructed by the control current is formed from a scalar multiplied by the load voltage plus an offset. [0038] Referring back to Figure 2, the constrained SOA 24 is an operating locus for the power MOSFET 1 where peak power is constrained by the initial drain current (Id(initial)) and the maximum drain-source voltage (Vds) of the power MOSFET 1. [0039] The power MOSFET 1 peak operating point at peak Vds is: VdS = Vd - V Vd = Vbat V = -VD1 - (TH + Id- 1/m)- (R2zjR1 + 1) VdS = Vbat + VD1 + (VTH + Id 1/m).- (R2/R + 1) [0040] Thus, using the above described typical parameters: Vds = 12V + VD + (4.2V). (R 2 /R + 1) C:\pof\ord\SPCN-969363.docx 11 [0041] Whilst the invention has been described in conjunction with a limited number of embodiments, it will be appreciated by those skilled in the art that many alternatives, modifications and variations are possible in light of the foregoing description. The present invention is intended to embrace all such alternatives, modifications and variations as may fall within the spirit and scope of the invention as disclosed. C:\pof\ord\SPCN-969363.docx
Claims (10)
1. A method of constraining a Safe Operating Area (SOA) locus for a power semiconductor device during operation of the power semiconductor device placed between a power source and a load, the method including: taking a voltage measurement across the load (VLOAD); selecting a scalar for scaling the voltage measurement taken across the load (VLOAD); and constructing a control voltage for controlling the power semiconductor device with a control circuit according to the voltage measurement taken across the load (VLOAD) multiplied by the scalar so as to constrain an output voltage of the power semiconductor.
2. A method as claimed in claim 1, selecting a first impedance (Ri) in the control circuit between an output electrode of the power semiconductor device and a control electrode of the power semiconductor device and selecting a second impedance (R 2 ) in the control circuit between an output of the load and the control electrode of the power semiconductor device to form the scalar.
3. A method as claimed in claim 2, wherein the scalar is: -1/ /(R2/R1
4. A method as claimed in claim 3, further including offsetting the control voltage for the control circuit by adding an offset to the control voltage.
5. A method as claimed in claim 4, wherein the control circuit further incudes a non-linear element (D1) placed between the load and the control electrode of the power semiconductor device and the offset includes a voltage measurement taken across the non-linear element (VD1) multiplied by the scalar.
6. A method as claimed in claim 5, wherein the control voltage is: C:\po~wodSPCN-969363.docx 13 LOAD D", R, R + R 2 1 +1
7. A method as claimed in any one of claims 1 to 6, wherein the power semiconductor device is an N-Channel Enhancement-Mode Power MOSFET.
8. A control circuit for constraining a Safe Operating Area (SOA) locus for a power semiconductor device during operation of the power semiconductor device placed between a power source and a load, the control circuit including: a first resistor having a first impedance (RI) between an output of the power semiconductor device and a control electrode of the power semiconductor device; and a second resistor having a second impedance (R 2 ) between an output of the load and the control electrode of the power semiconductor device, wherein the first and second impedances form a scalar for scaling a voltage measurement taken across the load (VLOAD), and wherein the control circuit constructs a control voltage for controlling the power semiconductor device according to the voltage measurement taken across the load (VLOAD) multiplied by the scalar so as to constrain an output voltage of the power semiconductor.
9. A control circuit as claimed in claim 8, wherein the control voltage is offset by adding an offset to the control voltage.
10. A control circuit as claimed in claim 9, further including a non-linear element placed between the load and the control electrode of the power semiconductor device, wherein the offset includes a voltage measurement taken across the non linear element multiplied by the scalar. <filenanme>
Priority Applications (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| AU2013205395A AU2013205395B1 (en) | 2013-04-23 | 2013-04-23 | Method of constraining a safe operating area locus for a power semiconductor device |
| DE202014102444.1U DE202014102444U1 (en) | 2013-04-23 | 2014-04-22 | Circuit for limiting a location of a safe work area for a power semiconductor device |
| DE102014005856.5A DE102014005856B4 (en) | 2013-04-23 | 2014-04-22 | Method for restricting a location of a safe work area for a power semiconductor device |
| CN201420339498.XU CN204288036U (en) | 2013-04-23 | 2014-04-23 | The control circuit of the safety operation area track of constraint power semiconductor device |
| FR1453627A FR3004873B1 (en) | 2013-04-23 | 2014-04-23 | METHOD FOR RESTRICTING A SAFE WORK AREA LOCATION FOR A POWER SEMICONDUCTOR DEVICE |
| CN201410286170.0A CN104122921B (en) | 2013-04-23 | 2014-04-23 | Method of constraining a safe operating area locus for a power semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| AU2013205395A AU2013205395B1 (en) | 2013-04-23 | 2013-04-23 | Method of constraining a safe operating area locus for a power semiconductor device |
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| Publication Number | Publication Date |
|---|---|
| AU2013205395B1 true AU2013205395B1 (en) | 2014-01-16 |
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ID=49919067
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|---|---|---|---|
| AU2013205395A Active AU2013205395B1 (en) | 2013-04-23 | 2013-04-23 | Method of constraining a safe operating area locus for a power semiconductor device |
Country Status (4)
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|---|---|
| CN (2) | CN204288036U (en) |
| AU (1) | AU2013205395B1 (en) |
| DE (2) | DE102014005856B4 (en) |
| FR (1) | FR3004873B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016030483A1 (en) * | 2014-08-28 | 2016-03-03 | Ellenberger & Poensgen Gmbh | Electronic circuit breaker |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| AU2013205395B1 (en) * | 2013-04-23 | 2014-01-16 | Robert Bosch (Australia) Pty Ltd | Method of constraining a safe operating area locus for a power semiconductor device |
| US20170222641A1 (en) * | 2016-01-29 | 2017-08-03 | Ford Global Technologies, Llc | Dynamic igbt gate drive to reduce switching loss |
| US10349195B1 (en) * | 2017-12-21 | 2019-07-09 | Harman International Industries, Incorporated | Constrained nonlinear parameter estimation for robust nonlinear loudspeaker modeling for the purpose of smart limiting |
| CN112994128B (en) * | 2019-12-13 | 2023-04-18 | 华润微电子（重庆）有限公司 | Lithium battery protection circuit, protection system, protection module packaging structure and method |
| CN113608089B (en) * | 2021-06-18 | 2023-11-03 | 苏州浪潮智能科技有限公司 | SOA test method, system and device for switching power supply MOS tube and readable storage medium |
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| US5485341A (en) * | 1992-09-21 | 1996-01-16 | Kabushiki Kaisha Toshiba | Power transistor overcurrent protection circuit |
| DE69431521T2 (en) * | 1994-10-27 | 2003-06-05 | Cons Ric Microelettronica | Method and circuit arrangement for transistor protection against switching off and voltage regulator using this method |
| AU2003261089A1 (en) * | 2002-06-26 | 2004-01-19 | Gibson Guitar Corp. | System and method for protecting an audio amplifier output stage power transistor |
| CN101118450B (en) * | 2007-08-08 | 2011-03-30 | 中国航天时代电子公司第七七一研究所 | Returning type current limiting circuit used for linearity voltage stabilizer |
| US8476965B2 (en) * | 2008-03-10 | 2013-07-02 | Atmel Corporation | Method and circuit for an operating area limiter |
| CN101964517A (en) * | 2009-07-21 | 2011-02-02 | 登丰微电子股份有限公司 | Metal oxide semiconductor current limiting circuit, linear voltage regulator and voltage converting circuit |
| AU2013205395B1 (en) * | 2013-04-23 | 2014-01-16 | Robert Bosch (Australia) Pty Ltd | Method of constraining a safe operating area locus for a power semiconductor device |
-
2013
- 2013-04-23 AU AU2013205395A patent/AU2013205395B1/en active Active
-
2014
- 2014-04-22 DE DE102014005856.5A patent/DE102014005856B4/en active Active
- 2014-04-22 DE DE202014102444.1U patent/DE202014102444U1/en not_active Expired - Lifetime
- 2014-04-23 FR FR1453627A patent/FR3004873B1/en active Active
- 2014-04-23 CN CN201420339498.XU patent/CN204288036U/en not_active Expired - Lifetime
- 2014-04-23 CN CN201410286170.0A patent/CN104122921B/en active Active
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| US5581432A (en) * | 1995-07-25 | 1996-12-03 | Motorola, Inc. | Clamp circuit and method for identifying a safe operating area |
| US8299767B1 (en) * | 2006-08-18 | 2012-10-30 | Picor Corporation | Dynamic safe operating area control |
| US20100327828A1 (en) * | 2009-06-30 | 2010-12-30 | Green Solution Technology Co., Ltd. | Mosfet current limiting circuit, linear voltage regulator and voltage converting circuit |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2016030483A1 (en) * | 2014-08-28 | 2016-03-03 | Ellenberger & Poensgen Gmbh | Electronic circuit breaker |
| US10389110B2 (en) | 2014-08-28 | 2019-08-20 | Ellenberger & Poensgen Gmbh | Electronic circuit breaker |
Also Published As
| Publication number | Publication date |
|---|---|
| FR3004873B1 (en) | 2019-05-17 |
| CN204288036U (en) | 2015-04-22 |
| CN104122921A (en) | 2014-10-29 |
| DE202014102444U1 (en) | 2014-10-16 |
| DE102014005856B4 (en) | 2021-05-06 |
| CN104122921B (en) | 2017-01-11 |
| DE102014005856A1 (en) | 2014-10-23 |
| FR3004873A1 (en) | 2014-10-24 |
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