AU2003251186A1 - Delay locked loop for generating multi-phase clocks without voltage-controlled oscillator - Google Patents

Delay locked loop for generating multi-phase clocks without voltage-controlled oscillator

Info

Publication number
AU2003251186A1
AU2003251186A1 AU2003251186A AU2003251186A AU2003251186A1 AU 2003251186 A1 AU2003251186 A1 AU 2003251186A1 AU 2003251186 A AU2003251186 A AU 2003251186A AU 2003251186 A AU2003251186 A AU 2003251186A AU 2003251186 A1 AU2003251186 A1 AU 2003251186A1
Authority
AU
Australia
Prior art keywords
voltage
locked loop
controlled oscillator
delay locked
phase clocks
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2003251186A
Inventor
Kwang Oh Kim
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Dawin Technology Inc
Original Assignee
Dawin Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dawin Technology Inc filed Critical Dawin Technology Inc
Publication of AU2003251186A1 publication Critical patent/AU2003251186A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/089—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses
    • H03L7/0891—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector generating up-down pulses the up-down pulses controlling source and sink current generators, e.g. a charge pump
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0816—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/14—Preventing false-lock or pseudo-lock of the PLL
AU2003251186A 2003-07-23 2003-08-06 Delay locked loop for generating multi-phase clocks without voltage-controlled oscillator Abandoned AU2003251186A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
KR10-2003-0050746 2003-07-23
KR10-2003-0050746A KR100531457B1 (en) 2003-07-23 2003-07-23 Delay Locked Loop For Generating Multi-Phase Clocks Without Voltage-Controlled Oscillator
PCT/KR2003/001581 WO2005008894A1 (en) 2003-07-23 2003-08-06 Delay locked loop for generating multi-phase clocks without voltage-controlled oscillator

Publications (1)

Publication Number Publication Date
AU2003251186A1 true AU2003251186A1 (en) 2005-02-04

Family

ID=34074955

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2003251186A Abandoned AU2003251186A1 (en) 2003-07-23 2003-08-06 Delay locked loop for generating multi-phase clocks without voltage-controlled oscillator

Country Status (3)

Country Link
KR (1) KR100531457B1 (en)
AU (1) AU2003251186A1 (en)
WO (1) WO2005008894A1 (en)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4879569B2 (en) * 2005-11-29 2012-02-22 パナソニック株式会社 Phase adjustment circuit
KR100715154B1 (en) * 2005-12-21 2007-05-10 삼성전자주식회사 Phase locked loop with high locking speed and clock locking method using the same
KR100840697B1 (en) * 2006-10-30 2008-06-24 삼성전자주식회사 Delay-locked loop circuit for generating multi-phase clock signals and method of controlling the same
KR100789408B1 (en) 2006-11-21 2007-12-28 삼성전자주식회사 Delay locked loops circuits and method of generating multiplied clock thereof
KR100892637B1 (en) * 2007-04-13 2009-04-09 주식회사 하이닉스반도체 Clock signal distribution circuit and interface apparatus using the same
KR101202682B1 (en) 2010-06-21 2012-11-19 에스케이하이닉스 주식회사 Phase locked loop
US9793900B1 (en) 2016-06-29 2017-10-17 Microsoft Technology Licensing, Llc Distributed multi-phase clock generator having coupled delay-locked loops
CN115065359B (en) * 2022-08-11 2022-11-04 睿力集成电路有限公司 Delay-locked loop, clock synchronization circuit and memory

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4425426B2 (en) * 2000-05-11 2010-03-03 Ｎｅｃエレクトロニクス株式会社 Oversampling clock recovery circuit
KR100446291B1 (en) * 2001-11-07 2004-09-01 삼성전자주식회사 Delay locked loop circuit capable of adjusting locking resolution using CAS latency

Also Published As

Publication number Publication date
KR100531457B1 (en) 2005-11-28
KR20050011586A (en) 2005-01-29
WO2005008894A1 (en) 2005-01-27

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase