AU2003225292A1 - Ferroelectric memory - Google Patents
Ferroelectric memoryInfo
- Publication number
- AU2003225292A1 AU2003225292A1 AU2003225292A AU2003225292A AU2003225292A1 AU 2003225292 A1 AU2003225292 A1 AU 2003225292A1 AU 2003225292 A AU2003225292 A AU 2003225292A AU 2003225292 A AU2003225292 A AU 2003225292A AU 2003225292 A1 AU2003225292 A1 AU 2003225292A1
- Authority
- AU
- Australia
- Prior art keywords
- cell
- bit lines
- bit
- memory
- line
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Dram (AREA)
- Semiconductor Memories (AREA)
- Inorganic Insulating Materials (AREA)
Abstract
A ferroelectric memory including a bit line pair, a drive line parallel to and located between the bit lines, and an associated memory cell. The memory cell includes two capacitors, each capacitor connected to one of said bit lines via a transistor, and each capacitor is also connected to the drive line via a transistor. The gates of all three of the transistors are connected to a word line perpendicular to the bit lines and drive line, so that when the word line is not selected, the capacitors are completely isolated from any disturb. The bit lines may be complementary and the cell a one-bit cell, or the cell may be a two-bit cell. In the latter case, the memory includes a dummy cell identical to the above cell, in which the two dummy capacitors are complementary. A sense amplifier with three bit line inputs compares the cell bit line with a signal derived from the two dummy bit lines. The logic states of the dummy capacitors alternate in each cycle, preventing imprint and fatigue. The bit lines are partitioned into a plurality of second level bit lines, each connected to a top level bit line via a group select transistor. The memory includes a plurality of such cells, divided into groups, each group connected to one of the second level bit lines. The memory cells are read with a non-destructive read out method that differentiates between the different capacitances of a ferroelectric capacitor in different ferroelectric polarization states.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/139,426 US6809949B2 (en) | 2002-05-06 | 2002-05-06 | Ferroelectric memory |
US10/139,426 | 2002-05-06 | ||
PCT/US2003/014015 WO2003096352A2 (en) | 2002-05-06 | 2003-05-05 | Ferroelectric memory |
Publications (2)
Publication Number | Publication Date |
---|---|
AU2003225292A1 true AU2003225292A1 (en) | 2003-11-11 |
AU2003225292A8 AU2003225292A8 (en) | 2003-11-11 |
Family
ID=29269544
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU2003225292A Abandoned AU2003225292A1 (en) | 2002-05-06 | 2003-05-05 | Ferroelectric memory |
Country Status (11)
Country | Link |
---|---|
US (2) | US6809949B2 (en) |
EP (1) | EP1502265B1 (en) |
JP (1) | JP2005530283A (en) |
KR (1) | KR20050025176A (en) |
CN (1) | CN100533590C (en) |
AT (1) | ATE344525T1 (en) |
AU (1) | AU2003225292A1 (en) |
DE (1) | DE60309461T2 (en) |
HK (1) | HK1081320A1 (en) |
TW (1) | TWI301271B (en) |
WO (1) | WO2003096352A2 (en) |
Families Citing this family (58)
Publication number | Priority date | Publication date | Assignee | Title |
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US6822891B1 (en) * | 2003-06-16 | 2004-11-23 | Kabushiki Kaisha Toshiba | Ferroelectric memory device |
US7193880B2 (en) * | 2004-06-14 | 2007-03-20 | Texas Instruments Incorporated | Plateline voltage pulsing to reduce storage node disturbance in ferroelectric memory |
JP3970259B2 (en) * | 2003-09-11 | 2007-09-05 | 三洋電機株式会社 | memory |
JP4074279B2 (en) * | 2003-09-22 | 2008-04-09 | 株式会社東芝 | Semiconductor integrated circuit device, digital camera, digital video camera, computer system, portable computer system, logic variable LSI device, IC card, navigation system, robot, image display device, optical disk storage device |
KR100583112B1 (en) * | 2003-11-27 | 2006-05-23 | 주식회사 하이닉스반도체 | FeRAM having single ended sensing architecture |
US7099179B2 (en) * | 2003-12-22 | 2006-08-29 | Unity Semiconductor Corporation | Conductive memory array having page mode and burst mode write capability |
US7009864B2 (en) * | 2003-12-29 | 2006-03-07 | Texas Instruments Incorporated | Zero cancellation scheme to reduce plateline voltage in ferroelectric memory |
WO2005078732A1 (en) * | 2004-02-05 | 2005-08-25 | Iota Technology, Inc. | Electronic memory with tri-level cell pair |
US7352619B2 (en) * | 2004-02-05 | 2008-04-01 | Iota Technology, Inc. | Electronic memory with binary storage elements |
US7133304B2 (en) * | 2004-03-22 | 2006-11-07 | Texas Instruments Incorporated | Method and apparatus to reduce storage node disturbance in ferroelectric memory |
NO322040B1 (en) * | 2004-04-15 | 2006-08-07 | Thin Film Electronics Asa | Bimodal operation of ferroelectric and electret memory cells and devices |
US6970371B1 (en) * | 2004-05-17 | 2005-11-29 | Texas Instruments Incorporated | Reference generator system and methods for reading ferroelectric memory cells using reduced bitline voltages |
US20050274396A1 (en) * | 2004-06-09 | 2005-12-15 | Hong Shih | Methods for wet cleaning quartz surfaces of components for plasma processing chambers |
US7472309B2 (en) * | 2004-12-22 | 2008-12-30 | Intel Corporation | Methods and apparatus to write a file to a nonvolatile memory |
EP1833091A4 (en) * | 2004-12-28 | 2008-08-13 | Spansion Llc | Semiconductor device and operation control method for same |
JP4912016B2 (en) * | 2005-05-23 | 2012-04-04 | ルネサスエレクトロニクス株式会社 | Semiconductor memory device |
US20070190670A1 (en) * | 2006-02-10 | 2007-08-16 | Forest Carl A | Method of making ferroelectric and dielectric layered superlattice materials and memories utilizing same |
US7561458B2 (en) * | 2006-12-26 | 2009-07-14 | Texas Instruments Incorporated | Ferroelectric memory array for implementing a zero cancellation scheme to reduce plateline voltage in ferroelectric memory |
KR100866751B1 (en) * | 2006-12-27 | 2008-11-03 | 주식회사 하이닉스반도체 | Semiconductor memory device with ferroelectric device and method for refresh thereof |
KR100866705B1 (en) * | 2007-07-04 | 2008-11-03 | 주식회사 하이닉스반도체 | Semiconductor memory device with ferroelectric device |
KR100849794B1 (en) | 2007-07-04 | 2008-07-31 | 주식회사 하이닉스반도체 | Semiconductor memory device with ferroelectric device |
JP2009043307A (en) * | 2007-08-06 | 2009-02-26 | Toshiba Corp | Semiconductor storage device |
US7920404B2 (en) * | 2007-12-31 | 2011-04-05 | Texas Instruments Incorporated | Ferroelectric memory devices with partitioned platelines |
US8130559B1 (en) | 2008-08-06 | 2012-03-06 | Altera Corporation | MEMS switching device and conductive bridge device based circuits |
US7898837B2 (en) * | 2009-07-22 | 2011-03-01 | Texas Instruments Incorporated | F-SRAM power-off operation |
CN101819811B (en) * | 2010-03-31 | 2013-10-16 | 清华大学 | Three-value FeRAM circuit |
JP6030298B2 (en) * | 2010-12-28 | 2016-11-24 | 株式会社半導体エネルギー研究所 | Buffer storage device and signal processing circuit |
JP5673414B2 (en) * | 2011-07-20 | 2015-02-18 | 富士通セミコンダクター株式会社 | Manufacturing method of semiconductor device |
US8756558B2 (en) * | 2012-03-30 | 2014-06-17 | Texas Instruments Incorporated | FRAM compiler and layout |
US20140029326A1 (en) * | 2012-07-26 | 2014-01-30 | Texas Instruments Incorporated | Ferroelectric random access memory with a non-destructive read |
KR102330412B1 (en) * | 2014-04-25 | 2021-11-25 | 가부시키가이샤 한도오따이 에네루기 켄큐쇼 | Semiconductor device, electronic component, and electronic device |
US9767879B2 (en) * | 2015-02-17 | 2017-09-19 | Texas Instruments Incorporated | Setting of reference voltage for data sensing in ferroelectric memories |
US9460770B1 (en) | 2015-09-01 | 2016-10-04 | Micron Technology, Inc. | Methods of operating ferroelectric memory cells, and related ferroelectric memory cells |
US9443576B1 (en) * | 2015-11-09 | 2016-09-13 | Microsoft Technology Licensing, Llc | Josephson magnetic random access memory with an inductive-shunt |
US9786347B1 (en) * | 2016-03-16 | 2017-10-10 | Micron Technology, Inc. | Cell-specific reference generation and sensing |
US9721639B1 (en) * | 2016-06-21 | 2017-08-01 | Micron Technology, Inc. | Memory cell imprint avoidance |
KR102369776B1 (en) | 2016-08-31 | 2022-03-03 | 마이크론 테크놀로지, 인크. | Ferroelectric memory cells |
KR102314663B1 (en) | 2016-08-31 | 2021-10-21 | 마이크론 테크놀로지, 인크. | Apparatus and method for including and accessing a 2 transistor-1 capacitor memory |
EP3507805A4 (en) | 2016-08-31 | 2020-06-03 | Micron Technology, Inc. | Apparatuses and methods including ferroelectric memory and for operating ferroelectric memory |
EP3507806B1 (en) | 2016-08-31 | 2022-01-19 | Micron Technology, Inc. | Apparatuses and methods including ferroelectric memory and for accessing ferroelectric memory |
US10418084B2 (en) * | 2017-02-07 | 2019-09-17 | Micron Technology, Inc. | Pre-writing memory cells of an array |
JP6915372B2 (en) * | 2017-05-16 | 2021-08-04 | 富士通株式会社 | Error correction method for memory cells, memory modules, information processing devices, and memory cells |
US10867675B2 (en) | 2017-07-13 | 2020-12-15 | Micron Technology, Inc. | Apparatuses and methods for memory including ferroelectric memory cells and dielectric memory cells |
US10163480B1 (en) * | 2017-07-27 | 2018-12-25 | Micron Technology, Inc. | Periphery fill and localized capacitance |
US10032496B1 (en) | 2017-07-27 | 2018-07-24 | Micron Technology, Inc. | Variable filter capacitance |
US10410721B2 (en) * | 2017-11-22 | 2019-09-10 | Micron Technology, Inc. | Pulsed integrator and memory techniques |
US11139310B2 (en) * | 2017-12-04 | 2021-10-05 | Sony Semiconductor Solutions Corporation | Semiconductor memory device, electronic apparatus, and method of reading data |
US10622050B2 (en) | 2018-05-09 | 2020-04-14 | Micron Technology, Inc. | Ferroelectric memory plate power reduction |
US10825513B2 (en) * | 2018-06-26 | 2020-11-03 | Sandisk Technologies Llc | Parasitic noise control during sense operations |
US11482529B2 (en) | 2019-02-27 | 2022-10-25 | Kepler Computing Inc. | High-density low voltage non-volatile memory with unidirectional plate-line and bit-line and pillar capacitor |
CN110428857B (en) * | 2019-07-09 | 2021-09-24 | 清华大学 | Memory based on hysteresis characteristic device |
CN111292782B (en) * | 2019-10-21 | 2021-11-02 | 北京潼荔科技有限公司 | Non-volatile random access memory and access method |
US11729989B2 (en) * | 2020-01-06 | 2023-08-15 | Iu-Meng Tom Ho | Depletion mode ferroelectric transistors |
US11527277B1 (en) | 2021-06-04 | 2022-12-13 | Kepler Computing Inc. | High-density low voltage ferroelectric memory bit-cell |
US20230051863A1 (en) * | 2021-08-10 | 2023-02-16 | Micron Technology, Inc. | Memory device for wafer-on-wafer formed memory and logic |
US11737283B1 (en) | 2021-11-01 | 2023-08-22 | Kepler Computing Inc. | Method of forming a stack of non-planar capacitors including capacitors with non-linear polar material and linear dielectric for common mode compensation in a memory bit-cell |
US11482270B1 (en) * | 2021-11-17 | 2022-10-25 | Kepler Computing Inc. | Pulsing scheme for a ferroelectric memory bit-cell to minimize read or write disturb effect and refresh logic |
US11997853B1 (en) | 2022-03-07 | 2024-05-28 | Kepler Computing Inc. | 1TnC memory bit-cell having stacked and folded planar capacitors with lateral offset |
Family Cites Families (28)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4873664A (en) | 1987-02-12 | 1989-10-10 | Ramtron Corporation | Self restoring ferroelectric memory |
US4888733A (en) | 1988-09-12 | 1989-12-19 | Ramtron Corporation | Non-volatile memory cell and sensing method |
US5038323A (en) | 1990-03-06 | 1991-08-06 | The United States Of America As Represented By The Secretary Of The Navy | Non-volatile memory cell with ferroelectric capacitor having logically inactive electrode |
US5262982A (en) | 1991-07-18 | 1993-11-16 | National Semiconductor Corporation | Nondestructive reading of a ferroelectric capacitor |
US5666305A (en) * | 1993-03-29 | 1997-09-09 | Olympus Optical Co., Ltd. | Method of driving ferroelectric gate transistor memory cell |
US5373463A (en) * | 1993-07-06 | 1994-12-13 | Motorola Inc. | Ferroelectric nonvolatile random access memory having drive line segments |
US5406510A (en) | 1993-07-15 | 1995-04-11 | Symetrix Corporation | Non-volatile memory |
JP3218844B2 (en) | 1994-03-22 | 2001-10-15 | 松下電器産業株式会社 | Semiconductor memory device |
EP1069573B1 (en) | 1995-08-02 | 2003-04-23 | Matsushita Electric Industrial Co., Ltd | Ferroelectric memory device with reset circuit |
US5598366A (en) | 1995-08-16 | 1997-01-28 | Ramtron International Corporation | Ferroelectric nonvolatile random access memory utilizing self-bootstrapping plate line segment drivers |
SG79200A1 (en) | 1995-08-21 | 2001-03-20 | Matsushita Electric Ind Co Ltd | Ferroelectric memory devices and method for testing them |
DE69736080T2 (en) * | 1996-03-25 | 2006-10-19 | Matsushita Electric Industrial Co., Ltd., Kadoma | Ferroelekrische storage arrangement |
US5737260A (en) | 1996-03-27 | 1998-04-07 | Sharp Kabushiki Kaisha | Dual mode ferroelectric memory reference scheme |
KR100206713B1 (en) | 1996-10-09 | 1999-07-01 | 윤종용 | Nondestructive accessing method of ferroelectric memory device and its accessing circuit |
US5966318A (en) * | 1996-12-17 | 1999-10-12 | Raytheon Company | Nondestructive readout memory utilizing ferroelectric capacitors isolated from bitlines by buffer amplifiers |
JP3495905B2 (en) | 1998-02-19 | 2004-02-09 | シャープ株式会社 | Semiconductor storage device |
KR100268947B1 (en) | 1998-04-03 | 2000-10-16 | 김영환 | Nonvolatile ferroelectric memory and control circuot of the same |
KR100281125B1 (en) | 1998-12-29 | 2001-03-02 | 김영환 | Nonvolatile Ferroelectric Memory Device |
KR100363102B1 (en) * | 1998-07-15 | 2003-02-19 | 주식회사 하이닉스반도체 | Ferroelectric memory |
US5995407A (en) | 1998-10-13 | 1999-11-30 | Celis Semiconductor Corporation | Self-referencing ferroelectric memory |
US6147895A (en) * | 1999-06-04 | 2000-11-14 | Celis Semiconductor Corporation | Ferroelectric memory with two ferroelectric capacitors in memory cell and method of operating same |
US6330180B2 (en) * | 2000-03-24 | 2001-12-11 | Fujitsu Limited | Semiconductor memory device with reduced power consumption and with reduced test time |
JP2001319472A (en) * | 2000-05-10 | 2001-11-16 | Toshiba Corp | Semiconductor memory |
CN1236452C (en) * | 2000-09-25 | 2006-01-11 | 塞姆特里克斯公司 | Ferroelectric memory and method of operating same |
JP2002109875A (en) * | 2000-09-29 | 2002-04-12 | Nec Corp | Shadow ram cell using ferroelectric capacitor, and nonvolatile memory device and its control method |
KR100428652B1 (en) * | 2001-03-28 | 2004-04-29 | 주식회사 하이닉스반도체 | FeRAM FOR HAVING ADJACENT CELLS SHARING CELL PLATE |
US6522570B1 (en) * | 2001-12-13 | 2003-02-18 | Micron Technology, Inc. | System and method for inhibiting imprinting of capacitor structures of a memory |
US6873536B2 (en) * | 2002-04-19 | 2005-03-29 | Texas Instruments Incorporated | Shared data buffer in FeRAM utilizing word line direction segmentation |
-
2002
- 2002-05-06 US US10/139,426 patent/US6809949B2/en not_active Expired - Lifetime
-
2003
- 2003-05-05 KR KR1020047017893A patent/KR20050025176A/en not_active Application Discontinuation
- 2003-05-05 CN CNB038159813A patent/CN100533590C/en not_active Expired - Fee Related
- 2003-05-05 EP EP03722013A patent/EP1502265B1/en not_active Expired - Lifetime
- 2003-05-05 DE DE60309461T patent/DE60309461T2/en not_active Expired - Fee Related
- 2003-05-05 JP JP2004504239A patent/JP2005530283A/en active Pending
- 2003-05-05 AT AT03722013T patent/ATE344525T1/en not_active IP Right Cessation
- 2003-05-05 WO PCT/US2003/014015 patent/WO2003096352A2/en active IP Right Grant
- 2003-05-05 AU AU2003225292A patent/AU2003225292A1/en not_active Abandoned
- 2003-05-06 TW TW092112308A patent/TWI301271B/en not_active IP Right Cessation
- 2003-11-10 US US10/704,847 patent/US7212427B2/en not_active Expired - Lifetime
-
2006
- 2006-01-27 HK HK06101273.0A patent/HK1081320A1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
CN100533590C (en) | 2009-08-26 |
HK1081320A1 (en) | 2006-05-12 |
JP2005530283A (en) | 2005-10-06 |
CN1666293A (en) | 2005-09-07 |
TWI301271B (en) | 2008-09-21 |
EP1502265A2 (en) | 2005-02-02 |
TW200400509A (en) | 2004-01-01 |
US7212427B2 (en) | 2007-05-01 |
DE60309461D1 (en) | 2006-12-14 |
US20030206430A1 (en) | 2003-11-06 |
AU2003225292A8 (en) | 2003-11-11 |
US6809949B2 (en) | 2004-10-26 |
WO2003096352A3 (en) | 2004-06-24 |
US20040105296A1 (en) | 2004-06-03 |
WO2003096352A2 (en) | 2003-11-20 |
EP1502265B1 (en) | 2006-11-02 |
KR20050025176A (en) | 2005-03-11 |
ATE344525T1 (en) | 2006-11-15 |
DE60309461T2 (en) | 2007-09-20 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MK6 | Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase | ||
TH | Corrigenda |
Free format text: IN VOL 18, NO 2, PAGE(S) 590 UNDER THE HEADING APPLICATIONS OPI - NAME INDEX UNDER THE NAME SYMETRIX CORPORATION, APPLICATION NO. 2003225292, UNDER INID (71) CORRECT THE NAME TO READ SYMETRIX CORPORATION; IOTA TECHNOLOGY, INC. |
|
TH | Corrigenda |
Free format text: IN VOL 18, NO 2, PAGE(S) 590 UNDER THE HEADING APPLICATIONS OPI - NAME INDEX UNDER THE NAME IOTA TECHNOLOGY, INC. AND SYMETRIX CORPORATION, APPLICATION NO. 2003225292, UNDER INID (43) CORRECT THE PUBLICATION DATE TO READ 24.11.2003 |