AU2002356823A1 - Method of manufacture of a multi-layered substrate with a thin single crystalline layer - Google Patents

Method of manufacture of a multi-layered substrate with a thin single crystalline layer

Info

Publication number
AU2002356823A1
AU2002356823A1 AU2002356823A AU2002356823A AU2002356823A1 AU 2002356823 A1 AU2002356823 A1 AU 2002356823A1 AU 2002356823 A AU2002356823 A AU 2002356823A AU 2002356823 A AU2002356823 A AU 2002356823A AU 2002356823 A1 AU2002356823 A1 AU 2002356823A1
Authority
AU
Australia
Prior art keywords
manufacture
single crystalline
crystalline layer
layered substrate
thin single
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002356823A
Inventor
William Carr
Alexander Usenko
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Individual
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US10/202,566 external-priority patent/US6696352B1/en
Application filed by Individual filed Critical Individual
Publication of AU2002356823A1 publication Critical patent/AU2002356823A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67132Apparatus for placing on an insulating substrate, e.g. tape
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00349Creating layers of material on a substrate
    • B81C1/00357Creating layers of material on a substrate involving bonding one or several substrates on a non-temporary support, e.g. another substrate
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00436Shaping materials, i.e. techniques for structuring the substrate or the layers on the substrate
    • B81C1/005Bulk micromachining
    • B81C1/00507Formation of buried layers by techniques other than deposition, e.g. by deep implantation of elements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3223Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering using cavities formed by hydrogen or noble gas ion implantation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00Manufacture or treatment of microstructural devices or systems
    • B81C2201/01Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0174Manufacture or treatment of microstructural devices or systems in or on a substrate for making multi-layered devices, film deposition or growing
    • B81C2201/019Bonding or gluing multiple substrate layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
AU2002356823A 2002-07-24 2002-10-18 Method of manufacture of a multi-layered substrate with a thin single crystalline layer Abandoned AU2002356823A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/202,566 2002-07-24
US10/202,566 US6696352B1 (en) 2001-09-11 2002-07-24 Method of manufacture of a multi-layered substrate with a thin single crystalline layer and a versatile sacrificial layer
PCT/US2002/033278 WO2004010481A1 (en) 2002-07-24 2002-10-18 Method of manufacture of a multi-layered substrate with a thin single crystalline layer

Publications (1)

Publication Number Publication Date
AU2002356823A1 true AU2002356823A1 (en) 2004-02-09

Family

ID=30769855

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002356823A Abandoned AU2002356823A1 (en) 2002-07-24 2002-10-18 Method of manufacture of a multi-layered substrate with a thin single crystalline layer

Country Status (2)

Country Link
AU (1) AU2002356823A1 (en)
WO (1) WO2004010481A1 (en)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102004007060B3 (en) 2004-02-13 2005-07-07 Thallner, Erich, Dipl.-Ing. Semiconductor wafer bonding device using application of adhesive before alignment and contacting of corresponding surfaces of semiconductor wafers
FR2905801B1 (en) * 2006-09-12 2008-12-05 Soitec Silicon On Insulator METHOD FOR TRANSFERRING A HIGH TEMPERATURE LAYER
US8324031B2 (en) 2008-06-24 2012-12-04 Globalfoundries Singapore Pte. Ltd. Diffusion barrier and method of formation thereof
FR2978603B1 (en) 2011-07-28 2013-08-23 Soitec Silicon On Insulator METHOD FOR TRANSFERRING A MONOCRYSTALLINE SEMICONDUCTOR LAYER TO A SUPPORT SUBSTRATE

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3112106B2 (en) * 1991-10-11 2000-11-27 キヤノン株式会社 Manufacturing method of semiconductor substrate
US5877070A (en) * 1997-05-31 1999-03-02 Max-Planck Society Method for the transfer of thin layers of monocrystalline material to a desirable substrate
JPH1126733A (en) * 1997-07-03 1999-01-29 Seiko Epson Corp Transfer method of thin film device, thin film device, thin film integrated circuit device, active matrix substrate, liquid crystal display and electronic equipment
US6423614B1 (en) * 1998-06-30 2002-07-23 Intel Corporation Method of delaminating a thin film using non-thermal techniques

Also Published As

Publication number Publication date
WO2004010481A1 (en) 2004-01-29

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase