AU2002344110A1 - Processor having multi-bank register and processor control method - Google Patents

Processor having multi-bank register and processor control method

Info

Publication number
AU2002344110A1
AU2002344110A1 AU2002344110A AU2002344110A AU2002344110A1 AU 2002344110 A1 AU2002344110 A1 AU 2002344110A1 AU 2002344110 A AU2002344110 A AU 2002344110A AU 2002344110 A AU2002344110 A AU 2002344110A AU 2002344110 A1 AU2002344110 A1 AU 2002344110A1
Authority
AU
Australia
Prior art keywords
processor
control method
bank register
processor control
bank
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002344110A
Inventor
Yuko Matsumoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Tops Systems Corp
Original Assignee
Tops Systems Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tops Systems Corp filed Critical Tops Systems Corp
Publication of AU2002344110A1 publication Critical patent/AU2002344110A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30098—Register arrangements
    • G06F9/3012—Organisation of register space, e.g. banked or distributed register file

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
AU2002344110A 2002-10-18 2002-10-18 Processor having multi-bank register and processor control method Abandoned AU2002344110A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/JP2002/010832 WO2004036416A1 (en) 2002-10-18 2002-10-18 Processor having multi-bank register and processor control method

Publications (1)

Publication Number Publication Date
AU2002344110A1 true AU2002344110A1 (en) 2004-05-04

Family

ID=32104835

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002344110A Abandoned AU2002344110A1 (en) 2002-10-18 2002-10-18 Processor having multi-bank register and processor control method

Country Status (3)

Country Link
JP (1) JP3958320B2 (en)
AU (1) AU2002344110A1 (en)
WO (1) WO2004036416A1 (en)

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5696353A (en) * 1979-12-12 1981-08-04 Mitsubishi Electric Corp Multiprocessor control device
JPS62154166A (en) * 1985-12-27 1987-07-09 Matsushita Electric Ind Co Ltd Microcomputer
JP2551167B2 (en) * 1989-06-19 1996-11-06 日本電気株式会社 Microcomputer
KR920008597A (en) * 1990-10-31 1992-05-28 가나이 쯔또무 Micro computer
JPH04195226A (en) * 1990-11-22 1992-07-15 Toshiba Corp Parallel processing microprocessor
JP3511529B2 (en) * 1994-09-13 2004-03-29 松下電器産業株式会社 Complex arithmetic processing unit
US5680641A (en) * 1995-08-16 1997-10-21 Sharp Microelectronics Technology, Inc. Multiple register bank system for concurrent I/O operation in a CPU datapath
JPH1011352A (en) * 1996-06-19 1998-01-16 Hitachi Ltd Data processor and its register address converting method
JPH1091430A (en) * 1996-09-13 1998-04-10 Matsushita Electric Ind Co Ltd Instruction decoding device

Also Published As

Publication number Publication date
WO2004036416A1 (en) 2004-04-29
JPWO2004036416A1 (en) 2006-02-16
JP3958320B2 (en) 2007-08-15

Similar Documents

Publication Publication Date Title
AU2003248675A1 (en) Gaming system and method
AU2003282580A1 (en) Contrast therapy system and method
AU2003206526A1 (en) Predictive control system and method
GB0228219D0 (en) Collusion detection and control
AU2003279950A1 (en) System and method for providing access control
AU2003292421A1 (en) System and method for data prefetching
AU2003272596A1 (en) Non-volatile memory and its sensing method
AU2003260957A1 (en) General drive control system and general drive control method
AU2003244310A1 (en) Inter-authentication method and device
AU2003291684A1 (en) Financial account transferapparatus and method
AU2003266616A1 (en) Test system and control method thereof
AU2003209365A1 (en) Method and apparatus to control memory accesses
AU2003277407A1 (en) Non-intrusive sensor and method
AU2003273033A1 (en) Information processor and program
AU2003245157A1 (en) Telehealth system and method
AU2002351206A1 (en) Lateral lubistor structure and method
AU2003218434A1 (en) Hardware-translator-based custom method invocation system and method
AU2003287182A1 (en) Nanomotion sensing system and method
AU2003221002A1 (en) Ultrasonic telediagnosis/teletreatment method and ultrasonic telediagnosis/teletreatment system
AU2003253830A1 (en) Application modification system and method
AU2003219438A1 (en) Signal processing method and arrangement
AU2003245214A1 (en) Learning system and method
AU2003271690A1 (en) Access control unit and method for carrying out said method
AU2003235298A1 (en) Magnetic memory and its operating method
AU2003262734A1 (en) Neuro-mimetic control systems and methods

Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase