AU2002223720A1 - Method and system for adjusting the step clock of a delta-sigma transformer and/or switched capacitor filter - Google Patents

Method and system for adjusting the step clock of a delta-sigma transformer and/or switched capacitor filter

Info

Publication number
AU2002223720A1
AU2002223720A1 AU2002223720A AU2372002A AU2002223720A1 AU 2002223720 A1 AU2002223720 A1 AU 2002223720A1 AU 2002223720 A AU2002223720 A AU 2002223720A AU 2372002 A AU2372002 A AU 2372002A AU 2002223720 A1 AU2002223720 A1 AU 2002223720A1
Authority
AU
Australia
Prior art keywords
delta
sigma
transformer
adjusting
switched capacitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002223720A
Inventor
Heikki Laamanen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infinera Oy
Original Assignee
Tellabs Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tellabs Oy filed Critical Tellabs Oy
Publication of AU2002223720A1 publication Critical patent/AU2002223720A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
    • H03L7/0991—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider
    • H03L7/0992—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider
    • H03L7/0993—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider comprising a counter or a frequency divider and a circuit for adding and deleting pulses
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/322—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M3/368—Continuously compensating for, or preventing, undesired influence of physical parameters of noise other than the quantisation noise already being shaped inherently by delta-sigma modulators
    • H03M3/37—Compensation or reduction of delay or phase error
    • H03M3/372—Jitter reduction
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H19/00—Networks using time-varying elements, e.g. N-path filters
    • H03H19/004—Switched capacitor networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M3/00—Conversion of analogue values to or from differential modulation
    • H03M3/30—Delta-sigma modulation
    • H03M3/458—Analogue/digital converters using delta-sigma modulation as an intermediate step
    • H03M3/494—Sampling or signal conditioning arrangements specially adapted for delta-sigma type analogue/digital conversion systems
    • H03M3/496—Details of sampling arrangements or methods
    • H03M3/498—Variable sample rate

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Compression, Expansion, Code Conversion, And Decoders (AREA)
  • Filters That Use Time-Delay Elements (AREA)
AU2002223720A 2000-11-22 2001-11-22 Method and system for adjusting the step clock of a delta-sigma transformer and/or switched capacitor filter Abandoned AU2002223720A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FI20002564 2000-11-22
FI20002564A FI109384B (en) 2000-11-22 2000-11-22 Method and system for digitally adjusting the step clock of a delta sigma converter and / or switched capacitor filter
PCT/FI2001/001018 WO2002043247A1 (en) 2000-11-22 2001-11-22 Method and system for adjusting the step clock of a delta-sigma transformer and/or switched capacitor filter

Publications (1)

Publication Number Publication Date
AU2002223720A1 true AU2002223720A1 (en) 2002-06-03

Family

ID=8559555

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002223720A Abandoned AU2002223720A1 (en) 2000-11-22 2001-11-22 Method and system for adjusting the step clock of a delta-sigma transformer and/or switched capacitor filter

Country Status (4)

Country Link
US (1) US6940435B2 (en)
AU (1) AU2002223720A1 (en)
FI (1) FI109384B (en)
WO (1) WO2002043247A1 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7379831B1 (en) 2004-05-12 2008-05-27 Zilog, Inc. Error correction in an oversampled ADC using few stored calibration coefficients
US6993441B1 (en) * 2004-05-12 2006-01-31 Zilog, Inc. Adaptive error correction in an oversampled ADC
DE102006054776B4 (en) * 2006-11-17 2010-03-18 Ihp Gmbh - Innovations For High Performance Microelectronics / Leibniz-Institut Für Innovative Mikroelektronik Apparatus and method for sigma-delta modulation
US7382300B1 (en) * 2006-11-29 2008-06-03 Cirrus Logic, Inc. System-on-chip (SoC) integrated circuit including interleaved delta-sigma analog-to-digital converter (ADC)
US7782237B2 (en) * 2008-06-13 2010-08-24 The Board Of Trustees Of The Leland Stanford Junior University Semiconductor sensor circuit arrangement
CN101610086B (en) * 2008-06-20 2014-11-26 瑞昱半导体股份有限公司 Integral triangle modulator capable of controlling output speed and interrelated method thereof

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4965531A (en) * 1989-11-22 1990-10-23 Carleton University Frequency synthesizers having dividing ratio controlled by sigma-delta modulator
US5349352A (en) * 1992-12-21 1994-09-20 Harris Corporation Analog-to-digital converter having high AC line noise rejection and insensitive to AC line frequency variations
US5834987A (en) * 1997-07-30 1998-11-10 Ercisson Inc. Frequency synthesizer systems and methods for three-point modulation with a DC response
US6169506B1 (en) * 1998-08-17 2001-01-02 Linear Technology Corp. Oversampling data converter with good rejection capability
WO2000028666A1 (en) * 1998-11-10 2000-05-18 Infineon Technologies Ag Frequency synthesizer, method for operating a frequency synthesizer and integrated circuit comprising a frequency synthesizer
EP1157471B1 (en) * 1999-02-23 2003-12-10 AudioLogic, Incorporated Methods and apparatus for correction of higher order delta sigma convertors
US6456164B1 (en) * 2001-03-05 2002-09-24 Koninklijke Philips Electronics N.V. Sigma delta fractional-N frequency divider with improved noise and spur performance
US6839010B1 (en) * 2002-12-27 2005-01-04 Zilog, Inc. Sigma-delta analog-to-digital converter with reduced quantization noise
US6873281B1 (en) * 2003-08-28 2005-03-29 Impinj, Inc. Interleaved digital correction for MASH delta-sigma ADC
US6842129B1 (en) * 2003-10-22 2005-01-11 Northrop Grumman Corporation Delta-sigma analog-to-digital converter
US6825784B1 (en) * 2004-02-18 2004-11-30 Texas Instruments Incorporated Dithering method for sigma-delta analog-to-digital converters

Also Published As

Publication number Publication date
WO2002043247A1 (en) 2002-05-30
US20040037386A1 (en) 2004-02-26
FI20002564A0 (en) 2000-11-22
FI20002564A (en) 2002-05-23
US6940435B2 (en) 2005-09-06
FI109384B (en) 2002-07-15

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