AU2001291000A1 - Method and system for decoding a row address to assert multiple adjacent rows in a memory structure - Google Patents

Method and system for decoding a row address to assert multiple adjacent rows in a memory structure

Info

Publication number
AU2001291000A1
AU2001291000A1 AU2001291000A AU9100001A AU2001291000A1 AU 2001291000 A1 AU2001291000 A1 AU 2001291000A1 AU 2001291000 A AU2001291000 A AU 2001291000A AU 9100001 A AU9100001 A AU 9100001A AU 2001291000 A1 AU2001291000 A1 AU 2001291000A1
Authority
AU
Australia
Prior art keywords
decoding
row address
adjacent rows
memory structure
multiple adjacent
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001291000A
Inventor
Jason Eisenberg
Spencer M. Gold
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Publication of AU2001291000A1 publication Critical patent/AU2001291000A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Static Random-Access Memory (AREA)
AU2001291000A 2000-09-13 2001-09-13 Method and system for decoding a row address to assert multiple adjacent rows in a memory structure Abandoned AU2001291000A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/660,721 2000-09-13
US09/660,721 US6711664B1 (en) 2000-09-13 2000-09-13 Method and system for decoding a row address to assert multiple adjacent rows in a memory structure
PCT/US2001/028922 WO2002023549A2 (en) 2000-09-13 2001-09-13 Method and system for decoding a row address to assert multiple adjacent rows in a memory structure

Publications (1)

Publication Number Publication Date
AU2001291000A1 true AU2001291000A1 (en) 2002-03-26

Family

ID=24650703

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001291000A Abandoned AU2001291000A1 (en) 2000-09-13 2001-09-13 Method and system for decoding a row address to assert multiple adjacent rows in a memory structure

Country Status (3)

Country Link
US (1) US6711664B1 (en)
AU (1) AU2001291000A1 (en)
WO (1) WO2002023549A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7233542B2 (en) * 2005-02-11 2007-06-19 International Business Machines Corporation Method and apparatus for address generation

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59180324A (en) * 1983-03-31 1984-10-13 Fujitsu Ltd Semiconductor storage device
US4593383A (en) 1983-11-02 1986-06-03 Raytheon Company Integated circuit memory
US4729119A (en) * 1984-05-21 1988-03-01 General Computer Corporation Apparatus and methods for processing data through a random access memory system
JPS6381688A (en) * 1986-09-26 1988-04-12 Hitachi Ltd Semiconductor memory device
US5274596A (en) 1987-09-16 1993-12-28 Kabushiki Kaisha Toshiba Dynamic semiconductor memory device having simultaneous operation of adjacent blocks
JP2582587B2 (en) * 1987-09-18 1997-02-19 日本テキサス・インスツルメンツ株式会社 Semiconductor storage device
US5235545A (en) * 1991-03-29 1993-08-10 Micron Technology, Inc. Memory array write addressing circuit for simultaneously addressing selected adjacent memory cells
JPH04311897A (en) * 1991-04-11 1992-11-04 Toshiba Corp Semiconductor memory
US5367655A (en) * 1991-12-23 1994-11-22 Motorola, Inc. Memory and associated method including an operating mode for simultaneously selecting multiple rows of cells
US5339277A (en) 1993-04-30 1994-08-16 Sgs-Thomson Microelectronics, Inc. Address buffer
JPH11306751A (en) 1998-04-22 1999-11-05 Toshiba Corp Semiconductor storage
JPH11306571A (en) 1998-04-24 1999-11-05 Sony Corp Driving device of optical recording medium

Also Published As

Publication number Publication date
US6711664B1 (en) 2004-03-23
WO2002023549A2 (en) 2002-03-21
WO2002023549A3 (en) 2003-07-10

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