AU2001266887A1 - Compiler-based cache line optimization - Google Patents

Compiler-based cache line optimization

Info

Publication number
AU2001266887A1
AU2001266887A1 AU2001266887A AU6688701A AU2001266887A1 AU 2001266887 A1 AU2001266887 A1 AU 2001266887A1 AU 2001266887 A AU2001266887 A AU 2001266887A AU 6688701 A AU6688701 A AU 6688701A AU 2001266887 A1 AU2001266887 A1 AU 2001266887A1
Authority
AU
Australia
Prior art keywords
compiler
cache line
based cache
line optimization
optimization
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2001266887A
Inventor
Nicolai Kosche
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sun Microsystems Inc
Original Assignee
Sun Microsystems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sun Microsystems Inc filed Critical Sun Microsystems Inc
Publication of AU2001266887A1 publication Critical patent/AU2001266887A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0862—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches with prefetch
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/60—Details of cache memory
    • G06F2212/6028—Prefetching based on hints or prefetch instructions

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
AU2001266887A 2000-06-15 2001-06-13 Compiler-based cache line optimization Abandoned AU2001266887A1 (en)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/594,430 US6564297B1 (en) 2000-06-15 2000-06-15 Compiler-based cache line optimization
US09/594,430 2000-06-15
PCT/US2001/018969 WO2001097041A2 (en) 2000-06-15 2001-06-13 Compiler-based cache line optimization

Publications (1)

Publication Number Publication Date
AU2001266887A1 true AU2001266887A1 (en) 2001-12-24

Family

ID=24378833

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2001266887A Abandoned AU2001266887A1 (en) 2000-06-15 2001-06-13 Compiler-based cache line optimization

Country Status (3)

Country Link
US (1) US6564297B1 (en)
AU (1) AU2001266887A1 (en)
WO (1) WO2001097041A2 (en)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2365375A1 (en) * 2001-12-18 2003-06-18 Ibm Canada Limited-Ibm Canada Limitee Optimizing source code for iterative execution
GB0202728D0 (en) * 2002-02-06 2002-03-27 Transitive Technologies Ltd Condition code flag emulation for program code conversion
US7331040B2 (en) * 2002-02-06 2008-02-12 Transitive Limted Condition code flag emulation for program code conversion
US7735073B1 (en) 2004-02-28 2010-06-08 Oracle International Corporation Method and apparatus for data object profiling
US7827543B1 (en) 2004-02-28 2010-11-02 Oracle America, Inc. Method and apparatus for profiling data addresses
US8065665B1 (en) 2004-02-28 2011-11-22 Oracle America, Inc. Method and apparatus for correlating profile data
US7707554B1 (en) 2004-04-21 2010-04-27 Oracle America, Inc. Associating data source information with runtime events
US7434002B1 (en) * 2006-04-24 2008-10-07 Vmware, Inc. Utilizing cache information to manage memory access and cache utilization
US7581064B1 (en) 2006-04-24 2009-08-25 Vmware, Inc. Utilizing cache information to manage memory access and cache utilization
US7530060B1 (en) * 2008-01-08 2009-05-05 International Business Machines Corporation Methods and computer program product for optimizing binaries with coding style formalization
US8561043B2 (en) * 2008-03-28 2013-10-15 International Business Machines Corporation Data transfer optimized software cache for irregular memory references
US8527974B2 (en) * 2008-03-28 2013-09-03 International Business Machines Corporation Data transfer optimized software cache for regular memory references
US8561044B2 (en) * 2008-10-07 2013-10-15 International Business Machines Corporation Optimized code generation targeting a high locality software cache
US8135911B2 (en) * 2008-10-21 2012-03-13 International Business Machines Corporation Managing a region cache
US9996356B2 (en) 2015-12-26 2018-06-12 Intel Corporation Method and apparatus for recovering from bad store-to-load forwarding in an out-of-order processor
US9696973B1 (en) 2016-02-24 2017-07-04 Semmle Limited Compilation cache with imports scanner
US11593117B2 (en) * 2018-06-29 2023-02-28 Qualcomm Incorporated Combining load or store instructions

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0668565B1 (en) 1994-02-22 2002-07-17 Advanced Micro Devices, Inc. Virtual memory system
US5704053A (en) 1995-05-18 1997-12-30 Hewlett-Packard Company Efficient explicit data prefetching analysis and code generation in a low-level optimizer for inserting prefetch instructions into loops of applications
JP3218932B2 (en) 1995-07-06 2001-10-15 株式会社日立製作所 Data prefetch code generation method
US6049669A (en) 1997-04-17 2000-04-11 Hewlett-Packard Company Exploiting case correlation to increase performance of programs with branch/switch instructions
US5809450A (en) 1997-11-26 1998-09-15 Digital Equipment Corporation Method for estimating statistics of properties of instructions processed by a processor pipeline

Also Published As

Publication number Publication date
WO2001097041A3 (en) 2002-11-21
US6564297B1 (en) 2003-05-13
WO2001097041A2 (en) 2001-12-20

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