AU2001247662A1 - Memory management apparatus and method - Google Patents
Memory management apparatus and methodInfo
- Publication number
- AU2001247662A1 AU2001247662A1 AU2001247662A AU4766201A AU2001247662A1 AU 2001247662 A1 AU2001247662 A1 AU 2001247662A1 AU 2001247662 A AU2001247662 A AU 2001247662A AU 4766201 A AU4766201 A AU 4766201A AU 2001247662 A1 AU2001247662 A1 AU 2001247662A1
- Authority
- AU
- Australia
- Prior art keywords
- management apparatus
- memory management
- memory
- management
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
- G06F9/345—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes of multiple operands or results
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
- G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
- G06F9/3877—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor
- G06F9/3879—Concurrent instruction execution, e.g. pipeline or look ahead using a slave processor, e.g. coprocessor for non-native instruction execution, e.g. executing a command; for Java instruction set
Landscapes
- Engineering & Computer Science (AREA)
- Software Systems (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Bus Control (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US19131000P | 2000-03-21 | 2000-03-21 | |
US60191310 | 2000-03-21 | ||
PCT/US2001/009107 WO2001071505A1 (en) | 2000-03-21 | 2001-03-21 | Memory management apparatus and method |
Publications (1)
Publication Number | Publication Date |
---|---|
AU2001247662A1 true AU2001247662A1 (en) | 2001-10-03 |
Family
ID=22704981
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU2001247662A Abandoned AU2001247662A1 (en) | 2000-03-21 | 2001-03-21 | Memory management apparatus and method |
Country Status (3)
Country | Link |
---|---|
US (1) | US20020032846A1 (en) |
AU (1) | AU2001247662A1 (en) |
WO (1) | WO2001071505A1 (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6785743B1 (en) * | 2000-03-22 | 2004-08-31 | University Of Washington | Template data transfer coprocessor |
WO2008004158A1 (en) * | 2006-07-03 | 2008-01-10 | Nxp B.V. | Method and system for configuration of a hardware peripheral |
KR101113755B1 (en) * | 2011-01-28 | 2012-02-27 | 엘아이지넥스원 주식회사 | Memory management method using free memory management structure |
US11218360B2 (en) * | 2019-12-09 | 2022-01-04 | Quest Automated Services, LLC | Automation system with edge computing |
CN114448587B (en) * | 2021-12-21 | 2023-09-15 | 北京长焜科技有限公司 | Method for moving LTE uplink antenna data by using EDMA in DSP |
Family Cites Families (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5761690A (en) * | 1994-07-21 | 1998-06-02 | Motorola, Inc. | Address generation apparatus and method using a peripheral address generation unit and fast interrupts |
US5625824A (en) * | 1995-03-03 | 1997-04-29 | Compaq Computer Corporation | Circuit for selectively preventing a microprocessor from posting write cycles |
-
2001
- 2001-03-21 WO PCT/US2001/009107 patent/WO2001071505A1/en active Application Filing
- 2001-03-21 AU AU2001247662A patent/AU2001247662A1/en not_active Abandoned
- 2001-03-21 US US09/814,671 patent/US20020032846A1/en not_active Abandoned
Also Published As
Publication number | Publication date |
---|---|
WO2001071505A1 (en) | 2001-09-27 |
US20020032846A1 (en) | 2002-03-14 |
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