AU2001222261A1 - Semiconductor device, metal laminated plate for fabricating circuit on semiconductor, and method of fabricating circuit - Google Patents
Semiconductor device, metal laminated plate for fabricating circuit on semiconductor, and method of fabricating circuitInfo
- Publication number
- AU2001222261A1 AU2001222261A1 AU2001222261A AU2226101A AU2001222261A1 AU 2001222261 A1 AU2001222261 A1 AU 2001222261A1 AU 2001222261 A AU2001222261 A AU 2001222261A AU 2226101 A AU2226101 A AU 2226101A AU 2001222261 A1 AU2001222261 A1 AU 2001222261A1
- Authority
- AU
- Australia
- Prior art keywords
- fabricating circuit
- semiconductor
- laminated plate
- metal laminated
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000004065 semiconductor Substances 0.000 title 2
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000002184 metal Substances 0.000 title 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
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- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02377—Fan-in arrangement
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/05001—Internal layers
- H01L2224/05005—Structure
- H01L2224/05008—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
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- H01L2224/05023—Disposition the whole internal layer protruding from the surface
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- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/05026—Disposition the internal layer being disposed in a recess of the surface
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/0554—External layer
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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- H01L2224/0556—Disposition
- H01L2224/05569—Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
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- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
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- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Manufacturing Of Printed Circuit Boards (AREA)
- Electrodes Of Semiconductors (AREA)
- Manufacturing Of Printed Wiring (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000004041A JP2001196381A (en) | 2000-01-12 | 2000-01-12 | Semiconductor device, metallic laminated board used for formation of circuit on semiconductor, and method for forming circuit |
JP2000-4041 | 2000-01-12 | ||
PCT/JP2000/009255 WO2001052322A1 (en) | 2000-01-12 | 2000-12-26 | Semiconductor device, metal laminated plate for fabricating circuit on semiconductor, and method of fabricating circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
AU2001222261A1 true AU2001222261A1 (en) | 2001-07-24 |
Family
ID=18532874
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AU2001222261A Abandoned AU2001222261A1 (en) | 2000-01-12 | 2000-12-26 | Semiconductor device, metal laminated plate for fabricating circuit on semiconductor, and method of fabricating circuit |
Country Status (8)
Country | Link |
---|---|
US (1) | US6841877B2 (en) |
EP (1) | EP1255295A4 (en) |
JP (1) | JP2001196381A (en) |
KR (1) | KR100722729B1 (en) |
CN (1) | CN1433571A (en) |
AU (1) | AU2001222261A1 (en) |
TW (1) | TW522773B (en) |
WO (1) | WO2001052322A1 (en) |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001308092A (en) * | 2000-04-18 | 2001-11-02 | Toyo Kohan Co Ltd | Multilayered metal plate used for forming interconnection on semiconductor wafer, and method for forming the interconnection on semiconductor wafer |
JP2001308095A (en) * | 2000-04-19 | 2001-11-02 | Toyo Kohan Co Ltd | Semiconductor device and method of manufacture |
KR100598259B1 (en) * | 2003-07-31 | 2006-07-07 | 동부일렉트로닉스 주식회사 | Method for formating hybrid layer wire in semiconductor |
US7495179B2 (en) | 2003-10-06 | 2009-02-24 | Tessera, Inc. | Components with posts and pads |
KR100702805B1 (en) * | 2005-12-28 | 2007-04-03 | 동부일렉트로닉스 주식회사 | Method for forming metal wiring layer of semiconductor device |
JP5080067B2 (en) * | 2006-11-24 | 2012-11-21 | 新光電気工業株式会社 | Manufacturing method of semiconductor device |
KR101388538B1 (en) | 2007-09-28 | 2014-04-23 | 테세라, 인코포레이티드 | Flip chip interconnection with double post |
US8003512B2 (en) * | 2009-02-03 | 2011-08-23 | International Business Machines Corporation | Structure of UBM and solder bumps and methods of fabrication |
US8330272B2 (en) * | 2010-07-08 | 2012-12-11 | Tessera, Inc. | Microelectronic packages with dual or multiple-etched flip-chip connectors |
US8580607B2 (en) | 2010-07-27 | 2013-11-12 | Tessera, Inc. | Microelectronic packages with nanoparticle joining |
US20120139095A1 (en) * | 2010-12-03 | 2012-06-07 | Manusharow Mathew J | Low-profile microelectronic package, method of manufacturing same, and electronic assembly containing same |
US8853558B2 (en) | 2010-12-10 | 2014-10-07 | Tessera, Inc. | Interconnect structure |
US9269681B2 (en) * | 2012-11-16 | 2016-02-23 | Qualcomm Incorporated | Surface finish on trace for a thermal compression flip chip (TCFC) |
US10886250B2 (en) | 2015-07-10 | 2021-01-05 | Invensas Corporation | Structures and methods for low temperature bonding using nanoparticles |
US9633971B2 (en) | 2015-07-10 | 2017-04-25 | Invensas Corporation | Structures and methods for low temperature bonding using nanoparticles |
CN105253854B (en) * | 2015-11-12 | 2017-05-24 | 中国工程物理研究院电子工程研究所 | Method for protecting metal electrode during SOI MEMS sacrificial layer etching |
CN106378583B (en) * | 2016-09-14 | 2018-11-30 | 厦门大学 | A kind of High-temperature Packaging is cold-pressed the preparation method of prefabricated film with Sn/Cu/Sn |
TW202414634A (en) | 2016-10-27 | 2024-04-01 | 美商艾德亞半導體科技有限責任公司 | Structures and methods for low temperature bonding |
WO2020263014A1 (en) * | 2019-06-28 | 2020-12-30 | 주식회사 아모그린텍 | Thin film foil and method for manufacturing thin film foil |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2428373C2 (en) * | 1974-06-12 | 1982-05-27 | Siemens AG, 1000 Berlin und 8000 München | Method for the production of solderable connection contacts on a semiconductor arrangement |
JPH0710030B2 (en) * | 1990-05-18 | 1995-02-01 | インターナシヨナル・ビジネス・マシーンズ・コーポレーシヨン | Method for manufacturing multilayer wiring board |
JPH085664A (en) * | 1994-06-22 | 1996-01-12 | Hitachi Chem Co Ltd | Inspection board for semiconductor device and its production |
JP3356921B2 (en) * | 1995-03-24 | 2002-12-16 | 新光電気工業株式会社 | Semiconductor device and method of manufacturing the same |
KR100218996B1 (en) * | 1995-03-24 | 1999-09-01 | 모기 쥰이찌 | Semiconductor device |
EP0734059B1 (en) | 1995-03-24 | 2005-11-09 | Shinko Electric Industries Co., Ltd. | Chip sized semiconductor device and a process for making it |
JP3569585B2 (en) * | 1995-03-24 | 2004-09-22 | 新光電気工業株式会社 | Semiconductor device |
US5851911A (en) * | 1996-03-07 | 1998-12-22 | Micron Technology, Inc. | Mask repattern process |
JPH09246274A (en) * | 1996-03-11 | 1997-09-19 | Ricoh Co Ltd | Semiconductor device |
US5904859A (en) * | 1997-04-02 | 1999-05-18 | Lucent Technologies Inc. | Flip chip metallization |
JP3925752B2 (en) | 1997-08-08 | 2007-06-06 | 日立化成工業株式会社 | Bumped wiring board and manufacturing method of semiconductor package |
JPH11204576A (en) * | 1998-01-19 | 1999-07-30 | Citizen Watch Co Ltd | Structure of semiconductor wiring |
TW450861B (en) | 1998-05-13 | 2001-08-21 | Toyo Kohan Co Ltd | Manufacturing method of a combination material of metal foil and ceramic, and metal foil laminated ceramic substrate |
JPH11354563A (en) * | 1998-06-11 | 1999-12-24 | Citizen Watch Co Ltd | Structure of semiconductor wiring |
JP4409137B2 (en) * | 1999-06-03 | 2010-02-03 | 東洋鋼鈑株式会社 | Method for manufacturing printed wiring board |
CN1190836C (en) * | 1999-06-10 | 2005-02-23 | 东洋钢钣株式会社 | Clad plate for forming interposer for seiconductor device interposer for semiconductor device, and method of manufacturing them |
TW495438B (en) * | 1999-06-16 | 2002-07-21 | Toyo Kohan Co Ltd | Material for mounting, circuit for mounting using that material, printed circuit board using that circuit |
-
2000
- 2000-01-12 JP JP2000004041A patent/JP2001196381A/en active Pending
- 2000-12-26 AU AU2001222261A patent/AU2001222261A1/en not_active Abandoned
- 2000-12-26 EP EP00985900A patent/EP1255295A4/en not_active Withdrawn
- 2000-12-26 US US10/169,917 patent/US6841877B2/en not_active Expired - Fee Related
- 2000-12-26 KR KR1020027008871A patent/KR100722729B1/en active IP Right Grant
- 2000-12-26 WO PCT/JP2000/009255 patent/WO2001052322A1/en not_active Application Discontinuation
- 2000-12-26 CN CN00818330A patent/CN1433571A/en active Pending
- 2000-12-27 TW TW089127912A patent/TW522773B/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
EP1255295A1 (en) | 2002-11-06 |
EP1255295A4 (en) | 2005-03-02 |
KR100722729B1 (en) | 2007-05-29 |
JP2001196381A (en) | 2001-07-19 |
CN1433571A (en) | 2003-07-30 |
US20030134497A1 (en) | 2003-07-17 |
KR20020093788A (en) | 2002-12-16 |
TW522773B (en) | 2003-03-01 |
WO2001052322A1 (en) | 2001-07-19 |
US6841877B2 (en) | 2005-01-11 |
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