ATE96599T1 - Asynchroner und universeller sender/empfaenger. - Google Patents

Asynchroner und universeller sender/empfaenger.

Info

Publication number
ATE96599T1
ATE96599T1 AT88302642T AT88302642T ATE96599T1 AT E96599 T1 ATE96599 T1 AT E96599T1 AT 88302642 T AT88302642 T AT 88302642T AT 88302642 T AT88302642 T AT 88302642T AT E96599 T1 ATE96599 T1 AT E96599T1
Authority
AT
Austria
Prior art keywords
uart
special character
receiver
user
characters
Prior art date
Application number
AT88302642T
Other languages
English (en)
Inventor
Dale E Gulick
Terry G Lawell
Charles Crowe
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Application granted granted Critical
Publication of ATE96599T1 publication Critical patent/ATE96599T1/de

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/901—Buffering arrangements using storage descriptor, e.g. read or write pointers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00—Packet switching elements
    • H04L49/90—Buffering arrangements
    • H04L49/9063—Intermediate storage in different physical parts of a node or terminal
    • H04L49/9068—Intermediate storage in different physical parts of a node or terminal in the network interface card
    • H04L49/9073—Early interruption upon arrival of a fraction of a packet
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
    • H04L69/12—Protocol engines

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Communication Control (AREA)
  • Burglar Alarm Systems (AREA)
  • Measuring Pulse, Heart Rate, Blood Pressure Or Blood Flow (AREA)
AT88302642T 1987-04-02 1988-03-25 Asynchroner und universeller sender/empfaenger. ATE96599T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US3568487A 1987-04-02 1987-04-02
EP88302642A EP0285334B1 (de) 1987-04-02 1988-03-25 Asynchroner und universeller Sender/Empfänger

Publications (1)

Publication Number Publication Date
ATE96599T1 true ATE96599T1 (de) 1993-11-15

Family

ID=21884192

Family Applications (1)

Application Number Title Priority Date Filing Date
AT88302642T ATE96599T1 (de) 1987-04-02 1988-03-25 Asynchroner und universeller sender/empfaenger.

Country Status (4)

Country Link
EP (1) EP0285334B1 (de)
JP (1) JP2724322B2 (de)
AT (1) ATE96599T1 (de)
DE (1) DE3885136T2 (de)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0285330A3 (de) * 1987-04-03 1989-09-06 Advanced Micro Devices, Inc. Daten-Protokoll-Steuerung
US5185862A (en) * 1989-10-30 1993-02-09 International Business Machines Corp. Apparatus for constructing data frames for transmission over a data link
US5101477A (en) * 1990-02-16 1992-03-31 International Business Machines Corp. System for high speed transfer of data frames between a channel and an input/output device with request and backup request count registers
JPH04162856A (ja) * 1990-10-26 1992-06-08 Nec Corp エラー表示方式
EP0489504B1 (de) * 1990-11-30 1997-03-05 International Business Machines Corporation Bidirektionaler FIFO-Puffer zur Schnittstellenbildung zwischen zwei Bussen
EP0534030B1 (de) * 1991-09-26 1996-07-10 International Business Machines Corporation Rahmenübertragungsanordnung in einem mit vorgegebenem Rahmenformat arbeitenden Übertragungsnetz
US5623449A (en) * 1995-08-11 1997-04-22 Lucent Technologies Inc. Flag detection for first-in-first-out memories
DE102019135713A1 (de) * 2019-12-23 2021-06-24 Phoenix Contact Gmbh & Co. Kg I/O-Modul, Betriebsverfahren und Steuerungsanordnung

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1984003192A1 (en) * 1983-02-07 1984-08-16 American Telephone & Telegraph Data network interface
US4700358A (en) * 1985-11-18 1987-10-13 Hayes Microcomputer Products, Inc. Synchronous/asynchronous modem
EP0285330A3 (de) * 1987-04-03 1989-09-06 Advanced Micro Devices, Inc. Daten-Protokoll-Steuerung

Also Published As

Publication number Publication date
DE3885136T2 (de) 1994-05-19
EP0285334B1 (de) 1993-10-27
EP0285334A2 (de) 1988-10-05
EP0285334A3 (en) 1989-09-06
JPS63258140A (ja) 1988-10-25
DE3885136D1 (de) 1993-12-02
JP2724322B2 (ja) 1998-03-09

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