ATE521898T1 - A DIGITAL SYSTEM AND METHOD FOR TESTING ANALOG AND DIGITAL/ANALOG CIRCUITS OR SYSTEMS - Google Patents
A DIGITAL SYSTEM AND METHOD FOR TESTING ANALOG AND DIGITAL/ANALOG CIRCUITS OR SYSTEMSInfo
- Publication number
- ATE521898T1 ATE521898T1 AT03760088T AT03760088T ATE521898T1 AT E521898 T1 ATE521898 T1 AT E521898T1 AT 03760088 T AT03760088 T AT 03760088T AT 03760088 T AT03760088 T AT 03760088T AT E521898 T1 ATE521898 T1 AT E521898T1
- Authority
- AT
- Austria
- Prior art keywords
- digital
- analog
- input signal
- testing
- merit
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequences by preliminary fault modelling, e.g. analysis, simulation
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/3167—Testing of combined analog and digital circuits
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
- G01R31/318371—Methodologies therefor, e.g. algorithms, procedures
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Tests Of Electronic Circuits (AREA)
- Mobile Radio Communication Systems (AREA)
- Testing, Inspecting, Measuring Of Stereoscopic Televisions And Televisions (AREA)
Abstract
A method of optimising a digital test signal for testing an analogue or mixed-signal circuit comprising determining a measure, for example a figure of merit, that is indicative of differences between the output of a fault free and the output of a known faulty circuit in response to an applied digital input signal. The digital input signal is then varied and another figure of merit is calculated for the fault free and the known faulty circuit for the new input signal. This is repeated a number of times, the digital input signal being varied each time. An optimum test signal is selected based on the determined figures of merit.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
GBGB0213882.4A GB0213882D0 (en) | 2002-06-17 | 2002-06-17 | A digital system & method for testing analogue & mixed-signal circuits or systems |
PCT/GB2003/002599 WO2003107019A2 (en) | 2002-06-17 | 2003-06-17 | A digital system and method for testing analogue and mixed-signal circuits or systems |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE521898T1 true ATE521898T1 (en) | 2011-09-15 |
Family
ID=9938726
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT03760088T ATE521898T1 (en) | 2002-06-17 | 2003-06-17 | A DIGITAL SYSTEM AND METHOD FOR TESTING ANALOG AND DIGITAL/ANALOG CIRCUITS OR SYSTEMS |
Country Status (7)
Country | Link |
---|---|
US (1) | US7174491B2 (en) |
EP (1) | EP1514125B1 (en) |
JP (1) | JP2005530161A (en) |
AT (1) | ATE521898T1 (en) |
AU (1) | AU2003250369A1 (en) |
GB (1) | GB0213882D0 (en) |
WO (1) | WO2003107019A2 (en) |
Families Citing this family (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1382975B1 (en) * | 2002-07-19 | 2008-01-02 | Qimonda AG | Method of generating a test pattern for the simulation and/or test of the layout of an integrated circuit |
US7823128B2 (en) * | 2004-04-19 | 2010-10-26 | Verigy (Singapore) Pte. Ltd. | Apparatus, system and/or method for combining multiple tests to a single test in a multiple independent port test environment |
US20050278160A1 (en) * | 2004-06-14 | 2005-12-15 | Donnelly James M | Reduction of settling time in dynamic simulations |
US7747405B2 (en) | 2006-03-24 | 2010-06-29 | Ics Triplex Technology Ltd. | Line frequency synchronization |
US7476891B2 (en) | 2006-03-24 | 2009-01-13 | Ics Triplex Technology, Ltd. | Fault detection method and apparatus |
US7729098B2 (en) | 2006-03-24 | 2010-06-01 | Ics Triplex Technology Limited | Overload protection method |
US7613974B2 (en) | 2006-03-24 | 2009-11-03 | Ics Triplex Technology Limited | Fault detection method and apparatus |
US7504975B2 (en) | 2006-03-24 | 2009-03-17 | Ics Triplex Technology Limited | Method and apparatus for output current control |
US8166362B2 (en) | 2006-03-24 | 2012-04-24 | Rockwell Automation Limited | Fault detection method and apparatus for analog to digital converter circuits |
US7688560B2 (en) | 2006-03-24 | 2010-03-30 | Ics Triplex Technology Limited | Overload protection method |
EP1837992B1 (en) * | 2006-03-24 | 2011-02-23 | ICS Triplex Technology Limited | Digital output module overload protection |
US9459316B2 (en) | 2011-09-06 | 2016-10-04 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and apparatus for testing a semiconductor device |
CN103064009B (en) * | 2012-12-28 | 2015-03-11 | 辽宁大学 | Artificial circuit fault diagnosis method based on wavelet analysis and limited gauss mixed model expectation maximization (EM) method |
FI126901B (en) * | 2014-09-12 | 2017-07-31 | Enics Ag | Method and system for testing an electronic unit |
CN105223495A (en) * | 2015-10-20 | 2016-01-06 | 国家电网公司 | A kind of method of testing of the Analog-digital circuit fault diagnosis based on expert system |
CN110088462A (en) | 2016-12-22 | 2019-08-02 | 维斯塔斯风力***集团公司 | Electric fault detection in wind turbine generator control system |
CN112444737B (en) * | 2020-09-21 | 2021-10-22 | 电子科技大学 | Method for determining fault parameter range of analog circuit |
CN112684282B (en) * | 2020-11-12 | 2022-07-19 | 国网河北省电力有限公司电力科学研究院 | Power distribution network single-phase earth fault identification method and device and terminal equipment |
CN113051862B (en) * | 2021-04-19 | 2022-07-26 | 电子科技大学 | Digital-analog hybrid circuit test vector set optimization method based on genetic algorithm |
CN115085194B (en) * | 2022-07-20 | 2022-12-23 | 南方电网科学研究院有限责任公司 | Power system stability control strategy generation method, system, device and storage medium |
CN117970039B (en) * | 2024-04-01 | 2024-06-04 | 山东大学 | Distribution line fault moment detection method |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5694356A (en) | 1994-11-02 | 1997-12-02 | Invoice Technology, Inc. | High resolution analog storage EPROM and flash EPROM |
US5646521A (en) | 1995-08-01 | 1997-07-08 | Schlumberger Technologies, Inc. | Analog channel for mixed-signal-VLSI tester |
US5745409A (en) | 1995-09-28 | 1998-04-28 | Invox Technology | Non-volatile memory with analog and digital interface and storage |
US5793778A (en) * | 1997-04-11 | 1998-08-11 | National Semiconductor Corporation | Method and apparatus for testing analog and digital circuitry within a larger circuit |
CA2206738A1 (en) * | 1997-06-02 | 1998-12-02 | Naim Ben Hamida | Fault modeling and simulation for mixed-signal circuits and systems |
US6467058B1 (en) * | 1999-01-20 | 2002-10-15 | Nec Usa, Inc. | Segmented compaction with pruning and critical fault elimination |
US20020188904A1 (en) * | 2001-06-11 | 2002-12-12 | International Business Machines Corporation | Efficiency of fault simulation by logic backtracking |
US6898746B2 (en) * | 2001-06-19 | 2005-05-24 | Intel Corporation | Method of and apparatus for testing a serial differential/mixed signal device |
-
2002
- 2002-06-17 GB GBGB0213882.4A patent/GB0213882D0/en not_active Ceased
-
2003
- 2003-06-17 US US10/518,743 patent/US7174491B2/en not_active Expired - Lifetime
- 2003-06-17 AU AU2003250369A patent/AU2003250369A1/en not_active Abandoned
- 2003-06-17 EP EP03760088A patent/EP1514125B1/en not_active Expired - Lifetime
- 2003-06-17 WO PCT/GB2003/002599 patent/WO2003107019A2/en active Application Filing
- 2003-06-17 JP JP2004513786A patent/JP2005530161A/en active Pending
- 2003-06-17 AT AT03760088T patent/ATE521898T1/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
GB0213882D0 (en) | 2002-07-31 |
US7174491B2 (en) | 2007-02-06 |
AU2003250369A1 (en) | 2003-12-31 |
JP2005530161A (en) | 2005-10-06 |
EP1514125B1 (en) | 2011-08-24 |
AU2003250369A8 (en) | 2003-12-31 |
WO2003107019A3 (en) | 2004-07-01 |
WO2003107019A2 (en) | 2003-12-24 |
EP1514125A2 (en) | 2005-03-16 |
US20060242498A1 (en) | 2006-10-26 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |