ATE520037T1 - METHOD FOR MONITORING AND ADJUSTING A CIRCUIT PERFORMANCE - Google Patents

METHOD FOR MONITORING AND ADJUSTING A CIRCUIT PERFORMANCE

Info

Publication number
ATE520037T1
ATE520037T1 AT08834058T AT08834058T ATE520037T1 AT E520037 T1 ATE520037 T1 AT E520037T1 AT 08834058 T AT08834058 T AT 08834058T AT 08834058 T AT08834058 T AT 08834058T AT E520037 T1 ATE520037 T1 AT E520037T1
Authority
AT
Austria
Prior art keywords
testing
monitoring
adjusting
bist
failures
Prior art date
Application number
AT08834058T
Other languages
German (de)
Inventor
Anand Dixit
Raymond Heald
Steven Boyle
Original Assignee
Oracle America Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Oracle America Inc filed Critical Oracle America Inc
Application granted granted Critical
Publication of ATE520037T1 publication Critical patent/ATE520037T1/en

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3187—Built-in tests

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

A method for testing an integrated circuit implemented in an electronic system. The method includes placing an integrated circuit (or portion thereof) that is implemented in an operational system (e.g., in a computer system) in an offline status. An electrical parameter of the integrated system (e.g., a voltage, clock frequency, etc.) is set, and a built-in self-test (BIST) is conducted. Any failures that occur during the BIST are recorded. Testing is then repeated for each of a plurality of predetermined values of the electrical parameter, recording any failures that occur. Once testing is complete a failure rate/range is determined for each of the predetermined values.
AT08834058T 2007-09-26 2008-09-24 METHOD FOR MONITORING AND ADJUSTING A CIRCUIT PERFORMANCE ATE520037T1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/861,403 US7797596B2 (en) 2007-09-26 2007-09-26 Method for monitoring and adjusting circuit performance
PCT/US2008/077511 WO2009042678A1 (en) 2007-09-26 2008-09-24 Method for monitoring and adjusting circuit performance

Publications (1)

Publication Number Publication Date
ATE520037T1 true ATE520037T1 (en) 2011-08-15

Family

ID=40042904

Family Applications (1)

Application Number Title Priority Date Filing Date
AT08834058T ATE520037T1 (en) 2007-09-26 2008-09-24 METHOD FOR MONITORING AND ADJUSTING A CIRCUIT PERFORMANCE

Country Status (5)

Country Link
US (1) US7797596B2 (en)
EP (1) EP2201396B1 (en)
CN (1) CN101981460B (en)
AT (1) ATE520037T1 (en)
WO (1) WO2009042678A1 (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8140902B2 (en) * 2008-11-12 2012-03-20 International Business Machines Corporation Internally controlling and enhancing advanced test and characterization in a multiple core microprocessor
WO2010104428A1 (en) * 2009-03-10 2010-09-16 Saab Ab Built-in test system with prognostic capability and method
US8122312B2 (en) * 2009-04-14 2012-02-21 International Business Machines Corporation Internally controlling and enhancing logic built-in self test in a multiple core microprocessor
CN101984492B (en) * 2010-06-11 2016-03-23 上海华虹宏力半导体制造有限公司 A kind of structure and method thereof reducing standby power consumption of flash memory
US9003244B2 (en) 2013-07-31 2015-04-07 International Business Machines Corporation Dynamic built-in self-test system
US9500705B2 (en) * 2013-08-28 2016-11-22 Wisconsin Alumni Research Foundation Integrated circuit providing fault prediction
US10141071B2 (en) * 2015-12-26 2018-11-27 Intel Corporation Predictive count fail byte (CFBYTE) for non-volatile memory
EP3432014A1 (en) * 2017-07-19 2019-01-23 Siemens Aktiengesellschaft Method and system for predictive maintenance of integrated circuits
US10901023B2 (en) * 2018-08-09 2021-01-26 Nxp B.V. Apparatuses and methods involving adjustable circuit-stress test conditions for stressing regional circuits
US11693753B2 (en) 2018-10-15 2023-07-04 Nvidia Corporation Enhanced in-system test coverage based on detecting component degradation

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6795788B2 (en) * 2000-06-06 2004-09-21 Hewlett-Packard Development Company, L.P. Method and apparatus for discovery of operational boundaries for shmoo tests
JP3405713B2 (en) * 2000-06-27 2003-05-12 松下電器産業株式会社 Semiconductor device life estimation method and reliability simulation method
US7309998B2 (en) * 2002-12-02 2007-12-18 Burns Lawrence M Process monitor for monitoring an integrated circuit chip
US7065676B1 (en) * 2002-12-27 2006-06-20 Unisys Corporation Multi-threaded memory management test system with feedback to adjust input parameters in response to performance
WO2004077081A1 (en) 2003-02-20 2004-09-10 International Business Machines Corporation Integrated circuit testing methods using well bias modification
DE10334801B3 (en) * 2003-07-30 2005-01-27 Infineon Technologies Ag Semiconductor circuit for exchanging external data, addresses and/or commands during normal operation has a test interface for a test operation with a built-in self-test
US6900656B1 (en) * 2003-11-10 2005-05-31 Texas Instruments Incorporated Method of testing an integrated circuit and an integrated circuit test apparatus
JP4846223B2 (en) 2004-10-12 2011-12-28 株式会社アドバンテスト Test apparatus and test method
US7450452B2 (en) * 2006-06-23 2008-11-11 Texas Instruments Incorporated Method to identify or screen VMIN drift on memory cells during burn-in or operation
US20080040089A1 (en) * 2006-07-18 2008-02-14 Wendemagagnehu Beyene Efficient Characterization of High-Speed Circuits
US20080036487A1 (en) * 2006-08-09 2008-02-14 Arm Limited Integrated circuit wearout detection
US7385864B2 (en) * 2006-09-12 2008-06-10 Texas Instruments Incorporated SRAM static noise margin test structure suitable for on chip parametric measurements
WO2008036921A2 (en) * 2006-09-21 2008-03-27 Impact Technologies, Llc Systems and methods for predicting failure of electronic systems and assessing level of degradation and remaining useful life

Also Published As

Publication number Publication date
CN101981460B (en) 2014-06-04
WO2009042678A1 (en) 2009-04-02
US7797596B2 (en) 2010-09-14
CN101981460A (en) 2011-02-23
EP2201396A1 (en) 2010-06-30
EP2201396B1 (en) 2011-08-10
US20090083598A1 (en) 2009-03-26

Similar Documents

Publication Publication Date Title
ATE520037T1 (en) METHOD FOR MONITORING AND ADJUSTING A CIRCUIT PERFORMANCE
TW200707873A (en) Circuit and method for monitoring the integrity of a power supply
GB2466761B (en) System, controller and method for synchronized capture and synchronized play back of data
CN104581605A (en) System and Method for Automatic Calibration of Transducer
WO2008100520A3 (en) Low power scan testing techniques and apparatus
DE602005016310D1 (en) DIAGNOSTICS DEVICE FOR A PROCESS CONTROL SYSTEM
WO2008134222A3 (en) A system for and method of integrating test structures into an integrated circuit
WO2004053944A3 (en) Fast localization of electrical failures on an integrated circuit system and method
ATE516506T1 (en) WIRING TEST DEVICE
WO2008103619A3 (en) Test fixture and method for circuit board testing
Immler et al. Secure physical enclosures from covers with tamper-resistance
WO2008008952A3 (en) High-speed signal testing system having oscilloscope functionality
RU2504828C1 (en) System of automatic operability control and fault diagnostics of electronics
DE602006016417D1 (en) TEST EQUIPMENT, TEST PROCEDURE, MANUFACTURING METHOD FOR ELECTRONIC COMPONENTS, TEST SIMULATOR AND TESTING SIMULATION METHOD
TW200629284A (en) Semiconductor memory device and method of testing the same
EP3702794A4 (en) Apparatus and method for testing circuit board included in battery management system
DE502005003338D1 (en) Electronic circuit, system with an electronic circuit and method for testing an electronic circuit
DE602007011335D1 (en) An electronic circuit comprising a test mode secured using an identifier, and associated method
DE102014010658A1 (en) CIRCUIT ARRANGEMENT AND METHOD FOR MONITORING AN ENERGY SUPPLY OF AN ELECTRONIC DEVICE
WO2008114602A1 (en) Test equipment and electronic device
TW200500618A (en) Ancillary equipment for testing semiconductor integrated circuit
US9551744B2 (en) Detecting early failures in printed wiring boards
WO2009115744A3 (en) Device for powering an electronic circuit, in particular a digital circuit, and associated method
ATE464571T1 (en) METHOD AND TEST DEVICE FOR TESTING INTEGRATED CIRCUITS
BE1020310A5 (en) SIGNAL TEST CIRCUIT AND METHOD.

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties