ATE504043T1 - Umkonfigurierbares anweisungs-zellen-array - Google Patents

Umkonfigurierbares anweisungs-zellen-array

Info

Publication number
ATE504043T1
ATE504043T1 AT06743871T AT06743871T ATE504043T1 AT E504043 T1 ATE504043 T1 AT E504043T1 AT 06743871 T AT06743871 T AT 06743871T AT 06743871 T AT06743871 T AT 06743871T AT E504043 T1 ATE504043 T1 AT E504043T1
Authority
AT
Austria
Prior art keywords
instruction
cells
program instructions
processor
reconfigurable
Prior art date
Application number
AT06743871T
Other languages
English (en)
Inventor
Tughrul Sati Arslan
Mark Millward
Sami Khawam
Ioannis Nousias
Ying Yi
Original Assignee
Univ Edinburgh
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from GB0508589A external-priority patent/GB0508589D0/en
Priority claimed from GB0604428A external-priority patent/GB0604428D0/en
Application filed by Univ Edinburgh filed Critical Univ Edinburgh
Application granted granted Critical
Publication of ATE504043T1 publication Critical patent/ATE504043T1/de

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G06F30/347—Physical level, e.g. placement or routing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking
    • G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2117/00—Details relating to the type or aim of the circuit design
    • G06F2117/04—Clock gating
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Devices For Executing Special Programs (AREA)
  • Executing Machine-Instructions (AREA)
  • Logic Circuits (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)
AT06743871T 2005-04-28 2006-04-28 Umkonfigurierbares anweisungs-zellen-array ATE504043T1 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GB0508589A GB0508589D0 (en) 2005-04-28 2005-04-28 Reconfigurable instruction cell array
GB0604428A GB0604428D0 (en) 2006-03-06 2006-03-06 Reconfigurable instruction cell array
PCT/GB2006/001556 WO2006114642A1 (en) 2005-04-28 2006-04-28 Reconfigurable instruction cell array

Publications (1)

Publication Number Publication Date
ATE504043T1 true ATE504043T1 (de) 2011-04-15

Family

ID=36685859

Family Applications (1)

Application Number Title Priority Date Filing Date
AT06743871T ATE504043T1 (de) 2005-04-28 2006-04-28 Umkonfigurierbares anweisungs-zellen-array

Country Status (6)

Country Link
US (1) US20100122105A1 (de)
EP (1) EP1877927B1 (de)
JP (1) JP6059413B2 (de)
AT (1) ATE504043T1 (de)
DE (1) DE602006021001D1 (de)
WO (1) WO2006114642A1 (de)

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Also Published As

Publication number Publication date
US20100122105A1 (en) 2010-05-13
JP6059413B2 (ja) 2017-01-11
EP1877927B1 (de) 2011-03-30
DE602006021001D1 (de) 2011-05-12
EP1877927A1 (de) 2008-01-16
WO2006114642A1 (en) 2006-11-02
JP2008539485A (ja) 2008-11-13

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