ATE491208T1 - Verfahren und vorrichtung zur verbesserung der speicherleistungsfähigkeit - Google Patents
Verfahren und vorrichtung zur verbesserung der speicherleistungsfähigkeitInfo
- Publication number
- ATE491208T1 ATE491208T1 AT04820020T AT04820020T ATE491208T1 AT E491208 T1 ATE491208 T1 AT E491208T1 AT 04820020 T AT04820020 T AT 04820020T AT 04820020 T AT04820020 T AT 04820020T AT E491208 T1 ATE491208 T1 AT E491208T1
- Authority
- AT
- Austria
- Prior art keywords
- memory
- memory performance
- improving memory
- memory cell
- read
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/22—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using ferroelectric elements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0866—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches for peripheral storage systems, e.g. disk cache
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Semiconductor Memories (AREA)
- Local Oxidation Of Silicon (AREA)
- Transition And Organic Metals Composition Catalysts For Addition Polymerization (AREA)
- Cephalosporin Compounds (AREA)
- Static Random-Access Memory (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/722,813 US20050114588A1 (en) | 2003-11-26 | 2003-11-26 | Method and apparatus to improve memory performance |
PCT/US2004/037773 WO2005055242A1 (en) | 2003-11-26 | 2004-11-12 | Method and apparatus to improve memory performance |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE491208T1 true ATE491208T1 (de) | 2010-12-15 |
Family
ID=34592083
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT04820020T ATE491208T1 (de) | 2003-11-26 | 2004-11-12 | Verfahren und vorrichtung zur verbesserung der speicherleistungsfähigkeit |
Country Status (8)
Country | Link |
---|---|
US (1) | US20050114588A1 (de) |
EP (1) | EP1695352B1 (de) |
JP (1) | JP2007512657A (de) |
KR (1) | KR100825684B1 (de) |
AT (1) | ATE491208T1 (de) |
DE (1) | DE602004030475D1 (de) |
TW (1) | TWI259954B (de) |
WO (1) | WO2005055242A1 (de) |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050204090A1 (en) * | 2004-03-10 | 2005-09-15 | Eilert Sean S. | Hardware stack for blocked nonvolatile memories |
US7613868B2 (en) * | 2004-06-09 | 2009-11-03 | Headway Technologies, Inc. | Method and system for optimizing the number of word line segments in a segmented MRAM array |
US7653846B2 (en) * | 2006-12-28 | 2010-01-26 | Intel Corporation | Memory cell bit valve loss detection and restoration |
US8009489B2 (en) * | 2009-05-28 | 2011-08-30 | Freescale Semiconductor, Inc. | Memory with read cycle write back |
US8607089B2 (en) | 2011-05-19 | 2013-12-10 | Intel Corporation | Interface for storage device access over memory bus |
WO2013095530A1 (en) | 2011-12-22 | 2013-06-27 | Intel Corporation | Efficient pcms refresh mechanism background |
US10082964B2 (en) | 2016-04-27 | 2018-09-25 | Micron Technology, Inc | Data caching for ferroelectric memory |
US9613676B1 (en) * | 2016-06-29 | 2017-04-04 | Micron Technology, Inc. | Writing to cross-point non-volatile memory |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6230233B1 (en) * | 1991-09-13 | 2001-05-08 | Sandisk Corporation | Wear leveling techniques for flash EEPROM systems |
US5367484A (en) * | 1993-04-01 | 1994-11-22 | Microchip Technology Incorporated | Programmable high endurance block for EEPROM device |
US5406510A (en) * | 1993-07-15 | 1995-04-11 | Symetrix Corporation | Non-volatile memory |
US5913215A (en) * | 1996-04-09 | 1999-06-15 | Seymour I. Rubinstein | Browse by prompted keyword phrases with an improved method for obtaining an initial document set |
US6201731B1 (en) * | 1999-05-28 | 2001-03-13 | Celis Semiconductor Corporation | Electronic memory with disturb prevention function |
JP3957469B2 (ja) * | 2000-04-11 | 2007-08-15 | Necエレクトロニクス株式会社 | 半導体記憶装置 |
US6396744B1 (en) | 2000-04-25 | 2002-05-28 | Multi Level Memory Technology | Flash memory with dynamic refresh |
US6522568B1 (en) * | 2001-07-24 | 2003-02-18 | Intel Corporation | Ferroelectric memory and method for reading the same |
US6611448B2 (en) * | 2001-07-30 | 2003-08-26 | Intel Corporation | Ferroelectric memory and method for reading the same |
NO314606B1 (no) | 2001-09-03 | 2003-04-14 | Thin Film Electronics Asa | Ikke-flyktig minneinnretning |
US7260672B2 (en) * | 2001-09-07 | 2007-08-21 | Intel Corporation | Using data stored in a destructive-read memory |
US20030058681A1 (en) * | 2001-09-27 | 2003-03-27 | Intel Corporation | Mechanism for efficient wearout counters in destructive readout memory |
US6683803B2 (en) * | 2001-12-14 | 2004-01-27 | Thin Film Electronics Asa | Apparatus and methods for data storage and retrieval |
JP3770171B2 (ja) * | 2002-02-01 | 2006-04-26 | ソニー株式会社 | メモリ装置およびそれを用いたメモリシステム |
US6801980B2 (en) * | 2002-04-25 | 2004-10-05 | International Business Machines Corporation | Destructive-read random access memory system buffered with destructive-read memory cache |
US7035967B2 (en) * | 2002-10-28 | 2006-04-25 | Sandisk Corporation | Maintaining an average erase count in a non-volatile storage system |
US6724645B1 (en) * | 2003-01-30 | 2004-04-20 | Agilent Technologies, Inc. | Method and apparatus for shortening read operations in destructive read memories |
US20050055495A1 (en) * | 2003-09-05 | 2005-03-10 | Nokia Corporation | Memory wear leveling |
-
2003
- 2003-11-26 US US10/722,813 patent/US20050114588A1/en not_active Abandoned
-
2004
- 2004-11-12 DE DE602004030475T patent/DE602004030475D1/de active Active
- 2004-11-12 EP EP04820020A patent/EP1695352B1/de not_active Not-in-force
- 2004-11-12 KR KR1020067010196A patent/KR100825684B1/ko not_active IP Right Cessation
- 2004-11-12 JP JP2006541268A patent/JP2007512657A/ja not_active Withdrawn
- 2004-11-12 AT AT04820020T patent/ATE491208T1/de not_active IP Right Cessation
- 2004-11-12 WO PCT/US2004/037773 patent/WO2005055242A1/en active Application Filing
- 2004-11-18 TW TW093135415A patent/TWI259954B/zh not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
TWI259954B (en) | 2006-08-11 |
US20050114588A1 (en) | 2005-05-26 |
DE602004030475D1 (de) | 2011-01-20 |
EP1695352B1 (de) | 2010-12-08 |
JP2007512657A (ja) | 2007-05-17 |
TW200530811A (en) | 2005-09-16 |
EP1695352A1 (de) | 2006-08-30 |
KR100825684B1 (ko) | 2008-04-29 |
WO2005055242A1 (en) | 2005-06-16 |
KR20060101503A (ko) | 2006-09-25 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |