ATE421147T1 - Dreidimensionales speicher-array - Google Patents
Dreidimensionales speicher-arrayInfo
- Publication number
- ATE421147T1 ATE421147T1 AT05025371T AT05025371T ATE421147T1 AT E421147 T1 ATE421147 T1 AT E421147T1 AT 05025371 T AT05025371 T AT 05025371T AT 05025371 T AT05025371 T AT 05025371T AT E421147 T1 ATE421147 T1 AT E421147T1
- Authority
- AT
- Austria
- Prior art keywords
- nanoscale
- wires
- storage array
- selecting
- dimensional storage
- Prior art date
Links
- 239000002070 nanowire Substances 0.000 abstract 2
Classifications
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B82—NANOTECHNOLOGY
- B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
- B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N99/00—Subject matter not provided for in other groups of this subclass
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0023—Address circuits or decoders
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/02—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using elements whose operation depends upon chemical change
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/02—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using elements whose operation depends upon chemical change
- G11C13/025—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using elements whose operation depends upon chemical change using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/10—Decoders
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
- H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
- H01L29/0669—Nanowires or nanotubes
- H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/71—Three dimensional array
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/77—Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/81—Array wherein the array conductors, e.g. word lines, bit lines, are made of nanowires
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/70—Nanostructure
- Y10S977/762—Nanowire or quantum wire, i.e. axially elongated structure having two dimensions of 100 nm or less
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S977/00—Nanotechnology
- Y10S977/902—Specified use of nanostructure
- Y10S977/932—Specified use of nanostructure for electronic or optoelectronic application
- Y10S977/943—Information storage or retrieval using nanostructure
Applications Claiming Priority (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US39894302P | 2002-07-25 | 2002-07-25 | |
US40039402P | 2002-08-01 | 2002-08-01 | |
US41517602P | 2002-09-30 | 2002-09-30 | |
US42901002P | 2002-11-25 | 2002-11-25 | |
US44199503P | 2003-01-23 | 2003-01-23 | |
US46535703P | 2003-04-25 | 2003-04-25 | |
US46738803P | 2003-05-02 | 2003-05-02 |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE421147T1 true ATE421147T1 (de) | 2009-01-15 |
Family
ID=32097212
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT03796282T ATE360873T1 (de) | 2002-07-25 | 2003-07-24 | Sublithographische nanobereichs- speicherarchitektur |
AT05025371T ATE421147T1 (de) | 2002-07-25 | 2003-07-24 | Dreidimensionales speicher-array |
Family Applications Before (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT03796282T ATE360873T1 (de) | 2002-07-25 | 2003-07-24 | Sublithographische nanobereichs- speicherarchitektur |
Country Status (7)
Country | Link |
---|---|
US (2) | US6900479B2 (de) |
EP (3) | EP1525585A2 (de) |
JP (2) | JP2006512782A (de) |
AT (2) | ATE360873T1 (de) |
AU (2) | AU2003298529A1 (de) |
DE (2) | DE60325903D1 (de) |
WO (2) | WO2004034467A2 (de) |
Families Citing this family (73)
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US20060175601A1 (en) * | 2000-08-22 | 2006-08-10 | President And Fellows Of Harvard College | Nanoscale wires and related devices |
US7301199B2 (en) * | 2000-08-22 | 2007-11-27 | President And Fellows Of Harvard College | Nanoscale wires and related devices |
KR100995457B1 (ko) * | 2000-08-22 | 2010-11-18 | 프레지던트 앤드 펠로우즈 오브 하버드 칼리지 | 나노센서 제조 방법 |
KR20030055346A (ko) * | 2000-12-11 | 2003-07-02 | 프레지던트 앤드 펠로우즈 오브 하버드 칼리지 | 나노센서 |
US7073157B2 (en) | 2002-01-18 | 2006-07-04 | California Institute Of Technology | Array-based architecture for molecular electronics |
ATE360873T1 (de) | 2002-07-25 | 2007-05-15 | California Inst Of Techn | Sublithographische nanobereichs- speicherarchitektur |
EP1388521B1 (de) * | 2002-08-08 | 2006-06-07 | Sony Deutschland GmbH | Verfahren zur Herstellung einer Kreuzschienenstruktur von Nanodrähten |
AU2003283973B2 (en) | 2002-09-30 | 2008-10-30 | Oned Material Llc | Large-area nanoenabled macroelectronic substrates and uses therefor |
US7135728B2 (en) * | 2002-09-30 | 2006-11-14 | Nanosys, Inc. | Large-area nanoenabled macroelectronic substrates and uses therefor |
US7242601B2 (en) | 2003-06-02 | 2007-07-10 | California Institute Of Technology | Deterministic addressing of nanoscale devices assembled at sublithographic pitches |
US7274208B2 (en) | 2003-06-02 | 2007-09-25 | California Institute Of Technology | Nanoscale wire-based sublithographic programmable logic arrays |
US7692952B2 (en) * | 2003-07-24 | 2010-04-06 | California Institute Of Technology | Nanoscale wire coding for stochastic assembly |
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US7310004B2 (en) * | 2004-05-28 | 2007-12-18 | California Institute Of Technology | Apparatus and method of interconnecting nanoscale programmable logic array clusters |
US20070264623A1 (en) * | 2004-06-15 | 2007-11-15 | President And Fellows Of Harvard College | Nanosensors |
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US8883568B2 (en) | 2008-06-10 | 2014-11-11 | Brown University Research Foundation | Method providing radial addressing of nanowires |
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US20100227382A1 (en) | 2005-05-25 | 2010-09-09 | President And Fellows Of Harvard College | Nanoscale sensors |
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US8183554B2 (en) * | 2006-04-03 | 2012-05-22 | Blaise Laurent Mouttet | Symmetrical programmable memresistor crossbar structure |
US20070233761A1 (en) * | 2006-04-03 | 2007-10-04 | Mouttet Blaise L | Crossbar arithmetic processor |
US7302513B2 (en) * | 2006-04-03 | 2007-11-27 | Blaise Laurent Mouttet | Programmable crossbar signal processor |
JP2009540333A (ja) | 2006-06-12 | 2009-11-19 | プレジデント アンド フェロウズ オブ ハーバード カレッジ | ナノセンサーおよび関連技術 |
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JP5009993B2 (ja) | 2006-11-09 | 2012-08-29 | ナノシス・インク. | ナノワイヤの配列方法および堆積方法 |
EP2095100B1 (de) | 2006-11-22 | 2016-09-21 | President and Fellows of Harvard College | Verfahren zum Betreiben eines Nanodraht-Feldeffekttransistorsensors |
US9806273B2 (en) * | 2007-01-03 | 2017-10-31 | The United States Of America As Represented By The Secretary Of The Army | Field effect transistor array using single wall carbon nano-tubes |
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US7763978B2 (en) * | 2007-03-28 | 2010-07-27 | Hewlett-Packard Development Company, L.P. | Three-dimensional crossbar array systems and methods for writing information to and reading information stored in three-dimensional crossbar array junctions |
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US7492624B2 (en) * | 2007-06-29 | 2009-02-17 | Stmicroelectronics S.R.L. | Method and device for demultiplexing a crossbar non-volatile memory |
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KR101161060B1 (ko) * | 2009-11-30 | 2012-06-29 | 서강대학교산학협력단 | 나노입자를 기둥형태로 조직화시키기 위한 배열장치 및 그 배열방법 |
WO2011088340A2 (en) | 2010-01-15 | 2011-07-21 | Board Of Regents, The University Of Texas System | A carbon nanotube crossbar based nano-architecture |
US7982504B1 (en) | 2010-01-29 | 2011-07-19 | Hewlett Packard Development Company, L.P. | Interconnection architecture for multilayer circuits |
US9324718B2 (en) | 2010-01-29 | 2016-04-26 | Hewlett Packard Enterprise Development Lp | Three dimensional multilayer circuit |
US9368599B2 (en) | 2010-06-22 | 2016-06-14 | International Business Machines Corporation | Graphene/nanostructure FET with self-aligned contact and gate |
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US9442695B2 (en) | 2014-05-02 | 2016-09-13 | International Business Machines Corporation | Random bit generator based on nanomaterials |
US9720772B2 (en) * | 2015-03-04 | 2017-08-01 | Kabushiki Kaisha Toshiba | Memory system, method for controlling magnetic memory, and device for controlling magnetic memory |
CN107564946A (zh) * | 2016-07-01 | 2018-01-09 | 清华大学 | 纳米晶体管 |
CN107564917B (zh) * | 2016-07-01 | 2020-06-09 | 清华大学 | 纳米异质结构 |
CN107564947A (zh) * | 2016-07-01 | 2018-01-09 | 清华大学 | 纳米异质结构 |
CN107564910B (zh) * | 2016-07-01 | 2020-08-11 | 清华大学 | 半导体器件 |
US11943940B2 (en) | 2018-07-11 | 2024-03-26 | The Regents Of The University Of California | Nucleic acid-based electrically readable, read-only memory |
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US20040248381A1 (en) | 2000-11-01 | 2004-12-09 | Myrick James J. | Nanoelectronic interconnection and addressing |
KR101008294B1 (ko) * | 2001-03-30 | 2011-01-13 | 더 리전트 오브 더 유니버시티 오브 캘리포니아 | 나노구조체 및 나노와이어의 제조 방법 및 그로부터 제조되는 디바이스 |
AU2002307129A1 (en) * | 2001-04-03 | 2002-10-21 | Carnegie Mellon University | Electronic circuit device, system and method |
US6385075B1 (en) * | 2001-06-05 | 2002-05-07 | Hewlett-Packard Company | Parallel access of cross-point diode memory arrays |
US6706402B2 (en) * | 2001-07-25 | 2004-03-16 | Nantero, Inc. | Nanotube films and articles |
US7073157B2 (en) * | 2002-01-18 | 2006-07-04 | California Institute Of Technology | Array-based architecture for molecular electronics |
US6760245B2 (en) * | 2002-05-01 | 2004-07-06 | Hewlett-Packard Development Company, L.P. | Molecular wire crossbar flash memory |
ATE360873T1 (de) | 2002-07-25 | 2007-05-15 | California Inst Of Techn | Sublithographische nanobereichs- speicherarchitektur |
US6682951B1 (en) * | 2002-09-26 | 2004-01-27 | International Business Machines Corporation | Arrangements of microscopic particles for performing logic computations, and method of use |
-
2003
- 2003-07-24 AT AT03796282T patent/ATE360873T1/de not_active IP Right Cessation
- 2003-07-24 AT AT05025371T patent/ATE421147T1/de not_active IP Right Cessation
- 2003-07-24 JP JP2005508519A patent/JP2006512782A/ja active Pending
- 2003-07-24 US US10/627,405 patent/US6900479B2/en not_active Expired - Lifetime
- 2003-07-24 WO PCT/US2003/023199 patent/WO2004034467A2/en active IP Right Grant
- 2003-07-24 JP JP2005501049A patent/JP2005539404A/ja active Pending
- 2003-07-24 AU AU2003298529A patent/AU2003298529A1/en not_active Abandoned
- 2003-07-24 WO PCT/US2003/023198 patent/WO2004061859A2/en active Application Filing
- 2003-07-24 EP EP03796281A patent/EP1525585A2/de not_active Withdrawn
- 2003-07-24 DE DE60325903T patent/DE60325903D1/de not_active Expired - Lifetime
- 2003-07-24 DE DE60313462T patent/DE60313462T2/de not_active Expired - Lifetime
- 2003-07-24 EP EP03796282A patent/EP1525586B1/de not_active Expired - Lifetime
- 2003-07-24 AU AU2003298530A patent/AU2003298530A1/en not_active Abandoned
- 2003-07-24 EP EP06022522A patent/EP1758126A3/de not_active Withdrawn
- 2003-07-24 US US10/627,406 patent/US6963077B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US6900479B2 (en) | 2005-05-31 |
EP1758126A2 (de) | 2007-02-28 |
DE60313462D1 (de) | 2007-06-06 |
US20040113139A1 (en) | 2004-06-17 |
EP1758126A3 (de) | 2007-03-14 |
AU2003298529A8 (en) | 2004-07-29 |
US6963077B2 (en) | 2005-11-08 |
AU2003298530A8 (en) | 2004-05-04 |
JP2005539404A (ja) | 2005-12-22 |
JP2006512782A (ja) | 2006-04-13 |
US20040113138A1 (en) | 2004-06-17 |
EP1525586B1 (de) | 2007-04-25 |
ATE360873T1 (de) | 2007-05-15 |
DE60325903D1 (de) | 2009-03-05 |
AU2003298529A1 (en) | 2004-07-29 |
EP1525586A2 (de) | 2005-04-27 |
WO2004034467A2 (en) | 2004-04-22 |
EP1525585A2 (de) | 2005-04-27 |
WO2004061859A2 (en) | 2004-07-22 |
DE60313462T2 (de) | 2008-01-03 |
AU2003298530A1 (en) | 2004-05-04 |
WO2004034467A3 (en) | 2004-08-26 |
WO2004061859A3 (en) | 2005-02-03 |
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