ATE413731T1 - Modifizierte, sich wiederholende zellenvergleichstechnik für integrierte schaltungen - Google Patents

Modifizierte, sich wiederholende zellenvergleichstechnik für integrierte schaltungen

Info

Publication number
ATE413731T1
ATE413731T1 AT02769266T AT02769266T ATE413731T1 AT E413731 T1 ATE413731 T1 AT E413731T1 AT 02769266 T AT02769266 T AT 02769266T AT 02769266 T AT02769266 T AT 02769266T AT E413731 T1 ATE413731 T1 AT E413731T1
Authority
AT
Austria
Prior art keywords
output
mismatch
circuit
cell
output circuit
Prior art date
Application number
AT02769266T
Other languages
English (en)
Inventor
Rodney Kranz
Charles Lane
David Jarman
Original Assignee
Analog Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Analog Devices Inc filed Critical Analog Devices Inc
Application granted granted Critical
Publication of ATE413731T1 publication Critical patent/ATE413731T1/de

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H03M1/0617—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence
    • H03M1/0675—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy
    • H03M1/0678—Continuously compensating for, or preventing, undesired influence of physical parameters characterised by the use of methods or means not specific to a particular type of detrimental influence using redundancy using additional components or elements, e.g. dummy components
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/34—Analogue value compared with reference values
    • H03M1/36—Analogue value compared with reference values simultaneously only, i.e. parallel type

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Analogue/Digital Conversion (AREA)
  • Investigating Or Analysing Biological Materials (AREA)
  • Logic Circuits (AREA)
AT02769266T 2001-05-08 2002-04-12 Modifizierte, sich wiederholende zellenvergleichstechnik für integrierte schaltungen ATE413731T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/851,658 US6480136B1 (en) 2001-05-08 2001-05-08 Modified repetitive cell matching technique for integrated circuits

Publications (1)

Publication Number Publication Date
ATE413731T1 true ATE413731T1 (de) 2008-11-15

Family

ID=25311323

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02769266T ATE413731T1 (de) 2001-05-08 2002-04-12 Modifizierte, sich wiederholende zellenvergleichstechnik für integrierte schaltungen

Country Status (6)

Country Link
US (1) US6480136B1 (de)
EP (1) EP1386402B1 (de)
JP (1) JP4125602B2 (de)
AT (1) ATE413731T1 (de)
DE (1) DE60229737D1 (de)
WO (1) WO2002091583A1 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6738788B1 (en) * 2002-04-17 2004-05-18 Icid, Llc Database system using a record key having some randomly positioned, non-deterministic bits
US6802447B2 (en) * 2002-08-26 2004-10-12 Icid, Llc Method of authenticating an object or entity using a random binary ID code subject to bit drift
JP3830914B2 (ja) * 2003-05-09 2006-10-11 Ｎｅｃエレクトロニクス株式会社 Ａ／ｄ変換器用の繰り返し性のセルを含むモノリシックチップの集積回路
US9354890B1 (en) 2007-10-23 2016-05-31 Marvell International Ltd. Call stack structure for enabling execution of code outside of a subroutine and between call stack frames
US9442758B1 (en) 2008-01-21 2016-09-13 Marvell International Ltd. Dynamic processor core switching
US9582443B1 (en) 2010-02-12 2017-02-28 Marvell International Ltd. Serial control channel processor for executing time-based instructions
US9098694B1 (en) * 2011-07-06 2015-08-04 Marvell International Ltd. Clone-resistant logic

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4309768A (en) * 1979-12-31 1982-01-05 Bell Telephone Laboratories, Incorporated Mismatch detection circuit for duplicated logic units
US5175550A (en) 1990-06-19 1992-12-29 Analog Devices, Inc. Repetitive cell matching technique for integrated circuits
US6014098A (en) 1997-01-22 2000-01-11 Broadcom Corporation Analog to digital converter
US5835048A (en) 1997-01-22 1998-11-10 Broadcom Corporation Analog-to-digital converter with improved cell mismatch compensation
US6161213A (en) * 1999-02-17 2000-12-12 Icid, Llc System for providing an integrated circuit with a unique identification
US6356225B1 (en) * 1999-12-14 2002-03-12 Maxim Integrated Products, Inc. Averaging cell mismatches in integrated circuits

Also Published As

Publication number Publication date
DE60229737D1 (de) 2008-12-18
JP2004529570A (ja) 2004-09-24
EP1386402A4 (de) 2006-06-07
WO2002091583A1 (en) 2002-11-14
EP1386402A1 (de) 2004-02-04
US20020167435A1 (en) 2002-11-14
JP4125602B2 (ja) 2008-07-30
US6480136B1 (en) 2002-11-12
EP1386402B1 (de) 2008-11-05

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Legal Events

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