ATE341099T1 - Verfahren zur anisotropen ätzung von substraten - Google Patents
Verfahren zur anisotropen ätzung von substratenInfo
- Publication number
- ATE341099T1 ATE341099T1 AT00400462T AT00400462T ATE341099T1 AT E341099 T1 ATE341099 T1 AT E341099T1 AT 00400462 T AT00400462 T AT 00400462T AT 00400462 T AT00400462 T AT 00400462T AT E341099 T1 ATE341099 T1 AT E341099T1
- Authority
- AT
- Austria
- Prior art keywords
- substrate
- etching
- excitation power
- mixed gas
- gas
- Prior art date
Links
- 239000000758 substrate Substances 0.000 title abstract 8
- 238000005530 etching Methods 0.000 title abstract 6
- 238000000034 method Methods 0.000 title 1
- 230000005284 excitation Effects 0.000 abstract 3
- 238000002161 passivation Methods 0.000 abstract 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- 239000000463 material Substances 0.000 abstract 1
- 229920000642 polymer Polymers 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
- H01L21/30655—Plasma etching; Reactive-ion etching comprising alternated and repeated etching and passivation steps, e.g. Bosch process
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Plasma & Fusion (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Drying Of Semiconductors (AREA)
- ing And Chemical Polishing (AREA)
- Weting (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/295,100 US6383938B2 (en) | 1999-04-21 | 1999-04-21 | Method of anisotropic etching of substrates |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE341099T1 true ATE341099T1 (de) | 2006-10-15 |
Family
ID=23136218
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT00400462T ATE341099T1 (de) | 1999-04-21 | 2000-02-21 | Verfahren zur anisotropen ätzung von substraten |
Country Status (5)
Country | Link |
---|---|
US (1) | US6383938B2 (de) |
EP (1) | EP1047122B1 (de) |
JP (1) | JP4601113B2 (de) |
AT (1) | ATE341099T1 (de) |
DE (1) | DE60030905T2 (de) |
Families Citing this family (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20050158666A1 (en) * | 1999-10-15 | 2005-07-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lateral etch inhibited multiple etch method for etching material etchable with oxygen containing plasma |
US6921723B1 (en) * | 2002-04-23 | 2005-07-26 | Applied Materials, Inc. | Etching method having high silicon-to-photoresist selectivity |
DE10247913A1 (de) | 2002-10-14 | 2004-04-22 | Robert Bosch Gmbh | Plasmaanlage und Verfahren zum anisotropen Einätzen von Strukturen in ein Substrat |
US20040077178A1 (en) * | 2002-10-17 | 2004-04-22 | Applied Materials, Inc. | Method for laterally etching a semiconductor structure |
JP4065213B2 (ja) * | 2003-03-25 | 2008-03-19 | 住友精密工業株式会社 | シリコン基板のエッチング方法及びエッチング装置 |
US20050029226A1 (en) * | 2003-08-07 | 2005-02-10 | Advanced Power Technology, Inc. | Plasma etching using dibromomethane addition |
JP4161857B2 (ja) * | 2003-09-10 | 2008-10-08 | 株式会社デンソー | 半導体装置の製造方法 |
DE10345402B4 (de) * | 2003-09-30 | 2005-10-13 | Infineon Technologies Ag | Verfahren zur Bearbeitung einer Halbleiterstruktur mit einer Vertiefung |
CN100517595C (zh) * | 2004-07-02 | 2009-07-22 | 株式会社爱发科 | 蚀刻方法和*** |
US7183215B2 (en) * | 2004-07-21 | 2007-02-27 | Hewlett-Packard Development Company, L.P. | Etching with electrostatically attracted ions |
FR2880469B1 (fr) * | 2005-01-03 | 2007-04-27 | Cit Alcatel | Dispositif de fabrication d'un masque par gravure par plasma d'un substrat semiconducteur |
US20060168794A1 (en) * | 2005-01-28 | 2006-08-03 | Hitachi Global Storage Technologies | Method to control mask profile for read sensor definition |
DE102005031602A1 (de) * | 2005-07-06 | 2007-01-11 | Robert Bosch Gmbh | Reaktor zur Durchführung eines Ätzverfahrens für einen Stapel von maskierten Wafern und Ätzverfahren |
WO2007031778A1 (en) * | 2005-09-16 | 2007-03-22 | Aviza Technology Limited | A method of etching a feature in a silicone substrate |
US8071481B2 (en) | 2009-04-23 | 2011-12-06 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method for forming highly strained source/drain trenches |
US8901004B2 (en) * | 2009-07-27 | 2014-12-02 | Lam Research Corporation | Plasma etch method to reduce micro-loading |
JP5537324B2 (ja) * | 2010-08-05 | 2014-07-02 | 株式会社東芝 | 半導体装置の製造方法 |
JP5845754B2 (ja) * | 2010-09-15 | 2016-01-20 | 東京エレクトロン株式会社 | プラズマエッチング処理方法 |
US9318341B2 (en) * | 2010-12-20 | 2016-04-19 | Applied Materials, Inc. | Methods for etching a substrate |
KR101251072B1 (ko) * | 2011-07-12 | 2013-04-12 | 에이피티씨 주식회사 | 반도체소자의 식각방법 |
CN103159163B (zh) * | 2011-12-19 | 2016-06-08 | 北京北方微电子基地设备工艺研究中心有限责任公司 | 基片刻蚀方法及基片处理设备 |
CN104134611B (zh) * | 2013-05-03 | 2017-09-29 | 无锡华润上华半导体有限公司 | 硅释放工艺 |
JP2015032597A (ja) * | 2013-07-31 | 2015-02-16 | 日本ゼオン株式会社 | プラズマエッチング方法 |
KR102170856B1 (ko) | 2014-02-19 | 2020-10-29 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
US9978606B2 (en) * | 2015-10-02 | 2018-05-22 | Applied Materials, Inc. | Methods for atomic level resolution and plasma processing control |
CN106653594B (zh) * | 2015-10-30 | 2019-05-28 | 中微半导体设备(上海)股份有限公司 | 一种在高宽比硅刻蚀中用于提高侧壁刻蚀效果的方法 |
US9691625B2 (en) * | 2015-11-04 | 2017-06-27 | Lam Research Corporation | Methods and systems for plasma etching using bi-modal process gas composition responsive to plasma power level |
US9607847B1 (en) * | 2015-12-18 | 2017-03-28 | Texas Instruments Incorporated | Enhanced lateral cavity etch |
KR102489215B1 (ko) * | 2016-09-06 | 2023-01-16 | 도쿄엘렉트론가부시키가이샤 | 유사 원자층 에칭 방법 |
US9941121B1 (en) | 2017-01-24 | 2018-04-10 | International Business Machines Corporation | Selective dry etch for directed self assembly of block copolymers |
KR20210011974A (ko) * | 2018-05-17 | 2021-02-02 | 에바텍 아크티엔게젤샤프트 | 기판 처리 방법 및 진공 증착 장치 |
US11393703B2 (en) * | 2018-06-18 | 2022-07-19 | Applied Materials, Inc. | Apparatus and method for controlling a flow process material to a deposition chamber |
US20230386787A1 (en) * | 2020-10-19 | 2023-11-30 | Tokyo Electron Limited | Substrate processing method and substrate processing apparatus |
CN117080062B (zh) * | 2023-10-13 | 2024-01-26 | 无锡邑文微电子科技股份有限公司 | 碗状刻蚀的方法 |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0682616B2 (ja) * | 1984-10-11 | 1994-10-19 | キヤノン株式会社 | 堆積膜形成方法 |
US4784720A (en) | 1985-05-03 | 1988-11-15 | Texas Instruments Incorporated | Trench etch process for a single-wafer RIE dry etch reactor |
JP2603217B2 (ja) | 1985-07-12 | 1997-04-23 | 株式会社日立製作所 | 表面処理方法及び表面処理装置 |
US4666555A (en) * | 1985-08-23 | 1987-05-19 | Intel Corporation | Plasma etching of silicon using fluorinated gas mixtures |
JPS62253785A (ja) | 1986-04-28 | 1987-11-05 | Tokyo Univ | 間欠的エツチング方法 |
US4729815A (en) | 1986-07-21 | 1988-03-08 | Motorola, Inc. | Multiple step trench etching process |
KR900007687B1 (ko) | 1986-10-17 | 1990-10-18 | 가부시기가이샤 히다찌세이사꾸쇼 | 플라즈마처리방법 및 장치 |
US4698128A (en) * | 1986-11-17 | 1987-10-06 | Motorola, Inc. | Sloped contact etch process |
US4983253A (en) * | 1988-05-27 | 1991-01-08 | University Of Houston-University Park | Magnetically enhanced RIE process and apparatus |
JP2918892B2 (ja) * | 1988-10-14 | 1999-07-12 | 株式会社日立製作所 | プラズマエッチング処理方法 |
JP2941572B2 (ja) | 1992-08-11 | 1999-08-25 | 三菱電機株式会社 | プラズマエッチング装置及び半導体装置の製造方法 |
DE4241045C1 (de) | 1992-12-05 | 1994-05-26 | Bosch Gmbh Robert | Verfahren zum anisotropen Ätzen von Silicium |
DE4420962C2 (de) | 1994-06-16 | 1998-09-17 | Bosch Gmbh Robert | Verfahren zur Bearbeitung von Silizium |
US5779926A (en) | 1994-09-16 | 1998-07-14 | Applied Materials, Inc. | Plasma process for etching multicomponent alloys |
US5716534A (en) | 1994-12-05 | 1998-02-10 | Tokyo Electron Limited | Plasma processing method and plasma etching method |
JP2728010B2 (ja) * | 1995-03-15 | 1998-03-18 | 株式会社日立製作所 | プラズマ処理方法 |
US5759921A (en) * | 1995-09-21 | 1998-06-02 | Lsi Logic Corporation | Integrated circuit device fabrication by plasma etching |
US5637189A (en) * | 1996-06-25 | 1997-06-10 | Xerox Corporation | Dry etch process control using electrically biased stop junctions |
ATE251341T1 (de) | 1996-08-01 | 2003-10-15 | Surface Technology Systems Plc | Verfahren zur ätzung von substraten |
DE19706682C2 (de) | 1997-02-20 | 1999-01-14 | Bosch Gmbh Robert | Anisotropes fluorbasiertes Plasmaätzverfahren für Silizium |
US5807789A (en) * | 1997-03-20 | 1998-09-15 | Taiwan Semiconductor Manufacturing, Co., Ltd. | Method for forming a shallow trench with tapered profile and round corners for the application of shallow trench isolation (STI) |
DE19736370C2 (de) | 1997-08-21 | 2001-12-06 | Bosch Gmbh Robert | Verfahren zum anisotropen Ätzen von Silizium |
-
1999
- 1999-04-21 US US09/295,100 patent/US6383938B2/en not_active Expired - Lifetime
-
2000
- 2000-02-21 AT AT00400462T patent/ATE341099T1/de not_active IP Right Cessation
- 2000-02-21 DE DE60030905T patent/DE60030905T2/de not_active Expired - Lifetime
- 2000-02-21 EP EP00400462A patent/EP1047122B1/de not_active Expired - Lifetime
- 2000-03-01 JP JP2000055248A patent/JP4601113B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
DE60030905T2 (de) | 2007-09-20 |
JP4601113B2 (ja) | 2010-12-22 |
US6383938B2 (en) | 2002-05-07 |
EP1047122A2 (de) | 2000-10-25 |
EP1047122A3 (de) | 2001-12-05 |
US20010044213A1 (en) | 2001-11-22 |
EP1047122B1 (de) | 2006-09-27 |
JP2000323454A (ja) | 2000-11-24 |
DE60030905D1 (de) | 2006-11-09 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |