ATE339041T1 - Synchronisierungsverfahren - Google Patents
SynchronisierungsverfahrenInfo
- Publication number
- ATE339041T1 ATE339041T1 AT00907144T AT00907144T ATE339041T1 AT E339041 T1 ATE339041 T1 AT E339041T1 AT 00907144 T AT00907144 T AT 00907144T AT 00907144 T AT00907144 T AT 00907144T AT E339041 T1 ATE339041 T1 AT E339041T1
- Authority
- AT
- Austria
- Prior art keywords
- output signal
- phase shifted
- pulse train
- signal
- oscillator
- Prior art date
Links
- 230000001934 delay Effects 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
- G06F5/12—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
- G06F5/14—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations for overflow or underflow handling, e.g. full or empty flags
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/02—Digital function generators
- G06F1/025—Digital function generators for functions having two-valued amplitude, e.g. Walsh functions
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
- G06F5/12—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
- H03L7/0995—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop the oscillator comprising a ring oscillator
- H03L7/0996—Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/22—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop
- H03L7/23—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using more than one loop with pulse counters or frequency dividers
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F2205/06—Indexing scheme relating to groups G06F5/06 - G06F5/16
- G06F2205/061—Adapt frequency, i.e. clock frequency at one side is adapted to clock frequency, or average clock frequency, at the other side; Not pulse stuffing only
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2205/00—Indexing scheme relating to group G06F5/00; Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F2205/12—Indexing scheme relating to groups G06F5/12 - G06F5/14
- G06F2205/126—Monitoring of intermediate fill level, i.e. with additional means for monitoring the fill level, e.g. half full flag, almost empty flag
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Supplying Of Containers To The Packaging Station (AREA)
- Mobile Radio Communication Systems (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11872699P | 1999-02-05 | 1999-02-05 |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE339041T1 true ATE339041T1 (de) | 2006-09-15 |
Family
ID=22380375
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT00907144T ATE339041T1 (de) | 1999-02-05 | 2000-02-04 | Synchronisierungsverfahren |
Country Status (5)
Country | Link |
---|---|
EP (1) | EP1149482B1 (de) |
AT (1) | ATE339041T1 (de) |
AU (1) | AU2869000A (de) |
DE (1) | DE60030538T2 (de) |
WO (1) | WO2000046949A1 (de) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
AU2002235260A1 (en) | 2000-12-20 | 2002-07-01 | Primarion, Inc. | Pll/dll dual loop data synchronization utilizing a granular fifo fill level indicator |
AU2002251700A1 (en) * | 2000-12-20 | 2002-07-30 | Primarion, Inc. | Pll/dll dual loop data synchronization |
US7162002B2 (en) * | 2002-03-01 | 2007-01-09 | Broadcom Corporation | Phase-interpolator based PLL frequency synthesizer |
US7161443B2 (en) | 2004-09-30 | 2007-01-09 | Broadcom Corporation | Temperature compensated crystal oscillator |
US9998129B1 (en) * | 2017-09-21 | 2018-06-12 | Qualcomm Incorporated | PLL post divider phase continuity |
CN112433970B (zh) * | 2020-12-02 | 2024-02-20 | 上海集成电路研发中心有限公司 | efuse控制器、芯片及efuse读写*** |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5493243A (en) * | 1994-01-04 | 1996-02-20 | Level One Communications, Inc. | Digitally controlled first order jitter attentuator using a digital frequency synthesizer |
US5502750A (en) * | 1994-06-15 | 1996-03-26 | Pericom Semiconductor Corp. | Digital jitter attenuator using selection of multi-phase clocks and auto-centering elastic buffer for a token ring network |
US5793824A (en) * | 1996-04-30 | 1998-08-11 | Adtran, Inc. | Digital phase locked loop having adaptive bandwidth for pulse stuffing synchronized digital communication system |
US5844436A (en) * | 1996-11-06 | 1998-12-01 | Northern Telecom Ltd. | Method of recovering a sampling clock in a framed data communications format with reduced phase jitter and wander |
-
2000
- 2000-02-04 EP EP00907144A patent/EP1149482B1/de not_active Expired - Lifetime
- 2000-02-04 WO PCT/US2000/002849 patent/WO2000046949A1/en active IP Right Grant
- 2000-02-04 AU AU28690/00A patent/AU2869000A/en not_active Abandoned
- 2000-02-04 DE DE60030538T patent/DE60030538T2/de not_active Expired - Lifetime
- 2000-02-04 AT AT00907144T patent/ATE339041T1/de not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
EP1149482A1 (de) | 2001-10-31 |
AU2869000A (en) | 2000-08-25 |
DE60030538D1 (de) | 2006-10-19 |
DE60030538T2 (de) | 2007-09-13 |
EP1149482B1 (de) | 2006-09-06 |
WO2000046949A1 (en) | 2000-08-10 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
RER | Ceased as to paragraph 5 lit. 3 law introducing patent treaties |