ATE128256T1 - ARRANGEMENT FOR CHECKING THE FUNCTIONALITY OF STORAGE SLOTS OF A READ-WRITE MEMORY. - Google Patents
ARRANGEMENT FOR CHECKING THE FUNCTIONALITY OF STORAGE SLOTS OF A READ-WRITE MEMORY.Info
- Publication number
- ATE128256T1 ATE128256T1 AT90103503T AT90103503T ATE128256T1 AT E128256 T1 ATE128256 T1 AT E128256T1 AT 90103503 T AT90103503 T AT 90103503T AT 90103503 T AT90103503 T AT 90103503T AT E128256 T1 ATE128256 T1 AT E128256T1
- Authority
- AT
- Austria
- Prior art keywords
- memory
- read
- write
- storage
- arrangement
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/26—Accessing multiple arrays
- G11C29/28—Dependent multiple arrays, e.g. multi-bit arrays
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The invention relates to an arrangement for verifying the correct functioning of memory locations of a read/write memory (4a and 4b) in a computer, the CPU (1) of which is connected to the read/write memory (4a and 4b) via a data and address bus (2, 3). To provide the possibility of a verification of the read/write memory (4a and 4b) of any complexity at any time and without time restriction independently of the process run and even during interrupt processing, a number of storage locations corresponding to the number of storage locations is made available in a physically separate read/write memory (4b and 4a) which is operated via the same data and address bus (2, 3) by the same CPU (1). These storage locations of the two read/write memories (4a and 4b) are selected by a common control logic (5) in such a manner that both storage areas can be used as separately addressable memories, of which one storage area is optionally used as working memory whilst the other storage area is subjected to a verification program. In this arrangement, the write operations of the continuously presented process data occur in parallel in both memory areas between the alternations of the two memory areas for work and test purposes following one another in time. However, read operations only occur from the memory area which is currently being used as working memory, until all data have been transferred from the memory area used in each case as working memory into the tested memory area by reading-out and writing-back the entire working memory volume with the aid of the CPU (1).
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP90103503A EP0443070B1 (en) | 1990-02-23 | 1990-02-23 | Device for verifying the correct functioning of memory locations in a read-write-memory |
Publications (1)
Publication Number | Publication Date |
---|---|
ATE128256T1 true ATE128256T1 (en) | 1995-10-15 |
Family
ID=8203683
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
AT90103503T ATE128256T1 (en) | 1990-02-23 | 1990-02-23 | ARRANGEMENT FOR CHECKING THE FUNCTIONALITY OF STORAGE SLOTS OF A READ-WRITE MEMORY. |
Country Status (4)
Country | Link |
---|---|
EP (1) | EP0443070B1 (en) |
AT (1) | ATE128256T1 (en) |
DE (1) | DE59009690D1 (en) |
ES (1) | ES2078916T3 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CA2595818C (en) | 2004-12-30 | 2014-04-08 | 3M Innovative Properties Company | Stain-resistant fluorochemical compositions |
CA2593694A1 (en) | 2004-12-30 | 2006-07-13 | 3M Innovative Properties Company | Articles comprising a fluorochemical surface layer and related methods |
EP2145917B1 (en) * | 2008-07-17 | 2012-06-06 | W.L. Gore & Associates GmbH | Polymer coating comprising a complex of an ionic fluoropolyether and a counter ionic agent |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS55500695A (en) * | 1978-08-12 | 1980-09-25 |
-
1990
- 1990-02-23 AT AT90103503T patent/ATE128256T1/en not_active IP Right Cessation
- 1990-02-23 ES ES90103503T patent/ES2078916T3/en not_active Expired - Lifetime
- 1990-02-23 DE DE59009690T patent/DE59009690D1/en not_active Expired - Fee Related
- 1990-02-23 EP EP90103503A patent/EP0443070B1/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0443070B1 (en) | 1995-09-20 |
DE59009690D1 (en) | 1995-10-26 |
EP0443070A1 (en) | 1991-08-28 |
ES2078916T3 (en) | 1996-01-01 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
REN | Ceased due to non-payment of the annual fee |