WO2024061318A1 - Method and apparatus for transmitting signals to rgb interface of display device - Google Patents
Method and apparatus for transmitting signals to rgb interface of display device Download PDFInfo
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- 238000010586 diagram Methods 0.000 description 6
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/2092—Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto
- G09G3/2096—Details of the interface to the display terminal specific for a flat panel
Definitions
- the present disclosure relates to a method and device for transmitting signals to an RGB (red, green, and blue) interface of a display device.
- the present disclosure relates to a method and device for transmitting signals to an RGB interface of a display device, which can drive a display device using an RGB interface without an RGB dedicated interface or a dedicated interface chip, thereby enabling more types of devices to drive using the RGB interface.
- the RGB interface display device increases the selection range of the device and reduces the hardware cost of the device.
- a method of transmitting a signal to an RGB interface of a display device includes: using a multi-channel serial bus module to generate a clock CLK signal; using a counter module to generate a horizontal synchronization HSYNC signal, a vertical synchronization VSYNC signal and a data enable DE signal; and using a multi-channel serial bus module to generate the image data signal and clock
- the CLK signal is transmitted to the RGB interface, and the HSYNC signal, VSYNC signal and DE signal are transmitted to the RGB interface using the general-purpose input and output GPIO module.
- an apparatus for transmitting a signal to an RGB interface of a display device includes: a multi-channel serial bus module that generates a clock CLK signal and transmits the image data signal and clock CLK signal to the RGB interface; a counter module that generates a horizontal synchronization HSYNC signal, a vertical synchronization VSYNC signal and a data enable DE signal ; and a general-purpose input and output GPIO module, which transmits HSYNC signals, VSYNC signals and DE signals to the RGB interface.
- Figure 1 schematically shows a known scheme for communication between a device and a display device.
- Figure 2 schematically shows a known scheme for communication between a device and a display device.
- FIG. 3 shows a timing diagram of various signals related to the RGB interface.
- FIG. 4 is a schematic diagram of a device for transmitting signals to an RGB interface of a display device according to an embodiment of the present disclosure.
- FIG. 5 schematically shows the process of outputting image data signals by the multi-channel serial bus module of the device according to the embodiment of the present disclosure.
- FIG. 6 schematically shows a flow chart of reading and writing image data in a device according to an embodiment of the present disclosure.
- FIG. 7 is a flowchart of a method of transmitting signals to an RGB interface of a display device according to an embodiment of the present disclosure.
- RGB interfaces As mentioned above, currently display devices usually use RGB interfaces to achieve image data transmission. This requires that the device for transmitting image data (such as a microcontroller (MCU) or a microprocessor (MPU)) connected to the display device also adopts a corresponding dedicated RGB interface chip. Some devices also have built-in dedicated interfaces such as RGB or MIPI interfaces.
- Figures 1 and 2 schematically show known schemes for communication between a device (shown as an MCU/MPU) and a display device. In order to achieve high-resolution color image display, control signals and data signals need to be transmitted between the device and the display device.
- the control signals transmitted between the device and the display device include: (1) horizontal synchronization (HSYNC) signal, also known as line synchronization signal; (2) vertical synchronization (VSYNC) signal, also known as frame synchronization signal; (3) data enable (DE) signal; (4) clock (CLK) signal.
- the data signal transmitted between the device and the display device includes image data for controlling the display brightness of red, green, and blue, respectively, shown as R/G/B.
- the RGB interface of the MCU/MPU is used to transmit the above control signals and data signals.
- the solution in Figure 2 uses a dedicated RGB bridge chip, so that the RGB bridge chip and the MCU/MPU can communicate using a serial interface (such as SPI) or a parallel interface (such as an 8080 interface), and the RGB bridge chip and the display device communicate using an RGB interface to transmit the above control signals and data signals.
- a serial interface such as SPI
- a parallel interface such as an 8080 interface
- the RGB bridge chip and the display device communicate using an RGB interface to transmit the above control signals and data signals.
- the hardware cost of the device will be increased, which will make it difficult to select the hardware of the device.
- Embodiments of the present disclosure propose a method and device for transmitting signals to an RGB interface of a display device, which can drive a display device using an RGB interface without a dedicated RGB interface or dedicated interface chip, thereby enabling more types of devices to Driving display devices using RGB interfaces increases the selection range of devices and reduces the hardware costs of the devices.
- Figure 3 shows the timing diagram of various signals related to the RGB interface.
- image data is output line by line in a sequence of pixel lines, and one frame of image consists of multiple pixel lines.
- frame-by-frame display of image data can be achieved.
- Table 1 below shows the meaning of each signal or parameter in Figure 3.
- each row of pixels relies on the first pulse edge of the HSYNC signal for synchronization
- Each row of pixel display needs to output (HBP+HDOTS+HFP) data clock bits.
- Each frame of pixel display relies on the first pulse edge of the VSYNC signal for synchronization.
- Each line time outputs (HBP+HDOTS+HFP) data clock bits, so in order to display each frame of image (i.e.
- the number of data clock bits that need to be transmitted is (HBP+HDOTS+HFP)*(VBP+VDOTS +VFP).
- the interface When the interface outputs valid pixel data, the interface generates the first pulse edge of the DE signal (for example, the rising edge when the high level is active); when the output of valid pixel data is completed, the interface generates the second pulse edge of the DE signal (for example, the high level is active). When it is valid, it is the falling edge).
- the HSW, HBP, HDOTS, HFP, VSW, VBP, VDOTS and VFP parameters of the display device are all known.
- the method and device for transmitting signals to the RGB interface of the display device use the above parameters to generate and provide the control signals HSYNC, HSYNC, and VSYNC, DE, CLK and data signals R/G/B, so display devices using RGB interfaces can be driven without a dedicated RGB interface or dedicated interface chip, allowing more types of devices to drive displays using RGB interfaces equipment, increasing the selection range of devices used for driving and reducing their hardware costs.
- FIG. 4 is a schematic diagram of an apparatus 400 for transmitting signals to an RGB interface of a display device according to an embodiment of the present disclosure.
- the device 400 may be a general-purpose processor, such as an MCU/MPU. As shown in FIG. 4 , the device 400 may include a multi-channel serial bus module 410 , a counter module 420 and a general purpose input and output (GPIO) module 430 .
- the device 400 can use its own modules to generate the above control signals HSYNC, VSYNC, DE, CLK and data signals R/G/B, and transmit them to the RGB interface of the display device without the need for a RGB dedicated interface or a dedicated interface chip.
- Multiplex serial bus module 410 may generate the CLK signal described with respect to FIG. 3 and Table 1.
- the clock signal of the multi-channel serial bus module itself can be used as the CLK signal output to the RGB interface of the display device.
- Multiplexed serial bus module 410 may include a Quad-Line Serial Peripheral Interface (QSPI), an Eight-Line Serial Peripheral Interface (OSPI), or a FlexIO module (such as the FlexIO module in NXP's I.MX RT series ), etc., to realize multi-bit serial transmission of R/G/B image data signals to the RGB interface of the display device.
- the QSPI module includes 4 serial data lines, which can realize 4-bit R/G/B serial data output.
- the OSPI module includes 8 serial data lines, which can realize 8-bit R/G/B serial data output.
- the FlexIO module Can be configured to include 4 or 8 data buses, enabling 4-bit or 8-bit R/G/B serial data output.
- FIG. 5 schematically shows the process of the multi-channel serial bus module 410 outputting R/G/B image data signals.
- the multi-channel serial bus module 410 can send the binary image data (shown as bit0 to bit31) in its data buffer area to the output terminal in batches according to the number N of the bus.
- the CLK port of the multi-channel serial bus module 410 outputs a pulse.
- the data in the data buffer area is shifted to the right by N bits. Each bit of the shifted binary data is mapped separately.
- Counter module 420 may generate the HSYNC signal, VSYNC signal, and DE signal described with respect to FIG. 3 and Table 1.
- the counter module 420 may include a first pulse counter module 421 , a second pulse counter module 422 and a third pulse counter module 423 for generating an HSYNC signal, a VSYNC signal and a DE signal respectively.
- the apparatus 400 may include a general purpose input output (GPIO) module 430 that transmits the HSYNC signal, VSYNC signal and DE signal generated by the counter module 420 to the RGB interface of the display device.
- GPIO general purpose input output
- the pulse counting source, counting period, channel matching value, output mode, etc. of the first pulse counter module 421, the second pulse counter module 422, and the third pulse counter module 423 can be set to output the above signal.
- the counter module can generally include one or more channels. By setting the corresponding counting period and the channel matching value, the counter can be made to generate a counter whose period corresponds to the counting period and has a corresponding channel matching value. pulse width.
- the channel matching value C1 determines the pulse width of the pulse generated by the first pulse counter module 421, that is, the effective duration. (3) Set the output mode of the first pulse counter module 421 to the pulse width modulation (PWM) pulse continuous output mode, so that the first pulse counter module 421 can continuously output PWM pulses. (4) Set the pulse counting source of the first pulse counter module 421 to the CLK signal generated by the multi-channel serial bus module 410, so that every time a CLK signal is received, the count of the first pulse counter module 421 will increase by 1.
- the PWM pulse output by the first pulse counter module 421 can be set to be a high level or a low level according to whether the HSYNC signal to be output is high level or low level.
- the first pulse counter module 421 will output a PWM with a pulse width of HSW and a period of (HBP+HDOTS+HFP) Pulse, the above-mentioned HSYNC signal.
- the channel matching value C2,1 determines the pulse width of the pulse generated by the second pulse counter module 422, that is, the effective duration. (3) Set the output mode of the second pulse counter module 422 to the PWM pulse continuous output mode, so that the second pulse counter module 422 can continuously output PWM pulses. (4) Set the pulse counting source of the second pulse counter module 422 to the HSYNC signal generated by the first pulse counter module 421. number, so that every time an HSYNC signal is received, the count of the second pulse counter module 422 will be increased by 1.
- the PWM pulse output by the second pulse counter module 422 can be set to be a high level or a low level according to whether the VSYNC signal to be output is high level or low level.
- the second pulse counter module 422 will output a pulse width of VSW , a PWM pulse with a period of (VBP+VDOTS+VFP), which is the above-mentioned VSYNC signal.
- the third pulse counter module 423 After the third pulse counter module 423 is triggered, it starts counting from 0 and outputs the first pulse edge (for the case where DE is a high level active, the first pulse edge can be a falling edge). When the count value reaches HBP, the third pulse counter module 423 outputs a second pulse edge (for the case where DE is active high, the second pulse edge may be a rising edge). When the count value reaches HBP+HDOTS, the third pulse counter module 423 stops counting and outputs the third pulse edge (for the case where DE is high-level active, the third pulse edge may be a falling edge).
- the counting of the first pulse counter module 421 overflows and is reset.
- the overflow flag of the first pulse counter module 421 becomes 1, thereby triggering the third pulse counter module 423 to restart counting.
- the third pulse counter module 423 can be enabled when the count value of the second pulse counter module 422 reaches VBP, and the third pulse can be disabled when the count value of the second pulse counter module 422 reaches (VBP+VDOTS).
- Counter module 423 may also include a central processing unit (CPU) 440.
- CPU central processing unit
- the second channel of the second pulse counter module 422 may trigger an interrupt request to enable the third pulse counter module 423 through the CPU 440 .
- the third channel of the second pulse counter module 422 triggers an interrupt request to disable the third pulse counter module 423 through the CPU 440 .
- the device 400 may also include a direct memory access (DMA) module 450 and a data storage module 460.
- the data storage module 460 may be a memory, for example.
- the DMA module 450 can read the R/G/B image data signal from the data storage module 460 and write the R/G/B image data signal to the multiplex serial bus module 410 without relying on a large number of interrupt operations of the CPU 440 .
- FIG. 6 schematically shows a flow chart of the DMA module 450 reading image data from the data storage module 460 and writing the image data to the multi-channel serial bus module 410.
- the DMA module 450 is initialized. This initialization may include setting a source address from which the DMA module 450 reads image data, a target address to which the DMA module 450 writes image data, and a target count value.
- the above target count value corresponds to the total data amount of one frame of image/the amount of data stored in the storage space of the data storage module 460 corresponding to each address.
- the counter value of the DMA module 450 is set correspondingly according to the target count value.
- the DMA module 450 may read the image data address by address and write it into the data buffer area of the multiplex serial bus module 410 , where the destination address corresponds to the address of the data buffer area of the multiplex serial bus module 410 .
- step S620 the DMA module 450 transfers the image data from the source address to the destination address.
- step S630 the DMA module 450 updates the source address pointer to point to the next data storage address in the data storage module 460 as the new source address.
- step S640 the counter value of the DMA module 450 is decremented by 1, which indicates that the DMA module 450 has completed a data transmission task.
- step S650 the multi-channel serial bus module 410 performs output according to the timing sequence of FIG. 5, and sends the image data signal and CLK signal to the RGB interface of the display device.
- step S660 it is determined whether the data buffer area of the multi-channel serial bus module 410 is empty. If it is not empty, it means that the image data in the data buffer area has not been completely output, so return to step S650 to continue the above operation. If the data cache area is empty, proceed to step S670.
- step S670 it is determined whether the counter value of the DMA module 450 has decremented to 0. If it is not 0, it means that one frame of image data has not been completely output, so return to step S620 to continue the above operation. If the counter value is 0, it means that one frame of image data has been completely output, and it is necessary to return to the original source address to read and read the next frame of image. output. Therefore, in step S680, the DMA module 450 updates the source address pointer to point to the original source address and resets the counter value to the target count value, that is, restores the initialization settings, and then repeats the above steps S620 to S680 to perform the next DMA transfer cycle. Transmit a new frame of image data.
- the RGB interface of the existing display device currently supports three working modes, namely SYNC mode (control signals are HSYNC, VSYNC, CLK, excluding DE), SYNC+DE mode (control signals are HSYNC, VSYNC, CLK, DE), and DE mode (control signals are CLK, DE, excluding HSYNC and VSYNC).
- SYNC mode control signals are HSYNC, VSYNC, CLK, excluding DE
- SYNC+DE mode control signals are HSYNC, VSYNC, CLK, DE
- DE mode control signals are CLK, DE, excluding HSYNC and VSYNC.
- the technical solution described above is aimed at the most complex SYNC+DE mode.
- the above technical solution can be modified as required to implement the other two working modes.
- the third pulse counter module 423 may not be set, and there is no need to perform interrupt-related operations.
- the second pulse counter module 422 may not be set, and the third pulse counter module 423 may be enabled at the initial stage, so that there is no need to perform interrupt-related operations. It can be seen that for the SYNC mode and the DE mode, since there is no need to execute interrupts, the method and device according to the embodiment of the present disclosure do not need to occupy the CPU's time resources, thereby reducing the burden on the CPU. Even for the SYNC+DE mode, except for the second pulse counter module 422 triggering interrupt requests twice to occupy the CPU, the rest of the operations are implemented by the hardware module of the device 400, and the two interrupt requests of the second pulse counter module 422 are only for enabling and disabling the third pulse counter module 423, respectively. The relevant instructions are simple, occupy less CPU time resources, and greatly reduce the burden on the CPU.
- the device for transmitting signals to the RGB interface of the display device can drive the display device using the RGB interface without the RGB dedicated interface or dedicated interface chip, so that more types of devices can drive the display device using the RGB interface, increase the selection range of the device, and reduce the hardware cost of the device. In addition, the burden on the CPU of the device can be reduced.
- FIG. 7 is a flowchart of a method 700 of transmitting signals to an RGB interface of a display device according to an embodiment of the present disclosure.
- the method 700 may be performed by the apparatus 400 described with reference to FIG. 4 .
- Device 400 may be a general-purpose processor, such as an MCU/MPU.
- the method 700 is briefly described below with reference to FIG. 4 and FIG. 7 .
- the method 700 begins at step S710, where the CLK signal described with respect to FIG. 3 is generated by the multiplex serial bus module 410 of the device 400.
- Multiplex serial bus modules can include Quad-Line Serial Peripheral Interface (QSPI), Eight-Line Serial Peripheral Interface (OSPI), or FlexIO modules.
- QSPI Quad-Line Serial Peripheral Interface
- OSPI Eight-Line Serial Peripheral Interface
- FlexIO FlexIO
- the HSYNC signal, VSYNC signal and DE signal described with respect to FIG. 3 are generated by the counter module 420 of the device 400.
- the multi-channel serial bus module 410 of the device 400 transmits the image data signal and the CLK signal to the RGB interface of the display device, and the GPIO module 430 of the device 400 transmits the HSYNC signal, VSYNC signal and DE signal to the display device.
- the RGB interface of the device The RGB interface of the device.
- Generating the HSYNC signal by the counter module 420 of the device 400 in step S720 may include: setting the counting period of the first pulse counter module 421 to the sum of HBP, HDOTS, and HFP; setting the channel matching value of the first pulse counter module 421 to HSW ; Set the output mode of the first pulse counter module 421 to the PWM pulse continuous output mode, and set the pulse counting source of the first pulse counter module 421 to the CLK signal.
- Generating the VSYNC signal by the counter module 420 of the device 400 in step S720 may include: setting the counting period of the second pulse counter module 422 to the sum of VBP, VDOTS, and VFP; The first channel matching value of 422 is set to VSW; the output mode of the second pulse counter module 422 is set to the PWM pulse continuous output mode, and the pulse counting source of the second pulse counter module 422 is set to the HSYNC signal.
- Generating the DE signal by the counter module 420 of the device 400 in step S720 may include: setting the counting period of the third pulse counter module 423 to the sum of HBP and HDOTS; setting the channel matching value of the third pulse counter module 423 to HBP; The output mode of the third pulse counter module 423 is set to the single pulse output mode, the pulse counting source of the third pulse counter module 423 is set to the CLK signal, and the trigger source of the third pulse counter module 423 is set to the first pulse counter module 421 overflow flag.
- Generating the DE signal by the counter module 420 of the device 400 in step S720 may also include: setting the second channel matching value of the second pulse counter module 422 to VBP and setting the third channel matching value of the second pulse counter module 422 to VBP. and VDOTS, such that the third pulse counter module 423 is enabled when the count value of the second pulse counter module 422 reaches VBP, and is disabled when the count value of the second pulse counter module 422 reaches the sum of VBP and VDOTS. Pulse counter module 423.
- Enabling the third pulse counter module 423 when the count value of the second pulse counter module 422 reaches VBP may include: when the count value of the second pulse counter module 422 reaches VBP, the second channel of the second pulse counter module 422 triggers an interrupt. A request is made to enable the third pulse counter module 423 via the CPU 440.
- Disabling the third pulse counter module 423 when the count value of the second pulse counter module 422 reaches the sum of VBP and VDOTS may include: when the count value of the second pulse counter module 422 reaches the sum of VBP and VDOTS, the second pulse counter module The third channel of 422 triggers an interrupt request to disable the third pulse counter module 423 through the CPU 440.
- step S730 the image data signal transmitted by the multi-channel serial bus module 410 of the device 400 to the RGB interface of the display device may be read from the data storage module 460 using the DMA module 450 and written to the multi-channel serial bus module 410. .
- the method of transmitting signals to the RGB interface of a display device can drive a display device using an RGB interface without an RGB dedicated interface or a dedicated interface chip, thereby enabling more types of devices to drive using the RGB interface.
- display equipment improve the selection range of the device, and reduce the hardware cost of the device.
- the load on the device's CPU can be reduced.
- Processes and logic flows described in this specification may be performed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating output. Processes and logic flows may also be executed by, and devices may be implemented as, dedicated logic circuits, such as FPGAs (Field Programmable Gate Arrays) or ASICs (Application Specific Integrated Circuits).
- FPGAs Field Programmable Gate Arrays
- ASICs Application Specific Integrated Circuits
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Abstract
A method and apparatus (400) for transmitting signals to an RGB interface of a display device. The apparatus (400) comprises: a multi-channel serial bus module (410), which generates a clock CLK signal, and transmits an image data signal and the clock CLK signal to an RGB interface; a counter module (420), which generates a horizontal sync HSYNC signal, a vertical sync VSYNC signal, and a data enable DE signal; and a general purpose input/output (GPIO) module (430), which transmits the HSYNC signal, the VSYNC signal and the DE signal to the RGB interface. A display device which employs the RGB interface can be driven without an RGB-specific interface or a specific interface chip, so that more models of apparatuses can drive the display device which employs the RGB interface, a model selection range of the apparatus is increased, and hardware costs of the apparatus are reduced.
Description
本公开涉及一种向显示设备的RGB(红绿蓝)接口传输信号的方法、装置。The present disclosure relates to a method and device for transmitting signals to an RGB (red, green, and blue) interface of a display device.
随着显示器技术的发展,越来越多的人机界面产品趋向于采用色彩丰富、图像细腻、视角宽阔的显示器,如彩色高分辨率薄膜晶体管(TFT)液晶显示器。由于显示器分辨率的提高,图像数据的传输量也随之提高。以往仅支持低传输率的显示器接口,如串行外设接口(Serial Peripheral Interface,SPI)、8080并行接口等,已不能满足高分辨率彩色显示器的数据传输要求。取而代之的是RGB接口、低电压差分信号(Low Voltage Differential Signaling,LVDS)接口、移动行业处理器接口(Mobile Industry Processor Interface,MIPI)等。With the development of display technology, more and more human-machine interface products tend to use displays with rich colors, detailed images, and wide viewing angles, such as color high-resolution thin film transistor (TFT) liquid crystal displays. As display resolution increases, the amount of image data transferred increases. In the past, only low-transmission rate display interfaces were supported, such as Serial Peripheral Interface (SPI), 8080 parallel interface, etc., which can no longer meet the data transmission requirements of high-resolution color displays. Replaced by RGB interface, Low Voltage Differential Signaling (LVDS) interface, Mobile Industry Processor Interface (MIPI), etc.
发明内容Contents of the invention
本公开涉及一种向显示设备的RGB接口传输信号的方法、装置,其能够在没有RGB专用接口或专用接口芯片的情况下驱动采用RGB接口的显示设备,从而使更多型号的装置能够驱动采用RGB接口的显示设备,提高装置的选型范围,降低装置的硬件成本。The present disclosure relates to a method and device for transmitting signals to an RGB interface of a display device, which can drive a display device using an RGB interface without an RGB dedicated interface or a dedicated interface chip, thereby enabling more types of devices to drive using the RGB interface. The RGB interface display device increases the selection range of the device and reduces the hardware cost of the device.
根据本公开的第一方面,提供了一种向显示设备的RGB接口传输信号的方法。该方法包括:利用多路串行总线模块产生时钟CLK信号;利用计数器模块产生水平同步HSYNC信号、垂直同步VSYNC信号和数据使能DE信号;以及利用多路串行总线模块将图像数据信号和时钟CLK信号传输至RGB接口,以及利用通用输入输出GPIO模块将HSYNC信号、VSYNC信号和DE信号传输到RGB接口。According to a first aspect of the present disclosure, a method of transmitting a signal to an RGB interface of a display device is provided. The method includes: using a multi-channel serial bus module to generate a clock CLK signal; using a counter module to generate a horizontal synchronization HSYNC signal, a vertical synchronization VSYNC signal and a data enable DE signal; and using a multi-channel serial bus module to generate the image data signal and clock The CLK signal is transmitted to the RGB interface, and the HSYNC signal, VSYNC signal and DE signal are transmitted to the RGB interface using the general-purpose input and output GPIO module.
根据本公开的第二方面,提供了一种向显示设备的RGB接口传输信号的装置。该装置包括:多路串行总线模块,其产生时钟CLK信号,将图像数据信号和时钟CLK信号传输至RGB接口;计数器模块,其产生水平同步HSYNC信号、垂直同步VSYNC信号和数据使能DE信号;以及通用输入输出GPIO模块,其将HSYNC信号、VSYNC信号和DE信号传输到RGB接口。According to a second aspect of the present disclosure, an apparatus for transmitting a signal to an RGB interface of a display device is provided. The device includes: a multi-channel serial bus module that generates a clock CLK signal and transmits the image data signal and clock CLK signal to the RGB interface; a counter module that generates a horizontal synchronization HSYNC signal, a vertical synchronization VSYNC signal and a data enable DE signal ; and a general-purpose input and output GPIO module, which transmits HSYNC signals, VSYNC signals and DE signals to the RGB interface.
通过下面结合附图对实施例的描述,本公开的方面、特征和优点将变得更加清楚和容易理解,其中:Aspects, features and advantages of the present disclosure will become clearer and easier to understand through the following description of the embodiments in conjunction with the accompanying drawings, in which:
图1示意性示出了装置和显示设备之间进行通信的已知方案。Figure 1 schematically shows a known scheme for communication between a device and a display device.
图2示意性示出了装置和显示设备之间进行通信的已知方案。
Figure 2 schematically shows a known scheme for communication between a device and a display device.
图3示出了与RGB接口相关的各个信号的时序图。FIG. 3 shows a timing diagram of various signals related to the RGB interface.
图4是根据本公开实施例的向显示设备的RGB接口传输信号的装置的示意图。FIG. 4 is a schematic diagram of a device for transmitting signals to an RGB interface of a display device according to an embodiment of the present disclosure.
图5示意性地示出了本公开实施例的装置的多路串行总线模块输出图像数据信号的过程。FIG. 5 schematically shows the process of outputting image data signals by the multi-channel serial bus module of the device according to the embodiment of the present disclosure.
图6示意性地示出了本公开实施例的装置中的图像数据的读取和写入的流程图。FIG. 6 schematically shows a flow chart of reading and writing image data in a device according to an embodiment of the present disclosure.
图7是根据本公开实施例的向显示设备的RGB接口传输信号的方法的流程图。FIG. 7 is a flowchart of a method of transmitting signals to an RGB interface of a display device according to an embodiment of the present disclosure.
下面将参考本公开的示例性实施例对本公开进行详细描述。然而,本公开不限于这里所描述的实施例,其可以以许多不同的形式来实施。所描述的实施例仅用于使本公开彻底和完整,并全面地向本领域的技术人员传递本公开的构思。所描述的各个实施例的特征可以互相组合或替换,除非明确排除或根据上下文应当排除。The present disclosure will be described in detail below with reference to exemplary embodiments of the present disclosure. However, the present disclosure is not limited to the embodiments described herein, but may be implemented in many different forms. The described embodiments are merely intended to make this disclosure thorough and complete, and to fully convey the concept of the disclosure to those skilled in the art. Features of the various embodiments described may be combined with or substituted for each other unless expressly excluded or should be excluded by context.
如上所述,目前显示设备通常使用RGB接口等来实现图像数据传输。这要求与显示设备连接的用于传输图像数据的装置(例如微控制器(MCU)或微处理器(MPU))也采用对应的专用RGB接口芯片等。也有一些装置自带RGB或MIPI接口等专用接口。图1和图2分别示意性示出了装置(示出为MCU/MPU)和显示设备之间进行通信的已知方案。为了实现高分辨率的彩色图像显示,装置与显示设备之间需要传输控制信号和数据信号。具体地,如图1和图2所示,装置与显示设备之间传输的控制信号包括:(1)水平同步(HSYNC)信号,也称为行同步信号;(2)垂直平同步(VSYNC)信号,也称为帧同步信号;(3)数据使能(DE)信号;(4)时钟(CLK)信号。装置与显示设备之间传输的数据信号包括分别控制红色、绿色、蓝色的显示亮度的图像数据,示出为R/G/B。在图1的方案中,利用MCU/MPU自带的RGB接口来传输上述控制信号和数据信号。图2的方案中利用了专用RGB桥接芯片,使得RGB桥接芯片与MCU/MPU之间可采用串行接口(如SPI)或并行接口(如8080接口)进行通信,而RGB桥接芯片与显示设备之间采用RGB接口进行通信,从而传输上述控制信号和数据信号。然而,无论是采用专用接口芯片的方案还是自带专用接口的方案,都会提高装置的硬件成本,给装置的硬件选型带来难度。As mentioned above, currently display devices usually use RGB interfaces to achieve image data transmission. This requires that the device for transmitting image data (such as a microcontroller (MCU) or a microprocessor (MPU)) connected to the display device also adopts a corresponding dedicated RGB interface chip. Some devices also have built-in dedicated interfaces such as RGB or MIPI interfaces. Figures 1 and 2 schematically show known schemes for communication between a device (shown as an MCU/MPU) and a display device. In order to achieve high-resolution color image display, control signals and data signals need to be transmitted between the device and the display device. Specifically, as shown in Figures 1 and 2, the control signals transmitted between the device and the display device include: (1) horizontal synchronization (HSYNC) signal, also known as line synchronization signal; (2) vertical synchronization (VSYNC) signal, also known as frame synchronization signal; (3) data enable (DE) signal; (4) clock (CLK) signal. The data signal transmitted between the device and the display device includes image data for controlling the display brightness of red, green, and blue, respectively, shown as R/G/B. In the scheme of Figure 1, the RGB interface of the MCU/MPU is used to transmit the above control signals and data signals. The solution in Figure 2 uses a dedicated RGB bridge chip, so that the RGB bridge chip and the MCU/MPU can communicate using a serial interface (such as SPI) or a parallel interface (such as an 8080 interface), and the RGB bridge chip and the display device communicate using an RGB interface to transmit the above control signals and data signals. However, whether it is a solution using a dedicated interface chip or a solution with a dedicated interface, the hardware cost of the device will be increased, which will make it difficult to select the hardware of the device.
本公开的实施例提出一种向显示设备的RGB接口传输信号的方法、装置,能够在没有RGB专用接口或专用接口芯片的情况下驱动采用RGB接口的显示设备,从而使更多型号的装置能够驱动采用RGB接口的显示设备,提高装置的选型范围,降低装置的硬件成本。Embodiments of the present disclosure propose a method and device for transmitting signals to an RGB interface of a display device, which can drive a display device using an RGB interface without a dedicated RGB interface or dedicated interface chip, thereby enabling more types of devices to Driving display devices using RGB interfaces increases the selection range of devices and reduces the hardware costs of the devices.
图3示出了与RGB接口相关的各个信号的时序图。根据RGB接口协议,图像数据是按照像素行的序列逐行输出的,一帧图像由多个像素行组成。通过图3中各个信号的时序的配合,可以实现图像数据的逐帧显示。下面的表1示出了图3中各个信号或参数的含义。
Figure 3 shows the timing diagram of various signals related to the RGB interface. According to the RGB interface protocol, image data is output line by line in a sequence of pixel lines, and one frame of image consists of multiple pixel lines. Through the cooperation of the timing of each signal in Figure 3, frame-by-frame display of image data can be achieved. Table 1 below shows the meaning of each signal or parameter in Figure 3.
表1
Table 1
Table 1
结合表1和图3可以理解,每一行像素的显示依靠HSYNC信号的第一脉冲沿来进行同步,显示一行像素数据所需要的时间HSYNC=(HBP+HDOTS+HFP)个CLK周期。每一行像素显示需要输出(HBP+HDOTS+HFP)个数据时钟位。每一帧像素显示依靠VSYNC信号的第一脉冲沿来进行同步,显示一帧像素数据所需要的时间VSYNC=(VBP+VDOTS+VFP)个行时间HSYNC。每个行时间输出(HBP+HDOTS+HFP)个数据时钟位,因此为了显示每帧图像(即一屏图像),需要传输的数据时钟位数为(HBP+HDOTS+HFP)*(VBP+VDOTS+VFP)。当接口输出有效像素数据时,接口产生DE信号的第一脉冲沿(例如高电平有效时为上升沿);当有效像素数据输出完成时,接口产生DE信号的第二脉冲沿(例如高电平有效时为下降沿)。显示设备的HSW、HBP、HDOTS、HFP、VSW、VBP、VDOTS和VFP这些参数都是已知的。Combining Table 1 and Figure 3, it can be understood that the display of each row of pixels relies on the first pulse edge of the HSYNC signal for synchronization, and the time required to display one row of pixel data is HSYNC = (HBP + HDOTS + HFP) CLK cycles. Each row of pixel display needs to output (HBP+HDOTS+HFP) data clock bits. Each frame of pixel display relies on the first pulse edge of the VSYNC signal for synchronization. The time required to display one frame of pixel data is VSYNC = (VBP + VDOTS + VFP) line time HSYNC. Each line time outputs (HBP+HDOTS+HFP) data clock bits, so in order to display each frame of image (i.e. one screen image), the number of data clock bits that need to be transmitted is (HBP+HDOTS+HFP)*(VBP+VDOTS +VFP). When the interface outputs valid pixel data, the interface generates the first pulse edge of the DE signal (for example, the rising edge when the high level is active); when the output of valid pixel data is completed, the interface generates the second pulse edge of the DE signal (for example, the high level is active). When it is valid, it is the falling edge). The HSW, HBP, HDOTS, HFP, VSW, VBP, VDOTS and VFP parameters of the display device are all known.
根据本公开的实施例的向显示设备的RGB接口传输信号的方法、装置正是通过利用上述参数,来产生和向显示设备的RGB接口提供满足图3中示出的时序关系的控制信号HSYNC、VSYNC、DE、CLK和数据信号R/G/B,因此可以在没有RGB专用接口或专用接口芯片的情况下驱动采用RGB接口的显示设备,从而使更多型号的装置能够驱动采用RGB接口的显示设备,提高用于驱动的装置的选型范围和降低其硬件成本。The method and device for transmitting signals to the RGB interface of the display device according to the embodiments of the present disclosure use the above parameters to generate and provide the control signals HSYNC, HSYNC, and VSYNC, DE, CLK and data signals R/G/B, so display devices using RGB interfaces can be driven without a dedicated RGB interface or dedicated interface chip, allowing more types of devices to drive displays using RGB interfaces equipment, increasing the selection range of devices used for driving and reducing their hardware costs.
图4是根据本公开实施例的向显示设备的RGB接口传输信号的装置400的示意图。该装置400可以是通用处理器,例如MCU/MPU。如图4所示,装置400可以包括多路串行总线模块410、计数器模块420和通用输入输出(GPIO)模块430。装置400可以利用自身的这些模块产生上述控制信号HSYNC、VSYNC、DE、CLK和数据信号R/G/B,并将其传输至显示设备的RGB接口,而不需要RGB专用接口或专用接口芯片。FIG. 4 is a schematic diagram of an apparatus 400 for transmitting signals to an RGB interface of a display device according to an embodiment of the present disclosure. The device 400 may be a general-purpose processor, such as an MCU/MPU. As shown in FIG. 4 , the device 400 may include a multi-channel serial bus module 410 , a counter module 420 and a general purpose input and output (GPIO) module 430 . The device 400 can use its own modules to generate the above control signals HSYNC, VSYNC, DE, CLK and data signals R/G/B, and transmit them to the RGB interface of the display device without the need for a RGB dedicated interface or a dedicated interface chip.
多路串行总线模块410可以产生关于图3和表1描述的CLK信号。多路串行总线模块自身的时钟信号即可作为向显示设备的RGB接口输出的CLK信号。多路串行总线模块410可以包括四数据线串行外设接口(QSPI)、八数据线串行外设接口(OSPI)或FlexIO模块(例如恩智浦公司的I.MX RT系列中的FlexIO模块)等,以实现R/G/B图像数据信号到显示设备的RGB接口的多位(bit)串行传输。QSPI模块包括4路串行数据线,可实现4位R/G/B串行数据输出,OSPI模块包括8路串行数据线,可实现8位R/G/B串行数据输出,FlexIO模块可配置成包括4路或8路数据总线,可实现4位或8位R/G/B串行数据输出。Multiplex serial bus module 410 may generate the CLK signal described with respect to FIG. 3 and Table 1. The clock signal of the multi-channel serial bus module itself can be used as the CLK signal output to the RGB interface of the display device. Multiplexed serial bus module 410 may include a Quad-Line Serial Peripheral Interface (QSPI), an Eight-Line Serial Peripheral Interface (OSPI), or a FlexIO module (such as the FlexIO module in NXP's I.MX RT series ), etc., to realize multi-bit serial transmission of R/G/B image data signals to the RGB interface of the display device. The QSPI module includes 4 serial data lines, which can realize 4-bit R/G/B serial data output. The OSPI module includes 8 serial data lines, which can realize 8-bit R/G/B serial data output. The FlexIO module Can be configured to include 4 or 8 data buses, enabling 4-bit or 8-bit R/G/B serial data output.
图5示意性地示出了多路串行总线模块410输出R/G/B图像数据信号的过程。多路串行总线模块410可以其数据缓存区中的二进制图像数据(示出为bit0至bit31)按照总线的路数N分批派送到输出端。图5以多路串行总线模块410为QSPI模块为例,示出了通过N=4路串行数据线实现4位R/G/B串行数据输出。如图5所示,每派送一次二进制图像数据,多路串行总线模块410的CLK端口输出一个脉冲,同时数据缓存区的数据向右移N位,被移出的二进制数据的每1位分别映射在多路串行总线模块410的数据输出端口。这种数据移位派送操作会一直进行下去直到数据缓存区的所有数据都被移出。通过
把图像数据依次写入多路串行总线模块410的数据缓存区,多路串行总线模块410的CLK端口和数据输出端口便会输出时钟信号和图像数据信号。FIG. 5 schematically shows the process of the multi-channel serial bus module 410 outputting R/G/B image data signals. The multi-channel serial bus module 410 can send the binary image data (shown as bit0 to bit31) in its data buffer area to the output terminal in batches according to the number N of the bus. Figure 5 takes the multi-channel serial bus module 410 as a QSPI module as an example, showing that 4-bit R/G/B serial data output is achieved through N=4 serial data lines. As shown in Figure 5, every time binary image data is sent, the CLK port of the multi-channel serial bus module 410 outputs a pulse. At the same time, the data in the data buffer area is shifted to the right by N bits. Each bit of the shifted binary data is mapped separately. At the data output port of the multi-channel serial bus module 410. This data shift dispatch operation will continue until all data in the data buffer has been moved out. pass The image data is sequentially written into the data buffer area of the multi-channel serial bus module 410, and the CLK port and data output port of the multi-channel serial bus module 410 will output clock signals and image data signals.
计数器模块420可以产生关于图3和表1描述的HSYNC信号、VSYNC信号和DE信号。具体地,如图4所示,计数器模块420可以包括分别用于产生HSYNC信号、VSYNC信号和DE信号的第一脉冲计数器模块421、第二脉冲计数器模块422和第三脉冲计数器模块423。此外,装置400可以包括通用输入输出(GPIO)模块430,其将计数器模块420产生的HSYNC信号、VSYNC信号和DE信号传输到显示设备的RGB接口。Counter module 420 may generate the HSYNC signal, VSYNC signal, and DE signal described with respect to FIG. 3 and Table 1. Specifically, as shown in FIG. 4 , the counter module 420 may include a first pulse counter module 421 , a second pulse counter module 422 and a third pulse counter module 423 for generating an HSYNC signal, a VSYNC signal and a DE signal respectively. In addition, the apparatus 400 may include a general purpose input output (GPIO) module 430 that transmits the HSYNC signal, VSYNC signal and DE signal generated by the counter module 420 to the RGB interface of the display device.
可以通过对第一脉冲计数器模块421、第二脉冲计数器模块422和第三脉冲计数器模块423的脉冲计数源、计数周期、通道匹配值、输出模式等进行设置,来使其输出上述信号。如本领域技术人员已知的,计数器模块通常可以包括一个或多个通道,通过设置对应的计数周期和通道匹配值,可以使得计数器产生其周期对应于该计数周期、具有对应于通道匹配值的脉冲宽度的脉冲。The pulse counting source, counting period, channel matching value, output mode, etc. of the first pulse counter module 421, the second pulse counter module 422, and the third pulse counter module 423 can be set to output the above signal. As known to those skilled in the art, the counter module can generally include one or more channels. By setting the corresponding counting period and the channel matching value, the counter can be made to generate a counter whose period corresponds to the counting period and has a corresponding channel matching value. pulse width.
在一个实施例中,第一脉冲计数器模块421可以为单通道计数器模块,可以如下设置第一脉冲计数器模块421以使其产生上述HSYNC信号:(1)将第一脉冲计数器模块421的计数周期T1设置为关于图3和表1描述的HBP、HDOTS、HFP的总和,即T1=HBP+HDOTS+HFP。该计数周期T1决定第一脉冲计数器模块421产生的脉冲的周期。(2)将第一脉冲计数器模块421的通道匹配值C1设置为关于图3和表1描述的HSW,即C1=HSW。该通道匹配值C1决定第一脉冲计数器模块421产生的脉冲的脉冲宽度,即有效持续时间。(3)将第一脉冲计数器模块421的输出模式设置为脉宽调制(PWM)脉冲连续输出模式,这样第一脉冲计数器模块421可以连续输出PWM脉冲。(4)将第一脉冲计数器模块421的脉冲计数源设置为多路串行总线模块410产生的CLK信号,这样每接收一个CLK信号,第一脉冲计数器模块421的计数就会加1。此外,可以根据需要输出的HSYNC信号为高电平有效还是低电平有效,来对应设置第一脉冲计数器模块421输出的PWM脉冲为高电平还是低电平。通过上述设置,当多路串行总线模块410输出CLK信号和R/G/B图像数据信号时,第一脉冲计数器模块421会输出脉冲宽度为HSW、周期为(HBP+HDOTS+HFP)的PWM脉冲,即上述HSYNC信号。In one embodiment, the first pulse counter module 421 can be a single-channel counter module, and the first pulse counter module 421 can be set as follows to generate the above-mentioned HSYNC signal: (1) Set the counting period T1 of the first pulse counter module 421 to Set to the sum of HBP, HDOTS, HFP as described with respect to Figure 3 and Table 1, i.e. T1=HBP+HDOTS+HFP. The counting period T1 determines the period of the pulses generated by the first pulse counter module 421 . (2) Set the channel matching value C1 of the first pulse counter module 421 to the HSW described with respect to FIG. 3 and Table 1, that is, C1=HSW. The channel matching value C1 determines the pulse width of the pulse generated by the first pulse counter module 421, that is, the effective duration. (3) Set the output mode of the first pulse counter module 421 to the pulse width modulation (PWM) pulse continuous output mode, so that the first pulse counter module 421 can continuously output PWM pulses. (4) Set the pulse counting source of the first pulse counter module 421 to the CLK signal generated by the multi-channel serial bus module 410, so that every time a CLK signal is received, the count of the first pulse counter module 421 will increase by 1. In addition, the PWM pulse output by the first pulse counter module 421 can be set to be a high level or a low level according to whether the HSYNC signal to be output is high level or low level. Through the above settings, when the multi-channel serial bus module 410 outputs the CLK signal and the R/G/B image data signal, the first pulse counter module 421 will output a PWM with a pulse width of HSW and a period of (HBP+HDOTS+HFP) Pulse, the above-mentioned HSYNC signal.
在一个实施例中,第二脉冲计数器模块422可以为单通道或多通道计数器模块,可以如下设置第二脉冲计数器模块422以使其产生上述VSYNC信号:(1)将第二脉冲计数器模块422的计数周期T2设置为关于图3和表1描述的VBP、VDOTS、VFP的总和,即T2=VBP+VDOTS+VFP。该计数周期T2决定第二脉冲计数器模块422产生的脉冲的周期。(2)将第二脉冲计数器模块422的第一通道匹配值C2,1设置为关于图3和表1描述的VSW,即C2,1=VSW。该通道匹配值C2,1决定第二脉冲计数器模块422产生的脉冲的脉冲宽度,即有效持续时间。(3)将第二脉冲计数器模块422的输出模式设置为PWM脉冲连续输出模式,这样第二脉冲计数器模块422可以连续输出PWM脉冲。(4)将第二脉冲计数器模块422的脉冲计数源设置为第一脉冲计数器模块421产生的HSYNC信
号,这样每接收一个HSYNC信号,第二脉冲计数器模块422的计数就会加1。此外,可以根据需要输出的VSYNC信号为高电平有效还是低电平有效,来对应设置第二脉冲计数器模块422输出的PWM脉冲为高电平还是低电平。通过上述设置,当多路串行总线模块410输出CLK信号和R/G/B图像数据信号时,随着第一脉冲计数器模块421输出HSYNC信号,第二脉冲计数器模块422会输出脉冲宽度为VSW、周期为(VBP+VDOTS+VFP)的PWM脉冲,即上述VSYNC信号。In one embodiment, the second pulse counter module 422 can be a single-channel or multi-channel counter module, and the second pulse counter module 422 can be set as follows to generate the above-mentioned VSYNC signal: (1) Set the second pulse counter module 422 to The counting period T2 is set to the sum of VBP, VDOTS, VFP described with respect to Figure 3 and Table 1, that is, T2=VBP+VDOTS+VFP. The counting period T2 determines the period of the pulses generated by the second pulse counter module 422 . (2) Set the first channel matching value C2,1 of the second pulse counter module 422 to the VSW described with respect to FIG. 3 and Table 1, that is, C2,1=VSW. The channel matching value C2,1 determines the pulse width of the pulse generated by the second pulse counter module 422, that is, the effective duration. (3) Set the output mode of the second pulse counter module 422 to the PWM pulse continuous output mode, so that the second pulse counter module 422 can continuously output PWM pulses. (4) Set the pulse counting source of the second pulse counter module 422 to the HSYNC signal generated by the first pulse counter module 421. number, so that every time an HSYNC signal is received, the count of the second pulse counter module 422 will be increased by 1. In addition, the PWM pulse output by the second pulse counter module 422 can be set to be a high level or a low level according to whether the VSYNC signal to be output is high level or low level. Through the above settings, when the multi-channel serial bus module 410 outputs the CLK signal and the R/G/B image data signal, as the first pulse counter module 421 outputs the HSYNC signal, the second pulse counter module 422 will output a pulse width of VSW , a PWM pulse with a period of (VBP+VDOTS+VFP), which is the above-mentioned VSYNC signal.
在一个实施例中,第三脉冲计数器模块423可以为单通道计数器模块,可以如下设置第三脉冲计数器模块423以使其产生上述DE信号:(1)将第三脉冲计数器模块423的计数周期T3设置为关于图3和表1描述的HBP和所述HDOTS的总和,即T3=HBP+HDOTS。(2)将第三脉冲计数器模块423的通道匹配值C3设置为关于图3和表1描述的HBP,即C3=HBP。该通道匹配值C3决定第三脉冲计数器模块423产生的脉冲的脉冲宽度,即有效持续时间。(3)将第三脉冲计数器模块423的输出模式设置为单脉冲输出模式,这样第三脉冲计数器模块423每次被触发源触发时输出一个脉冲。可以根据需要输出的DE信号为高电平有效还是低电平有效,来对应设置第三脉冲计数器模块423输出的单脉冲为低电平还是高电平。(4)将第三脉冲计数器模块423的脉冲计数源设置为多路串行总线模块410产生的CLK信号,这样每接收一个CLK信号,第三脉冲计数器模块423的计数就会加1。(5)将第三脉冲计数器模块423的触发源设置为第一脉冲计数器模块421的溢出标志位。第三脉冲计数器模块423被触发后,从0开始计数,输出第一脉冲沿(对于DE为高电平有效的情况,该第一脉冲沿可以为下降沿)。当计数值达到HBP时,第三脉冲计数器模块423输出第二脉冲沿(对于DE为高电平有效的情况,该第二脉冲沿可以为上升沿)。当计数值达到HBP+HDOTS时,第三脉冲计数器模块423停止计数,输出第三脉冲沿(对于DE为高电平有效的情况,该第三脉冲沿可以为下降沿)。由于第一脉冲计数器模块421的计数周期T1=HBP+HDOTS+HFP,比第三脉冲计数器模块423的计数周期大,所以第三脉冲计数器模块423在输出第三脉冲沿后维持停止状态一直到第一脉冲计数器模块421的计数值达到T1=HBP+HDOTS+HFP。由此,第一脉冲计数器模块421的计数溢出从而复位,这时第一脉冲计数器模块421的溢出标志位变为1,从而触发第三脉冲计数器模块423重新开始计数。通过上述设置,当多路串行总线模块410输出CLK信号和R/G/B图像数据信号时,第三脉冲计数器模块422会输出上述DE信号。In one embodiment, the third pulse counter module 423 may be a single-channel counter module, and the third pulse counter module 423 may be configured as follows to generate the above DE signal: (1) Set the counting period T3 of the third pulse counter module 423 Set to the sum of HBP and the HDOTS described with respect to Figure 3 and Table 1, ie T3=HBP+HDOTS. (2) Set the channel matching value C3 of the third pulse counter module 423 to the HBP described with respect to FIG. 3 and Table 1, that is, C3=HBP. The channel matching value C3 determines the pulse width of the pulse generated by the third pulse counter module 423, that is, the effective duration. (3) Set the output mode of the third pulse counter module 423 to the single pulse output mode, so that the third pulse counter module 423 outputs one pulse each time it is triggered by the trigger source. The single pulse output by the third pulse counter module 423 can be set to be low level or high level according to whether the DE signal to be output is high level or low level. (4) Set the pulse counting source of the third pulse counter module 423 to the CLK signal generated by the multi-channel serial bus module 410, so that every time a CLK signal is received, the count of the third pulse counter module 423 will increase by 1. (5) Set the trigger source of the third pulse counter module 423 to the overflow flag of the first pulse counter module 421 . After the third pulse counter module 423 is triggered, it starts counting from 0 and outputs the first pulse edge (for the case where DE is a high level active, the first pulse edge can be a falling edge). When the count value reaches HBP, the third pulse counter module 423 outputs a second pulse edge (for the case where DE is active high, the second pulse edge may be a rising edge). When the count value reaches HBP+HDOTS, the third pulse counter module 423 stops counting and outputs the third pulse edge (for the case where DE is high-level active, the third pulse edge may be a falling edge). Since the counting period T1=HBP+HDOTS+HFP of the first pulse counter module 421 is larger than the counting period of the third pulse counter module 423, the third pulse counter module 423 maintains the stopped state after outputting the third pulse edge until the third pulse edge. The count value of a pulse counter module 421 reaches T1=HBP+HDOTS+HFP. As a result, the counting of the first pulse counter module 421 overflows and is reset. At this time, the overflow flag of the first pulse counter module 421 becomes 1, thereby triggering the third pulse counter module 423 to restart counting. Through the above settings, when the multi-channel serial bus module 410 outputs the CLK signal and the R/G/B image data signal, the third pulse counter module 422 will output the above-mentioned DE signal.
根据RGB接口协议,可以仅在显示一帧有效像素数据(即有效显示像素行)时才产生DE信号以防止干扰。因此,在一个实施例中,可以通过第二脉冲计数器模块422来使能和禁用第三脉冲计数器模块423,以使第三脉冲计数器模块423仅在显示有效显示像素行时才产生DE信号。由此,可以进行如下设置:(1)将第二脉冲计数器模块422的第二通道匹配值C2,2设置为关于图3和表1描述的VBP,即C2,2=VBP。(2)将第二脉冲计数器模块422的第三通道匹配值C2,3设置为关于图3和表1描述的VBP和VDOTS的
总和,即C2,3=VBP+VDOTS。通过上述设置,可以使得在第二脉冲计数器模块422的计数值达到VBP时使能第三脉冲计数器模块423,并且在第二脉冲计数器模块422的计数值达到(VBP+VDOTS)时禁用第三脉冲计数器模块423。具体地,上述使能和禁用可以通过触发中断请求来进行。因此,如图4所示,在一个实施例中,装置400还可以包括中央处理器(CPU)440。在第二脉冲计数器模块422的计数值达到第二通道匹配值C2,2=VBP时,第二脉冲计数器模块422的第二通道可以触发中断请求以通过该CPU 440使能第三脉冲计数器模块423。在第二脉冲计数器模块422的计数值达到第三通道匹配值C2,3=VBP+VDOTS时,第二脉冲计数器模块422的第三通道触发中断请求以通过该CPU440禁用第三脉冲计数器模块423。According to the RGB interface protocol, the DE signal can be generated only when one frame of valid pixel data is displayed (that is, a valid display pixel row) to prevent interference. Therefore, in one embodiment, the third pulse counter module 423 can be enabled and disabled by the second pulse counter module 422 so that the third pulse counter module 423 only generates the DE signal when a valid display pixel row is displayed. Therefore, the following settings can be made: (1) Set the second channel matching value C2,2 of the second pulse counter module 422 to the VBP described with respect to FIG. 3 and Table 1, that is, C2,2=VBP. (2) Set the third channel matching value C2,3 of the second pulse counter module 422 to the VBP and VDOTS described in Figure 3 and Table 1 The sum is C2,3=VBP+VDOTS. Through the above settings, the third pulse counter module 423 can be enabled when the count value of the second pulse counter module 422 reaches VBP, and the third pulse can be disabled when the count value of the second pulse counter module 422 reaches (VBP+VDOTS). Counter module 423. Specifically, the above enabling and disabling can be performed by triggering an interrupt request. Therefore, as shown in Figure 4, in one embodiment, the apparatus 400 may also include a central processing unit (CPU) 440. When the count value of the second pulse counter module 422 reaches the second channel matching value C2,2=VBP, the second channel of the second pulse counter module 422 may trigger an interrupt request to enable the third pulse counter module 423 through the CPU 440 . When the count value of the second pulse counter module 422 reaches the third channel matching value C2,3=VBP+VDOTS, the third channel of the second pulse counter module 422 triggers an interrupt request to disable the third pulse counter module 423 through the CPU 440 .
在一个实施例中,为了减轻装置400的CPU 440的中断负担,装置400还可以包括直接存储器存取(DMA)模块450和数据存储模块460。数据存储模块460例如可以为存储器。DMA模块450可以从数据存储模块460读取R/G/B图像数据信号和将R/G/B图像数据信号写入多路串行总线模块410,而不需要依赖于CPU 440的大量中断操作。In one embodiment, in order to reduce the interrupt burden of the CPU 440 of the device 400, the device 400 may also include a direct memory access (DMA) module 450 and a data storage module 460. The data storage module 460 may be a memory, for example. The DMA module 450 can read the R/G/B image data signal from the data storage module 460 and write the R/G/B image data signal to the multiplex serial bus module 410 without relying on a large number of interrupt operations of the CPU 440 .
图6示意性地示出了DMA模块450从数据存储模块460读取图像数据和将图像数据写入多路串行总线模块410的流程图。在步骤S610,DMA模块450被初始化。该初始化可以包括设置DMA模块450从其读取图像数据的源地址、DMA模块450向其写入图像数据的目标地址、以及目标计数值。数据存储模块460中存在一段连续地址空间以存储一帧图像数据,上述源地址对应于这段连续地址空间的起始地址。上述目标计数值对应于一帧图像的总数据量/每个地址对应的数据存储模块460的存储空间中存储的数据量。根据该目标计数值对应设置DMA模块450的计数器值。DMA模块450可以逐地址地读取图像数据并将其写入多路串行总线模块410的数据缓存区,上述目的地址对应于多路串行总线模块410的数据缓存区的地址。FIG. 6 schematically shows a flow chart of the DMA module 450 reading image data from the data storage module 460 and writing the image data to the multi-channel serial bus module 410. In step S610, the DMA module 450 is initialized. This initialization may include setting a source address from which the DMA module 450 reads image data, a target address to which the DMA module 450 writes image data, and a target count value. There is a continuous address space in the data storage module 460 to store one frame of image data, and the above-mentioned source address corresponds to the starting address of this continuous address space. The above target count value corresponds to the total data amount of one frame of image/the amount of data stored in the storage space of the data storage module 460 corresponding to each address. The counter value of the DMA module 450 is set correspondingly according to the target count value. The DMA module 450 may read the image data address by address and write it into the data buffer area of the multiplex serial bus module 410 , where the destination address corresponds to the address of the data buffer area of the multiplex serial bus module 410 .
在步骤S620,DMA模块450将图像数据从源地址传输到目的地址。In step S620 , the DMA module 450 transfers the image data from the source address to the destination address.
在步骤S630,DMA模块450更新源地址指针以指向数据存储模块460中下一个数据存储地址,将其作为新的源地址。In step S630, the DMA module 450 updates the source address pointer to point to the next data storage address in the data storage module 460 as the new source address.
在步骤S640,DMA模块450的计数器值递减1,这指示DMA模块450完成了一次数据传输任务。In step S640, the counter value of the DMA module 450 is decremented by 1, which indicates that the DMA module 450 has completed a data transmission task.
在步骤S650,多路串行总线模块410根据图5的时序进行输出,把图像数据信号和CLK信号发送至显示设备的RGB接口。In step S650, the multi-channel serial bus module 410 performs output according to the timing sequence of FIG. 5, and sends the image data signal and CLK signal to the RGB interface of the display device.
在步骤S660,确定多路串行总线模块410的数据缓存区是否为空。如果不为空,则表示数据缓存区的图像数据还没完全输出,因此返回至步骤S650继续进行上述操作。如果数据缓存区为空,则进入步骤S670。In step S660, it is determined whether the data buffer area of the multi-channel serial bus module 410 is empty. If it is not empty, it means that the image data in the data buffer area has not been completely output, so return to step S650 to continue the above operation. If the data cache area is empty, proceed to step S670.
在步骤S670,确定DMA模块450的计数器值是否已递减到0。如果不为0,则表示一帧图像数据还没完全输出,因此返回至步骤S620继续进行上述操作。如果计数器值为0,则表示一帧图像数据已完全输出,需要返回到最初的源地址进行下一帧图像的读取和
输出。因此,在步骤S680,DMA模块450更新源地址指针以指向最初的源地址并将计数器值重置为目标计数值,即恢复初始化设置,接着重复上述步骤S620至S680以执行下一个DMA传输周期来传输新一帧图像数据。In step S670, it is determined whether the counter value of the DMA module 450 has decremented to 0. If it is not 0, it means that one frame of image data has not been completely output, so return to step S620 to continue the above operation. If the counter value is 0, it means that one frame of image data has been completely output, and it is necessary to return to the original source address to read and read the next frame of image. output. Therefore, in step S680, the DMA module 450 updates the source address pointer to point to the original source address and resets the counter value to the target count value, that is, restores the initialization settings, and then repeats the above steps S620 to S680 to perform the next DMA transfer cycle. Transmit a new frame of image data.
需要指出的是,目前现有显示设备的RGB接口支持3种工作模式,分别为SYNC模式(控制信号为HSYNC、VSYNC、CLK,不包括DE)、SYNC+DE模式(控制信号为HSYNC、VSYNC、CLK、DE)、DE模式(控制信号为CLK、DE,不包括HSYNC、VSYNC)。上述描述的技术方案针对的是其中最复杂的SYNC+DE模式。可以根据需求对上述技术方案进行修改来实现其它两种工作模式。例如对于SYNC模式,可以不设置第三脉冲计数器模块423,并且也不需要执行中断相关操作。对于DE模式,可以不设置第二脉冲计数器模块422,并且可以在初始时就使能第三脉冲计数器模块423,从而也不需要执行中断相关操作。可以看出,对于SYNC模式和DE模式,由于不需要执行中断,根据本公开实施例的方法和装置不需要占用CPU的时间资源,从而减轻了CPU的负担。即使对于SYNC+DE模式,除了发生两次第二脉冲计数器模块422触发中断请求从而占用CPU之外,其余操作都是由装置400的硬件模块来实现的,而第二脉冲计数器模块422的两次中断请求分别只是针对第三脉冲计数器模块423的使能和禁止,相关指令简单,对CPU的时间资源占用较少,也大大减轻了CPU的负担。It should be pointed out that the RGB interface of the existing display device currently supports three working modes, namely SYNC mode (control signals are HSYNC, VSYNC, CLK, excluding DE), SYNC+DE mode (control signals are HSYNC, VSYNC, CLK, DE), and DE mode (control signals are CLK, DE, excluding HSYNC and VSYNC). The technical solution described above is aimed at the most complex SYNC+DE mode. The above technical solution can be modified as required to implement the other two working modes. For example, for the SYNC mode, the third pulse counter module 423 may not be set, and there is no need to perform interrupt-related operations. For the DE mode, the second pulse counter module 422 may not be set, and the third pulse counter module 423 may be enabled at the initial stage, so that there is no need to perform interrupt-related operations. It can be seen that for the SYNC mode and the DE mode, since there is no need to execute interrupts, the method and device according to the embodiment of the present disclosure do not need to occupy the CPU's time resources, thereby reducing the burden on the CPU. Even for the SYNC+DE mode, except for the second pulse counter module 422 triggering interrupt requests twice to occupy the CPU, the rest of the operations are implemented by the hardware module of the device 400, and the two interrupt requests of the second pulse counter module 422 are only for enabling and disabling the third pulse counter module 423, respectively. The relevant instructions are simple, occupy less CPU time resources, and greatly reduce the burden on the CPU.
根据本公开的实施例的向显示设备的RGB接口传输信号的装置能够在没有RGB专用接口或专用接口芯片的情况下驱动采用RGB接口的显示设备,从而使更多型号的装置能够驱动采用RGB接口的显示设备,提高装置的选型范围,降低装置的硬件成本。此外,还能减轻该装置的CPU的负担。According to the embodiment of the present disclosure, the device for transmitting signals to the RGB interface of the display device can drive the display device using the RGB interface without the RGB dedicated interface or dedicated interface chip, so that more types of devices can drive the display device using the RGB interface, increase the selection range of the device, and reduce the hardware cost of the device. In addition, the burden on the CPU of the device can be reduced.
图7是根据本公开实施例的向显示设备的RGB接口传输信号的方法700的流程图。方法700可以由参照图4描述的装置400来执行。装置400可以是通用处理器,例如MCU/MPU。下面结合图4和图7对方法700进行简单描述。方法700开始于步骤S710,其中由装置400的多路串行总线模块410产生关于图3描述的CLK信号。多路串行总线模块可以包括四数据线串行外设接口(QSPI)、八数据线串行外设接口(OSPI)或FlexIO模块。在步骤S720,由装置400的计数器模块420产生关于图3描述的HSYNC信号、VSYNC信号和DE信号。在步骤S730,由装置400的多路串行总线模块410将图像数据信号和CLK信号传输到显示设备的RGB接口,以及由装置400的GPIO模块430将HSYNC信号、VSYNC信号和DE信号传输到显示设备的RGB接口。Figure 7 is a flowchart of a method 700 of transmitting signals to an RGB interface of a display device according to an embodiment of the present disclosure. The method 700 may be performed by the apparatus 400 described with reference to FIG. 4 . Device 400 may be a general-purpose processor, such as an MCU/MPU. The method 700 is briefly described below with reference to FIG. 4 and FIG. 7 . The method 700 begins at step S710, where the CLK signal described with respect to FIG. 3 is generated by the multiplex serial bus module 410 of the device 400. Multiplex serial bus modules can include Quad-Line Serial Peripheral Interface (QSPI), Eight-Line Serial Peripheral Interface (OSPI), or FlexIO modules. At step S720, the HSYNC signal, VSYNC signal and DE signal described with respect to FIG. 3 are generated by the counter module 420 of the device 400. In step S730, the multi-channel serial bus module 410 of the device 400 transmits the image data signal and the CLK signal to the RGB interface of the display device, and the GPIO module 430 of the device 400 transmits the HSYNC signal, VSYNC signal and DE signal to the display device. The RGB interface of the device.
步骤S720中由装置400的计数器模块420产生HSYNC信号可以包括:将第一脉冲计数器模块421的计数周期设置为HBP、HDOTS、HFP的总和;将第一脉冲计数器模块421的通道匹配值设置为HSW;将第一脉冲计数器模块421的输出模式设置为PWM脉冲连续输出模式,并且将第一脉冲计数器模块421的脉冲计数源设置为CLK信号。Generating the HSYNC signal by the counter module 420 of the device 400 in step S720 may include: setting the counting period of the first pulse counter module 421 to the sum of HBP, HDOTS, and HFP; setting the channel matching value of the first pulse counter module 421 to HSW ; Set the output mode of the first pulse counter module 421 to the PWM pulse continuous output mode, and set the pulse counting source of the first pulse counter module 421 to the CLK signal.
步骤S720中由装置400的计数器模块420产生VSYNC信号可以包括:将第二脉冲计数器模块422的计数周期设置为VBP、VDOTS、VFP的总和;将第二脉冲计数器模块
422的第一通道匹配值设置为VSW;将第二脉冲计数器模块422的输出模式设置为PWM脉冲连续输出模式,并且将第二脉冲计数器模块422的脉冲计数源设置为HSYNC信号。Generating the VSYNC signal by the counter module 420 of the device 400 in step S720 may include: setting the counting period of the second pulse counter module 422 to the sum of VBP, VDOTS, and VFP; The first channel matching value of 422 is set to VSW; the output mode of the second pulse counter module 422 is set to the PWM pulse continuous output mode, and the pulse counting source of the second pulse counter module 422 is set to the HSYNC signal.
步骤S720中由装置400的计数器模块420产生DE信号可以包括:将第三脉冲计数器模块423的计数周期设置为HBP和HDOTS的总和;将第三脉冲计数器模块423的通道匹配值设置为HBP;将第三脉冲计数器模块423的输出模式设置为单脉冲输出模式,将第三脉冲计数器模块423的脉冲计数源设置为CLK信号,并且将第三脉冲计数器模块423的触发源设置为第一脉冲计数器模块421的溢出标志位。Generating the DE signal by the counter module 420 of the device 400 in step S720 may include: setting the counting period of the third pulse counter module 423 to the sum of HBP and HDOTS; setting the channel matching value of the third pulse counter module 423 to HBP; The output mode of the third pulse counter module 423 is set to the single pulse output mode, the pulse counting source of the third pulse counter module 423 is set to the CLK signal, and the trigger source of the third pulse counter module 423 is set to the first pulse counter module 421 overflow flag.
步骤S720中由装置400的计数器模块420产生DE信号还可以包括:将第二脉冲计数器模块422的第二通道匹配值设置为VBP以及将第二脉冲计数器模块422的第三通道匹配值设置为VBP和VDOTS的总和,以使得在第二脉冲计数器模块422的计数值达到VBP时使能第三脉冲计数器模块423,并且在第二脉冲计数器模块422的计数值达到VBP和VDOTS的总和时禁用第三脉冲计数器模块423。Generating the DE signal by the counter module 420 of the device 400 in step S720 may also include: setting the second channel matching value of the second pulse counter module 422 to VBP and setting the third channel matching value of the second pulse counter module 422 to VBP. and VDOTS, such that the third pulse counter module 423 is enabled when the count value of the second pulse counter module 422 reaches VBP, and is disabled when the count value of the second pulse counter module 422 reaches the sum of VBP and VDOTS. Pulse counter module 423.
在第二脉冲计数器模块422的计数值达到VBP时使能第三脉冲计数器模块423可以包括:在第二脉冲计数器模块422的计数值达到VBP时,第二脉冲计数器模块422的第二通道触发中断请求以通过CPU 440使能第三脉冲计数器模块423。在第二脉冲计数器模块422的计数值达到VBP和VDOTS的总和时禁用第三脉冲计数器模块423可以包括:在第二脉冲计数器模块422的计数值达到VBP和VDOTS的总和时,第二脉冲计数器模块422的第三通道触发中断请求以通过CPU 440禁用第三脉冲计数器模块423。Enabling the third pulse counter module 423 when the count value of the second pulse counter module 422 reaches VBP may include: when the count value of the second pulse counter module 422 reaches VBP, the second channel of the second pulse counter module 422 triggers an interrupt. A request is made to enable the third pulse counter module 423 via the CPU 440. Disabling the third pulse counter module 423 when the count value of the second pulse counter module 422 reaches the sum of VBP and VDOTS may include: when the count value of the second pulse counter module 422 reaches the sum of VBP and VDOTS, the second pulse counter module The third channel of 422 triggers an interrupt request to disable the third pulse counter module 423 through the CPU 440.
步骤S730中由装置400的多路串行总线模块410传输至显示设备的RGB接口的图像数据信号可以是利用DMA模块450从数据存储模块460读取并写入到多路串行总线模块410的。In step S730, the image data signal transmitted by the multi-channel serial bus module 410 of the device 400 to the RGB interface of the display device may be read from the data storage module 460 using the DMA module 450 and written to the multi-channel serial bus module 410. .
根据本公开的实施例的向显示设备的RGB接口传输信号的方法能够在没有RGB专用接口或专用接口芯片的情况下驱动采用RGB接口的显示设备,从而使更多型号的装置能够驱动采用RGB接口的显示设备,提高装置的选型范围,降低装置的硬件成本。此外,还能减轻该装置的CPU的负担。The method of transmitting signals to the RGB interface of a display device according to embodiments of the present disclosure can drive a display device using an RGB interface without an RGB dedicated interface or a dedicated interface chip, thereby enabling more types of devices to drive using the RGB interface. display equipment, improve the selection range of the device, and reduce the hardware cost of the device. In addition, the load on the device's CPU can be reduced.
需要注意的是,虽然上面以特定顺序描述了各个步骤,但是这不应该被理解为要求以所描述的特定顺序或先后顺序执行这些步骤。It should be noted that although the various steps are described above in a specific order, this should not be understood as requiring that these steps be performed in the specific order or sequence described.
本公开中涉及的装置、设备、***的方框图仅是示例性的,并不意图要求或暗示必须按照方框图示出的方式进行连接、布置、配置。如本领域技术人员将认识到的,可以按任意方式连接、布置、配置这些电路、器件、装置、设备、***,只要能够实现所期望的目的即可。The block diagrams of devices, equipment, and systems involved in the present disclosure are only exemplary, and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these circuits, devices, devices, equipment, and systems may be connected, arranged, and configured in any manner as long as the desired purpose is achieved.
本说明书中描述的过程和逻辑流程可以由执行一个或多个计算机程序以通过对输入数据进行操作并生成输出来执行功能的一个或多个可编程处理器来执行。过程和逻辑流程也可以由专用逻辑电路执行,并且装置也可以被实现为专用逻辑电路,专用逻辑电路例如是FPGA(现场可编程门阵列)或ASIC(专用集成电路)。
The processes and logic flows described in this specification may be performed by one or more programmable processors executing one or more computer programs to perform functions by operating on input data and generating output. Processes and logic flows may also be executed by, and devices may be implemented as, dedicated logic circuits, such as FPGAs (Field Programmable Gate Arrays) or ASICs (Application Specific Integrated Circuits).
本说明书中在单独的实施例的上下文中描述的某些特征也可以组合。相反,在单独实施例的上下文中描述的各种特征也可以在多个实施例中单独实施或者以任何合适的子组合实施。Certain features described in this specification in the context of separate embodiments may also be combined. Conversely, various features that are described in the context of separate embodiments can also be implemented in multiple embodiments separately or in any suitable subcombination.
本领域技术人员应该理解,上述的具体实施例仅是示例而非限制,可以根据设计需求和其它因素对本公开的实施例进行各种修改、组合、部分组合和替换,只要它们在所附权利要求或其等同的范围内,即属于本公开所要保护的权利范围。
Those skilled in the art should understand that the above-mentioned specific embodiments are only examples and not limitations, and the embodiments of the present disclosure can be variously modified, combined, partially combined and replaced according to design requirements and other factors, as long as they are in the appended claims. or its equivalent scope, it shall fall within the scope of rights to be protected by this disclosure.
Claims (16)
- 一种向显示设备的RGB接口传输信号的方法,包括:A method of transmitting signals to the RGB interface of a display device, including:利用多路串行总线模块产生时钟CLK信号;Use multiple serial bus modules to generate clock CLK signals;利用计数器模块产生水平同步HSYNC信号、垂直同步VSYNC信号和数据使能DE信号;以及Use the counter module to generate the horizontal synchronization HSYNC signal, vertical synchronization VSYNC signal and data enable DE signal; and利用所述多路串行总线模块将图像数据信号和所述时钟CLK信号传输至所述RGB接口,以及利用通用输入输出GPIO模块将所述HSYNC信号、所述VSYNC信号和所述DE信号传输到所述RGB接口。The multi-channel serial bus module is used to transmit the image data signal and the clock CLK signal to the RGB interface, and the general input and output GPIO module is used to transmit the HSYNC signal, the VSYNC signal and the DE signal to The RGB interface.
- 根据权利要求1所述的方法,其中所述计数器模块包括第一脉冲计数器模块,利用所述计数器模块产生所述HSYNC信号包括:The method of claim 1, wherein the counter module includes a first pulse counter module, and using the counter module to generate the HSYNC signal includes:将所述第一脉冲计数器模块的计数周期设置为水平同步信号后肩HBP、每行有效显示RGB像素总数HDOTS、水平同步信号前肩HFP的总和;The counting period of the first pulse counter module is set to the sum of the horizontal synchronization signal back shoulder HBP, the total number of effective display RGB pixels in each row HDOTS, and the horizontal synchronization signal front shoulder HFP;将所述第一脉冲计数器模块的通道匹配值设置为所述HSYNC信号的脉冲宽度HSW;Set the channel matching value of the first pulse counter module to the pulse width HSW of the HSYNC signal;将所述第一脉冲计数器模块的输出模式设置为脉宽调制PWM脉冲连续输出模式,并且将所述第一脉冲计数器模块的脉冲计数源设置为所述CLK信号。The output mode of the first pulse counter module is set to the pulse width modulation PWM pulse continuous output mode, and the pulse counting source of the first pulse counter module is set to the CLK signal.
- 根据权利要求2所述的方法,其中所述计数器模块包括第二脉冲计数器模块,利用所述计数器模块产生所述VSYNC信号包括:The method of claim 2, wherein the counter module includes a second pulse counter module, and using the counter module to generate the VSYNC signal includes:将所述第二脉冲计数器模块的计数周期设置为垂直同步信号后肩VBP、有效显示像素行VDOTS、垂直同步信号前肩VFP的总和;The counting period of the second pulse counter module is set to the sum of the vertical synchronization signal rear shoulder VBP, the effective display pixel row VDOTS, and the vertical synchronization signal front shoulder VFP;将所述第二脉冲计数器模块的第一通道匹配值设置为所述VSYNC信号的脉冲宽度VSW;Set the first channel matching value of the second pulse counter module to the pulse width VSW of the VSYNC signal;将所述第二脉冲计数器模块的输出模式设置为脉宽调制PWM脉冲连续输出模式,并且将所述第二脉冲计数器模块的脉冲计数源设置为所述HSYNC信号。The output mode of the second pulse counter module is set to the pulse width modulation PWM pulse continuous output mode, and the pulse counting source of the second pulse counter module is set to the HSYNC signal.
- 根据权利要求3所述的方法,其中所述计数器模块包括第三脉冲计数器模块,利用所述计数器模块产生所述DE信号包括:The method of claim 3, wherein the counter module includes a third pulse counter module, and using the counter module to generate the DE signal includes:将所述第三脉冲计数器模块的计数周期设置为所述HBP和所述HDOTS的总和;Set the counting period of the third pulse counter module to the sum of the HBP and the HDOTS;将所述第三脉冲计数器模块的通道匹配值设置为所述HBP;Setting the channel matching value of the third pulse counter module to the HBP;将所述第三脉冲计数器模块的输出模式设置为单脉冲输出模式,将所述第三脉冲计数器模块的脉冲计数源设置为所述CLK信号,并且将所述第三脉冲计数器模块的触发源设置为所述第一脉冲计数器模块的溢出标志位。The output mode of the third pulse counter module is set to the single pulse output mode, the pulse counting source of the third pulse counter module is set to the CLK signal, and the trigger source of the third pulse counter module is set is the overflow flag bit of the first pulse counter module.
- 根据权利要求4所述的方法,其中利用所述计数器模块产生所述DE信号还包括:The method of claim 4, wherein using the counter module to generate the DE signal further includes:将所述第二脉冲计数器模块的第二通道匹配值设置为所述VBP以及将所述第二脉冲计数器模块的第三通道匹配值设置为所述VBP和所述VDOTS的总和,以使得在所述第二脉冲计数器模块的计数值达到所述VBP时使能所述第三脉冲计数器模块,并且在所述第二 脉冲计数器模块的计数值达到所述VBP和所述VDOTS的总和时禁用所述第三脉冲计数器模块。The second channel matching value of the second pulse counter module is set to the VBP and the third channel matching value of the second pulse counter module is set to the sum of the VBP and the VDOTS, so that at the The third pulse counter module is enabled when the count value of the second pulse counter module reaches the VBP, and when the second The third pulse counter module is disabled when the count value of the pulse counter module reaches the sum of the VBP and the VDOTS.
- 根据权利要求5所述的方法,其中:The method of claim 5, wherein:在所述第二脉冲计数器模块的计数值达到所述VBP时,所述第二脉冲计数器模块的第二通道触发中断请求以通过中央处理器使能所述第三脉冲计数器模块;When the count value of the second pulse counter module reaches the VBP, the second channel of the second pulse counter module triggers an interrupt request to enable the third pulse counter module through the central processor;在所述第二脉冲计数器模块的计数值达到所述VBP和所述VDOTS的总和时,所述第二脉冲计数器模块的第三通道触发中断请求以通过中央处理器禁用所述第三脉冲计数器模块。When the count value of the second pulse counter module reaches the sum of the VBP and the VDOTS, the third channel of the second pulse counter module triggers an interrupt request to disable the third pulse counter module through the central processor. .
- 根据权利要求1所述的方法,其中利用直接存储器存取DMA模块从数据存储模块读取所述图像数据信号和将所述图像数据信号写入所述多路串行总线模块。The method according to claim 1, wherein a direct memory access DMA module is used to read the image data signal from the data storage module and write the image data signal to the multiplex serial bus module.
- 根据权利要求1所述的方法,其中所述多路串行总线模块包括四数据线串行外设接口(QSPI)、八数据线串行外设接口(OSPI)或FlexIO模块。The method of claim 1, wherein the multi-channel serial bus module includes a four-line serial peripheral interface (QSPI), an eight-line serial peripheral interface (OSPI) or a FlexIO module.
- 一种向显示设备的RGB接口传输信号的装置,包括:A device for transmitting signals to the RGB interface of a display device, including:多路串行总线模块,其产生时钟CLK信号,将图像数据信号和所述时钟CLK信号传输至所述RGB接口;A multi-channel serial bus module generates a clock CLK signal and transmits the image data signal and the clock CLK signal to the RGB interface;计数器模块,其产生水平同步HSYNC信号、垂直同步VSYNC信号和数据使能DE信号;以及a counter module, which generates a horizontal synchronization HSYNC signal, a vertical synchronization VSYNC signal and a data enable DE signal; and通用输入输出GPIO模块,其将所述HSYNC信号、所述VSYNC信号和所述DE信号传输到所述RGB接口。General input and output GPIO module, which transmits the HSYNC signal, the VSYNC signal and the DE signal to the RGB interface.
- 根据权利要求9所述的装置,其中所述计数器模块包括第一脉冲计数器模块,所述计数器模块产生所述HSYNC信号包括:The device of claim 9, wherein the counter module includes a first pulse counter module, and the counter module generating the HSYNC signal includes:将所述第一脉冲计数器模块的计数周期设置为水平同步信号后肩HBP、每行有效显示RGB像素总数HDOTS、水平同步信号前肩HFP的总和;The counting period of the first pulse counter module is set to the sum of the horizontal synchronization signal back shoulder HBP, the total number of effective display RGB pixels in each row HDOTS, and the horizontal synchronization signal front shoulder HFP;将所述第一脉冲计数器模块的通道匹配值设置为所述HSYNC信号的脉冲宽度HSW;Set the channel matching value of the first pulse counter module to the pulse width HSW of the HSYNC signal;将所述第一脉冲计数器模块的输出模式设置为脉宽调制PWM脉冲连续输出模式,并且将所述第一脉冲计数器模块的脉冲计数源设置为所述CLK信号。The output mode of the first pulse counter module is set to the pulse width modulation PWM pulse continuous output mode, and the pulse counting source of the first pulse counter module is set to the CLK signal.
- 根据权利要求10所述的装置,其中所述计数器模块包括第二脉冲计数器模块,所述计数器模块产生所述VSYNC信号包括:The device according to claim 10, wherein the counter module comprises a second pulse counter module, and the counter module generates the VSYNC signal comprising:将所述第二脉冲计数器模块的计数周期设置为垂直同步信号后肩VBP、有效显示像素行VDOTS、垂直同步信号前肩VFP的总和;The counting period of the second pulse counter module is set to the sum of the vertical synchronization signal rear shoulder VBP, the effective display pixel row VDOTS, and the vertical synchronization signal front shoulder VFP;将所述第二脉冲计数器模块的第一通道匹配值设置为所述VSYNC信号的脉冲宽度VSW;Set the first channel matching value of the second pulse counter module to the pulse width VSW of the VSYNC signal;将所述第二脉冲计数器模块的输出模式设置为脉宽调制PWM脉冲连续输出模式,并且将所述第二脉冲计数器模块的脉冲计数源设置为所述HSYNC信号。The output mode of the second pulse counter module is set to the pulse width modulation PWM pulse continuous output mode, and the pulse counting source of the second pulse counter module is set to the HSYNC signal.
- 根据权利要求11所述的装置,其中所述计数器模块包括第三脉冲计数器模块,所 述计数器模块产生所述DE信号包括:The device of claim 11, wherein the counter module includes a third pulse counter module, the The counter module generating the DE signal includes:将所述第三脉冲计数器模块的计数周期设置为所述HBP和所述HDOTS的总和;Set the counting period of the third pulse counter module to the sum of the HBP and the HDOTS;将所述第三脉冲计数器模块的通道匹配值设置为所述HBP;Set the channel matching value of the third pulse counter module to the HBP;将所述第三脉冲计数器模块的输出模式设置为单脉冲输出模式,将所述第三脉冲计数器模块的脉冲计数源设置为所述CLK信号,并且将所述第三脉冲计数器模块的触发源设置为所述第一脉冲计数器模块的溢出标志位。The output mode of the third pulse counter module is set to the single pulse output mode, the pulse counting source of the third pulse counter module is set to the CLK signal, and the trigger source of the third pulse counter module is set is the overflow flag bit of the first pulse counter module.
- 根据权利要求12所述的装置,其中所述计数器模块产生所述DE信号还包括:The apparatus of claim 12, wherein generating the DE signal by the counter module further includes:将所述第二脉冲计数器模块的第二通道匹配值设置为所述VBP以及将所述第二脉冲计数器模块的第三通道匹配值设置为所述VBP和所述VDOTS的总和,以使得在所述第二脉冲计数器模块的计数值达到所述VBP时使能所述第三脉冲计数器模块,并且在所述第二脉冲计数器模块的计数值达到所述VBP和所述VDOTS的总和时禁用所述第三脉冲计数器模块。The second channel matching value of the second pulse counter module is set to the VBP and the third channel matching value of the second pulse counter module is set to the sum of the VBP and the VDOTS, so that at the The third pulse counter module is enabled when the count value of the second pulse counter module reaches the VBP, and is disabled when the count value of the second pulse counter module reaches the sum of the VBP and the VDOTS. The third pulse counter module.
- 根据权利要求13所述的装置,还包括中央处理器,其中:The apparatus of claim 13, further comprising a central processing unit, wherein:在所述第二脉冲计数器模块的计数值达到所述VBP时,所述第二脉冲计数器模块的第二通道触发中断请求以通过所述中央处理器使能所述第三脉冲计数器模块;When the count value of the second pulse counter module reaches the VBP, the second channel of the second pulse counter module triggers an interrupt request to enable the third pulse counter module through the central processor;在所述第二脉冲计数器模块的计数值达到所述VBP和所述VDOTS的总和时,所述第二脉冲计数器模块的第三通道触发中断请求以通过所述中央处理器禁用所述第三脉冲计数器模块。When the count value of the second pulse counter module reaches the sum of the VBP and the VDOTS, the third channel of the second pulse counter module triggers an interrupt request to disable the third pulse through the central processor Counter module.
- 根据权利要求9所述的装置,还包括直接存储器存取DMA模块和数据存储模块,其中所述DMA模块从所述数据存储模块读取所述图像数据信号和将所述图像数据信号写入所述多路串行总线模块。The apparatus of claim 9, further comprising a direct memory access DMA module and a data storage module, wherein the DMA module reads the image data signal from the data storage module and writes the image data signal to the data storage module. Described multi-channel serial bus module.
- 根据权利要求9所述的装置,其中所述多路串行总线模块包括四数据线串行外设接口(QSPI)、八数据线串行外设接口(OSPI)或FlexIO模块。 The device of claim 9, wherein the multi-channel serial bus module includes a four-line serial peripheral interface (QSPI), an eight-line serial peripheral interface (OSPI), or a FlexIO module.
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CN101405940A (en) * | 2006-05-24 | 2009-04-08 | 夏普株式会社 | Counter circuit, display unit and control signal generation circuit equipped with the counter circuit |
CN101656056A (en) * | 2008-08-20 | 2010-02-24 | 三星电子株式会社 | Timing controller and display apparatus having the same |
CN102074205A (en) * | 2009-11-19 | 2011-05-25 | 航天信息股份有限公司 | Liquid crystal display (LCD) controller and control method thereof |
CN110933340A (en) * | 2018-09-19 | 2020-03-27 | 杭州钜研图像技术有限公司 | Image acquisition circuit and method based on counting synchronization |
CN114428753A (en) * | 2020-10-29 | 2022-05-03 | 施耐德电器工业公司 | Display data transmission device and display data transmission method |
CN114694558A (en) * | 2020-12-30 | 2022-07-01 | 新唐科技股份有限公司 | Control device and display device |
-
2022
- 2022-09-23 CN CN202211168223.XA patent/CN117809542A/en active Pending
-
2023
- 2023-09-21 WO PCT/CN2023/120401 patent/WO2024061318A1/en unknown
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US20070200843A1 (en) * | 2006-02-28 | 2007-08-30 | Jong-Kon Bae | Display driving integrated circuit and method of generating system clock signal using oscillator clock signal |
CN101405940A (en) * | 2006-05-24 | 2009-04-08 | 夏普株式会社 | Counter circuit, display unit and control signal generation circuit equipped with the counter circuit |
CN101656056A (en) * | 2008-08-20 | 2010-02-24 | 三星电子株式会社 | Timing controller and display apparatus having the same |
CN102074205A (en) * | 2009-11-19 | 2011-05-25 | 航天信息股份有限公司 | Liquid crystal display (LCD) controller and control method thereof |
CN110933340A (en) * | 2018-09-19 | 2020-03-27 | 杭州钜研图像技术有限公司 | Image acquisition circuit and method based on counting synchronization |
CN114428753A (en) * | 2020-10-29 | 2022-05-03 | 施耐德电器工业公司 | Display data transmission device and display data transmission method |
CN114694558A (en) * | 2020-12-30 | 2022-07-01 | 新唐科技股份有限公司 | Control device and display device |
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