WO2024046063A1 - 显示装置和刷新驱动方法 - Google Patents
显示装置和刷新驱动方法 Download PDFInfo
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- WO2024046063A1 WO2024046063A1 PCT/CN2023/111902 CN2023111902W WO2024046063A1 WO 2024046063 A1 WO2024046063 A1 WO 2024046063A1 CN 2023111902 W CN2023111902 W CN 2023111902W WO 2024046063 A1 WO2024046063 A1 WO 2024046063A1
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- display area
- frequency
- refresh
- goa
- refresh frequency
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- 230000007704 transition Effects 0.000 claims description 17
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/02—Details of power systems and of start or stop of display operation
- G09G2330/021—Power management, e.g. power saving
Definitions
- the present disclosure relates to the field of display technology, and in particular, to a display device and a refresh driving method.
- an embodiment of the present disclosure provides a display device, including a display panel and a driving module; the display panel includes a first display area, a second display area, and multiple rows and columns of pixel circuits;
- the driving module is used to control the refresh frequency of the pixel circuit provided in the first display area to be a first refresh frequency, and to control the refresh frequency of the pixel circuit provided in the second display area to be different from the first refresh frequency.
- the driving module is used to control the image displayed in a part of the display area included in the display panel when it is determined that the image displayed in another part of the display area included in the display panel does not change.
- the refresh frequency of the pixel circuit is the first refresh frequency, and the refresh frequency of the other part of the display area is controlled to be less than the first refresh frequency; the part of the display area is an updated display area, and the other part of the display area is not updated. display area; the updated display area is the first display area, and the unupdated display area is the second display area.
- the driving module is also used to adjust the update display area by controlling the frequency of the first start signal and the frequency of the second start signal when at least one row of pixel circuits is provided in the update display area.
- the driver module includes a first updated GOA module and a second updated GOA module;
- the first updated GOA module is used to provide N-type scanning signals for the at least one row of pixel circuits
- the second updated GOA module is used to provide P-type scanning signals for the at least one row of pixel circuits
- the first updated GOA module includes multiple levels of first updated GOA circuits, and the second updated GOA module includes multiple sets of second updated GOA circuits;
- the first update GOA circuit included in the first update GOA module is connected to the first start signal, and the first update GOA circuit included in the second update GOA module is connected to the first update GOA circuit. 2. Start signal.
- the non-updated display area is provided with two adjacent pixel circuit groups adjacent to at least one row of pixel circuits in the updated display area; the adjacent pixel circuit groups include at least one row of transition pixel circuits;
- the driving module is used to control the refresh frequency of the at least one row of transition pixel circuits to a second refresh frequency, and the The second refresh frequency is lower than the first refresh frequency, and the second refresh frequency is higher than the refresh frequency of the other part of the display area.
- the non-updated display area is also provided with a non-adjacent pixel circuit group in addition to the adjacent pixel circuit group; the non-adjacent pixel circuit group includes at least one row of pixel circuits;
- the driving module is used to control the refresh frequency of the pixel circuits included in the non-adjacent pixel circuit group to be a third refresh frequency; the third refresh frequency is smaller than the second refresh frequency.
- the pixel circuit when M rows and N columns of pixel circuits are provided in the update display area, and N is less than the total number of columns of pixel circuits included in the display panel, the pixel circuit includes a write control circuit; M and N is a positive integer;
- the control end of the write control circuit is electrically connected to the write control line, the first end of the write control circuit is electrically connected to the data line, and the second end of the write control circuit is electrically connected to the data write node. ;
- the write control circuit is used to control the communication between the data line and the data write node under the control of the write control signal provided by the write control line;
- the driving module is used to control the frequency of the write control signal connected to the control end of the write control circuit included in the pixel circuit located in the same row and different columns as the M rows and N columns pixel circuit, so that the frequency is in accordance with the The refresh frequency of the pixel circuits in M rows and N columns located in the same row but in different columns is less than the first refresh frequency.
- the driving module is also used to control the frequency of the write control signal connected to the control end of the write control circuit included in the M rows and N columns pixel circuit, so that the M rows and N columns pixels
- the refresh frequency of the circuit is the first refresh frequency.
- an embodiment of the present disclosure provides a refresh driving method applied to a display device, where the display device includes a display panel and a driving module; the display panel includes a first display area, a second display area and a Multi-row and multi-column pixel circuits; the refresh driving method includes:
- the driving module controls the refresh frequency of the pixel circuit provided in the first display area to be the first refresh frequency, and the driving module controls the refresh frequency of the pixel circuit provided in the second display area to be the same as the first refresh frequency.
- the frequency is different.
- the refresh driving method includes:
- the refresh frequency of the pixel circuit in the partial display area is controlled to be the first refresh frequency. , controlling the refresh frequency of the other part of the display area to be less than the first refresh frequency;
- the partial display area is the updated display area, and the other part of the display area is the non-updated display area; the updated display area is the first display area, and the non-updated display area is the second display area.
- At least one embodiment of the present disclosure includes: when at least one row of pixel circuits is provided in the update display area, adjusting the update display area by controlling the frequency of the first start signal and the frequency of the second start signal. The refresh frequency of at least one row of pixel circuits.
- the display panel further includes a first update GOA module and a second update GOA module, the first update GOA module is used to provide N-type scanning signals for the at least one row of pixel circuits, and the third update GOA module
- the second updated GOA module is used to provide P-type scanning signals for the at least one row of pixel circuits;
- the first updated GOA module includes a multi-level An updated GOA circuit, the second updated GOA module includes a plurality of sets of second updated GOA circuits; the first updated GOA circuit included in the first updated GOA module is connected to the first start signal, so The first-level second update GOA circuit included in the second update GOA module is connected to the second start signal.
- the non-updated display area is provided with two adjacent pixel circuit groups adjacent to at least one row of pixel circuits in the updated display area; the adjacent pixel circuit groups include at least one row of transition pixel circuits;
- the refresh driving method further includes: controlling the refresh frequency of the at least one row of transition pixel circuits to a second refresh frequency, where the second refresh frequency is smaller than the first refresh frequency.
- the non-updated display area is also provided with a non-adjacent pixel circuit group in addition to the adjacent pixel circuit group; the non-adjacent pixel circuit group includes non-adjacent pixel circuits;
- the refresh driving method further includes: controlling the refresh frequency of the non-adjacent pixel circuit to a third refresh frequency; the third refresh frequency is smaller than the second refresh frequency.
- the pixel circuit when there are M rows and N columns of pixel circuits in the update display area, and N is less than the total number of columns of pixel circuits included in the display panel, the pixel circuit includes a write control circuit; the write The control end of the write control circuit is electrically connected to the write control line, the first end of the write control circuit is electrically connected to the data line, and the second end of the write control circuit is electrically connected to the data write node;
- the write control circuit is used to control the communication between the data line and the data write node under the control of the write control signal provided by the write control line; M and N are positive integers;
- the refresh driver Methods include:
- the refresh frequencies of pixel circuits in the same row and different columns are less than the first refresh frequency.
- the refresh driving method according to at least one embodiment of the present disclosure also includes:
- the refresh frequency of the M rows and N columns pixel circuit is the first refresh frequency.
- FIG. 1 is a schematic diagram of partitions of a display panel of a display device according to the present disclosure
- Figure 2 is a structural diagram of at least one embodiment of the display device according to the present disclosure.
- Figure 3 is an operating sequence diagram of at least one embodiment of the display device shown in Figure 2;
- Figure 4 is a structural diagram of at least one embodiment of the display device according to the present disclosure.
- Figure 5 is an operating sequence diagram of at least one embodiment of the display device shown in Figure 4.
- FIG. 6 is a schematic diagram of partitions of the display panel of the display device according to the present disclosure.
- Figure 7 is another operating sequence diagram of at least one embodiment of the display device shown in Figure 4.
- FIG. 8 is a circuit diagram of at least one embodiment of a pixel circuit in a display device according to the present disclosure.
- Figure 9 is a circuit diagram of at least one embodiment of the pixel circuit
- Figure 10 is a schematic diagram of the partitions of the display panel
- FIG. 11 is a circuit diagram of at least one embodiment of the first GOA circuit in the display device of the present disclosure.
- FIG. 12 is a circuit diagram of at least one embodiment of the second GOA circuit in the display device of the present disclosure.
- the display device includes a display panel and a driving module; the display panel includes a first display area, a second display area and multiple rows and multiple columns of pixel circuits;
- the driving module is used to control the refresh frequency of the pixel circuit provided in the first display area to be a first refresh frequency, and to control the refresh frequency of the pixel circuit provided in the second display area to be different from the first refresh frequency.
- the display device described in the embodiments of the present disclosure can set corresponding refresh frequencies for different display areas, so as to reduce power consumption while displaying images normally.
- At least one row and at least one column of pixel circuits are provided in the first display area, and at least one row and at least one column of pixel circuits are provided in the second display area.
- the display device includes a display panel and a driving module
- the display panel includes multiple rows and multiple columns of pixel circuits
- the driving module is used to control the pixel circuit in the partial display area when it is determined that the picture displayed in a part of the display area included in the display panel changes and the picture displayed in another part of the display area included in the display panel does not change.
- the refresh frequency is a first refresh frequency, and the refresh frequency of the other part of the display area is controlled to be less than the first refresh frequency;
- the partial display area is the updated display area, and the other part of the display area is the non-updated display area; the updated display area is the first display area, and the non-updated display area is the second display area.
- the updated display area and the non-updated display area in this patent are relative terms.
- the non-updated display area refers to a display area with a lower update frequency, and the update frequency of this area is higher than the update frequency of the updated display area.
- the update frequency of the unupdated display area is 30HZ-45HZ lower than the update frequency of the updated display area; or, if the display area is not updated, it seems to the human eye that the picture has basically no change or changes very slowly, such as 0HZ ⁇ 30HZ. (0HZ can refer to the still state of the picture).
- the driving module determines that the picture displayed in part of the display area included in the display panel changes, but the picture displayed in another part of the display area included in the display panel does not change, so The driving module controls the refresh frequency of the pixel circuit in the display area where the picture is updated to be the first refresh frequency, and controls the refresh frequency of the pixel circuit in the display area where the picture is not updated to be less than the first refresh frequency, so as to be able to Reduce power consumption while displaying images normally.
- the related OLED (organic light-emitting diode) display when the display screen is updated, the full screen will be updated.
- the drive power consumption is high. If a display panel using low-frequency technology such as LTPO (Low Temperature Polycrystalline Oxide) can keep the display brightness unchanged for a long time, the local refresh driving method proposed in the embodiment of the present disclosure can be selected.
- the partial refresh driving method proposed in the embodiment of the present disclosure updates local data on the display screen, the display panel only refreshes the part of the screen data updated at high frequency, while other parts remain refreshed at low frequency, thereby minimizing the driving power consumption.
- the driving module is also used to adjust the frequency of the first start signal and the frequency of the second start signal by controlling the frequency of the first start signal and the frequency of the second start signal when at least one row of pixel circuits is provided in the update display area.
- the updating frequency of at least one row of pixel circuits in the display area is also used to adjust the frequency of the first start signal and the frequency of the second start signal by controlling the frequency of the first start signal and the frequency of the second start signal when at least one row of pixel circuits is provided in the update display area.
- the driving module can adjust the refresh frequency of the pixel circuit in the updated display area by controlling the frequency of the first start signal and the frequency of the second start signal.
- the driver module includes a first updated GOA (Gate On Array, array substrate row driver) module and a second updated GOA module;
- GOA Gate On Array, array substrate row driver
- the first updated GOA module is used to provide N-type scanning signals for the at least one row of pixel circuits
- the second updated GOA module is used to provide P-type scanning signals for the at least one row of pixel circuits
- the first updated GOA module includes multiple levels of first updated GOA circuits, and the second updated GOA module includes multiple sets of second updated GOA circuits;
- the first update GOA circuit included in the first update GOA module is connected to the first start signal, and the first update GOA circuit included in the second update GOA module is connected to the first update GOA circuit. 2. Start signal.
- the first updated GOA module is used to provide N-type scanning signals for the pixel circuits in the updated display area
- the second updated GOA module is used to provide P-type scanning signals for the pixel circuits in the updated display area
- the drive module may also include a drive control unit. At least one embodiment of the present disclosure may control the first start signal connected to the first update GOA circuit of the first stage through the drive control unit, and the first stage
- the second update GOA circuit receives a second start signal to control and adjust the refresh frequency of the pixel circuit in the update display area.
- the non-updated display area is provided with two adjacent pixel circuit groups adjacent to at least one row of pixel circuits in the updated display area; the adjacent pixel circuit groups include at least A row of transition pixel circuits;
- the driving module is used to control the refresh frequency of the at least one row of transition pixel circuits to a second refresh frequency.
- the second refresh frequency is lower than the first refresh frequency.
- the second refresh frequency is higher than the other part of the display. How often the area is refreshed.
- the display area adjacent to the updated display area can be set as a transition display area, and the refresh frequency of the transition display area is a second refresh frequency, and the second refresh frequency is between the low frequency refresh frequency and the first refresh frequency. between them, thereby reducing the display difference, preventing the human eye from detecting it, and reducing the flicker and Mura (uneven display) problems that may be caused by the display difference in adjacent display areas.
- the low-frequency display frequency is the refresh frequency of the other part of the display area.
- the non-updated display area is also provided with a non-adjacent pixel circuit group in addition to the adjacent pixel circuit group; the non-adjacent pixel circuit group includes non-adjacent pixel circuits;
- the driving module is used to control the refresh frequency of the non-adjacent pixel circuit to a third refresh frequency; the third refresh frequency The new frequency is less than the second refresh frequency.
- the third refresh frequency is the low-frequency display frequency.
- the third refresh frequency may be less than or equal to 60 Hz.
- the third refresh frequency may be 1 Hz, 10 Hz, 20 Hz, 30 Hz, 40 Hz or 60 Hz, but is not limited thereto.
- the pixel circuit when M rows and N columns of pixel circuits are provided in the update display area, and N is less than the total number of columns of pixel circuits included in the display panel, the pixel circuit includes a write control circuit; M and N is a positive integer;
- the control end of the write control circuit is electrically connected to the write control line, the first end of the write control circuit is electrically connected to the data line, and the second end of the write control circuit is electrically connected to the data write node. ;
- the write control circuit is used to control the communication between the data line and the data write node under the control of the write control signal provided by the write control line;
- the driving module is used to control the frequency of the write control signal connected to the control end of the write control circuit included in the pixel circuit located in the same row and different columns as the M rows and N columns pixel circuit, so that the frequency is in accordance with the The refresh frequency of the pixel circuits in M rows and N columns located in the same row but in different columns is less than the first refresh frequency.
- the frequency of the write control signal can be controlled to The refresh frequency of the pixel circuits located in the same row but in different columns as the M rows and N columns of pixel circuits is controlled to be smaller than the first refresh frequency.
- the driving module is also used to control the frequency of the write control signal connected to the control end of the write control circuit included in the M rows and N columns pixel circuit, so that the The refresh frequency of the pixel circuits in M rows and N columns is the first refresh frequency.
- the effective display area of the display panel 10 can be divided into A display areas;
- the first preset display area is marked P1
- the second preset display area is marked P2
- the a-th preset display area is marked Pa
- the A-th preset display area is marked PA. area
- A is a positive integer, and a is a positive integer less than A.
- the corresponding display area can be automatically matched and refreshed according to the update of the display screen of the display panel, thereby minimizing power consumption.
- the driving module controls the a-th preset display area.
- the refresh frequency of the pixel circuit in the area Pa is the first refresh frequency; the driving module controls the refresh frequency of the pixel circuit in other display areas except the a-th preset display area Pa to be less than the first refresh frequency,
- the first refresh frequency may be 120 Hz, and the refresh frequency of the pixel circuits in other display areas except the a-th preset display area Pa may be 1 Hz; but it is not limited to this.
- the effective display area can be evenly divided into A display areas; or, the partitions can be divided into unequal partitions according to display rules.
- the desktop taskbar of an office computer can be divided into a separate display area
- the central display area when displaying a video can be divided into a separate display area
- the menu area and editing area of a text office can be divided into a separate display area respectively
- the folding display panel can be divided into two or Multi-fold areas can be divided into separate display areas; etc.
- the pixel circuit and the GOA circuit in the driving module can be partitioned;
- the driving module may include A first GOA modules and A second GOA modules; the a-th first GOA module corresponds to the a-th The default display area, the a-th second GOA module corresponds to the a-th default display area;
- the a-th first GOA module is used to provide corresponding N-type scanning signals to the pixel circuits disposed in the a-th preset display area;
- the a-th second GOA module is used to provide corresponding P-type scanning signals to the pixel circuits disposed in the a-th preset display area;
- the first updated GOA module is the a-th first GOA module
- the second updated GOA module is the a-th second GOA module.
- the driving module may include A first left GOA modules and A first right GOA modules. , A second left GOA module and A second right GOA module;
- the a-th first left GOA module and the a-th first right GOA module provide corresponding N-type scanning signals for the pixel circuit disposed in the a-th preset display area;
- the a-th second left GOA module and the a-th second right GOA module provide corresponding P-type scanning signals for the pixel circuit disposed in the a-th preset display area;
- the first updated GOA module includes the a-th first left GOA module and the a-th first right GOA module
- the The second updated GOA module includes the a-th second left GOA module and the a-th second right GOA module.
- each GOA module may include at least one level of GOA circuits cascaded with each other; the first GOA module may include at least one level of first GOA circuit, and the second GOA module may include at least one level of GOA circuit. Second GOA circuit;
- the first-level GOA circuit can provide corresponding N-type scanning signals for two rows of pixel circuits, and the second-level GOA circuit can provide corresponding P-type scanning signals for one row of pixel circuits; but it is not limited to this.
- the ones labeled are all rows of pixel circuits in the a-th preset display area
- labeled Xa+1 are all rows of pixel circuits in the a+1-th preset display area
- labeled XA-1 are the A-1th preset display All rows of pixel circuits in the area, labeled XA, are all rows of display circuits in the A-th preset display area;
- the one marked GN11 is the first left GOA module
- the one marked GNa-11 is the a-1 first left GOA module
- the one marked GNa1 is the a-th first left GOA module.
- Group, numbered GNa+11 is the a+1th one
- the first left GOA module, labeled GNA1, is the Ath first left GOA module;
- the one marked GN12 is the first first right GOA module
- the one marked GNa-12 is the a-1 first right GOA module
- the one marked GNa2 is the a-th first right GOA module.
- Group, numbered GNa+12 is the a+1th first right GOA module, numbered GNA2 is the Ath first right GOA module;
- the one marked GP11 is the first and second left GOA module, the one marked GPa-11 is the a-1 second left GOA module, and the one marked GPa1 is the a-th second left GOA module.
- the one labeled GPa+11 is the a+1 second left GOA module, and the one labeled GPA1 is the A second left GOA module;
- the one marked GP12 is the first and second right GOA module
- the one marked GPa-12 is the a-1 second right GOA module
- the one marked GPa2 is the a-th second right GOA module.
- the one labeled GPa+12 is the a+1 second right-hand GOA module
- the one labeled GPA2 is the A-th second right GOA module.
- the driving module may also include a driving control unit 20;
- the drive control unit 20 is used to provide the first first start signal NSTV1 to GN11 and GN12, provide the a-1th first start signal NSTVa-1 to GNa-11 and GNa-12, and provide the a-1th first start signal NSTVa-1 to GNa1 and GNa2.
- a first start signal NSTVa providing the a+1th first start signal NSTVa+1 to GNa+11 and GNa+12, and providing the Ath first start signal NSTVA to GNA1 and GNA2;
- the drive control unit 20 is used to provide the first second start signal GSTV1 for GP11 and GP12, provide the a-1 second start signal GSTVa-1 for GPa-11 and GPa-12, and provide the a-1 second start signal GSTVa-1 for GPa1 and GPa2.
- the a-th second start signal GSTVA is provided, the a+1-th second start signal GSTVA+1 is provided for GPa+11 and GPa+12, and the A-th second start signal GSTVA is provided for GPA1 and GPA2.
- the frequency of NSTV2a-1, the frequency of NSTV2a, the frequency of GSTV2a-1 and the frequency of GSTV2a can be increased. frequency to increase the refresh frequency of the pixel circuit located in the a-th preset display area.
- the gate of the eighth transistor T8 included in the pixel circuit is electrically connected to the first scan line GN, and the pixel circuit
- the gate of the second transistor T2 is electrically connected to the gate of the fourth transistor included in the pixel circuit and the second scan line GP. Therefore, the refresh frequency of the pixel circuit is related to the first GOA module that provides the first scan signal.
- the frequency of the accessed first start signal is related to the frequency of the second start signal accessed by the second GOA module that provides the second scanning signal.
- the frequency of the first start signal connected to the first GOA module is the same as the frequency of the first scanning signal output by the first GOA module, and the frequency of the first start signal connected to the second GOA module is the same.
- the frequency of the second starting signal is the same as the frequency of the second scanning signal output by the second GOA module, but is not limited to this.
- FIG. 3 is an operating sequence diagram of at least one embodiment shown in FIG. 2 .
- Vsync is the synchronization signal
- DE is the data enable signal
- Vd is the data voltage
- the frequency of NSTVa is greater than the frequency of NSTV1, the frequency of NSTVa is greater than the frequency of NSTVA; the frequency of GSTVa is greater than the frequency of GSTV1, the frequency of GSTVA is greater than the frequency of GSTVA; so that the frequency in the a-th preset display area
- the refresh frequency of the pixel circuit is greater than the refresh frequency of pixels located in other display areas.
- the first GOA module that provides the first scanning signal for the pixel circuits in the first display area when the refresh frequency of the pixel circuits in the first display area is 120 Hz, the first GOA module that provides the first scanning signal for the pixel circuits in the first display area is connected to The frequency of a starting signal, and the frequency of the second starting signal connected to the second GOA module that provides the second scanning signal for the pixel circuit in the first display area, may both be 120 Hz;
- the frequency of the first start signal accessed by the first GOA module that provides the first scanning signal to the pixel circuits in the first display area, and , the frequency of the second start signal accessed by the second GOA module that provides the second scanning signal to the pixel circuit in the first display area may all be the predetermined frequency.
- the ratio of the refresh frequency of the pixel circuit in the first display area to the refresh frequency of the pixel circuit in the second display area is 4, then the first scan signal of the first scan signal is provided for the pixel circuit in the first display area.
- the ratio of the frequency of the first start signal connected by the GOA module to the frequency of the first start signal connected by the first GOA module that provides the first scanning signal for the pixel circuit in the second display area can be 4, which is
- the frequency of the second start signal connected to the second GOA module that provides the second scan signal to the pixel circuit in the first display area is the same as the second GOA module that provides the second scan signal to the pixel circuit in the second display area.
- the ratio of the frequencies of the second start signal of the group access may be 4.
- the driving module may further include A lighting control modules and A third GOA modules;
- the one marked ES1 is the first light-emitting control module
- the one marked ESa-1 is the a-1th light-emitting control module
- the one marked ESa is the a-th light-emitting control module
- the one marked ESa+1 is the a+th one. 1.
- a light-emitting control module, the one labeled ESA is the A-th light-emitting control module; each light-emitting control module is used to provide light-emitting control signals for the pixel circuits provided in the corresponding display area;
- the one marked S1 is the first third GOA module
- the one marked Sa-1 is the a-1 third GOA module
- the one marked Sa is the a-th third GOA module
- the one marked Sa+ 1 is the a+1 third GOA module
- the one labeled SA is the A third GOA module
- each third GOA module is used to provide the third GOA module for the pixel circuit provided in the corresponding display area. Scan signal.
- the A lighting control modules included in the driving module can be cascaded with each other, and the first lighting control module is connected to the lighting control start signal ESTV;
- the A third GOA modules included in the driving module can be cascaded with each other, and the first third GOA module is connected to the third start signal STV3.
- the frequency of ESTV may be equal to the frequency of STV3, or the frequency of STV3 may be smaller than the frequency of ESTV.
- the frequency of ESTV may be greater than or equal to 120 Hz, and the frequency of STV3 may be greater than or equal to 120 Hz; for example, the frequency of ESTV may be 480 Hz, and the frequency of STV3 may be 240 Hz, but is not limited to this.
- the frequency of the data enable signal DE may be equal to the maximum refresh frequency of the pixel circuits in each display area included in the display panel, but is not limited to this.
- the frequency of Vd is related to the refresh frequency of the corresponding display area.
- the frequency of Vd is high.
- the frequency of Vd is high.
- the frequency of Vd is high.
- the frequency of Vd is low.
- the light-emitting control modules corresponding to different preset display areas can respectively correspond to a light-emitting start signal. At this time, the light-emitting control modules corresponding to the same preset display area are mutually phased. Connection, the lighting control modules corresponding to different preset display areas are not cascaded with each other;
- the third GOA modules corresponding to each different preset display area can respectively correspond to a third start signal. At this time, the third GOA modules corresponding to the same preset display area are cascaded with each other, corresponding to different The third GOA modules in the default display area are not cascaded with each other.
- FIG. 5 is an operating sequence diagram of at least one embodiment shown in FIG. 4 .
- Figure 5 adds a lighting control start signal ESTV on the basis of the working timing diagram shown in Figure 3, and the ESTV is provided to each lighting control module.
- each light-emitting control module and each third GOA module perform high-frequency refresh.
- the effective display area of the display panel 10 can be divided into A display areas;
- the first preset display area is marked P1
- the second preset display area is marked P2
- the a-1th preset display area is marked Pa-1
- the a-1th preset display area is marked Pa.
- a Default display area the one marked Pa+1 is the a+1 preset display area
- the one marked PA is the A-th preset display area;
- A is a positive integer, and a is a positive integer less than A.
- the display panel can be divided into A display areas.
- the adjacent areas to the updated display area can be used as transition display areas.
- the a-th preset display area Pa in FIG. 6 is an update display area
- the driving module is used to control the refresh frequency of the pixel circuit in Pa to be the first refresh frequency, and to control at least one of the refresh frequency of the pixel circuit in Pa-1 and the refresh frequency of the pixel circuit in Pa+1 to be the third refresh frequency.
- Second refresh frequency controlling at least one of the refresh frequency of the pixel circuit in P1 and the refresh frequency of the pixel circuit in PA to be a third refresh frequency;
- the first refresh frequency is greater than the second refresh frequency, and the second refresh frequency is greater than the third refresh frequency.
- the first refresh frequency may be, for example, 120 Hz
- the second refresh frequency may be, for example, 60 Hz
- the third refresh frequency may be, for example, 1 Hz, but is not limited thereto.
- FIG. 7 is another operating timing diagram of at least one embodiment shown in FIG. 4 .
- each The waveform of the starting signal is shown in Figure 7.
- the one labeled Vsync is the synchronization signal
- the one labeled DE is the data enable signal
- the one labeled ESTV is the lighting control start signal
- the one labeled GSTV1 is the first second start signal
- the one labeled GSTVA-1 is the a-1 second start signal
- the one labeled GSTVA is the a-th second start signal
- the starting signal, labeled GSTVA+1 is the a+1 second starting signal
- the one labeled GSTVA is the A-th second starting signal
- the one labeled NSTV1 is the first first starting signal
- labeled The one labeled NSTVa-1 is the a-1th first starting signal
- the one labeled NSTVa is the a-th first starting signal
- the one labeled NSTVa+1 is the a+1th first starting signal
- the one labeled NSTVA is the A-th first start signal
- the one labeled Vd is the data voltage.
- the frequency of GSTVa is greater than the frequency of GSTVA-1
- the frequency of GSTVA is greater than the frequency of GSTVA+1
- the frequency of GSTVA-1 is greater than the frequency of GSTVA1
- the frequency of GSTVA-1 is greater than the frequency of GSTVA
- the frequency of GSTVA+1 The frequency is greater than the frequency of GSTV1
- the frequency of GSTVA+1 is greater than the frequency of GSTVA;
- the frequency of NSTVa is greater than the frequency of NSTVa-1, the frequency of NSTVa is greater than the frequency of NSTVa+1, the frequency of NSTVa-1 is greater than the frequency of NSTV1, the frequency of NSTVa-1 is greater than the frequency of NSTVA, the frequency of NSTVa+1 is greater than the frequency of NSTV1, The frequency of NSTVa+1 is greater than the frequency of NSTVA.
- each light-emitting control module and each third GOA module perform high-frequency refresh.
- the structure of the pixel circuit may be as shown in FIG. 8 .
- At least one embodiment of the pixel circuit may include a first transistor T1 , a second transistor T2 , a third transistor T3 , a fourth transistor T4 , a fifth transistor T5 , a sixth transistor T6 , and a seventh transistor.
- the gate of T8 is electrically connected to the first scan line GN;
- the gate electrode of T2 and the gate electrode of T4 are both electrically connected to the second scan line GP;
- the gate electrode of T1, the gate electrode of T7 and the gate electrode of T9 are all electrically connected to the third scan line Sc;
- T5 and T6 are both electrically connected to the light-emitting control line EC;
- T3 is the drive transistor
- the first scan line GN is used to provide a first scan signal, and the first scan signal is an N-type scan signal;
- the second scan line GP is used to provide a second scan signal, and the second scan signal is a P-type scan signal;
- the third scan line Sc is used to provide a third scan signal
- the light emission control line Sc is used to provide a light emission control signal.
- the line marked D1 is the data line, and the data line D1 is used to provide the data voltage Vd; the line marked Vi1 is the first initial voltage, the line marked Vi2 is the second initial voltage, and the line marked Vref is the reference voltage. , the one marked VDD is the high voltage end, and the one marked VSS is the low voltage end.
- T2 and T4 are p-type transistors
- T8 is an n-type transistor
- T1 T7 and T9 are p-type transistors
- T5 and T6 are p-type transistors.
- the structure of the pixel circuit is not limited to that shown in FIG. 8.
- the pixel circuit can be controlled by a first scanning signal, a second scanning signal, a third scanning signal and a light emission control signal. Just shine.
- At least one embodiment of the pixel circuit may further include a write control circuit 90;
- the control end of the write control circuit 90 is electrically connected to the write control line XC, the first end of the write control circuit 90 is electrically connected to the data line D1, and the second end of the write control circuit 90 is electrically connected to the data line D1.
- the write node SX is electrically connected; the write control circuit 90 is used to control the connection between the data line D1 and the data write node SX under the control of the write control signal provided by the write control line XC. Connected.
- At least one embodiment of the pixel circuit may further include an auxiliary control circuit 91;
- the control terminal of the auxiliary control circuit 91 is electrically connected to the auxiliary control line GC.
- the first terminal of the auxiliary control circuit 91 is electrically connected to the gate of the eighth transistor T8. That is, the second terminal of the auxiliary control circuit 91 is electrically connected to the gate of the eighth transistor T8.
- the first scan line GN is connected; the auxiliary control circuit 91 is used to control the connection between the first scan line GN and the gate of the eighth transistor T8 under the control of the auxiliary control signal provided by the auxiliary control line GC. Connected.
- the first scan signal on the first scan line GN may be provided by a corresponding first GOA circuit included in the first GOA module.
- the auxiliary control line of the auxiliary control circuit 91 of the pixel circuit corresponding to the un-updated area Pa1 can be controlled.
- GC causing the eighth transistor to remain in an inactive state (for example, in a closed state). This ensures that even if other transistors of the pixel circuit in the un-updated area Pa1 operate, the reset of the data signal in the un-updated area Pa1 will not be affected.
- the auxiliary control line GC of the auxiliary control circuit 91 in the pixel circuit corresponding to the update area Pa0 can be controlled so that the eighth transistor of the pixel circuit in the update area Pa0 maintains a normal working state and the corresponding picture is updated.
- both the writing control circuit 90 and the auxiliary control circuit 91 can be implemented using field effect transistors (for example, they can have the same structure as other transistors in the pixel circuit, and can be P-type or N-type). I won’t go into details here.
- the refresh display area included in the effective display area of the display panel is the middle display area Pa0 included in the a-th preset display area;
- the display area on the left side of the refresh display area As included in the a-th preset display area is marked as Pa1, and the display area on the right side of the refresh display area As included in the a-th preset display area is marked as Pa2.
- the area marked P1 is the first preset display area
- the area marked PA is the A-th preset display area.
- the structure of the pixel circuit in the a-th preset display area may be as shown in Figure 9.
- the pixel circuit includes a write control circuit.
- the refresh frequency of the pixel circuit in Pa0 can be controlled as the first frequency by controlling the frequency of the write control signal, and the refresh frequency of the pixel circuit in Pa1 and the pixels in Pa2 can be controlled.
- the refresh frequency of the circuit is less than the first frequency.
- the writing control circuit 90 and the auxiliary control circuit 91 of FIG. 9 can be located in the display area of the display panel, or can also be located in the non-display area of the display panel.
- the write control circuit 90 is integrated in the driver module, or the write control circuit 9 is integrated in the data signal driver chip.
- the driving module can independently control the update frequency of the pixel circuit to achieve lateral partitioning (for example: P1...PA) by controlling the first update GOA module and the second update GOA module, etc. ); of course, vertical partitioning (for example: Pa1...Pa2) is achieved through the auxiliary control circuit 91 and/or the write control circuit 90.
- the drive module can also be combined with the auxiliary control circuit 91 and/or the write control circuit 90 to achieve horizontal and vertical mixed partitioning (as shown in Figure 10): for example: the drive module both controls the first update GOA module and The second update GOA module etc.
- FIG. 11 is a circuit diagram of at least one embodiment of a first GOA circuit for providing an N-type scan signal in at least one embodiment of the present disclosure.
- the first GOA circuit may include a first display control transistor M1, a second display control transistor M2, a third display control transistor M3, a fourth display control transistor M4, a fifth display control transistor Control transistor M5, sixth display control transistor M6, seventh display control transistor M7, eighth display control transistor M8, ninth display control transistor M9, tenth display control transistor M10, eleventh display control transistor M11, twelfth
- the terminal labeled CK is the first clock signal terminal
- the terminal labeled I1 is the first input terminal
- the terminal labeled CB is the second clock signal terminal
- the terminal labeled VGL is the low voltage terminal
- the terminal labeled VGH is is the high voltage end
- the one labeled PD1 is the first pull-down node
- the one labeled PU1 is the first pull-up node
- the one labeled SO1 is the first scan signal output terminal
- the one labeled R1 is the reset terminal.
- the second pole of M11 and the first pole of M8 may both be electrically connected to the high voltage terminal VGH.
- the first electrode may be a source electrode or a drain electrode
- the second electrode may be a drain electrode or a source electrode
- the first input end of the first-stage first GOA circuit included in each first GOA module is connected to the first start signal.
- the first first left GOA module and the first first right GOA module can both access the first first starting signal
- the a-1th first left GOA module and the ath -1 first right GOA module can access the a-1 first starting signal
- both a-th first left GOA module and a-th first right GOA module can access the a-1th first starting signal.
- the a first starting signal, the a+1 first left GOA module and the a+1 first right GOA module can both access the a+1 first starting signal, the Ath first Both a left GOA module and the A-th first right GOA module can access the A-th first start signal.
- At least one embodiment of the circuit shown in Figure 11 can also be used to provide a lighting control signal.
- the circuit can be a lighting control signal generating circuit included in each lighting control module; the first lighting control module includes a first The input terminal of the stage light-emitting control signal generating circuit can be connected with the light-emitting control start signal.
- At least one embodiment of the circuit shown in FIG. 11 can also be used to provide a third scan signal.
- the circuit can It is assumed that the third GOA circuit included in the third GOA module; the input end of the first-level third GOA circuit included in the first third GOA module is connected to the third start signal.
- At least one embodiment of the circuit shown in FIG. 11 can be used to provide an N-type scan signal, a lighting control signal or a third scan signal.
- the first clock The first clock signal provided by the signal terminal CK may be different from each other, and the two clock signals provided by the second clock signal terminal CB may be different from each other.
- FIG. 12 is a circuit diagram of at least one embodiment of a second GOA circuit for providing a P-type scan signal in at least one embodiment of the present disclosure.
- the second GOA circuit may include a fifteenth display control transistor M15 , a sixteenth display control transistor M16 , a seventeenth display control transistor M17 , and an eighteenth display control transistor M18 , the nineteenth display control transistor M19, the twentieth display control transistor M20, the twenty-first display control transistor M21, the twenty-second display control transistor M22, the twenty-third display control transistor M23, the twenty-fourth display control transistor Transistor M24, fourth capacitor C4 and fifth capacitor C5.
- the terminal labeled I2 is the second input terminal
- the terminal labeled R2 is the second reset terminal
- the terminal labeled VGL is the low voltage terminal
- the terminal labeled VGH is the high voltage terminal
- the terminal labeled SO2 is the second input terminal.
- the one labeled GCK1 is the first output clock signal line
- the one labeled GCK2 is the second output clock signal line
- the one labeled GCK3 is the third output clock signal line;
- the second scanning signal output terminal is used to provide a second scanning signal.
- the first output clock signal line GCK1 is used to provide a first output clock signal
- the second output clock signal line GCK2 is used to provide a second output clock signal
- the third output clock signal line GCK3 is used to A third output clock signal is provided.
- the second input end of the first-stage second GOA circuit included in the second GOA module is connected to the second start signal.
- At least one embodiment of the first GOA circuit can be used to provide an N-type scan signal for the first scan line GN
- at least one embodiment of the second GOA circuit can be used to provide the second scan line GN with an N-type scan signal.
- GP provides a P-type scan signal
- at least one embodiment of the light-emitting control signal generating circuit can be used to provide a light-emitting control circuit for the light-emitting control line EC
- at least one embodiment of the third GOA circuit can be used to provide a third scan line Sc.
- the structure of at least one embodiment of the first GOA circuit, the structure of at least one embodiment of the light emission control signal generation circuit, and the structure of at least one embodiment of the third GOA circuit can be as shown in Figure 11.
- the second GOA The structure of at least one embodiment of the circuit may be as shown in FIG. 12 .
- each first left GOA module and each first right GOA module can provide an N-type gate electrode of T8 in FIG. 8 Scanning signals
- each second left GOA circuit and each second right GOA circuit can provide P-type scanning signals for the gate of T2 in Figure 8 and the gate of T4 in Figure 8
- each light-emitting control module can To provide a lighting control signal for the gate of T5 in Figure 8 and the gate of T6 in Figure 8
- each third GOA module can provide a third GOA module for the gate of T7 in Figure 8 and the gate of T9 in Figure 8.
- Each first left GOA module and each first right GOA module can both provide N-type scanning signals for the gate of T8 in Figure 8 , and each second left GOA circuit can be used to provide T2 in Figure 8
- the gate of T4 in Figure 8 provides a P-type scan signal.
- Each second right GOA circuit can be used to provide a P-type scan signal for the gate of T4 in Figure 8.
- Each light-emitting control module can provide a P-type scan signal for the gate of T5 in Figure 8.
- the gate of T6 in FIG. 8 provides a light emitting control signal
- each third GOA module can provide a third scanning signal for the gate of T7 in FIG. 8 and the gate of T9 in FIG. 8 .
- the refresh driving method described in the embodiment of the present disclosure is applied to a display device.
- the display device includes a display panel.
- the display panel includes multiple rows and multiple columns of pixel circuits.
- the refresh frequency method includes:
- the refresh frequency of the pixel circuit in the partial display area is controlled to be the first refresh frequency. , controlling the refresh frequency of the other part of the display area to be less than the first refresh frequency; the part of the display area is an updated display area, and the other part of the display area is an unupdated display area.
- the driving module determines that the picture displayed in part of the display area included in the display panel changes, but the picture displayed in another part of the display area included in the display panel does not change, the The driving module controls the refresh frequency of the pixel circuit in the display area where the picture is updated to be the first refresh frequency, and controls the refresh frequency of the pixel circuit in the display area where the picture is not updated to be less than the first refresh frequency, so as to be able to Reduce power consumption while displaying the screen normally.
- the refresh driving method includes: when at least one row of pixel circuits is provided in the update display area, adjusting the update by controlling the frequency of the first start signal and the frequency of the second start signal.
- the refresh frequency of at least one row of pixel circuits in the display area includes: when at least one row of pixel circuits is provided in the update display area, adjusting the update by controlling the frequency of the first start signal and the frequency of the second start signal.
- the display panel further includes a first GOA module and a second GOA module.
- the first GOA module is used to provide N-type scanning signals for the at least one row of pixel circuits.
- the second GOA module A group is used to provide P-type scanning signals for the at least one row of pixel circuits;
- the first GOA module includes multiple levels of first GOA circuits, and the second GOA module includes multiple groups of second GOA circuits;
- the first The first-level first GOA circuit included in the GOA module is connected to the first start signal, and the first-level second GOA circuit included in the second GOA module is connected to the second start signal.
- the non-updated display area is provided with two adjacent pixel circuit groups adjacent to at least one row of pixel circuits in the updated display area; the adjacent pixel circuit groups include at least A row of transition pixel circuits;
- the refresh driving method further includes: controlling the refresh frequency of the at least one row of transition pixel circuits to a second refresh frequency, where the second refresh frequency is smaller than the first refresh frequency.
- the non-updated display area is also provided with a non-adjacent pixel circuit group in addition to the adjacent pixel circuit group; the non-adjacent pixel circuit group includes non-adjacent pixel circuits;
- the refresh driving method further includes: controlling the refresh frequency of the non-adjacent pixel circuit to a third refresh frequency; the third refresh frequency is smaller than the second refresh frequency.
- the pixel circuit when the update display area is provided with M rows and N columns of pixel circuits, and N When the total number of columns of pixel circuits included in the display panel is less than the total number of columns of pixel circuits included in the display panel, the pixel circuit includes a write control circuit; the control terminal of the write control circuit is electrically connected to the write control line, and the third terminal of the write control circuit One end is electrically connected to the data line, and the second end of the write control circuit is electrically connected to the data write node; the write control circuit is used to control the write control signal provided by the write control line. , controlling the connection between the data line and the data writing node; M and N are positive integers; the refresh driving method includes:
- the frequency of the write control signal connected to the control end of the write control circuit included in the pixel circuits located in the same row and different columns as the M rows and N columns of pixel circuits is less than the first refresh frequency.
- the display device provided in the embodiment of the present disclosure can be any product or component with a display function such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.
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Abstract
一种显示装置和刷新驱动方法。显示装置包括显示面板(10)和驱动模组;显示面板(10)包括第一显示区域、第二显示区域和多行多列像素电路;驱动模组用于控制设置于第一显示区域中的像素电路的刷新频率为第一刷新频率,控制设置于第二显示区域中的像素电路的刷新频率与第一刷新频率不同。能够在正常显示画面的同时降低功耗。
Description
相关申请的交叉引用
本申请主张在2022年8月29日在中国提交的中国专利申请号202211040233.5的优先权,其全部内容通过引用包含于此。
本公开涉及显示技术领域,尤其涉及一种显示装置和刷新驱动方法。
在相关的OLED(有机发光二极管)显示屏工作时,在显示画面更新时,会全屏更新,驱动功耗较高。
发明内容
在一个方面中,本公开实施例提供了一种显示装置,包括显示面板和驱动模组;所述显示面板包括第一显示区域、第二显示区域和多行多列像素电路;
所述驱动模组用于控制设置于第一显示区域中的像素电路的刷新频率为第一刷新频率,控制设置于第二显示区域中的像素电路的刷新频率与所述第一刷新频率不同。
可选的,所述驱动模组用于当判断到显示面板包括的部分显示区域显示的画面变化,所述显示面板包括的另一部分显示区域显示的画面不变化时,控制所述部分显示区域中的像素电路的刷新频率为第一刷新频率,控制所述另一部分显示区域的刷新频率小于所述第一刷新频率;所述部分显示区域为更新显示区域,所述的另一部分显示区域为未更新显示区域;所述更新显示区域为所述第一显示区域,所述未更新显示区域为所述第二显示区域。
可选的,所述驱动模组还用于当所述更新显示区域中设置有至少一行像素电路时,通过控制第一起始信号的频率和第二起始信号的频率来调节所述更新显示区域中的至少一行像素电路的刷新频率。
可选的,所述驱动模组包括第一更新GOA模组和第二更新GOA模组;
所述第一更新GOA模组用于为所述至少一行像素电路提供N型扫描信号;
所述第二更新GOA模组用于为所述至少一行像素电路提供P型扫描信号;
所述第一更新GOA模组包括多级第一更新GOA电路,所述第二更新GOA模组包括多组第二更新GOA电路;
所述第一更新GOA模组包括的第一级第一更新GOA电路接入所述第一起始信号,所述第二更新GOA模组包括的第一级第二更新GOA电路接入所述第二起始信号。
可选的,所述未更新显示区域中设置有与所述更新显示区域中的至少一行像素电路相邻的两个相邻像素电路组;所述相邻像素电路组包括至少一行过渡像素电路;
所述驱动模组用于控制所述至少一行过渡像素电路的刷新频率为第二刷新频率,所述
第二刷新频率小于所述第一刷新频率,所述第二刷新频率大于所述另一部分显示区域的刷新频率。
可选的,所述未更新显示区域中还设置有除了所述相邻像素电路组之外的不相邻像素电路组;所述不相邻像素电路组包括至少一行像素电路;
所述驱动模组用于控制所述不相邻像素电路组包括的像素电路的刷新频率为第三刷新频率;所述第三刷新频率小于所述第二刷新频率。
可选的,当所述更新显示区域中设置有M行N列像素电路,并N小于所述显示面板包括的像素电路的总列数时,所述像素电路包括写入控制电路;M和N为正整数;
所述写入控制电路的控制端与写入控制线电连接,所述写入控制电路的第一端与数据线电连接,所述写入控制电路的第二端与数据写入节点电连接;所述写入控制电路用于在所述写入控制线提供的写入控制信号的控制下,控制所述数据线与所述数据写入节点之间连通;
所述驱动模组用于通过控制与所述M行N列像素电路位于同一行不同列的像素电路包括的写入控制电路的控制端接入的写入控制信号的频率,以使得与所述M行N列像素电路位于同一行不同列的像素电路的刷新频率小于所述第一刷新频率。
可选的,所述驱动模组还用于通过控制所述M行N列像素电路包括的写入控制电路的控制端接入的写入控制信号的频率,以使得所述M行N列像素电路的刷新频率为所述第一刷新频率。
在第二个方面中,本公开实施例提供一种刷新驱动方法,应用于显示装置,所述显示装置包括显示面板和驱动模组;所述显示面板包括第一显示区域、第二显示区域和多行多列像素电路;所述刷新驱动方法包括:
所述驱动模组控制设置于第一显示区域中的像素电路的刷新频率为第一刷新频率,所述驱动模组控制设置于第二显示区域中的像素电路的刷新频率与所述第一刷新频率不同。
可选的,本公开至少一实施例所述的刷新驱动方法包括:
当判断到显示面板包括的部分显示区域显示的画面变化,所述显示面板包括的另一部分显示区域显示的画面不变化时,控制所述部分显示区域中的像素电路的刷新频率为第一刷新频率,控制所述另一部分显示区域的刷新频率小于所述第一刷新频率;
所述部分显示区域为更新显示区域,所述的另一部分显示区域为未更新显示区域;所述更新显示区域为所述第一显示区域,所述未更新显示区域为所述第二显示区域。
可选的,本公开至少一实施例包括:当所述更新显示区域中设置有至少一行像素电路时,通过控制第一起始信号的频率和第二起始信号的频率来调节所述更新显示区域中的至少一行像素电路的刷新频率。
可选的,所述显示面板还包括第一更新GOA模组和第二更新GOA模组,所述第一更新GOA模组用于为所述至少一行像素电路提供N型扫描信号,所述第二更新GOA模组用于为所述至少一行像素电路提供P型扫描信号;所述第一更新GOA模组包括多级第
一更新GOA电路,所述第二更新GOA模组包括多组第二更新GOA电路;所述第一更新GOA模组包括的第一级第一更新GOA电路接入所述第一起始信号,所述第二更新GOA模组包括的第一级第二更新GOA电路接入所述第二起始信号。
可选的,所述未更新显示区域中设置有与所述更新显示区域中的至少一行像素电路相邻的两个相邻像素电路组;所述相邻像素电路组包括至少一行过渡像素电路;
所述刷新驱动方法还包括:控制所述至少一行过渡像素电路的刷新频率为第二刷新频率,所述第二刷新频率小于所述第一刷新频率。
可选的,所述未更新显示区域中还设置有除了所述相邻像素电路组之外的不相邻像素电路组;所述不相邻像素电路组包括不相邻像素电路;
所述刷新驱动方法还包括:控制所述不相邻像素电路的刷新频率为第三刷新频率;所述第三刷新频率小于所述第二刷新频率。
可选的,当所述更新显示区域中设置有M行N列像素电路,并N小于所述显示面板包括的像素电路的总列数时,所述像素电路包括写入控制电路;所述写入控制电路的控制端与写入控制线电连接,所述写入控制电路的第一端与数据线电连接,所述写入控制电路的第二端与数据写入节点电连接;所述写入控制电路用于在所述写入控制线提供的写入控制信号的控制下,控制所述数据线与所述数据写入节点之间连通;M和N为正整数;所述刷新驱动方法包括:
通过控制与所述M行N列像素电路位于同一行不同列的像素电路包括的写入控制电路的控制端接入的写入控制信号的频率,以使得与所述M行N列像素电路位于同一行不同列的像素电路的刷新频率小于所述第一刷新频率。
可选的,本公开至少一实施例所述的刷新驱动方法还包括:
通过控制所述M行N列像素电路包括的写入控制电路的控制端接入的写入控制信号的频率,以使得所述M行N列像素电路的刷新频率为所述第一刷新频率。
图1是本公开所述的显示装置的显示面板的分区示意图;
图2是本公开所述的显示装置的至少一实施例的结构图;
图3是图2所示的显示装置的至少一实施例的工作时序图;
图4是本公开所述的显示装置的至少一实施例的结构图;
图5是图4所示的显示装置的至少一实施例的工作时序图;
图6是本公开所述的显示装置的显示面板的分区示意图;
图7是图4所示的显示装置的至少一实施例的另一工作时序图;
图8是本公开所述的显示装置中的像素电路的至少一实施例的电路图;
图9是所述像素电路的至少一实施例的电路图;
图10是所述显示面板的分区示意图;
图11是本公开所述的显示装置中的第一GOA电路的至少一实施例的电路图;
图12是本公开所述的显示装置中的第二GOA电路的至少一实施例的电路图。
下面将结合本公开实施例中的附图,对本公开实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例仅仅是本公开一部分实施例,而不是全部的实施例。基于本公开中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本公开保护的范围。
本公开实施例所述的显示装置包括显示面板和驱动模组;所述显示面板包括第一显示区域、第二显示区域和多行多列像素电路;
所述驱动模组用于控制设置于第一显示区域中的像素电路的刷新频率为第一刷新频率,控制设置于第二显示区域中的像素电路的刷新频率与所述第一刷新频率不同。
本公开实施例所述的显示装置可以针对不同的显示区域设定相应的刷新频率,以能够在正常显示画面的同时降低功耗。
在具体实施时,在所述第一显示区域中设置有至少一行至少一列像素电路,在第二显示区域中设置有至少一行至少一列像素电路。
本公开实施例所述的显示装置包括显示面板和驱动模组;
所述显示面板包括多行多列像素电路;
所述驱动模组用于当判断到显示面板包括的部分显示区域显示的画面变化,所述显示面板包括的另一部分显示区域显示的画面不变化时,控制所述部分显示区域中的像素电路的刷新频率为第一刷新频率,控制所述另一部分显示区域的刷新频率小于所述第一刷新频率;
所述部分显示区域为更新显示区域,所述的另一部分显示区域为未更新显示区域;所述更新显示区域为所述第一显示区域,所述未更新显示区域为所述第二显示区域。
可以理解的是,本专利中更新显示区域和未更新显示区域是相对而言,例如:未更新显示区域指的是更新频率较低的显示区域,该区域的更新频率较更新显示区域的更新频率低。例如:未更新显示区域的更新频率比更新显示区域的更新频率低30HZ-45HZ;或者,未更新显示区域,人眼看起来似乎画面基本没有变化或变化很慢,例如0HZ~30HZ。(0HZ可以是指画面静止状态)。
本公开实施例所述的显示装置在工作时,当驱动模组判断到显示面板包括的部分显示区域显示的画面变化,而所述显示面板包括的另一部分显示区域显示的画面不变化时,所述驱动模组控制画面更新的显示区域中的像素电路的刷新频率为第一刷新频率,控制所述画面不更新的显示区域中的像素电路的刷新频率小于所述第一刷新频率,以能够在正常显示画面的同时降低功耗。
在相关的OLED(有机发光二极管)显示屏工作时,在显示画面更新时,会全屏更新,
驱动功耗较高。采用LTPO(低温多晶氧化物)等低频技术的显示面板,可以长时间保持显示亮度不变,则可以选择本公开实施例中提出的局部刷新驱动方式。本公开实施例中提出的局部刷新驱动方式通过显示画面局部数据更新时,显示面板也只高频刷新画面数据更新的部分,其他部分保持低频刷新,从而最大限度降低驱动功耗。
在本公开至少一实施例中,所述驱动模组还用于当所述更新显示区域中设置有至少一行像素电路时,通过控制第一起始信号的频率和第二起始信号的频率来调节所述更新显示区域中的至少一行像素电路的刷新频率。
在具体实施时,所述驱动模组可以通过控制第一起始信号的频率和第二起始信号的频率来调节更新显示区域中的像素电路的刷新频率。
可选的,所述驱动模组包括第一更新GOA(Gate On Array,阵列基板行驱动)模组和第二更新GOA模组;
所述第一更新GOA模组用于为所述至少一行像素电路提供N型扫描信号;
所述第二更新GOA模组用于为所述至少一行像素电路提供P型扫描信号;
所述第一更新GOA模组包括多级第一更新GOA电路,所述第二更新GOA模组包括多组第二更新GOA电路;
所述第一更新GOA模组包括的第一级第一更新GOA电路接入所述第一起始信号,所述第二更新GOA模组包括的第一级第二更新GOA电路接入所述第二起始信号。
在具体实施时,第一更新GOA模组用于为更新显示区域中的像素电路提供N型扫描信号,第二更新GOA模组用于为更新显示区域中的像素电路提供P型扫描信号,所述驱动模组还可以包括驱动控制单元,本公开至少一实施例可以通过所述驱动控制单元控制所述第一级第一更新GOA电路接入的第一起始信号,以及,所述第一级第二更新GOA电路接入的第二起始信号,以控制调节更新显示区域中的像素电路的刷新频率。
在本公开至少一实施例中,所述未更新显示区域中设置有与所述更新显示区域中的至少一行像素电路相邻的两个相邻像素电路组;所述相邻像素电路组包括至少一行过渡像素电路;
所述驱动模组用于控制所述至少一行过渡像素电路的刷新频率为第二刷新频率,所述第二刷新频率小于所述第一刷新频率,所述第二刷新频率大于所述另一部分显示区域的刷新频率。
在具体实施时,可以将与更新显示区域相邻的显示区域设置为过渡显示区域,过渡显示区域的刷新频率为第二刷新频率,所述第二刷新频率介于低频刷新频率与第一刷新频率之间,从而减小显示差异,防止人眼发觉,减小相邻显示区域显示差异可能带来的闪烁、Mura(显示不均匀)问题。其中,所述低频显示频率为所述另一部分显示区域的刷新频率。
可选的,所述未更新显示区域中还设置有除了所述相邻像素电路组之外的不相邻像素电路组;所述不相邻像素电路组包括不相邻像素电路;
所述驱动模组用于控制所述不相邻像素电路的刷新频率为第三刷新频率;所述第三刷
新频率小于所述第二刷新频率。
在本公开至少一实施例中,所述第三刷新频率即为所述低频显示频率。
在本公开至少一实施例中,所述第三刷新频率可以小于等于60Hz,例如,所述第三刷新频率可以为1Hz、10Hz、20Hz、30Hz、40Hz或60Hz,但不以此为限。
可选的,当所述更新显示区域中设置有M行N列像素电路,并N小于所述显示面板包括的像素电路的总列数时,所述像素电路包括写入控制电路;M和N为正整数;
所述写入控制电路的控制端与写入控制线电连接,所述写入控制电路的第一端与数据线电连接,所述写入控制电路的第二端与数据写入节点电连接;所述写入控制电路用于在所述写入控制线提供的写入控制信号的控制下,控制所述数据线与所述数据写入节点之间连通;
所述驱动模组用于通过控制与所述M行N列像素电路位于同一行不同列的像素电路包括的写入控制电路的控制端接入的写入控制信号的频率,以使得与所述M行N列像素电路位于同一行不同列的像素电路的刷新频率小于所述第一刷新频率。
在本公开至少一实施例中,当所述更新显示区域中的像素电路的列数小于所述显示面板包括的像素电路的总列数时,可以通过控制所述写入控制信号的频率,以控制与所述M行N列像素电路位于同一行不同列的像素电路的刷新频率小于第一刷新频率。
在本公开至少一实施例中,所述驱动模组还用于通过控制所述M行N列像素电路包括的写入控制电路的控制端接入的写入控制信号的频率,以使得所述M行N列像素电路的刷新频率为所述第一刷新频率。
如图1所示,可以将显示面板10的有效显示区域划分为A个显示区域;
在图1中,标号为P1的第一预设显示区域,标号为P2的为第二预设显示区域,标号为Pa的为第a预设显示区域,标号为PA的为第A预设显示区域;
A为正整数,a为小于A的正整数。
在实际操作时,可以根据显示面板的显示画面的更新情况自动匹配刷新对应的显示区域,从而最大限度降低功耗。例如,当第a预设显示区域Pa的显示画面有更新时,而除了第a预设显示区域Pa之外的其他显示区域的显示画面无更新时,所述驱动模组控制第a预设显示区域Pa中的像素电路的刷新频率为第一刷新频率;所述驱动模组控制除了第a预设显示区域Pa之外的其他显示区域中的像素电路的刷新频率小于所述第一刷新频率,例如,所述第一刷新频率可以为120Hz,所述除了第a预设显示区域Pa之外的其他显示区域中的像素电路的刷新频率可以为1Hz;但不以此为限。
在本公开至少一实施例中,可以将所述有效显示区域平均分为A个显示区域;或者,可以根据显示规律不等分分区。例如,办公电脑桌面任务栏可以单独分一个显示区域,显示视频时的中心显示区域可以单独分一个显示区域,文字办公的菜单区、编辑区可以分别单独分一个显示区域;折叠显示面板的对折或多折的区域可以分别单独分一个显示区域;等等。
并且,当所述显示面板上的某一显示区域出现局部视频、图标闪烁、文字输入等场景时,会出现该显示区域的刷新频率需要切换的问题。
在具体实施时,在对显示区域分区的同时,可以对像素电路和驱动模组中的GOA电路进行分区;
当所述有效显示区域被划分为A个显示区域时,所述驱动模组可以包括A个第一GOA模组和A个第二GOA模组;第a个第一GOA模组对应于第a预设显示区域,第a个第二GOA模组对应于第a预设显示区域;
第a个第一GOA模组用于为设置于所述第a预设显示区域中的像素电路提供相应的N型扫描信号;
第a个第二GOA模组用于为设置于所述第a预设显示区域中的像素电路提供相应的P型扫描信号;
当第a预设显示区域为刷新显示区域时,所述第一更新GOA模组为所述第a个第一GOA模组,所述第二更新GOA模组为第a个第二GOA模组。
在本公开至少一实施例中,当所述有效显示区域被划分为A个显示区域时,所述驱动模组可以包括A个第一左侧GOA模组、A个第一右侧GOA模组、A个第二左侧GOA模组和A个第二右侧GOA模组;
第a个第一左侧GOA模组和第a个第一右侧GOA模组为设置于所述第a预设显示区域中的像素电路提供相应的N型扫描信号;
第a个第二左侧GOA模组和第a个第二右侧GOA模组为设置于所述第a预设显示区域中的像素电路提供相应的P型扫描信号;
当第a预设显示区域为刷新显示区域时,所述第一更新GOA模组包括所述第a个第一左侧GOA模组和所述第a个第一右侧GOA模组,所述第二更新GOA模组包括所述第a个第二左侧GOA模组和所述第a个第二右侧GOA模组。
在本公开至少一实施例中,各GOA模组可以包括相互级联的至少一级GOA电路;第一GOA模组可以包括至少一级第一GOA电路,第二GOA模组可以包括至少一级第二GOA电路;
一级第一GOA电路可以为两行像素电路提供相应的N型扫描信号,一级第二GOA电路可以为一行像素电路提供相应的P型扫描信号;但不以此为限。
如图2所示,标号为X1的为第一预设显示区域中的所有行像素电路;标号为Xa-1的为第a-1预设显示区域中的所有行像素电路,标号为Xa的为第a预设显示区域中的所有行像素电路,标号为Xa+1的为第a+1预设显示区域中的所有行像素电路,标号为XA-1的为第A-1预设显示区域中的所有行像素电路,标号为XA为第A预设显示区域中的所有行显示电路;
标号为GN11的为第一个第一左侧GOA模组,标号为GNa-11的为第a-1个第一左侧GOA模组,标号为GNa1的为第a个第一左侧GOA模组,标号为GNa+11的为第a+1个
第一左侧GOA模组,标号为GNA1的为第A个第一左侧GOA模组;
标号为GN12的为第一个第一右侧GOA模组,标号为GNa-12的为第a-1个第一右侧GOA模组,标号为GNa2的为第a个第一右侧GOA模组,标号为GNa+12的为第a+1个第一右侧GOA模组,标号为GNA2的为第A个第一右侧GOA模组;
标号为GP11的为第一个第二左侧GOA模组,标号为GPa-11的为第a-1个第二左侧GOA模组,标号为GPa1的为第a个第二左侧GOA模组,标号为GPa+11的为第a+1个第二左侧GOA模组,标号为GPA1的为第A个第二左侧GOA模组;
标号为GP12的为第一个第二右侧GOA模组,标号为GPa-12的为第a-1个第二右侧GOA模组,标号为GPa2的为第a个第二右侧GOA模组,标号为GPa+12的为第a+1个第二右侧GOA模组,标号为GPA2的为第A个第二右侧GOA模组。
如图2所示,所述驱动模组还可以包括驱动控制单元20;
所述驱动控制单元20用于为GN11和GN12提供第一个第一起始信号NSTV1,为GNa-11和GNa-12提供第a-1个第一起始信号NSTVa-1,为GNa1和GNa2提供第a个第一起始信号NSTVa,为GNa+11和GNa+12提供第a+1个第一起始信号NSTVa+1,为GNA1和GNA2提供第A个第一起始信号NSTVA;
所述驱动控制单元20用于为GP11和GP12提供第一个第二起始信号GSTV1,为GPa-11和GPa-12提供第a-1个第二起始信号GSTVa-1,为GPa1和GPa2提供第a个第二起始信号GSTVa,为GPa+11和GPa+12提供第a+1个第二起始信号GSTVa+1,为GPA1和GPA2提供第A个第二起始信号GSTVA。
当第a预设显示区域为更新显示区域,所述有效显示区域包括的其他显示区域为未更新显示区域时,可以通过提升NSTV2a-1的频率、NSTV2a的频率、GSTV2a-1的频率和GSTV2a的频率,以提升位于所述第a预设显示区域中的像素电路的刷新频率。
在本公开至少一实施例中,例如,当图8所示的像素电路的至少一实施例在工作时,像素电路包括的第八晶体管T8的栅极与第一扫描线GN电连接,像素电路包括的第二晶体管T2的栅极与像素电路包括的第四晶体管的栅极与第二扫描线GP电连接,因此,所述像素电路的刷新频率与提供第一扫描信号的第一GOA模组接入的第一起始信号的频率和提供第二扫描信号的第二GOA模组接入的第二起始信号的频率相关。
在具体实施时,所述第一GOA模组接入的第一起始信号的频率与所述第一GOA模组输出的第一扫描信号的频率相同,所述第二GOA模组接入的第二起始信号的频率与所述第二GOA模组输出的第二扫描信号的频率相同,但不以此为限。
图3是图2所示的至少一实施例的工作时序图。
在图3中,Vsync为同步信号,DE为数据使能信号,Vd为数据电压。
如图3所示,NSTVa的频率大于NSTV1的频率,NSTVa的频率大于NSTVA的频率;GSTV a的频率大于GSTV1的频率,GSTVa的频率大于GSTVA的频率;以使得位于第a预设显示区域中的像素电路的刷新频率大于位于其他显示区域中的像素的刷新频率。
在本公开至少一实施例中,当第一显示区域中的像素电路的刷新频率都为120Hz时,为第一显示区域中的像素电路提供第一扫描信号的第一GOA模组接入的第一起始信号的频率,以及,为第一显示区域中的像素电路提供第二扫描信号的第二GOA模组接入的第二起始信号的频率可以都为120Hz;
也即,当显示区域中的像素电路的刷新频率都为预定频率时,为第一显示区域中的像素电路提供第一扫描信号的第一GOA模组接入的第一起始信号的频率,以及,为第一显示区域中的像素电路提供第二扫描信号的第二GOA模组接入的第二起始信号的频率可以都为所述预定频率。
例如,当第一显示区域中的像素电路的刷新频率与第二显示区域中的像素电路的刷新频率的比值为4时,则为第一显示区域中的像素电路提供第一扫描信号的第一GOA模组接入的第一起始信号的频率,与为第二显示区域中的像素电路提供第一扫描信号的第一GOA模组接入的第一起始信号的频率的比值可以为4,为第一显示区域中的像素电路提供第二扫描信号的第二GOA模组接入的第二起始信号的频率,与为第二显示区域中的像素电路提供第二扫描信号的第二GOA模组接入的第二起始信号的频率的比值可以为4。
如图4所示,在图2所示的显示面板的至少一实施例的基础上,所述驱动模组还可以包括A个发光控制模组和A个第三GOA模组;
标号为ES1的为第一发光控制模组,标号为ESa-1的为第a-1发光控制模组,标号为ESa的为第a发光控制模组,标号为ESa+1的为第a+1发光控制模组,标号为ESA的为第A发光控制模组;各发光控制模组用于为设置于相应的显示区域中的像素电路提供发光控制信号;
标号为S1的为第一个第三GOA模组,标号为Sa-1的为第a-1个第三GOA模组,标号为Sa的为第a个第三GOA模组,标号为Sa+1的为第a+1个第三GOA模组,标号为SA的为第A个第三GOA模组;各第三GOA模组用于为设置于相应的显示区域中的像素电路提供第三扫描信号。
如图4所示,所述驱动模组包括的A个发光控制模组可以相互级联,第一发光控制模组接入发光控制起始信号ESTV;
所述驱动模组包括的A个第三GOA模组可以相互级联,第一个第三GOA模组接入第三起始信号STV3。
在具体实施时,ESTV的频率可以与STV3的频率相等,或者,STV3的频率可以小于ESTV的频率。
在本公开至少一实施例中,ESTV的频率可以大于等于120Hz,STV3的频率可以大于等于120Hz;例如,ESTV的频率可以为480Hz,STV3的频率可以为240Hz,但不以此为限。
可选的,数据使能信号DE的频率可以与显示面板包括的各显示区域中的像素电路的最大刷新频率相等,但不以此为限。
在具体实施时,Vd的频率与相应的显示区域的刷新频率有关,在当前扫描到的显示区域中的像素电路对应的刷新频率高时,Vd的频率高,在当前扫描到的显示区域中的像素电路对应的刷新频率低时,Vd的频率低。
在本公开至少一实施例中,各个不同的预设显示区域对应的发光控制模组可以分别对应于一个发光起始信号,此时,对应于相同的预设显示区域的发光控制模组相互级联,对应于不同的预设显示区域的发光控制模组不相互级联;
各个不同的预设显示区域对应的第三GOA模组可以分别对应于一个第三起始信号,此时,对应于相同的预设显示区域的第三GOA模组相互级联,对应于不同的预设显示区域的第三GOA模组不相互级联。
图5是图4所示的至少一实施例的工作时序图。
图5在图3所示的工作时序图的基础上,增加了发光控制起始信号ESTV,ESTV被提供至各发光控制模组。
如图5所示,ESTV的频率高。
在本公开至少一实施例中,为了解决低频flicker(闪烁)的问题,各发光控制模组和各第三GOA模组进行高频刷新。
如图6所示,可以将显示面板10的有效显示区域划分为A个显示区域;
在图6中,标号为P1的第一预设显示区域,标号为P2的为第二预设显示区域,标号为Pa-1的为第a-1预设显示区域,标号为Pa的为第a预设显示区域,标号为Pa+1的为第a+1预设显示区域,标号为PA的为第A预设显示区域;
A为正整数,a为小于A的正整数。
在具体实施时,可以将显示面板划分为A个显示区域,为了减小相邻区域差异可能带来的闪烁、Mura问题,可以将与更新显示区域的相邻区域作为过渡显示区域。
在本公开至少一实施例中,当图6中的第a预设显示区域Pa为更新显示区域时,第a-1预设显示区域Pa-1和第a+1预设显示区域Pa+1为过渡显示区域;
所述驱动模组用于控制Pa中的像素电路的刷新频率为第一刷新频率,控制Pa-1中的像素电路的刷新频率和Pa+1中的像素电路的刷新频率中的至少一个为第二刷新频率,控制P1中的像素电路的刷新频率和PA中的像素电路的刷新频率中的至少一个为第三刷新频率;
第一刷新频率大于第二刷新频率,第二刷新频率大于第三刷新频率。
在具体实施时,第一刷新频率例如可以为120Hz,第二刷新频率例如可以为60Hz,第三刷新频率例如可以为1Hz,但不以此为限。
图7是图4所示的至少一实施例的另一工作时序图。
在具体实施时,当第a预设显示区域Pa为更新显示区域时,第a-1预设显示区域Pa-1和第a+1预设显示区域Pa+1为过渡显示区域时,各起始信号的波形如图7所示。
在图7中,标号为Vsync的为同步信号,标号为DE的为数据使能信号,标号为ESTV
的为发光控制起始信号,标号为GSTV1的为第一个第二起始信号,标号为GSTVa-1的为第a-1个第二起始信号,标号为GSTVa的为第a个第二起始信号,标号为GSTVa+1的为第a+1个第二起始信号,标号为GSTVA的为第A个第二起始信号,标号为NSTV1的为第一个第一起始信号,标号为NSTVa-1的为第a-1个第一起始信号,标号为NSTVa的为第a个第一起始信号,标号为NSTVa+1的为第a+1个第一起始信号,标号为NSTVA的为第A个第一起始信号,标号为Vd的为数据电压。
如图7所示,GSTVa的频率大于GSTVa-1的频率,GSTVa的频率大于GSTVa+1的频率,GSTVa-1的频率大于GSTV1的频率,GSTVa-1的频率大于GSTVA的频率,GSTVa+1的频率大于GSTV1的频率,GSTVa+1的频率大于GSTVA的频率;
NSTVa的频率大于NSTVa-1的频率,NSTVa的频率大于NSTVa+1的频率,NSTVa-1的频率大于NSTV1的频率,NSTVa-1的频率大于NSTVA的频率,NSTVa+1的频率大于NSTV1的频率,NSTVa+1的频率大于NSTVA的频率。
如图7所示,ESTV的频率高。
在本公开至少一实施例中,为了解决低频flicker(闪烁)的问题,各发光控制模组和各第三GOA模组进行高频刷新。
在本公开至少一实施例中,所述像素电路的结构可以如图8所示。
如图8所示,所述像素电路的至少一实施例可以包括第一晶体管T1、第二晶体管T2、第三晶体管T3、第四晶体管T4、第五晶体管T5、第六晶体管T6、第七晶体管T7、第八晶体管T8、第九晶体管T9、存储电容Cst和有机发光二极管O1;
T8的栅极与第一扫描线GN电连接;
T2的栅极和T4的栅极都与第二扫描线GP电连接;
T1的栅极、T7的栅极和T9的栅极都与第三扫描线Sc电连接;
T5的栅极和T6的栅极都与发光控制线EC电连接;
T3为驱动晶体管;
所述第一扫描线GN用于提供第一扫描信号,所述第一扫描信号为N型扫描信号;
所述第二扫描线GP用于提供第二扫描信号,所述第二扫描信号为P型扫描信号;
所述第三扫描线Sc用于提供第三扫描信号;
所述发光控制线Sc用于提供发光控制信号。
在图8中,标号为D1的为数据线,数据线D1用于提供数据电压Vd;标号为Vi1的为第一初始电压,标号为Vi2的为第二初始电压,标号为Vref的为参考电压,标号为VDD的为高电压端,标号为VSS的为低电压端。
在图8所示的至少一实施例中,T2和T4为p型晶体管,T8为n型晶体管,T1、T7和T9为p型晶体管,T5和T6为p型晶体管。
在本公开至少一实施例中,所述像素电路的结构不限于如图8所示,所述像素电路能够在第一扫描信号、第二扫描信号、第三扫描信号和发光控制信号的控制下发光即可。
如图9所示,在图8所示的像素电路的至少一实施例的基础上,所述像素电路的至少一实施例还可以包括写入控制电路90;
所述写入控制电路90的控制端与写入控制线XC电连接,所述写入控制电路90的第一端与数据线D1电连接,所述写入控制电路90的第二端与数据写入节点SX电连接;所述写入控制电路90用于在所述写入控制线XC提供的写入控制信号的控制下,控制所述数据线D1与所述数据写入节点SX之间连通。
如图9所示,在图8所示的像素电路的至少一实施例的基础上,所述像素电路的至少一实施例还可以包括辅助控制电路91;
所述辅助控制电路91的控制端与辅助控制线GC电连接,所述辅助控制电路91的第一端与第八晶体管T8的栅极电性连接,也即辅助控制电路91的第二端与第一扫描线GN连接;所述辅助控制电路91,用于在所述辅助控制线GC提供的辅助控制信号的控制下,控制所述第一扫描线GN与第八晶体管T8的栅极之间连通。
在图9所示的至少一实施例中,所述第一扫描线GN上的第一扫描信号可以由第一GOA模组包括的对应的第一GOA电路提供。
例如:如图10所示,所述显示面板的有效显示区域包括的未更新区域Pa1时和更新显示区域Pa0时,可以通过控制未更新区域Pa1对应的像素电路的辅助控制电路91的辅助控制线GC,使得第八晶体管保持不工作状态(例如:关闭状态)。这样可以保证即使未更新区域Pa1的像素电路的其他晶体管工作,也不会影响未更新区域Pa1的数据信号被复位掉。同时,可以通过控制更新区域Pa0对应的像素电路中的辅助控制电路91的辅助控制线GC,使得更新区域Pa0的像素电路的第八晶体管保持正常工作状态,更新相应画面。
可选地,写入控制电路90和辅助控制电路91均可以采用场效应晶体管实现(例如可以与像素电路其他晶体管结构相同,可以为P型或N型)。在此不再赘述。如图10所示,所述显示面板的有效显示区域包括的刷新显示区域为第a预设显示区域包括的位于中间的显示区域Pa0;
第a预设显示区域包括的位于所述刷新显示区域As左侧的显示区域标示为Pa1,第a预设显示区域包括的位于所述刷新显示区域As右侧的显示区域标示为Pa2。
在图10中,标号为P1的为第一预设显示区域,标号为PA的为第A预设显示区域。
当所述刷新显示区域为第a预设显示区域包括的位于中间的显示区域Pa0时,第a预设显示区域中的像素电路的结构可以如图9所示,该像素电路包括写入控制电路;所述显示面板在工作时,可以通过控制所述写入控制信号的频率,以控制Pa0中的像素电路的刷新频率为第一频率,控制Pa1中的像素电路的刷新频率和Pa2中的像素电路的刷新频率小于第一频率。
可以理解的是,图9的写入控制电路90和辅助控制电路91可以位于显示面板的显示区域,还可以位于显示面板的非显示区。例如:写入控制电路90集成在驱动模组中,或者写入控制电路9集成在数据信号驱动芯片中。
可以理解的是,在一些实施例中,驱动模组可以单独通过控制第一更新GOA模组和第二更新GOA模组等来控制像素电路的更新频率实现横向分区(例如:P1。。。PA);当然通过辅助控制电路91和/或写入控制电路90以实现纵向分区(例如:Pa1。。。Pa2)。当然驱动模组也可以结合辅助控制电路91和/或写入控制电路90,以实现横向和纵向混合分区(如图10所示):例如:驱动模组既通过控制第一更新GOA模组和第二更新GOA模组等来控制像素电路的更新频率,结合通过写入控制电路90控制像素电路的数据线D1的写入控制信号的频率和辅助控制电路90控制像素电路的第八晶体管的工作频率,实现横向和纵向混合分区(如图10所示);当然,不限于此,还可以其他多个实施例的组合使用。
图11是在本公开至少一实施例中,第一GOA电路的至少一实施例的电路图,所述第一GOA电路用于提供N型扫描信号。
如图11所示,所述第一GOA电路的至少一实施例可以包括第一显示控制晶体管M1、第二显示控制晶体管M2、第三显示控制晶体管M3、第四显示控制晶体管M4、第五显示控制晶体管M5、第六显示控制晶体管M6、第七显示控制晶体管M7、第八显示控制晶体管M8、第九显示控制晶体管M9、第十显示控制晶体管M10、第十一显示控制晶体管M11、第十二显示控制晶体管M12、第十三显示控制晶体管M13、第十四显示控制晶体管M14、第一电容C1、第二电容C2和第三电容C3;
在图11中,标号为CK的为第一时钟信号端,标号为I1的为第一输入端,标号为CB的为第二时钟信号端,标号为VGL的为低电压端,标号为VGH的为高电压端,标号为PD1的为第一下拉节点,标号为PU1的为第一上拉节点,标号为SO1的为第一扫描信号输出端,标号为R1的为复位端。
在图11所示的第一GOA电路的至少一实施例中,M11的第二极与M8的第一极可以都与高电压端VGH电连接。
在具体实施时,所述第一极可以为源极或漏极,所述第二极可以为漏极或源极。
当所述第一GOA电路的至少一实施例用于提供N型扫描信号时,各第一GOA模组包括的第一级第一GOA电路的第一输入端接入第一起始信号。例如,第一个第一左侧GOA模组和第一个第一右侧GOA模组都可以接入第一个第一起始信号,第a-1个第一左侧GOA模组和第a-1个第一右侧GOA模组都可以接入第a-1个第一起始信号,第a个第一左侧GOA模组和第a个第一右侧GOA模组都可以接入第a个第一起始信号,第a+1个第一左侧GOA模组和第a+1个第一右侧GOA模组都可以接入第a+1个第一起始信号,第A个第一左侧GOA模组和第A个第一右侧GOA模组都可以接入第A个第一起始信号。
图11所示的电路的至少一实施例也可以用于提供发光控制信号,此时,该电路可以为各发光控制模组包括的发光控制信号生成电路;第一发光控制模组包括的第一级发光控制信号生成电路的输入端可以接入发光控制起始信号。
图11所示的电路的至少一实施例也可以用于提供第三扫描信号,此时,该该电路可
以为第三GOA模组包括的第三GOA电路;第一个第三GOA模组包括的第一级第三GOA电路的输入端接入第三起始信号。
图11所示的电路的至少一实施例可以用于提供N型扫描信号、发光控制信号或第三扫描信号,当图11所示的电路的至少一实施例提供不同的信号时,第一时钟信号端CK提供的第一时钟信号可以互不相同,第二时钟信号端CB提供的二时钟信号可以互不相同。
图12是在本公开至少一实施例中,第二GOA电路的至少一实施例的电路图,所述第二GOA电路用于提供P型扫描信号。
如图12所示,所述第二GOA电路的至少一实施例可以包括第十五显示控制晶体管M15、第十六显示控制晶体管M16、第十七显示控制晶体管M17、第十八显示控制晶体管M18、第十九显示控制晶体管M19、第二十显示控制晶体管M20、第二十一显示控制晶体管M21、第二十二显示控制晶体管M22、第二十三显示控制晶体管M23、第二十四显示控制晶体管M24、第四电容C4和第五电容C5。
在图12中,标号为I2的为第二输入端,标号为R2的为第二复位端,标号为VGL的为低电压端,标号为VGH的为高电压端,标号为SO2的为第二扫描信号输出端,标号为GCK1的为第一输出时钟信号线,标号为GCK2的为第二输出时钟信号线,标号为GCK3的为第三输出时钟信号线;
所述第二扫描信号输出端用于提供第二扫描信号。
在本公开至少一实施例中,第一输出时钟信号线GCK1用于提供第一输出时钟信号,第二输出时钟信号线GCK2用于提供第二输出时钟信号,第三输出时钟信号线GCK3用于提供第三输出时钟信号。
当所述第二GOA电路的至少一实施例用于提供P型扫描信号时,第二GOA模组包括的第一级第二GOA电路的第二输入端接入第二起始信号。
在本公开至少一实施例中,第一GOA电路的至少一实施例可以用于为第一扫描线GN提供N型扫描信号,第二GOA电路的至少一实施例可以用于为第二扫描线GP提供P型扫描信号,发光控制信号生成电路的至少一实施例可以用于为发光控制线EC提供发光控制电路,第三GOA电路的至少一实施例可以用于为第三扫描线Sc提供第三扫描信号;
第一GOA电路的至少一实施例的结构、发光控制信号生成电路的至少一实施例的结构,以及,第三GOA电路的至少一实施例的结构可以如图11所示,所述第二GOA电路的至少一实施例的结构可以如图12所示。
本公开如图4所示的显示装置的至少一实施例在工作时,各第一左侧GOA模组和各第一右侧GOA模组可以都为图8中的T8的栅极提供N型扫描信号,各第二左侧GOA电路和各第二右侧GOA电路可以都为图8中的T2的栅极和图8中的T4的栅极提供P型扫描信号,各发光控制模组可以为图8中的T5的栅极和图8中的T6的栅极提供发光控制信号,各第三GOA模组可以为图8中的T7的栅极和图8中的T9的栅极提供第三扫描信号;或者,
各第一左侧GOA模组和各第一右侧GOA模组可以都为图8中的T8的栅极提供N型扫描信号,各第二左侧GOA电路可以用于为图8中的T2的栅极提供P型扫描信号,各第二右侧GOA电路可以用于为图8中的T4的栅极提供P型扫描信号,各发光控制模组可以为图8中的T5的栅极和图8中的T6的栅极提供发光控制信号,各第三GOA模组可以为图8中的T7的栅极和图8中的T9的栅极提供第三扫描信号。
本公开实施例所述的刷新驱动方法,应用于显示装置,所述显示装置包括显示面板,所述显示面板包括多行多列像素电路,所述刷新频率方法包括:
当判断到显示面板包括的部分显示区域显示的画面变化,所述显示面板包括的另一部分显示区域显示的画面不变化时,控制所述部分显示区域中的像素电路的刷新频率为第一刷新频率,控制所述另一部分显示区域的刷新频率小于所述第一刷新频率;所述部分显示区域为更新显示区域,所述的另一部分显示区域为未更新显示区域。
在本公开实施例所述的刷新驱动方法中,当驱动模组判断到显示面板包括的部分显示区域显示的画面变化,而所述显示面板包括的另一部分显示区域显示的画面不变化时,所述驱动模组控制画面更新的显示区域中的像素电路的刷新频率为第一刷新频率,控制所述画面不更新的显示区域中的像素电路的刷新频率小于所述第一刷新频率,以能够在正常显示画面的同时降低功耗。
本公开至少一实施例所述的刷新驱动方法包括:当所述更新显示区域中设置有至少一行像素电路时,通过控制第一起始信号的频率和第二起始信号的频率来调节所述更新显示区域中的至少一行像素电路的刷新频率。
可选的,所述显示面板还包括第一GOA模组和第二GOA模组,所述第一GOA模组用于为所述至少一行像素电路提供N型扫描信号,所述第二GOA模组用于为所述至少一行像素电路提供P型扫描信号;所述第一GOA模组包括多级第一GOA电路,所述第二GOA模组包括多组第二GOA电路;所述第一GOA模组包括的第一级第一GOA电路接入所述第一起始信号,所述第二GOA模组包括的第一级第二GOA电路接入所述第二起始信号。
在本公开至少一实施例中,所述未更新显示区域中设置有与所述更新显示区域中的至少一行像素电路相邻的两个相邻像素电路组;所述相邻像素电路组包括至少一行过渡像素电路;
所述刷新驱动方法还包括:控制所述至少一行过渡像素电路的刷新频率为第二刷新频率,所述第二刷新频率小于所述第一刷新频率。
可选的,所述未更新显示区域中还设置有除了所述相邻像素电路组之外的不相邻像素电路组;所述不相邻像素电路组包括不相邻像素电路;
所述刷新驱动方法还包括:控制所述不相邻像素电路的刷新频率为第三刷新频率;所述第三刷新频率小于所述第二刷新频率。
在本公开至少一实施例中,当所述更新显示区域中设置有M行N列像素电路,并N
小于所述显示面板包括的像素电路的总列数时,所述像素电路包括写入控制电路;所述写入控制电路的控制端与写入控制线电连接,所述写入控制电路的第一端与数据线电连接,所述写入控制电路的第二端与数据写入节点电连接;所述写入控制电路用于在所述写入控制线提供的写入控制信号的控制下,控制所述数据线与所述数据写入节点之间连通;M和N为正整数;所述刷新驱动方法包括:
控制与所述M行N列像素电路位于同一行不同列的像素电路包括的写入控制电路的控制端接入的写入控制信号的频率小于所述第一刷新频率。
本公开实施例所提供的显示装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪等任何具有显示功能的产品或部件。
以上所述是本公开的优选实施方式,应当指出,对于本技术领域的普通技术人员来说,在不脱离本公开所述原理的前提下,还可以作出若干改进和润饰,这些改进和润饰也应视为本公开的保护范围。
Claims (16)
- 一种显示装置,包括显示面板和驱动模组;所述显示面板包括第一显示区域、第二显示区域和多行多列像素电路;所述驱动模组用于控制设置于第一显示区域中的像素电路的刷新频率为第一刷新频率,控制设置于第二显示区域中的像素电路的刷新频率与所述第一刷新频率不同。
- 如权利要求1所述的显示装置,其中,所述驱动模组用于当判断到显示面板包括的部分显示区域显示的画面变化,所述显示面板包括的另一部分显示区域显示的画面不变化时,控制所述部分显示区域中的像素电路的刷新频率为第一刷新频率,控制所述另一部分显示区域的刷新频率小于所述第一刷新频率;所述部分显示区域为更新显示区域,所述的另一部分显示区域为未更新显示区域;所述更新显示区域为所述第一显示区域,所述未更新显示区域为所述第二显示区域。
- 如权利要求2所述的显示装置,其中,所述驱动模组还用于当所述更新显示区域中设置有至少一行像素电路时,通过控制第一起始信号的频率和第二起始信号的频率来调节所述更新显示区域中的至少一行像素电路的刷新频率。
- 如权利要求3所述的显示装置,其中,所述驱动模组包括第一更新GOA模组和第二更新GOA模组;所述第一更新GOA模组用于为所述至少一行像素电路提供N型扫描信号;所述第二更新GOA模组用于为所述至少一行像素电路提供P型扫描信号;所述第一更新GOA模组包括多级第一更新GOA电路,所述第二更新GOA模组包括多组第二更新GOA电路;所述第一更新GOA模组包括的第一级第一更新GOA电路接入所述第一起始信号,所述第二更新GOA模组包括的第一级第二更新GOA电路接入所述第二起始信号。
- 如权利要求3所述的显示装置,其中,所述未更新显示区域中设置有与所述更新显示区域中的至少一行像素电路相邻的两个相邻像素电路组;所述相邻像素电路组包括至少一行过渡像素电路;所述驱动模组用于控制所述至少一行过渡像素电路的刷新频率为第二刷新频率,所述第二刷新频率小于所述第一刷新频率,所述第二刷新频率大于所述另一部分显示区域的刷 新频率。
- 如权利要求5所述的显示装置,其中,所述未更新显示区域中还设置有除了所述相邻像素电路组之外的不相邻像素电路组;所述不相邻像素电路组包括至少一行像素电路;所述驱动模组用于控制所述不相邻像素电路组包括的像素电路的刷新频率为第三刷新频率;所述第三刷新频率小于所述第二刷新频率。
- 如权利要求2或3所述的显示装置,其中,当所述更新显示区域中设置有M行N列像素电路,并N小于所述显示面板包括的像素电路的总列数时,所述像素电路包括写入控制电路;M和N为正整数;所述写入控制电路的控制端与写入控制线电连接,所述写入控制电路的第一端与数据线电连接,所述写入控制电路的第二端与数据写入节点电连接;所述写入控制电路用于在所述写入控制线提供的写入控制信号的控制下,控制所述数据线与所述数据写入节点之间连通;所述驱动模组用于通过控制与所述M行N列像素电路位于同一行不同列的像素电路包括的写入控制电路的控制端接入的写入控制信号的频率,以使得与所述M行N列像素电路位于同一行不同列的像素电路的刷新频率小于所述第一刷新频率。
- 如权利要求7所述的显示装置,其中,所述驱动模组还用于通过控制所述M行N列像素电路包括的写入控制电路的控制端接入的写入控制信号的频率,以使得所述M行N列像素电路的刷新频率为所述第一刷新频率。
- 一种刷新驱动方法,应用于显示装置,所述显示装置包括显示面板和驱动模组;所述显示面板包括第一显示区域、第二显示区域和多行多列像素电路;所述刷新驱动方法包括:所述驱动模组控制设置于第一显示区域中的像素电路的刷新频率为第一刷新频率,所述驱动模组控制设置于第二显示区域中的像素电路的刷新频率与所述第一刷新频率不同。
- 如权利要求9所述的刷新驱动方法,其中,包括:当判断到显示面板包括的部分显示区域显示的画面变化,所述显示面板包括的另一部分显示区域显示的画面不变化时,控制所述部分显示区域中的像素电路的刷新频率为第一刷新频率,控制所述另一部分显示区域的刷新频率小于所述第一刷新频率;所述部分显示区域为更新显示区域,所述的另一部分显示区域为未更新显示区域;所述更新显示区域为所述第一显示区域,所述未更新显示区域为所述第二显示区域。
- 如权利要求10所述的刷新驱动方法,其中,包括:当所述更新显示区域中设置有至少一行像素电路时,通过控制第一起始信号的频率和第二起始信号的频率来调节所述更新显示区域中的至少一行像素电路的刷新频率。
- 如权利要求11所述的刷新驱动方法,其中,所述显示面板还包括第一更新GOA模组和第二更新GOA模组,所述第一更新GOA模组用于为所述至少一行像素电路提供N型扫描信号,所述第二更新GOA模组用于为所述至少一行像素电路提供P型扫描信号;所述第一更新GOA模组包括多级第一更新GOA电路,所述第二更新GOA模组包括多组第二更新GOA电路;所述第一更新GOA模组包括的第一级第一更新GOA电路接入所述第一起始信号,所述第二更新GOA模组包括的第一级第二更新GOA电路接入所述第二起始信号。
- 如权利要求11所述的刷新驱动方法,其中,所述未更新显示区域中设置有与所述更新显示区域中的至少一行像素电路相邻的两个相邻像素电路组;所述相邻像素电路组包括至少一行过渡像素电路;所述刷新驱动方法还包括:控制所述至少一行过渡像素电路的刷新频率为第二刷新频率,所述第二刷新频率小于所述第一刷新频率。
- 如权利要求13所述的刷新驱动方法,其中,所述未更新显示区域中还设置有除了所述相邻像素电路组之外的不相邻像素电路组;所述不相邻像素电路组包括不相邻像素电路;所述刷新驱动方法还包括:控制所述不相邻像素电路的刷新频率为第三刷新频率;所述第三刷新频率小于所述第二刷新频率。
- 如权利要求10或11所述的刷新驱动方法,其中,当所述更新显示区域中设置有M行N列像素电路,并N小于所述显示面板包括的像素电路的总列数时,所述像素电路包括写入控制电路;所述写入控制电路的控制端与写入控制线电连接,所述写入控制电路的第一端与数据线电连接,所述写入控制电路的第二端与数据写入节点电连接;所述写入控制电路用于在所述写入控制线提供的写入控制信号的控制下,控制所述数据线与所述数据写入节点之间连通;M和N为正整数;所述刷新驱动方法包括:通过控制与所述M行N列像素电路位于同一行不同列的像素电路包括的写入控制电路的控制端接入的写入控制信号的频率,以使得与所述M行N列像素电路位于同一行不同列的像素电路的刷新频率小于所述第一刷新频率。
- 如权利要求15所述的刷新驱动方法,其中,还包括:通过控制所述M行N列像素电路包括的写入控制电路的控制端接入的写入控制信号的频率,以使得所述M行N列像素电路的刷新频率为所述第一刷新频率。
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