WO2023241244A1 - 掩膜板及电子装置、其制作方法 - Google Patents
掩膜板及电子装置、其制作方法 Download PDFInfo
- Publication number
- WO2023241244A1 WO2023241244A1 PCT/CN2023/091545 CN2023091545W WO2023241244A1 WO 2023241244 A1 WO2023241244 A1 WO 2023241244A1 CN 2023091545 W CN2023091545 W CN 2023091545W WO 2023241244 A1 WO2023241244 A1 WO 2023241244A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- substrate
- hole
- orthographic projection
- pad
- mask plate
- Prior art date
Links
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 239000000758 substrate Substances 0.000 claims abstract description 83
- 238000005476 soldering Methods 0.000 claims description 32
- 239000000463 material Substances 0.000 claims description 26
- 238000000034 method Methods 0.000 claims description 21
- 230000008569 process Effects 0.000 claims description 17
- 239000012528 membrane Substances 0.000 claims description 2
- 238000009413 insulation Methods 0.000 abstract 4
- 229910000679 solder Inorganic materials 0.000 description 18
- 238000010586 diagram Methods 0.000 description 13
- 239000002184 metal Substances 0.000 description 12
- 229910052751 metal Inorganic materials 0.000 description 12
- 238000003466 welding Methods 0.000 description 9
- 230000004907 flux Effects 0.000 description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 239000010949 copper Substances 0.000 description 4
- 230000000873 masking effect Effects 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 229910000765 intermetallic Inorganic materials 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 229910052759 nickel Inorganic materials 0.000 description 3
- 230000006870 function Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000001737 promoting effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Classifications
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B41—PRINTING; LINING MACHINES; TYPEWRITERS; STAMPS
- B41N—PRINTING PLATES OR FOILS; MATERIALS FOR SURFACES USED IN PRINTING MACHINES FOR PRINTING, INKING, DAMPING, OR THE LIKE; PREPARING SUCH SURFACES FOR USE AND CONSERVING THEM
- B41N1/00—Printing plates or foils; Materials therefor
- B41N1/24—Stencils; Stencil materials; Carriers therefor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
- H05K3/12—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern using thick film techniques, e.g. printing techniques to apply the conductive material or similar techniques for applying conductive paste or ink patterns
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/05—Patterning and lithography; Masks; Details of resist
- H05K2203/0548—Masks
Definitions
- the present disclosure relates to the field of display technology, and in particular, to a mask plate, an electronic device, and a manufacturing method thereof.
- SMT Surface Mount Technology (abbreviation for Surface Mounted Technology). It is the most popular technology and process in the electronic assembly industry. It is a method of placing electronic components with pins on a substrate with pads. The technology of soldering and assembling the surface of the base substrate through reflow soldering or dip soldering. In order to complete the fixed connection between the electronic components and the pads, solder needs to be placed on the pads to be electrically connected to the electronic components on the substrate, and then through a series of processes, the fixed connection between the electronic components and the pads is achieved.
- an embodiment of the present disclosure provides a mask plate configured to mask a backplane.
- the backplane includes a substrate, an insulating layer and a pad group located on the substrate, and the The pad group includes at least two pads, the insulating layer includes an opening, and the pads are protrudingly disposed at the opening relative to the insulating layer toward a side away from the substrate;
- the mask includes:
- Blind holes are arranged surrounding the through holes.
- the size of the blind holes in the thickness direction of the mask plate is greater than or equal to the size of the pad protruding from the insulating layer.
- the blind holes are located at the The orthographic projection on the substrate and the orthographic projection of the through hole on the substrate are spliced together to cover the orthographic projection of the pad on the substrate.
- the size of the blind hole in the thickness direction of the mask plate is less than or equal to 1/3 of the thickness of the mask plate.
- the orthographic projection of the through hole on the substrate is located within the orthographic projection of the pad on the substrate.
- the orthographic projection of the through hole on the substrate is located within the orthographic projection of the pad group on the substrate, and The orthographic projection of the through hole on the substrate and the orthographic projection of the at least two pads in the pad group on the substrate, and the spacing of the pads on the substrate The orthographic projections on all overlap each other.
- one of the blind holes surrounds one of the through holes.
- the orthographic projection of the blind hole on the substrate is oriented away from the orthographic projection of the bonding pad on the substrate.
- the direction of the through hole extends outward.
- two adjacent ones of the The distance between blind holes is greater than or equal to 100 ⁇ m.
- an embodiment of the present disclosure provides an electronic device, including: an electronic component and a backplane, the electronic component is electrically connected to the pad group, and the backplane adopts the above mask provided by the embodiment of the present disclosure.
- the board is masked.
- Figure 1 is a schematic diagram of the mask plate and the back plate after alignment and contact in the related art
- Figure 2 is a schematic structural diagram of a backplane provided by an embodiment of the present disclosure
- Figure 5 is a cross-sectional view along II' in Figure 4.
- Figure 8 is another structural schematic diagram of a mask provided by an embodiment of the present disclosure.
- Figure 9 is a schematic diagram of the back plate shown in Figure 7 and the mask plate shown in Figure 8 after they are in alignment and contact;
- Figure 11 is a cross-sectional view along IV-IV' in Figure 9;
- Figure 12 is a schematic diagram of the electrical connection between an electronic component and a pad group in the display device provided by an embodiment of the present disclosure
- Figure 13 is a flow chart of a manufacturing method of an electronic device provided by an embodiment of the present disclosure.
- Figure 14 is a schematic diagram of the alignment of the mask plate and the back plate provided by the embodiment of the present disclosure.
- Figure 16 is another schematic diagram of the mask plate and the back plate during the masking process provided by the embodiment of the present disclosure.
- Figure 17 is a schematic diagram of the separation of the mask plate and the back plate provided by an embodiment of the present disclosure.
- the insulating layer 101 has an opening K, and the surface of the pad 102 exposed by the opening K is 1 ⁇ m to 3 ⁇ m higher than the surface of the insulating layer 101.
- the flat mask M When the flat mask M is used to set In the case of soldering materials, to avoid short circuits between adjacent pads, the flat mask The area of the opening K of M is smaller than the surface area of the pad 102, that is, the flat mask M is in contact with the edge of the pad 102, and the scraper is moved in a specific direction, so that the soldering material can fall from the opening K onto the pad.
- the scraper there will be stress concentration at the position S where the pad 102 contacts the flat mask plate M.
- the film layers of the back plate are thin and relatively fragile, so the stress often occurs during the process of setting the welding material. Cause damage to the circuits on the backplane.
- the welding material includes any one of welding metal or welding auxiliary material.
- Mask 002 includes:
- Blind hole 202 is provided surrounding the through hole 201.
- the size a of the blind hole 202 in the thickness direction Z of the mask plate 002 is greater than or equal to the size b of the pad 102 protruding from the insulating layer 101.
- the blind hole 202 is on the substrate 100.
- the orthographic projection of the through hole 201 on the substrate 100 is spliced to cover the orthographic projection of the pad 102 on the substrate 100 .
- the pad group 102' includes two pads 102, which are a first pad P pad and a second pad N pad that are electrically connected to pins of a two-pin electronic component (such as a light-emitting diode).
- the material of the pad 102 may include nickel and/or gold.
- a nickel (Ni) layer with a thickness of 3 ⁇ m to 5 ⁇ m may be first formed on the conductive pattern (such as a wiring structure made of copper), and then passed through The substitution reaction causes a 0.03 ⁇ m thick gold (Au) layer to be plated on the surface of the nickel layer, and the exposed surface area in the conductive pattern forms the bonding pad 102 .
- the size a of the blind hole 202 in the thickness direction Z of the mask plate 002 is less than or equal to the mask plate 002 1/3 of the thickness c to prevent the mask plate 002 from being too thin and easily deformed, which would affect the life of the mask plate 002 and the masking effect.
- the thickness c of the mask plate 002 is 30 ⁇ m
- the size a of the blind hole 202 in the thickness direction Z of the mask plate 002 is larger than the size b of the pad 102 protruding from the insulating layer 101 and less than or equal to 10 ⁇ m.
- the surface thickness direction Z of the bonding pad 102 exceeds the surface dimension b of the insulating layer 101, b is greater than or equal to 1 ⁇ m and less than or equal to 3 ⁇ m, therefore, in the thickness direction Z of the mask plate 002, the distance between the blind hole 202 and the bonding pad 102
- the spacing is equal to (a-b), that is, greater than 0 and less than or equal to (7 ⁇ m-9 ⁇ m).
- the spacing between the blind hole 202 and the insulating layer 101 is equal to a, that is, greater than or equal to (1 ⁇ m-3 ⁇ m) and less than or equal to 10 ⁇ m.
- the distance between the blind hole 202 and the bonding pad 102 and the distance between the blind hole 202 and the insulating layer 101 are both small. Therefore, when the soldering metal (for example, with solder paste) falls into the bonding pad 102 through the through hole 201 After being applied, since the solder paste has a certain viscosity, it is difficult to flow and enter a smaller space, thereby effectively preventing the adjacent pads 102 from being short-circuited due to the solder paste.
- the orthographic projection of the through hole 201 on the substrate 100 is located at the position of the pad 102 on the substrate 100 .
- this allows the solder metal (for example, solder paste) to fall onto the corresponding pad 102 through the through hole 201, thereby preventing adjacent pads 102 from shorting each other due to the solder metal.
- the size of the through hole 201 is the same as the pin size of the electronic component electrically connected to the pad 102. In some embodiments, the size of the through hole 201 can be determined based on the pin size of the electronic component.
- the backplane 001 may include a plurality of pixel areas P, and each pixel area P includes three different Color sub-pixels, each sub-pixel is a light-emitting diode, one pad group 102' corresponds to one light-emitting diode, and one Each pad group 102' includes two pads 102, and one via group 201' includes the same number of vias 201 as the pads 102 of one pad group 102'.
- one pad group 102' may include the same number of pads 102 as the pins of the electronic component, and one via group 201' may include the same number of pads 102 as one pad group 102'. Via 201.
- the mask plate 002 provided by the embodiment of the present disclosure can be used to transfer soldering auxiliary materials (such as flux).
- through holes 201 can be provided in the substrate.
- the orthographic projection on the substrate 100 is within the orthographic projection of the pad group 102' on the substrate 100, and the orthographic projection of the via 201 on the substrate 100 is within the orthographic projection of at least two pads 102 in the pad group 102' on the substrate.
- the orthographic projection on the substrate 100 and the orthographic projection of the area g between adjacent pads 102 on the substrate 100 overlap with each other.
- a large blind hole with the same depth as the blind hole 202 can be formed first in the area where the blind hole 202 is to be made and the area surrounding the through hole 201 where the through hole 201 is to be made, and then the through hole 201 is formed in the area corresponding to the through hole 201 of the large blind hole. , and the area of the large blind hole corresponding to the blind hole 202 can be used as the blind hole 202. In this way, even if one blind hole 202 only surrounds one through hole 201, the through hole 201 located in the pad group 102' is orthogonally projected. The aperture is larger, and accordingly the aperture of the large blind hole is also larger. The difficulty of making the large blind hole is lower, which is beneficial to the production of the blind hole 202.
- the orthographic projection of the blind hole 202 on the substrate 100 is on the substrate 100 relative to the pad 102
- the orthographic projection of the blind hole 202 extends outward in the direction away from the through hole 201, which is equivalent to the orthographic projection of the blind hole 202 on the substrate 100 exceeding the orthographic projection of the pad 102 on the substrate 100, so that the mask plate 002 can better
- the blind hole 202 avoids the bonding pad 102 to prevent the stress concentration caused by the mask plate 002 overlapping the edge of the bonding pad 102, thereby effectively preventing the stress concentration from causing damage to the circuits of the backplane 001.
- the portion of the mask plate 002 between adjacent blind holes 202 is in contact with the insulating layer 101 of the backplane 001, In order to ensure that the mask plate 002 has a large contact surface with the insulating layer 101, to achieve effective support of the mask plate 002 by the insulating layer 101, and to ensure the structural stability of the mask plate 002, the mask plate 002 is placed in the adjacent blind position.
- the portion between the holes 202 needs to be sized appropriately.
- the distance e between two adjacent blind holes 202 is set to be greater than or equal to 100 ⁇ m, and may be, for example, 200 ⁇ m, 300 ⁇ m, etc.
- the backplane 001 may also include a first conductive layer 103, a flat layer 104, a second conductive layer 105, etc., wherein the materials of the first conductive layer 103 and the second conductive layer 105 may include copper (Cu), etc., and the first conductive layer 103 may be made of copper.
- Layer 103 and second conductive layer 105 are used to create the circuitry that drives electronic component 003 to operate.
- Other essential components of the backplane 001 are understood by those of ordinary skill in the art, and will not be described in detail here, nor should they be used to limit the present disclosure.
- the above-mentioned electronic device provided by the embodiment of the present disclosure can be a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, a smart watch, a fitness wristband, a personal digital assistant, or any other device with a display.
- the electronic device includes but is not limited to: radio frequency unit, network module, audio output & input unit, sensor, display unit, user input unit, interface unit, memory, processor, power supply and other components.
- the above structure does not constitute a limitation on the above-mentioned electronic device provided by the embodiment of the present disclosure.
- the above-mentioned electronic device provided by the embodiment of the present disclosure may include more or less of the above-mentioned ones. components, or combinations of certain components, or different arrangements of components.
- soldering material WM in the present disclosure may be soldering metal (such as solder paste) Or one of the soldering auxiliary materials (such as flux).
- soldering metal such as solder paste
- one of the soldering auxiliary materials such as flux.
- each pin 301 of the electronic component 003 can be electrically connected to each pad 102 through the solidified solder metal.
- connection portion WM' is further formed, so that each pin 301 of the electronic component 003 is electrically connected to each pad 102 through the connection portion WM', as shown in FIG. 12 .
- the orthographic shape of the connection portion WM′ on the substrate 100 is limited by the orthographic shapes of the pins 301 and the pads 102 on the substrate 100 .
- the shape of the orthographic projection of the connecting portion WM' and the electrically connected pin 301 on the substrate 100 and the orthographic shape of the pad 102 on the substrate 100 are basically the same, for example, approximately circular or square.
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
本公开提供了掩膜板及电子装置、其制作方法,其中掩膜板被配置为对背板进行掩膜,背板包括衬底,以及位于衬底上的绝缘层和焊盘组,焊盘组包括至少两个焊盘,绝缘层包括开口,焊盘在开口处相对于绝缘层朝向远离衬底的一侧凸出设置;掩膜板包括:通孔,通孔在衬底上的正投影与焊盘在衬底上的正投影相互交叠;盲孔,盲孔包围通孔设置,盲孔在掩膜板厚度方向上的尺寸大于等于焊盘凸出绝缘层的尺寸,盲孔在衬底上的正投影与通孔在衬底上的正投影拼接后覆盖焊盘在衬底上的正投影。
Description
相关申请的交叉引用
本申请要求在2022年06月17日提交中国专利局、申请号为202210692145.7、申请名称为“掩膜板及电子装置、其制作方法”的中国专利申请的优先权,其全部内容通过引用结合在本申请中。
本公开涉及显示技术领域,尤其涉及一种掩膜板及电子装置、其制作方法。
SMT是表面组装技术(表面贴装技术)(Surface Mounted Technology的缩写),是电子组装行业里最流行的一种技术和工艺,是一种将具有引脚的电子元件放置在具有焊盘的衬底基板的表面上,通过回流焊或浸焊等方法加以焊接组装的技术。为了完成电子元件与焊盘的固定连接,需要在衬底基板上待与电子元件电气连接的焊盘上设置焊料,再经过一系列工艺,实现电子元件与焊盘的固定连接。
发明内容
本公开实施例提供的掩膜板及电子装置、其制作方法,具体方案如下:
一方面,本公开实施例提供的一种掩膜板,被配置为对背板进行掩膜,所述背板包括衬底,以及位于所述衬底上的绝缘层和焊盘组,所述焊盘组包括至少两个焊盘,所述绝缘层包括开口,所述焊盘在所述开口处相对于所述绝缘层朝向远离所述衬底的一侧凸出设置;
所述掩膜板包括:
通孔,所述通孔在所述衬底上的正投影与所述焊盘在所述衬底上的正投影相互交叠;
盲孔,所述盲孔包围所述通孔设置,所述盲孔在所述掩膜板厚度方向上的尺寸大于等于所述焊盘凸出所述绝缘层的尺寸,所述盲孔在所述衬底上的正投影与所述通孔在所述衬底上的正投影拼接后覆盖所述焊盘在所述衬底上的正投影。
在一些实施例中,在本公开实施例提供的上述掩膜板中,所述盲孔在所述掩膜板厚度方向上的尺寸小于等于所述掩膜板厚度的1/3。
在一些实施例中,在本公开实施例提供的上述掩膜板中,所述通孔在所述衬底上的正投影位于所述焊盘在所述衬底上的正投影内。
在一些实施例中,在本公开实施例提供的上述掩膜板中,所述背板包括多个像素区,每相邻至少两个所述通孔构成与一个所述焊盘组对应的一个通孔组,一个所述像素区对应至少两个所述通孔组,一个所述盲孔包围一个所述像素区对应的至少两个所述通孔组中的各所述通孔。
在一些实施例中,在本公开实施例提供的上述掩膜板中,所述通孔在所述衬底上的正投影位于所述焊盘组在所述衬底上的正投影内,且所述通孔在所述衬底上的正投影与所述焊盘组中的所述至少两个焊盘在所述衬底上的正投影、以及所述焊盘的间距在所述衬底上的正投影均相互交叠。
在一些实施例中,在本公开实施例提供的上述掩膜板中,一个所述盲孔包围一个所述通孔。
在一些实施例中,在本公开实施例提供的上述掩膜板中,所述盲孔在所述衬底上的正投影相对于所述焊盘在所述衬底上的正投影朝向远离所述通孔的方向外延。
在一些实施例中,在本公开实施例提供的上述掩膜板中,所述盲孔远离所述通孔的边界在所述衬底上的正投影与所述焊盘在所述衬底上的正投影之间的距离大于等于30μm。
在一些实施例中,在本公开实施例提供的上述掩膜板中,相邻两个所述
盲孔之间的距离大于等于100μm。
另一方面,本公开实施例提供了一种电子装置,包括:电子元件和背板,所述电子元件与所述焊盘组电连接,所述背板采用本公开实施例提供的上述掩膜板进行掩膜。
另一方面,本公开实施例提供了一种上述电子装置的制作方法,包括:
将本公开实施例提供的上述掩膜板与背板进行对位,使得所述通孔与所述焊盘正对设置;
控制所述掩膜板在所述盲孔所在区与所述焊盘互不接触,并在所述盲孔所在区之外的区域与所述绝缘层接触;
在所述掩膜板上沿特定方向移动刮刀,将焊接材料推至所述通孔中,使得所述焊接材料通过所述通孔落入所述焊盘上;
将所述掩膜板从所述背板上移除;
将电子元件的各个引脚分别放置在各个所述焊盘处的所述焊接材料上;
通过回流焊工艺对所述焊接材料进行处理,使得所述电子元件的各个所述引脚与各个所述焊盘对应焊接在一起。
图1为相关技术中掩膜板与背板对位接触后的示意图;
图2为本公开实施例提供的背板的一种结构示意图;
图3为本公开实施例提供的掩膜板的一种结构示意图;
图4为图2所示背板与图3所示掩膜板对位接触后的示意图;
图5为沿图4中I-I'的截面图;
图6为沿图4中II-II'的截面图;
图7为本公开实施例提供的背板的又一种结构示意图;
图8为本公开实施例提供的掩膜板的又一种结构示意图;
图9为图7所示背板与图8所示掩膜板对位接触后的示意图;
图10为沿图9中III-III'的截面图;
图11为沿图9中IV-IV'的截面图;
图12为本公开实施例提供的显示装置中一个电子元件与一个焊盘组电连接的示意图;
图13为本公开实施例提供的电子装置的制作方法的流程图;
图14为本公开实施例提供的掩膜板与背板的对位示意图;
图15为本公开实施例提供的掩膜板与背板在掩膜过程中的一种示意图;
图16为本公开实施例提供的掩膜板与背板在掩膜过程中的又一种示意图;
图17为本公开实施例提供的掩膜板与背板分离的示意图;
图18为本公开实施例提供的电子元件与焊盘组的对位示意图。
为使本公开实施例的目的、技术方案和优点更加清楚,下面将结合本公开实施例的附图,对本公开实施例的技术方案进行清楚、完整地描述。需要注意的是,附图中各图形的尺寸和形状不反映真实比例,目的只是示意说明本公开内容。并且自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。
除非另作定义,此处使用的技术术语或者科学术语应当为本公开所属领域内具有一般技能的人士所理解的通常意义。本公开说明书以及权利要求书中使用的“第一”、“第二”以及类似的词语并不表示任何顺序、数量或者重要性,而只是用来区分不同的组成部分。“包括”或者“包含”等类似的词语意指出现该词前面的元件或者物件涵盖出现在该词后面列举的元件或者物件及其等同,而不排除其他元件或者物件。“内”、“外”、“上”、“下”等仅用于表示相对位置关系,当被描述对象的绝对位置改变后,则该相对位置关系也可能相应地改变。
如图1所示,相关技术中绝缘层101具有开口K,且开口K露出的焊盘102的表面相对于绝缘层101的表面要高出1μm~3μm的尺寸,在采用平板掩膜板M设置焊接材料的情况下,为避免相邻焊盘之间出现短路,平板掩膜板
M的开口K的面积小于焊盘102的表面面积,即平板掩膜板M与焊盘102的边缘相接触,沿特定方向移动刮刀,从而焊接材料可以从开口K落入到焊盘上,在移动刮刀的过程中,焊盘102与平板掩膜板M接触的位置S会有应力集中,而背板的各膜层较薄、比较脆弱,所以在设置焊接材料的过程中常常会因应力而对背板的线路造成损伤。
本公开实施例中,焊接材料包括焊接金属或焊接辅助材料中的任一种。
基于此,如图2至图6所示,本公开实施例提供了一种掩膜板002,被配置为对背板001进行掩膜,背板001包括衬底100,以及位于衬底100上的绝缘层101和焊盘组102',焊盘组102'包括至少两个焊盘102,绝缘层101包括开口K,焊盘102在开口K处相对于绝缘层101朝向远离衬底100的一侧凸出设置;
掩膜板002包括:
通孔201,通孔201在衬底100上的正投影与焊盘102在衬底100上的正投影相互交叠;
盲孔202,盲孔202包围通孔201设置,盲孔202在掩膜板002厚度方向Z上的尺寸a大于等于焊盘102凸出绝缘层101的尺寸b,盲孔202在衬底100上的正投影与通孔201在衬底100上的正投影拼接后覆盖焊盘102在衬底100上的正投影。
在本公开实施例提供的上述掩膜板002中,通过在掩膜板002的通孔201周围设置盲孔202,并设置盲孔202在掩膜板002厚度方向Z上的尺寸a(即深度)大于等于焊盘102凸出绝缘层101的尺寸b,盲孔202在衬底100上的正投影与通孔201在衬底100上的正投影拼接后覆盖焊盘102在衬底100上的正投影,使得掩膜板002经过对位后放置在背板001上,具体表现为掩膜板002的盲孔202所在位置与焊盘102互不接触,掩膜板002除盲孔202所在位置外的其他部分与绝缘层101接触,避免了掩膜板002搭接在焊盘102的边缘上造成的应力集中,因此可有效解决应力集中对背板001的线路造成损伤的问题。
可选地,焊盘组102'包括两个焊盘102,分别为与两引脚的电子元件(例如发光二极管)的引脚分别电连接的第一焊盘Ppad和第二焊盘Npad。本公开中
焊盘102的材料可以包括镍和/或金等,在一些实施例中,可在导电图案(例如采用铜制作的走线结构)上先形成3μm~5μm厚的镍(Ni)层,然后通过置换反应在镍层的表面镀上0.03μm厚的金(Au)层,导电图案中表面裸露的区域构成焊盘102。
在一些实施例中,在本公开实施例提供的上述掩膜板002中,如图5和图6所示,盲孔202在掩膜板002厚度方向Z上的尺寸a小于等于掩膜板002厚度c的1/3,以避免掩膜板002过薄、易变形而影响掩膜板002的寿命和掩膜效果。可选地,掩膜板002的厚度c为30μm,盲孔202在掩膜板002厚度方向Z上的尺寸a大于焊盘102凸出绝缘层101的尺寸b且小于等于10μm。由于焊盘102的表面厚度方向Z上超出绝缘层101的表面尺寸b,b大于等于1μm且小于等于3μm,因此,在掩膜板002厚度方向Z上,盲孔202与焊盘102之间的间距等于(a-b),即大于0且小于等于(7μm~9μm),盲孔202与绝缘层101之间的间距等于a,即大于等于(1μm~3μm)且小于等于10μm。可见,盲孔202与焊盘102之间的间距、以及盲孔202与绝缘层101之间的间距均较小,由此在焊接金属(例如具有锡膏)经由通孔201落入焊盘102上之后,由于锡膏具有一定粘度,很难流动并进入到尺寸较小的空间,从而有效避免了相邻焊盘102因为锡膏而发生短路。
在一些实施例中,在本公开实施例提供的上述掩膜板002中,如图4至图6所示,通孔201在衬底100上的正投影位于焊盘102在衬底100上的正投影内,这样可以使焊接金属(例如具有锡膏)经由通孔201落入对应的焊盘102上,避免相邻焊盘102因为焊接金属而相互短接。可选地,通孔201的尺寸与焊盘102上电连接的电子元件的引脚尺寸相同,在一些实施例中,可在电子元件的引脚尺寸的基础上,对通孔201的尺寸进行微调,以保证经由通孔201转移至焊盘102上的焊接金属在经过回流焊工艺后,可以完全位于电子元件的引脚与焊盘102之间,保证电子元件的引脚与焊盘102的电连接效果。
在一些实施例中,在本公开实施例提供的上述掩膜板002中,如图2至图4所示,背板001可以包括多个像素区P,每个像素区P中包括三个不同颜色的子像素,每个子像素为发光二极管,一个焊盘组102’与一个发光二极管对应,一
个焊盘组102'包括两个焊盘102,一个通孔组201'包括与一个焊盘组102'的焊盘102相同数量的通孔201。每相邻至少两个通孔201构成与一个焊盘组102'对应的一个通孔组201',一个像素区P对应至少两个通孔组201',一个盲孔202包围一个像素区P对应的至少两个通孔组201'中的各通孔201,相当于一个像素区P对应的至少两个通孔组201'中的各通孔201周围的盲孔202是相互连通的,由此使得盲孔202的尺寸较大,易于制作。并且由于盲孔202与焊盘102之间的间距、以及盲孔202与绝缘层101之间的间距均较小,因此在焊接金属(例如具有锡膏)经由通孔201落入焊盘102上之后,具有一定粘度的锡膏,很难流动并进入到尺寸较小的空间,从而有效防止了同一盲孔202所对应区域的不同焊盘102因为锡膏而发生短路。在其他的一些实施例中,一个焊盘组102'可以包括与电子元件的引脚相同数量的焊盘102,一个通孔组201'包括与一个焊盘组102'的焊盘102相同数量的通孔201。
在一些实施例中,本公开实施例提供的掩膜板002可用于转移焊接辅助材料(例如助焊剂),在此情况下,如图7至图11所示,可以设置通孔201在衬底100上的正投影位于焊盘组102'在衬底100上的正投影内,且通孔201在衬底100上的正投影与焊盘组102'中的至少两个焊盘102在衬底100上的正投影、以及相邻焊盘102之间的区域g在衬底100上的正投影均相互交叠。在具体实施时,焊接辅助材料(例如助焊剂)会经由同一通孔201同时落入焊盘组102'的至少两个焊盘102上、以及相邻焊盘102之间的区域g,但由于助焊剂仅起到促进焊接过程、以及防氧化的作用,并不具有导电性,因此,焊盘组102'的至少两个焊盘102不会通过助焊剂短接。并且,相较于图4所示正投影位于焊盘102内的通孔201,图9所示正投影位于焊盘组102'组内的通孔201的孔径较大,更易于制作。
在一些实施例中,在本公开实施例提供的上述掩膜板002中,如图7至图9所示,在通孔201在衬底100上的正投影与焊盘组102'中的至少两个焊盘102在衬底100上的正投影、以及相邻焊盘102之间的区域g在衬底100上的正投影均相互交叠的情况下,一个盲孔202可以包围一个通孔201。在一些实施例中,
可先在待制作盲孔202的区域及其包围的待制作通孔201的区域形成一个与盲孔202深度相同的大盲孔,然后在该大盲孔对应通孔201的区域形成通孔201,而该大盲孔对应盲孔202的区域则可做为盲孔202,如此,即使一个盲孔202仅包围一个通孔201,也因正投影位于焊盘组102'组内的通孔201的孔径较大,相应地大盲孔的孔径也较大,制作大盲孔的难度较低,利于实现盲孔202的制作。
在一些实施例中,在本公开实施例提供的上述掩膜板002中,如图4和图9所示,盲孔202在衬底100上的正投影相对于焊盘102在衬底100上的正投影朝向远离通孔201的方向外延,相当于盲孔202在衬底100上的正投影会超出焊盘102在衬底100上的正投影,这样掩膜板002就可以更好地在盲孔202处避开焊盘102,防止掩膜板002搭接在焊盘102的边缘上造成的应力集中,从而有效避免应力集中对背板001的线路造成损伤。
在一些实施例中,盲孔202的制作公差为10μm,掩膜板002与背板001的对位公差为20μm,为防止掩膜板002搭接在焊盘102上,在本公开实施例提供的上述掩膜板002中,如图4和图9所示,盲孔202远离通孔201的边界在衬底100上的正投影与焊盘102在衬底100上的正投影之间的距离d大于等于30μm。
在一些实施例中,在本公开实施例提供的上述掩膜板002中,如图11所示,掩膜板002在相邻盲孔202之间的部分与背板001的绝缘层101接触,为保证掩膜板002与绝缘层101具有较大的接触面,实现绝缘层101对掩膜板002的有效支撑,并保证掩膜板002的自身结构稳定性,掩膜板002在相邻盲孔202之间的部分的尺寸需要合理设置。在本公开中,如图4和图9所示,设置相邻两个盲孔202之间的距离e大于等于100μm,例如可以为200μm、300μm等。
基于同一公开构思,本公开实施例还提供了一种电子装置,如图12所示,包括:电子元件003,以及本公开实施例提供的上述背板001;其中,背板001可以采用上述掩膜板002进行掩膜;电子元件003与焊盘组102电连接,在一些实施例中,一个电子元件003与一个焊盘组102对应电连接。电子元件003可以为发光二极管、驱动芯片等。
在一些实施例中,如图5、图6、图10和图11所示,本公开实施例提供
的背板001还可以包括第一导电层103、平坦层104和第二导电层105等,其中,第一导电层103和第二导电层105的材料可以包括铜(Cu)等,第一导电层103和第二导电层105用于制作驱动电子元件003工作的电路。对于背板001的其它必不可少的组成部分均为本领域的普通技术人员应该理解具有的,在此不做赘述,也不应作为对本公开的限制。
在一些实施例中,本公开实施例提供的上述电子装置可以为手机、平板电脑、电视机、显示器、笔记本电脑、数码相框、导航仪、智能手表、健身腕带、个人数字助理等任何具有显示功能的产品或部件。该电子装置包括但不限于:射频单元、网络模块、音频输出&输入单元、传感器、显示单元、用户输入单元、接口单元、存储器、处理器、以及电源等部件。另外,本领域技术人员可以理解的是,上述结构并不构成对本公开实施例提供的上述电子装置的限定,换言之,在本公开实施例提供的上述电子装置中可以包括上述更多或更少的部件,或者组合某些部件,或者不同的部件布置。
基于同一公开构思,本公开实施例还提供了一种电子装置的制作方法,如图13所示,包括以下步骤:
S1301、将本公开实施例提供的掩膜板002与背板001进行对位,使得通孔201与焊盘102正对设置,如图14所示。
S1302、控制掩膜002在盲孔202所在区与焊盘102互不接触,并在盲孔202所在区之外的区域与绝缘层101接触,如图15所示。
S1303、在掩膜板002上沿特定方向移动刮刀,将焊接材料WM推至通孔201中,使得焊接材料WM通过通孔201落入焊盘102上,如图16所示。
S1304、将掩膜板002从背板001上移除,如图17所示。
S1305、将电子元件003的各个引脚301分别放置在各个焊盘102处的焊接材料WM上,如图18所示。
S1306、通过回流焊工艺对焊接材料WM进行处理,使得电子元件003的各个引脚301与各个焊盘102对应焊接在一起,如图12所示。
需要说明的是,本公开中的焊接材料WM可以为焊接金属(例如锡膏)
或焊接辅助材料(例如助焊剂)中的其中一种。在焊接材料WM为锡膏的情况下,电子元件003的各个引脚301可以设置助焊剂,在回流焊工艺处理后,电子元件003的各个引脚301可以通过固化后的焊接金属与各个焊盘102实现电连接。在焊接材料WM为助焊剂的情况下,因助焊剂仅起到促进焊接过程,同时具有防氧化的作用,并不具有导电性,所以需要在电子元件003的各个引脚301设置焊接金属(例如锡膏),在回流焊工艺处理后,电子元件003的各个引脚301可以通过固化后的焊接金属与各个焊盘102实现电连接。在具体实施时,在回流焊工艺中,焊接金属首先在高温下发生熔化,部分与焊盘102的表面材料形成金属间化合物(IMC),接着在冷却过程中,焊接金属和/或金属间化合物固化,进而构成连接部WM',使得电子元件003的各个引脚301通过连接部WM'与各个焊盘102电连接,如图12所示。连接部WM'在衬底100上的正投影形状受限于引脚301和焊盘102在衬底100上的正投影形状。通常连接部WM'与其电连接的引脚301在衬底100上的正投影的形状及焊盘102在衬底100上的正投影的形状基本相同,例如呈近似圆形或方形。
尽管本公开已描述了优选实施例,但应当理解的是,本领域的技术人员可以对本公开实施例进行各种改动和变型而不脱离本公开实施例的精神和范围。这样,倘若本公开实施例的这些修改和变型属于本公开权利要求及其等同技术的范围之内,则本公开也意图包含这些改动和变型在内。
Claims (11)
- 一种掩膜板,被配置为对背板进行掩膜,所述背板包括衬底,以及位于所述衬底上的绝缘层和焊盘组,所述焊盘组包括至少两个焊盘,所述绝缘层包括开口,所述焊盘在所述开口处相对于所述绝缘层朝向远离所述衬底的一侧凸出设置;所述掩膜板包括:通孔,所述通孔在所述衬底上的正投影与所述焊盘在所述衬底上的正投影相互交叠;盲孔,所述盲孔包围所述通孔设置,所述盲孔在所述掩膜板厚度方向上的尺寸大于等于所述焊盘凸出所述绝缘层的尺寸,所述盲孔在所述衬底上的正投影与所述通孔在所述衬底上的正投影拼接后覆盖所述焊盘在所述衬底上的正投影。
- 如权利要求1所述的掩膜板,其中,所述盲孔在所述掩膜板厚度方向上的尺寸小于等于所述掩膜板厚度的1/3。
- 如权利要求2所述的掩膜板,其中,所述通孔在所述衬底上的正投影位于所述焊盘在所述衬底上的正投影内。
- 如权利要求3所述的掩膜板,其中,所述背板包括多个像素区,每相邻至少两个所述通孔构成与一个所述焊盘组对应的一个通孔组,一个所述像素区对应至少两个所述通孔组,一个所述盲孔包围一个所述像素区对应的至少两个所述通孔组中的各所述通孔。
- 如权利要求2所述的掩膜板,其中,所述通孔在所述衬底上的正投影位于所述焊盘组在所述衬底上的正投影内,且所述通孔在所述衬底上的正投影与所述焊盘组中的所述至少两个焊盘在所述衬底上的正投影、以及所述焊盘的间距在所述衬底上的正投影均相互交叠。
- 如权利要求5所述的掩膜板,其中,一个所述盲孔包围一个所述通孔。
- 如权利要求1~6任一项所述的掩膜板,其中,所述盲孔在所述衬底上 的正投影相对于所述焊盘在所述衬底上的正投影朝向远离所述通孔的方向外延。
- 如权利要求7所述的掩膜板,其中,所述盲孔远离所述通孔的边界在所述衬底上的正投影与所述焊盘在所述衬底上的正投影之间的距离大于等于30μm。
- 如权利要求8所述的掩膜板,其中,相邻两个所述盲孔之间的距离大于等于100μm。
- 一种电子装置,其中,包括:电子元件和背板,所述电子元件与所述焊盘组电连接,所述背板采用如权利要求1~9任一项所述的掩膜板进行掩膜。
- 一种如权利要求10所述的电子装置的制作方法,其中,包括:将如权利要求1~9任一项所述的掩膜板与背板进行对位,使得所述通孔与所述焊盘正对设置;控制所述掩膜板在所述盲孔所在区与所述焊盘互不接触,并在所述盲孔所在区之外的区域与所述绝缘层接触;在所述掩膜板上沿特定方向移动刮刀,将焊接材料推至所述通孔中,使得所述焊接材料通过所述通孔落入所述焊盘上;将所述掩膜板从所述背板上移除;将电子元件的各个引脚分别放置在各个所述焊盘处的所述焊接材料上;通过回流焊工艺对所述焊接材料进行处理,使得所述电子元件的各个所述引脚与各个所述焊盘对应焊接在一起。
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Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
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US6316289B1 (en) * | 1998-11-12 | 2001-11-13 | Amerasia International Technology Inc. | Method of forming fine-pitch interconnections employing a standoff mask |
US20020023554A1 (en) * | 1998-02-24 | 2002-02-28 | Chad Cobbley | Method and stencil for extruding material on a substrate |
JP2008124282A (ja) * | 2006-11-13 | 2008-05-29 | Toyota Motor Corp | はんだ印刷用マスク |
CN217936140U (zh) * | 2022-06-17 | 2022-11-29 | 京东方科技集团股份有限公司 | 掩膜板及电子装置 |
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- 2022-06-17 CN CN202210692145.7A patent/CN117295251A/zh active Pending
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020023554A1 (en) * | 1998-02-24 | 2002-02-28 | Chad Cobbley | Method and stencil for extruding material on a substrate |
US6316289B1 (en) * | 1998-11-12 | 2001-11-13 | Amerasia International Technology Inc. | Method of forming fine-pitch interconnections employing a standoff mask |
JP2008124282A (ja) * | 2006-11-13 | 2008-05-29 | Toyota Motor Corp | はんだ印刷用マスク |
CN217936140U (zh) * | 2022-06-17 | 2022-11-29 | 京东方科技集团股份有限公司 | 掩膜板及电子装置 |
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