WO2022208909A1 - Power converter and motor module - Google Patents

Power converter and motor module Download PDF

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Publication number
WO2022208909A1
WO2022208909A1 PCT/JP2021/022217 JP2021022217W WO2022208909A1 WO 2022208909 A1 WO2022208909 A1 WO 2022208909A1 JP 2021022217 W JP2021022217 W JP 2021022217W WO 2022208909 A1 WO2022208909 A1 WO 2022208909A1
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Prior art keywords
fixed
period
phase
degrees
waveform example
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PCT/JP2021/022217
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French (fr)
Japanese (ja)
Inventor
恒司 佐藤
友博 福村
耕太郎 片岡
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日本電産株式会社
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Application filed by 日本電産株式会社 filed Critical 日本電産株式会社
Priority to CN202180094837.5A priority Critical patent/CN116897499A/en
Publication of WO2022208909A1 publication Critical patent/WO2022208909A1/en

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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
    • H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
    • H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode

Definitions

  • the present invention relates to power converters and motor modules.
  • a motor control device that drives a three-phase motor is known (for example, Patent Document 1).
  • the temperature rise of the switching element is suppressed by fixing each phase voltage of the three-phase voltage to 2 ⁇ /3 or ⁇ /3.
  • the present invention has been made in view of the above problems, and its object is to simultaneously suppress the heat generation of the first semiconductor switching element of a certain phase and the heat generation of the second semiconductor switching element of a certain phase, thereby suppressing the temperature rise of the power converter.
  • An object of the present invention is to provide a power converter and a motor module capable of suppressing and improving reliability.
  • An exemplary power converter of the present invention converts DC power into n-phase AC power.
  • the power converter includes n output terminals, a first power terminal, a second power terminal, and n series bodies.
  • the n output terminals output n-phase output voltages and n-phase output currents.
  • a first voltage is applied to the first power supply terminal.
  • a second voltage lower than the first voltage is applied to the second power supply terminal.
  • the n series bodies are formed by connecting two semiconductor switching elements in series.
  • n is the number of AC output phases and is an odd number of 3 or more.
  • the n series bodies are connected in parallel with each other. One end of each of the n series bodies is connected to the first power supply terminal.
  • Each of the n series bodies has the other end connected to the second power supply terminal.
  • Each of the n series bodies has a first semiconductor switching element and a second semiconductor switching element.
  • the first semiconductor switching element is connected to the first power terminal.
  • the second semiconductor switching element is connected to the second power terminal.
  • the first semiconductor switching element and the second semiconductor switching element are connected at a connection point.
  • the connection points in each of the n series bodies are connected to the n output terminals.
  • the first semiconductor switching element is switched on and off at a frequency higher than the frequency of the AC output.
  • the second semiconductor switching element is switched on and off at a frequency higher than the frequency of the AC output.
  • at least one phase of the AC output has a first fixed ON period during which the first semiconductor switching element is fixed ON and the second semiconductor switching element is ON.
  • It has a protection mode of operation having at least one of a fixed second ON fixed period.
  • the first fixed ON period is different from the first fixed ON period of any one of the other phases, or the second fixed ON period is different from the first fixed ON period of any other phase. is different from the second on-fixed period of any one phase.
  • An exemplary motor module of the present invention includes the power converter described above and a motor. The output of the power converter is input to the motor.
  • the exemplary present invention by simultaneously suppressing the heat generation of the first semiconductor switching element of a certain phase and the heat generation of the second semiconductor switching element of a certain phase, it is possible to suppress the temperature rise of the power converter and improve the reliability. .
  • FIG. 1 is a block diagram of a motor module according to an embodiment of the invention.
  • FIG. 2 is a circuit diagram showing an inverter section.
  • FIG. 3A is a diagram showing the output voltage.
  • FIG. 3B is a diagram showing switching losses.
  • FIG. 4 is a table showing the relationship between waveform examples and switching loss.
  • FIG. 5A is a diagram showing the output voltage.
  • FIG. 5B is a diagram showing switching losses.
  • FIG. 6A is a diagram showing the output voltage.
  • FIG. 6B is a diagram showing switching losses.
  • FIG. 7A is a diagram showing the output voltage.
  • FIG. 7B is a diagram showing switching losses.
  • FIG. 8A is a diagram showing the output voltage.
  • FIG. 8B is a diagram showing switching losses.
  • FIG. 9A is a diagram showing the output voltage.
  • FIG. 9B is a diagram showing switching losses.
  • FIG. 10A is a diagram showing the output voltage.
  • FIG. 10B is a diagram showing switching losses.
  • FIG. 11A is a diagram showing output voltages.
  • FIG. 11B is a diagram showing switching loss.
  • FIG. 12A is a diagram showing the output voltage.
  • FIG. 12B is a diagram showing switching losses.
  • FIG. 13A is a diagram showing the output voltage.
  • FIG. 13B is a diagram showing switching losses.
  • FIG. 14A is a diagram showing the output voltage.
  • FIG. 14B is a diagram showing switching losses.
  • FIG. 15A is a diagram showing output voltages.
  • FIG. 15B is a diagram showing switching losses.
  • FIG. 16 is a diagram showing switching loss.
  • FIG. 17 is a diagram for explaining switching of the UH_UL protection waveform.
  • FIG. 18 is a diagram for explaining switching of the UH_UL protection waveform.
  • FIG. 19 is a diagram showing switching loss.
  • FIG. 20 is a diagram for explaining switching of the UH_UL protection waveform.
  • FIG. 21 is a flow chart showing a protection waveform switching method.
  • FIG. 22 is a flow chart showing a protection waveform switching method.
  • FIG. 23 is a diagram showing a method of switching guard waveforms.
  • FIG. 24 is a diagram showing a method of switching guard waveforms.
  • FIG. 25 is a table showing the relationship between waveform examples and switching loss.
  • FIG. 26A is a diagram showing the output voltage.
  • FIG. 26B is a diagram showing switching loss.
  • FIG. 27A is a diagram showing the output voltage.
  • FIG. 27B is a diagram showing switching losses.
  • FIG. 28A is a diagram showing the output voltage.
  • FIG. 28B is a diagram showing switching losses.
  • FIG. 29A is a diagram showing the output voltage.
  • FIG. 29B is a diagram showing switching losses.
  • FIG. 30A is a diagram showing the output voltage.
  • FIG. 30B is a diagram showing switching losses.
  • FIG. 31A is a diagram showing the output voltage.
  • FIG. 31B is a diagram showing switching losses.
  • FIG. 32A is a diagram showing the output voltage.
  • FIG. 32B is a diagram showing switching losses.
  • FIG. 33A is a diagram showing the output voltage.
  • FIG. 33B is a diagram showing switching losses.
  • FIG. 34A is a diagram showing the output voltage.
  • FIG. 34A is a diagram showing the output voltage.
  • FIG. 34A is a diagram showing the output voltage.
  • FIG. 34A is
  • FIG. 34B is a diagram showing switching losses.
  • FIG. 35A is a diagram showing the output voltage.
  • FIG. 35B is a diagram showing switching losses.
  • FIG. 36A is a diagram showing the output voltage.
  • FIG. 36B is a diagram showing switching losses.
  • FIG. 37A is a diagram showing the output voltage.
  • FIG. 37B is a diagram showing switching losses.
  • FIG. 38A is a diagram showing the output voltage.
  • FIG. 38B is a diagram showing switching losses.
  • FIG. 39A is a diagram showing the output voltage.
  • FIG. 39B is a diagram showing switching losses.
  • FIG. 40A is a diagram showing the output voltage.
  • FIG. 40B is a diagram showing switching losses.
  • FIG. 41A is a diagram showing the output voltage.
  • FIG. 41B is a diagram showing switching losses.
  • FIG. 41A is a diagram showing the output voltage.
  • FIG. 41B is a diagram showing switching losses.
  • FIG. 41A is a diagram
  • FIG. 42A is a diagram showing the output voltage.
  • FIG. 42B is a diagram showing switching losses.
  • FIG. 43 is a diagram showing switching loss.
  • FIG. 44 is a diagram for explaining switching of the UH_VL protection waveform.
  • FIG. 45 is a diagram for explaining switching of the UH_VL protection waveform.
  • FIG. 46 is a diagram for explaining switching of the UH_VL protection waveform.
  • FIG. 47 is a flow chart showing a protection waveform switching method.
  • FIG. 48 is a diagram showing a method of switching guard waveforms.
  • FIG. 49 is a diagram showing a method of switching guard waveforms.
  • FIG. 50A is a diagram showing the output voltage.
  • FIG. 50B is a diagram showing switching losses.
  • FIG. 51A is a diagram showing output voltages.
  • FIG. 51A is a diagram showing output voltages.
  • FIG. 51B is a diagram showing switching loss.
  • FIG. 52A is a diagram showing the output voltage.
  • FIG. 52B is a diagram showing switching losses.
  • FIG. 53A is a diagram showing the output voltage.
  • FIG. 53B is a diagram showing switching losses.
  • FIG. 54A is a diagram showing the output voltage.
  • FIG. 54B is a diagram showing switching losses.
  • FIG. 55A is a diagram showing the output voltage.
  • FIG. 55B is a diagram showing switching losses.
  • FIG. 56A is a diagram showing the output voltage.
  • FIG. 56B is a diagram showing switching losses.
  • FIG. 57A is a diagram showing the output voltage.
  • FIG. 57B is a diagram showing switching losses.
  • FIG. 58A is a diagram showing the output voltage.
  • FIG. 58B is a diagram showing switching losses.
  • FIG. 59A is a diagram showing the output voltage.
  • FIG. 59B is a diagram showing switching losses.
  • FIG. 60A is a diagram showing the output voltage.
  • FIG. 60B is a diagram showing switching losses.
  • FIG. 61A is a diagram showing the output voltage.
  • FIG. 61B is a diagram showing switching losses.
  • FIG. 62A is a diagram showing the output voltage.
  • FIG. 62B is a diagram showing switching losses.
  • FIG. 63A is a diagram showing the output voltage.
  • FIG. 63B is a diagram showing switching losses.
  • FIG. 64A is a diagram showing the output voltage.
  • FIG. 64B is a diagram showing switching losses.
  • FIG. 65A is a diagram showing the output voltage.
  • FIG. 65B is a diagram showing switching losses.
  • FIG. 66A is a diagram showing the output voltage.
  • FIG. 66B is a diagram showing switching losses.
  • FIG. 1 is a block diagram of a motor module 200 according to an embodiment of the invention.
  • FIG. 2 is a circuit diagram showing the inverter section 110. As shown in FIG.
  • the motor module 200 includes a motor drive circuit 100 and a three-phase motor M.
  • a three-phase motor M is driven by a motor drive circuit 100 .
  • the three-phase motor M is, for example, a brushless DC motor.
  • a three-phase motor M has a U-phase, a V-phase and a W-phase.
  • the output of the motor drive circuit 100 is input to the three-phase motor M.
  • the motor drive circuit 100 corresponds to an example of a "power converter".
  • the motor drive circuit 100 controls driving of the three-phase motor M.
  • the motor drive circuit 100 includes an inverter section 110 and a signal generation section 120 .
  • the motor drive circuit 100 converts DC power into n-phase AC power.
  • n is the number of AC output phases and is an integer of 3 or more.
  • the motor drive circuit 100 converts DC power into three-phase AC power.
  • the motor drive circuit 100 has n output terminals 102 .
  • the motor drive circuit 100 has three output terminals 102 .
  • the three output terminals 102 include an output terminal 102u, an output terminal 102v, and an output terminal 102w.
  • the n output terminals 102 output n-phase output voltages and n-phase output currents.
  • the three output terminals 102 output three-phase output voltages and three-phase output currents to the three-phase motor M.
  • the output terminal 102u outputs the U-phase output voltage Vu and the U-phase output current Iu to the three-phase motor M.
  • Output terminal 102v outputs V-phase output voltage Vv and V-phase output current Iv to three-phase motor M.
  • FIG. The output terminal 102w outputs the W-phase output voltage Vw and the W-phase output current Iw to the three-phase motor M.
  • the motor drive circuit 100 includes a first power terminal P, a second power terminal N, a capacitor C, n series bodies 112, and six temperature sensors 20.
  • the motor drive circuit 100 includes a first power terminal P, a second power terminal N, a capacitor C, three series bodies 112 and six temperature sensors 20 .
  • the motor drive circuit 100 includes an inverter section 110.
  • the inverter section 110 includes a first power terminal P, a second power terminal N, a capacitor C, and three series bodies. 112 and six temperature sensors 20 .
  • Inverter section 110 further includes a DC voltage source B.
  • the DC voltage source B may be provided outside the inverter section 110 .
  • a first voltage V1 is applied to the first power supply terminal P.
  • a first power supply terminal P is connected to a DC voltage source B;
  • a second voltage V2 is applied to the second power supply terminal N.
  • a second power supply terminal N is connected to a DC voltage source B. As shown in FIG. The second voltage V2 is lower than the first voltage V1.
  • the capacitor C is connected between the first power terminal P and the second power terminal N.
  • the semiconductor switching element is, for example, an IGBT (insulated gate bipolar transistor). Note that the semiconductor switching element may be another transistor such as a field effect transistor.
  • the three series bodies 112 include a series body 112u, a series body 112v, and a series body 112w. The three series bodies 112 are connected in parallel with each other. Each of the three series bodies 112 is connected to the first power terminal P at one end. Each of the three series bodies 112 is connected to the second power terminal N at the other end.
  • a rectifying element D is connected in parallel to each of these semiconductor switching elements, with the first power supply terminal P side (upper side of the paper) as a cathode and the second power supply terminal N side (lower side of the paper) as an anode. If a field effect transistor is used as the semiconductor switching element, a parasitic diode may be used as this rectifying element.
  • Each of the three series bodies 112 has a first semiconductor switching element and a second semiconductor switching element.
  • the series body 112u has a first semiconductor switching element Up and a second semiconductor switching element Un.
  • Series body 112v has a first semiconductor switching element Vp and a second semiconductor switching element Vn.
  • the series body 112w has a first semiconductor switching element Wp and a second semiconductor switching element Wn.
  • the first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp are connected to the first power supply terminal P.
  • the first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp are semiconductor switching elements on the high voltage side.
  • the second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn are connected to the second power supply terminal N.
  • the second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn are semiconductor switching elements on the low voltage side.
  • the first semiconductor switching element and the second semiconductor switching element are connected at the connection point 114 .
  • the first semiconductor switching element Up and the second semiconductor switching element Un are connected at a connection point 114u.
  • the first semiconductor switching element Vp and the second semiconductor switching element Vn are connected at a connection point 114v.
  • the first semiconductor switching element Wp and the second semiconductor switching element Wn are connected at a connection point 114w.
  • connection point 114 in each of the three series bodies 112 is connected to the three output terminals 102 .
  • a connection point 114u in the series body 112u is connected to the output terminal 102u.
  • a connection point 114v in the series body 112v is connected to the output terminal 102v.
  • a connection point 114w in the series body 112w is connected to the output terminal 102w.
  • a PWM signal is input to the first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp.
  • a PWM signal is output from the signal generator 120 .
  • the PWM signal input to the first semiconductor switching element Up may be referred to as "UpPWM signal”.
  • the PWM signal input to the first semiconductor switching element Vp may be referred to as "Vp PWM signal”.
  • a PWM signal input to the first semiconductor switching element Wp may be referred to as a "Wp PWM signal”.
  • the first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp are switched on and off at a frequency higher than the frequency of the AC output.
  • the first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp are turned on when the UpPWM signal, the VpPWM signal, and the WpPWM signal are at HIGH level, respectively.
  • the first semiconductor switching element Up, the first semiconductor switching element Vp and the first semiconductor switching element Wp are turned off when the UpPWM signal, the VpPWM signal and the WpPWM signal are at LOW level, respectively.
  • a PWM signal is input to the second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn.
  • a PWM signal is output from the signal generator 120 .
  • the PWM signal input to the second semiconductor switching element Un may be referred to as "UnPWM signal”.
  • the PWM signal input to the second semiconductor switching element Vn may be referred to as "Vn PWM signal”.
  • a PWM signal input to the second semiconductor switching element Wn may be referred to as a "Wn PWM signal”.
  • the second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn are switched on and off at a frequency higher than the frequency of the AC output.
  • the second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn are turned on when the UnPWM signal, the VnPWM signal, and the WnPWM signal are at HIGH level, respectively.
  • the second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn are turned off when the UnPWM signal, the VnPWM signal, and the WnPWM signal are at LOW level, respectively.
  • the signal generation section 120 has a carrier generation section 122, a voltage command value generation section 124, and a comparison section 126.
  • the signal generator 120 is a hardware circuit configured by a processor such as a CPU (Central Processing Unit) and an ASIC (Application Specific Integrated Circuit).
  • the processor of signal generation unit 120 functions as carrier generation unit 122, voltage command value generation unit 124, and comparison unit 126 by executing computer programs stored in the storage device.
  • the signal generation section 120 controls the inverter section 110 . Specifically, the signal generation unit 120 controls the inverter unit 110 by generating a PWM signal and outputting the PWM signal. More specifically, signal generator 120 generates a PWM signal to be input to each of three serial bodies 112 .
  • the carrier generator 122 generates a carrier signal.
  • a carrier signal is, for example, a triangular wave. Note that the carrier signal may be a sawtooth wave.
  • the voltage command value generation unit 124 generates a voltage command value.
  • a voltage command value corresponds to a voltage value output from the motor drive circuit 100 . That is, voltage command value generation unit 124 generates voltage values corresponding to output voltage Vu, output voltage Vv, and output voltage Vw as voltage command values.
  • the comparator 126 generates a PWM signal by comparing the carrier signal and the voltage command value.
  • the six temperature sensors 20 include a temperature sensor 21u, a temperature sensor 21v, a temperature sensor 21w, a temperature sensor 22u, a temperature sensor 22v, and a temperature sensor 22w.
  • Six temperature sensors 20 are arranged in the vicinity of the semiconductor switching elements. Six temperature sensors 20 detect the temperature of the semiconductor switching elements. Specifically, the temperature sensor 21u is arranged near the first semiconductor switching element Up. The temperature sensor 21u detects the temperature of the first semiconductor switching element Up. The temperature sensor 21v is arranged near the first semiconductor switching element Vp. The temperature sensor 21v detects the temperature of the first semiconductor switching element Vp. The temperature sensor 21w is arranged near the first semiconductor switching element Wp. The temperature sensor 21w detects the temperature of the first semiconductor switching element Wp.
  • the temperature sensor 22u is arranged near the second semiconductor switching element Un.
  • the temperature sensor 22u detects the temperature of the second semiconductor switching element Un.
  • the temperature sensor 22v is arranged near the second semiconductor switching element Vn.
  • Temperature sensor 22v detects the temperature of second semiconductor switching element Vn.
  • the temperature sensor 22w is arranged near the second semiconductor switching element Wn.
  • the temperature sensor 22w detects the temperature of the second semiconductor switching element Wn.
  • FIG. 3A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 3B is a diagram showing switching losses. The switching loss of each element is shown as a relative value when the switching loss per switching element is 1 in the case of three-phase modulation in which all three phases are switched.
  • FIG. 3A shows waveform example 1 of the output voltage Vu, the output voltage Vv, and the output voltage Vw according to the embodiment of the present invention.
  • the output voltage Vu is indicated by a solid line
  • the output voltage Vv is indicated by a dashed line
  • the output voltage Vw is indicated by a dashed line.
  • the vertical axis of FIG. 3A represents the voltage value normalized by the input voltage V1-V2, and the output voltage of each phase takes a value in the range of 0-1.
  • Output voltage 0 is the state in which the output voltage substantially matches V2
  • output voltage 1 is the state in which the output voltage substantially matches V1.
  • This value also represents the duty value, which is the ratio of the ON time of the first semiconductor switching element of each phase to the PWM cycle.
  • the value obtained by subtracting the value on the vertical axis from 1 is the ratio of the ON time of the second semiconductor switching element to the PWM cycle.
  • complementary switching is performed after providing an appropriate dead time to prevent both from being turned on at the same time.
  • the horizontal axis of FIG. 3A represents the electrical rotation angle of the motor in degrees.
  • a waveform example 1 of the output voltage Vu, the output voltage Vv, and the output voltage Vw according to the embodiment of the present invention will be described with reference to FIG. 3A.
  • waveform example 1 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 30 degrees to 150 degrees. Also, the waveform is such that the output of any one phase is fixed to 0 at an electrical angle of 0 to 30 electrical degrees and at an electrical angle of 150 to 360 electrical degrees.
  • the period during which the output of any one phase is fixed to 1 may be referred to as a high-side-on application period T3.
  • the period during which the output of any one phase is fixed to 0 may be referred to as a low-side-on application period T4.
  • the high-side-on application period is T3 at an electrical angle of 30 degrees to 150 electrical degrees.
  • the low side-on application period T4 occurs at an electrical angle of 0 to 30 electrical degrees and at an electrical angle of 150 to 360 electrical degrees.
  • the difference between the two phases of the output voltage Vu, the output voltage Vv, and the output voltage Vw is a sine wave. Therefore, a sine wave can be output as the voltage between the output terminals.
  • a sine wave can be output as the voltage between the output terminals.
  • At least one phase of the AC output has a first fixed ON period T1 and a second fixed ON period T2.
  • the first fixed on period T1 is a period in which the first semiconductor switching element is fixed on.
  • the second fixed on period T2 is a period during which the second semiconductor switching element is fixed on.
  • the first fixed ON period T1 includes the first fixed ON period T1u.
  • the first fixed on period T1u is a period in which the first semiconductor switching element Up is fixed on.
  • the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees.
  • the first fixed ON period T1 only one of the n phases of the first semiconductor switching element is fixed on, and in all of the other n phases, at least one of the first semiconductor switching element and the second semiconductor switching element is fixed. indicates the switching period.
  • waveform example 1 in the first fixed on period T1u, only the U-phase first semiconductor switching element Up of the three phases is fixed on, and the V-phase first semiconductor switching element Vp or the second semiconductor switching element Vp of the three phases is fixed. At least one of the elements Vn and at least one of the W-phase first semiconductor switching element Wp or the second semiconductor switching element Wn switches.
  • the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
  • the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
  • the second fixed ON period T2v is from 0 electrical angle to 30 electrical degrees and from 330 electrical degrees to 360 electrical degrees.
  • the second fixed ON period T2w is from 150 electrical degrees to 210 electrical degrees.
  • the second fixed on period T2 only one of the n phases of the second semiconductor switching element is fixed on, and at least one of the first semiconductor switching element and the second semiconductor switching element is set in all the other phases of the n phases. indicates the switching period.
  • waveform example 1 in the second fixed on period T2u, only the U-phase second semiconductor switching element Un among the three phases is fixed on, and the V-phase first semiconductor switching element Vp or the second semiconductor switching element Vp among the three phases is fixed. At least one of the elements Vn and at least one of the W-phase first semiconductor switching element Wp or the second semiconductor switching element Wn switches.
  • One cycle of the AC output is divided into a plurality of periods, and each of the plurality of periods is the first fixed ON period of one of the phases or the second fixed ON period of one of the phases.
  • the second fixed ON period T2v is between an electrical angle of 0 degree and an electrical angle of 30 degrees.
  • the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees.
  • the second fixed ON period T2w is from 150 electrical degrees to 210 electrical degrees.
  • the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
  • the second fixed ON period T2v is from 330 electrical degrees to 360 electrical degrees. Therefore, since the switching of one phase is always stopped, temperature rise can be effectively suppressed, and the reliability of the inverter is enhanced.
  • the motor drive circuit 100 has a protection operation mode.
  • the protection operation mode has at least one of the first fixed ON period T1 and the second fixed ON period T2.
  • the first fixed ON period T1 is different from the first fixed ON period T1 of any one of the other phases, or the second fixed ON period T2 is different from the first fixed ON period T1 of any other phase. is different from the second on-fixed period T2 of any one phase. This also includes the case where any other phase does not have the first fixed ON period T1 and the second fixed ON period T2.
  • the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 1, the first fixed ON period T1u is 120 degrees, but there is no first fixed ON period T1v and no first fixed ON period T1w. That is, in Waveform Example 1, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 3B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
  • the second fixed ON period T2u differs from the second fixed ON period T2v and the second fixed ON period T2w in the U phase among the three phases.
  • the second fixed ON period T2u is 120 degrees, while the second fixed ON period T2v and the second fixed ON period T2w are 60 degrees. That is, in Waveform Example 1, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 3B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
  • the first fixed ON period T1 is set to the first ON period of the other phases. It differs from the fixed period T1. Therefore, heat generation of the first semiconductor switching element of the phase having the first fixed ON period longer than the first fixed ON period T1 of the other phase can be suppressed.
  • the second fixed ON period T2 is different from the second fixed ON periods T2 of the other phases. Therefore, heat generation of the second semiconductor switching element of the phase having the second fixed ON period longer than the second fixed ON period T2 of the other phase can be suppressed.
  • the first fixed ON period T1 is different from the first fixed ON periods T1 of other phases
  • the second fixed ON period T2 is different from that of the other phase. It is different from the second on-fixed period T2 of the phase. Therefore, by simultaneously suppressing the heat generation of the first semiconductor switching element of a certain phase and the heat generation of the second semiconductor switching element of a certain phase, temperature rise of the power converter (inverter) can be suppressed and reliability can be improved.
  • the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase may have heat-generating components in their vicinity, or may be arranged in positions with poor heat dissipation efficiency.
  • the switching heat generation of these two elements can be suppressed using the method of Waveform Example 1 to prevent the temperature of these two elements from rising excessively and improve the reliability of the power converter (inverter). can be enhanced.
  • waveform example 1 the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un can be suppressed at the same time.
  • the V-phase second semiconductor switching element Vn and the W Heat generation with the second semiconductor switching element Wn of the phase can also be suppressed at the same time. Therefore, when the temperature of the U phase is most likely to rise and the temperature of the second semiconductor switching elements of the other phases is likely to rise next, overheating of these elements is prevented to improve reliability.
  • the first fixed ON period of any one phase is longer than the first fixed ON period of the other phase
  • the second fixed ON period of any one phase is longer than the second fixed ON period of the other phase. long. Therefore, when the temperature of a specific phase becomes a problem due to a problem in the cooling water passage or the like, the heat generation of that phase can be suppressed, thereby increasing the reliability of the inverter.
  • a stall occurs and current continuously flows through the first semiconductor switching element of a certain phase and the second semiconductor switching element of another phase and the temperature rises, this operation is performed when exiting the stall and starting operation. By doing so, it is possible to suppress the heat generation of the semiconductor switching elements whose temperature has risen under the stall condition, and to quickly lower the temperature, thereby increasing the reliability of the inverter.
  • FIG. 4 is a table showing the relationship between waveform examples and switching loss.
  • UH represents the switching loss of the U-phase first semiconductor switching element Up.
  • UL represents the switching loss of the U-phase second semiconductor switching element Un.
  • VH represents the switching loss of the V-phase first semiconductor switching element Vp.
  • VL represents the switching loss of the V-phase second semiconductor switching element Vn.
  • WH represents the switching loss of the W-phase first semiconductor switching element Wp.
  • WL represents the switching loss of the W-phase second semiconductor switching element Wn.
  • waveform examples 1 to 12 are waveform examples capable of protecting the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un.
  • a waveform capable of protecting a first semiconductor switching element (eg Up) of a certain phase (eg U phase) and a second semiconductor switching element (eg Un) of the same phase may be referred to as a UH_UL protection waveform. .
  • FIG. 5A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 5B is a diagram showing switching losses.
  • waveform example 2 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 0 degree to 180 degrees.
  • waveform example 2 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 180 degrees to 360 degrees.
  • the high-side-on application period T3 is from 0 electrical angle to 180 electrical degrees.
  • the low-side-on application period T4 occurs at an electrical angle of 180 degrees to 360 degrees.
  • the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w.
  • the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees.
  • the first fixed ON period T1v is between 150 electrical degrees and 180 electrical degrees.
  • the first ON fixed period T1w is from an electrical angle of 0 degree to an electrical angle of 30 degrees.
  • the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
  • the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
  • the second fixed ON period T2v is from 330 electrical degrees to 360 electrical degrees.
  • the second fixed ON period T2w is between 180 electrical degrees and 210 electrical degrees.
  • the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 2, the first fixed ON period T1u is 120 degrees, while the first fixed ON period T1v and the first fixed ON period T1w are 30 degrees. That is, in Waveform Example 2, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 5B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
  • the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w.
  • the second fixed ON period T2u is 120 degrees, while the second fixed ON period T2v and the second fixed ON period T2w are 30 degrees. That is, in Waveform Example 2, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 5B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
  • waveform example 2 as well as in waveform example 1, the heat generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved.
  • the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un can be suppressed at the same time.
  • waveform example 2 as shown in FIG. 5B, the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
  • Waveform example 2 can be substituted with waveform example 9 (FIG. 12) described later, which has a higher effect of suppressing heat generation.
  • FIG. 6A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 6B is a diagram showing switching losses.
  • waveform example 3 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 0 to 210 electrical degrees and at an electrical angle of 330 to 360 electrical degrees.
  • waveform example 3 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 210 degrees to 330 degrees.
  • the high-side-on application period T3 occurs at an electrical angle of 0 to 210 electrical degrees and at an electrical angle of 330 to 360 electrical degrees.
  • the low-side-on application period is T4 at an electrical angle of 210 degrees to 330 electrical degrees.
  • the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w.
  • the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees.
  • the first fixed ON period T1v is between an electrical angle of 150 degrees and an electrical angle of 210 degrees.
  • the first fixed ON period T1w is from an electrical angle of 0 degrees to an electrical angle of 30 degrees and from an electrical angle of 330 degrees to an electrical angle of 360 degrees.
  • the second fixed ON period T2 includes the second fixed ON period T2u.
  • the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
  • the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 3, the first fixed ON period T1u is 120 degrees, while the first fixed ON period T1v and the first fixed ON period T1w are 60 degrees. That is, in Waveform Example 3, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 6B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
  • the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in Waveform Example 3, the second fixed ON period T2u is 120 degrees, whereas the second fixed ON period T2v and the second fixed ON period T2w are absent. That is, in Waveform Example 3, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 6B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
  • Waveform Example 3 As described above with reference to FIGS. 6A and 6B , in Waveform Example 3, as in Waveform Example 1, the heat generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 3, the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un can be suppressed at the same time.
  • Waveform Example 3 As shown in FIG. 6B, the heat generation of the V-phase first semiconductor switching element Vp and the W-phase first semiconductor switching element Wp can be suppressed at the same time.
  • FIG. 7A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 7B is a diagram showing switching losses.
  • waveform example 4 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 30 degrees to 180 degrees.
  • waveform example 4 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 to 30 degrees and at an electrical angle of 180 to 360 degrees.
  • the high-side-on application period T3 is at an electrical angle of 30 degrees to 180 degrees.
  • the low-side-on application period T4 occurs at an electrical angle of 0 to 30 electrical degrees and at an electrical angle of 180 to 360 electrical degrees.
  • the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v.
  • the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees.
  • the first fixed ON period T1v is between 150 electrical degrees and 180 electrical degrees.
  • the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
  • the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
  • the second fixed ON period T2v is from an electrical angle of 0 degree to an electrical angle of 30 degrees and from an electrical angle of 330 degrees to an electrical angle of 360 degrees.
  • the second fixed ON period T2w is between 180 electrical degrees and 210 electrical degrees.
  • the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 4, the first fixed ON period T1u is 120 degrees, the first fixed ON period T1v is 30 degrees, and there is no first fixed ON period T1w. That is, in Waveform Example 4, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 7B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
  • the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w.
  • the second fixed ON period T2u is 120 degrees
  • the second fixed ON period T2v is 60 degrees
  • the second fixed ON period T2w is 30 degrees. That is, in Waveform Example 4, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 7B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
  • Waveform Example 4 As described above with reference to FIGS. 7A and 7B, in Waveform Example 4, as in Waveform Example 1, the heat generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 4, the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un can be suppressed at the same time.
  • waveform example 4 as shown in FIG. 7B, the heat generated by the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
  • Waveform example 4 can be substituted with waveform example 6 (FIG. 9) described later, which has a higher effect of suppressing heat generation.
  • FIG. 8A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 8B is a diagram showing switching losses.
  • waveform example 5 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 30 degrees to 210 degrees.
  • waveform example 5 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 to 30 electrical degrees and at an electrical angle of 210 to 360 electrical degrees.
  • the high-side-on application period T3 is at an electrical angle of 30 degrees to 210 degrees.
  • the low-side-on application period T4 occurs at an electrical angle of 0 to 30 electrical degrees and at an electrical angle of 210 to 360 electrical degrees.
  • the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v.
  • the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees.
  • the first fixed ON period T1v is between an electrical angle of 150 degrees and an electrical angle of 210 degrees.
  • the second fixed ON period T2 includes a second fixed ON period T2u and a second fixed ON period T2v.
  • the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
  • the second fixed ON period T2v is from 0 electrical angle to 30 electrical degrees and from 330 electrical degrees to 360 electrical degrees.
  • the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 5, the first fixed ON period T1u is 120 degrees, the first fixed ON period T1v is 60 degrees, and there is no first fixed ON period T1w. That is, in Waveform Example 5, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 8B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
  • the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w.
  • the second fixed ON period T2u is 120 degrees
  • the second fixed ON period T2v is 60 degrees
  • Waveform Example 5 As described above with reference to FIGS. 8A and 8B, in Waveform Example 5 as well as in Waveform Example 1, the heat generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved.
  • the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un can be suppressed at the same time.
  • FIG. 9A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 9B is a diagram showing switching losses.
  • waveform example 6 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 30 degrees to 150 degrees and at an electrical angle of 180 degrees to 210 degrees.
  • the output of any one phase is fixed to 0 at an electrical angle of 0 to 30 electrical degrees, 150 to 180 electrical degrees, and 210 to 360 electrical degrees.
  • the high-side-on application period T3 occurs at an electrical angle of 30 degrees to 150 degrees and at an electrical angle of 180 degrees to 210 degrees.
  • the low side-on application period T4 occurs at an electrical angle of 0 to 30 electrical degrees, 150 to 180 electrical degrees, and 210 to 360 electrical degrees.
  • the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v.
  • the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees.
  • the first fixed ON period T1v is between an electrical angle of 180 degrees and an electrical angle of 210 degrees.
  • the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
  • the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
  • the second fixed ON period T2v is between an electrical angle of 330 degrees and an electrical angle of 360 degrees and between an electrical angle of 0 degrees and an electrical angle of 30 degrees.
  • the second fixed ON period T2w is between 150 electrical degrees and 180 electrical degrees.
  • the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 6, the first fixed ON period T1u is 120 degrees, the first fixed ON period T1v is 30 degrees, and there is no first fixed ON period T1w. That is, in Waveform Example 6, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 9B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
  • the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w.
  • the second fixed ON period T2u is 120 degrees
  • the second fixed ON period T2v is 60 degrees
  • the second fixed ON period T2w is 30 degrees. That is, in Waveform Example 6, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 9B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
  • Waveform Example 6 As described above with reference to FIGS. 9A and 9B, in Waveform Example 6, as in Waveform Example 1, the heat generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 6, the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un can be suppressed at the same time.
  • FIG. 10A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 10B is a diagram showing switching losses.
  • waveform example 7 is a waveform in which the output of any one phase is fixed to 1 in the electrical angle of 0 to 150 electrical degrees and in the electrical angle of 180 to 210 electrical degrees.
  • waveform example 7 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 150 degrees to 180 degrees and at an electrical angle of 210 degrees to 360 degrees.
  • the high-side-on application period T3 occurs at an electrical angle of 0 to 150 electrical degrees and at an electrical angle of 180 to 210 electrical degrees.
  • the low side-on application period T4 occurs at an electrical angle of 150 degrees to 180 degrees and at an electrical angle of 210 degrees to 360 degrees.
  • the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w.
  • the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees.
  • the first fixed ON period T1v is between an electrical angle of 180 degrees and an electrical angle of 210 degrees.
  • the first ON fixed period T1w is from 0 electrical angle to 30 electrical degrees.
  • the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
  • the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
  • the second fixed ON period T2v is between 330 electrical degrees and 360 electrical degrees.
  • the second fixed ON period T2w is between 150 electrical degrees and 180 electrical degrees.
  • the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 7, the first fixed ON period T1u is 120 degrees, while the first fixed ON period T1v and the first fixed ON period T1w are 30 degrees. That is, in Waveform Example 7, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 10B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
  • the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w.
  • the second fixed ON period T2u is 120 degrees, while the second fixed ON period T2v and the second fixed ON period T2w are 30 degrees. That is, in Waveform Example 7, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 10B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
  • Waveform Example 7 As described above with reference to FIGS. 10A and 10B , in Waveform Example 7, as in Waveform Example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 7, the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un can be suppressed at the same time.
  • waveform example 7 as shown in FIG. 10B, the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
  • Waveform example 7 can be substituted with waveform example 9 (FIG. 12), which will be described later and has a higher effect of suppressing heat generation.
  • FIG. 11A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 11B is a diagram showing switching loss.
  • Waveform Example 8 the output voltage of any one phase is fixed to 1 in a certain electrical angle section according to the electrical angle, and the output voltage of any one phase is fixed to 1 in another electrical angle section. is fixed to 0. Specifically, in waveform example 8, the output of any one phase is fixed to 1 at an electrical angle of 0 to 150 degrees, from 180 to 210 electrical degrees, and from 330 to 360 electrical degrees. waveform. Waveform example 8 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 150 degrees to 180 degrees and at an electrical angle of 210 degrees to 330 degrees.
  • the high side-on application period T3 is at the electrical angle of 0 to 150 electrical degrees, the electrical angle of 180 to 210 electrical degrees, and the electrical angle of 330 to 360 electrical degrees. Further, in Waveform Example 8, the low side-on application period T4 occurs at an electrical angle of 150 degrees to 180 degrees and at an electrical angle of 210 degrees to 330 degrees.
  • the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w.
  • the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees.
  • the first fixed ON period T1v is between an electrical angle of 180 degrees and an electrical angle of 210 degrees.
  • the first fixed ON period T1w is from an electrical angle of 0 degrees to an electrical angle of 30 degrees and from an electrical angle of 330 degrees to an electrical angle of 360 degrees.
  • the second fixed ON period T2 includes a second fixed ON period T2u and a second fixed ON period T2w.
  • the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
  • the second fixed ON period T2w is between 150 electrical degrees and 180 electrical degrees.
  • the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 8, the first fixed ON period T1u is 120 degrees, the first fixed ON period T1v is 30 degrees, and the first fixed ON period T1w is 60 degrees. That is, in Waveform Example 8, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 11B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
  • the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w.
  • the second fixed ON period T2u is 120 degrees
  • the second fixed ON period T2v is absent and the second fixed ON period T2w is 30 degrees. That is, in Waveform Example 8, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 11B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
  • Waveform Example 8 As described above with reference to FIGS. 11A and 11B, in Waveform Example 8, as in Waveform Example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 8, the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un can be suppressed at the same time.
  • waveform example 8 as shown in FIG. 11B, the heat generated by the V-phase first semiconductor switching element Vp, the W-phase first semiconductor switching element Wp, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
  • FIG. 12A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 12B is a diagram showing switching losses.
  • waveform example 9 the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, in waveform example 9, the output of any one phase is fixed to 1 at an electrical angle of 30 degrees to 150 degrees, from 180 degrees to 210 degrees, and from 330 degrees to 360 degrees. waveform. Further, waveform example 9 corresponds to an electrical angle of 0 degree to an electrical angle of 30 degrees, an electrical angle of 150 degrees to an electrical angle of 180 degrees, and an electrical angle of 210 degrees to an electrical angle of 330 degrees.
  • the electrical angle of 180 degrees to 210 degrees, and the electrical angle of 330 degrees to 360 degrees are the high side-on application period T3. Further, in waveform example 9, the low side-on application period T4 occurs at an electrical angle of 0 to 30 electrical degrees, 150 to 180 electrical degrees, and 210 to 330 electrical degrees.
  • the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w.
  • the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees.
  • the first fixed ON period T1v is between an electrical angle of 180 degrees and an electrical angle of 210 degrees.
  • the first fixed ON period T1w is from 330 electrical degrees to 360 electrical degrees.
  • the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
  • the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
  • the second fixed ON period T2v is from an electrical angle of 0 degrees to an electrical angle of 30 degrees.
  • the second fixed ON period T2w is between 150 electrical degrees and 180 electrical degrees.
  • the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 9, the first fixed ON period T1u is 120 degrees, while the first fixed ON period T1v and the first fixed ON period T1w are 30 degrees. That is, in Waveform Example 9, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 12B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
  • the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w.
  • the second fixed ON period T2u is 120 degrees, while the second fixed ON period T2v and the second fixed ON period T2w are 30 degrees. That is, in Waveform Example 9, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 12B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
  • Waveform Example 9 As described above with reference to FIGS. 12A and 12B, in Waveform Example 9, as in Waveform Example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In the waveform example 9, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un.
  • the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
  • FIG. 13A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 13B is a diagram showing switching losses.
  • waveform example 10 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 0 to 150 electrical degrees and at an electrical angle of 330 to 360 electrical degrees.
  • waveform example 10 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 150 degrees to 330 degrees.
  • the high-side-on application period T3 occurs at an electrical angle of 0 to 150 electrical degrees and at an electrical angle of 330 to 360 electrical degrees.
  • the low-side-on application period T4 occurs at an electrical angle of 150 degrees to 330 electrical degrees.
  • the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1w.
  • the first ON fixed period T1u is from 30 electrical degrees to 150 electrical degrees.
  • the first fixed ON period T1w is from an electrical angle of 0 degrees to an electrical angle of 30 degrees and from an electrical angle of 330 degrees to an electrical angle of 360 degrees.
  • the second fixed ON period T2 includes a second fixed ON period T2u and a second fixed ON period T2w.
  • the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
  • the second fixed ON period T2w is between 150 electrical degrees and 210 electrical degrees.
  • the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 10, the first fixed ON period T1u is 120 degrees, whereas the first fixed ON period T1v is absent and the first fixed ON period T1w is 60 degrees. That is, in waveform example 10, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 13B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
  • the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w.
  • the second fixed ON period T2u is 120 degrees, while the second fixed ON period T2v is absent and the second fixed ON period T2w is 60 degrees. That is, in waveform example 10, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 13B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
  • waveform example 10 As described above with reference to FIGS. 13A and 13B, in waveform example 10 as well as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved.
  • waveform example 10 it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un.
  • waveform example 10 as shown in FIG. 13B, the heat generation of the W-phase first semiconductor switching element Wp and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
  • FIG. 14A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 14B is a diagram showing switching losses.
  • waveform example 11 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 30 to 210 electrical degrees and at an electrical angle of 330 to 360 electrical degrees.
  • waveform example 11 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 to 30 degrees and at an electrical angle of 210 to 330 degrees.
  • the high side-on application period T3 occurs at an electrical angle of 30 to 210 electrical degrees and at an electrical angle of 330 to 360 electrical degrees.
  • the low side-on application period T4 occurs at an electrical angle of 0 to 30 electrical degrees and at an electrical angle of 210 to 330 electrical degrees.
  • the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w.
  • the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees.
  • the first fixed ON period T1v is between 150 electrical degrees and 210 electrical degrees.
  • the first fixed ON period T1w is from 330 electrical degrees to 360 electrical degrees.
  • the second fixed ON period T2 includes a second fixed ON period T2u and a second fixed ON period T2v.
  • the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
  • the second fixed ON period T2v is from 0 electrical angle to 30 electrical degrees.
  • the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 11, the first fixed ON period T1u is 120 degrees, the first fixed ON period T1v is 60 degrees, and the first fixed ON period T1w is 30 degrees. That is, in waveform example 11, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 14B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
  • the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w.
  • the second fixed ON period T2u is 120 degrees
  • the second fixed ON period T2v is 30 degrees
  • waveform example 11 As described above with reference to FIGS. 14A and 14B, in waveform example 11, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 11, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un.
  • waveform example 11 as shown in FIG. 14B, the heat generated by the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, and the W-phase first semiconductor switching element Wp can be suppressed at the same time.
  • FIG. 15A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 15B is a diagram showing switching losses.
  • waveform example 12 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 30 degrees to 150 degrees and at an electrical angle of 330 degrees to 360 degrees.
  • waveform example 12 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 to 30 electrical degrees and at an electrical angle of 150 to 330 electrical degrees.
  • the high side-on application period T3 occurs at an electrical angle of 30 degrees to 150 degrees and at an electrical angle of 330 degrees to 360 degrees.
  • the low side-on application period T4 occurs at an electrical angle of 0 to 30 electrical degrees and at an electrical angle of 150 to 330 electrical degrees.
  • the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1w.
  • the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees.
  • the first fixed ON period T1w is from 330 electrical degrees to 360 electrical degrees.
  • the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
  • the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
  • the second fixed ON period T2v is from 0 electrical angle to 30 electrical degrees.
  • the second fixed ON period T2w is from 150 electrical degrees to 210 electrical degrees.
  • the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 12, the first fixed ON period T1u is 120 degrees, whereas the first fixed ON period T1v is absent and the first fixed ON period T1w is 30 degrees. That is, in waveform example 12, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 15B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
  • the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w.
  • the second fixed ON period T2u is 120 degrees
  • the second fixed ON period T2v is 30 degrees
  • the second fixed ON period T2w is 60 degrees. That is, in waveform example 12, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 15B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
  • waveform example 12 As described above with reference to FIGS. 15A and 15B , in waveform example 12, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 12, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un.
  • waveform example 12 as shown in FIG. 15B, the heat generated by the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
  • FIG. 16 is a diagram showing switching loss.
  • the switching loss is 0.13. That is, in the U-phase, if the high-side first fixed ON period T1u is 120 degrees and the low-side second fixed ON period T2u is 120 degrees, the switching loss is 0.13.
  • the switching loss is 0.22. That is, in the U-phase, if the high-side first fixed ON period T1u is 120 degrees and the low-side second fixed ON period T2u is 100 degrees, the switching loss is 0.22.
  • the switching loss is 0.35. That is, in the U-phase, if the high-side first fixed ON period T1u is 80 degrees and the low-side second fixed ON period T2u is 100 degrees, the switching loss is 0.22.
  • the switching loss is 0.35. That is, in the U-phase, if the high-side first fixed ON period T1u is 80 degrees and the low-side second fixed ON period T2u is 80 degrees, the switching loss is 0.35.
  • the switching loss is 0.50. That is, in the U-phase, if the high-side first fixed ON period T1u is 60 degrees and the low-side second fixed ON period T2u is 60 degrees, the switching loss is 0.50.
  • both the first fixed ON period T1u and the second fixed ON period T2u are longer than ⁇ /3 (60 degrees) and 2 ⁇ /3 (120 degrees) or less. Preferably. More preferably, it is longer than 4 ⁇ /9 (80 degrees) and 2 ⁇ /3 (120 degrees) or less.
  • FIG. 17 is a diagram for explaining switching of the UH_UL protection waveform.
  • the waveforms of the output voltage and the switching loss are, from the left, (c) waveform example 3 (FIGS. 6A and 6B), (i) waveform example 9 (FIGS. 12A and 12B), (a) waveform example 1 (FIGS. 3A and 3B).
  • Waveform example 3 shown in the left diagram is a waveform example in which the first fixed ON period T1v and the first fixed ON period T1w are extended. In other words, this is a waveform example that emphasizes suppression of heat generation on the high side.
  • Waveform example 3 shown in the middle diagram is a waveform example in which the first fixed ON period T1v, the first fixed ON period T1w, the second fixed ON period T2v, and the second fixed ON period T2w are equalized. That is, it is a waveform example in which the first fixed ON period T1u and the period other than the first fixed ON period T1u are made uniform.
  • Waveform example 1 shown in the right figure is a waveform example in which the second fixed ON period T2v and the second fixed ON period T2w are extended. In other words, this is an example of a waveform that emphasizes suppression of heat generation on the low side.
  • the first fixed ON period T1v and the first fixed ON period T1w become longer as the diagram shifts to the left. Therefore, the switching losses of the V-phase first semiconductor switching element Vp (high side) and the W-phase first semiconductor switching element Wp (high side) decrease as the diagram shifts to the left.
  • the second fixed ON period T2v and the second fixed ON period T2w become longer as it shifts to the right figure. Therefore, the switching loss of the V-phase second semiconductor switching element Vn (low side) and the W-phase second semiconductor switching element Wn (low side) decreases as the diagram shifts to the left.
  • FIG. 16 is a diagram for explaining switching of the UH_UL protection waveform.
  • the waveform of the output voltage and the switching loss are, from left to right, (e) waveform example 5 (FIGS. 8A and 8B), (i) waveform example 9 (FIGS. 12A and 12B), (j) waveform example 10 (FIGS. 13A and 13B).
  • Waveform example 5 shown in the left diagram is a waveform example in which the first fixed ON period T1v and the second fixed ON period T2v are extended. In other words, this is an example of a waveform that emphasizes the V phase.
  • Waveform example 9 shown in the middle diagram is a waveform example in which the first fixed ON period T1v, the first fixed ON period T1w, the second fixed ON period T2v, and the second fixed ON period T2w are equalized. That is, it is a waveform example in which the first fixed ON period T1u and the period other than the first fixed ON period T1u are made uniform.
  • Waveform example 10 shown in the right figure is a waveform example in which the first fixed ON period T1w and the second fixed ON period T2w are extended. That is, it is an example of a waveform in which the W phase is emphasized.
  • the first fixed ON period T1v and the second fixed ON period T2v become longer as the diagram shifts to the left. Therefore, the switching losses of the V-phase first semiconductor switching element Vp (high side) and the V-phase second semiconductor switching element Vn (low side) decrease as the diagram shifts to the left.
  • the first fixed ON period T1w and the second fixed ON period T2w become longer as the figure shifts to the right. Therefore, the switching loss of the W-phase first semiconductor switching element Wp (high side) and the W-phase second semiconductor switching element Wn (low side) decreases as the drawing shifts to the right side.
  • FIG. 19 is a diagram showing switching loss.
  • FIG. 20 is a diagram for explaining switching of the UH_UL protection waveform.
  • the waveform diagram shown in FIG. 20 corresponds to (i) waveform example 9 (FIG. 12A).
  • Waveform example 1 corresponds to a waveform in which the second fixed ON period T2v and the second fixed ON period T2w are extended with respect to (i) waveform example 9. Therefore, the switching losses of the V-phase second semiconductor switching element Vn (VL) and the W-phase second semiconductor switching element Wn (WL) are reduced.
  • Waveform example 3 corresponds to a waveform in which the first fixed ON period T1v and the first fixed ON period T1w are extended with respect to (i) waveform example 9. Therefore, the switching losses of the V-phase first semiconductor switching element Vp (VH) and the W-phase first semiconductor switching element Wp (WH) are reduced.
  • Waveform example 5 corresponds to a waveform in which the first fixed ON period T1v and the second fixed ON period T2v are extended with respect to (i) waveform example 9. Therefore, the switching losses of the V-phase first semiconductor switching element Vp (VH) and the V-phase second semiconductor switching element Vn (VL) are reduced.
  • Waveform example 10 corresponds to a waveform in which the first fixed ON period T1w and the second fixed ON period T2w are extended with respect to (i) waveform example 9. Therefore, the switching losses of the W-phase first semiconductor switching element Wp (WH) and the W-phase second semiconductor switching element Wn (WL) are reduced.
  • Waveform example 6 corresponds to a waveform obtained by extending the second on-fixed period T2v from (i) waveform example 9. Therefore, the switching loss of the V-phase second semiconductor switching element Vn(VL) is reduced.
  • Waveform example 8 corresponds to a waveform obtained by extending the first fixed ON period T1w with respect to (i) waveform example 9. Therefore, the switching loss of the W-phase first semiconductor switching element Wp(WH) is reduced.
  • Waveform example 11 corresponds to a waveform obtained by extending the first fixed ON period T1v with respect to (i) waveform example 9. Therefore, the switching loss of the V-phase first semiconductor switching element Vp (VH) is reduced.
  • Waveform example 12 corresponds to a waveform obtained by extending the second on-fixed period T2w from (i) waveform example 9. Therefore, the switching loss of the W-phase second semiconductor switching element Wn(WL) is reduced.
  • FIG. 21 is a flow chart showing a protection waveform switching method.
  • Step S102 The signal generator 120 acquires the temperature T_UH, temperature T_UL, temperature T_VH, temperature T_VL, temperature T_WH, and temperature T_WH of each arm (semiconductor switching element).
  • a temperature T_UH indicates the temperature of the first semiconductor switching element Up.
  • a temperature T_UL indicates the temperature of the second semiconductor switching element Un.
  • a temperature T_VH indicates the temperature of the first semiconductor switching element Vp.
  • a temperature T_VL indicates the temperature of the second semiconductor switching element Vn.
  • a temperature T_WH indicates the temperature of the first semiconductor switching element Wp.
  • a temperature T_WL indicates the temperature of the second semiconductor switching element Wn.
  • the signal generation unit 120 sets the acquired temperature T_UH, temperature T_UL, temperature T_VH, temperature T_VL, temperature T_WH, and temperature T_WH to T_1, T_2, T_3, T_4, T_5, and T_6 in descending order of temperature. The process proceeds to step S104.
  • Step S104 The signal generator 120 determines whether or not the highest temperature upper arm (first semiconductor switching element) and the highest temperature lower arm (second semiconductor switching element) are in phase. When the signal generator 120 determines that the highest temperature upper arm (first semiconductor switching element) and the highest temperature lower arm (second semiconductor switching element) are not in phase (step S104: No), the process proceeds to step S108. proceed to When the signal generator 120 determines that the highest temperature upper arm (first semiconductor switching element) and the highest temperature lower arm (second semiconductor switching element) are in phase (step S104: Yes), the process proceeds to step Proceed to S106.
  • Step S106 The signal generator 120 modulates in a pattern that suppresses temperature rise in the upper and lower stages of the X phase.
  • the X phase is, for example, U phase, V phase or W phase. Processing ends. Detailed processing of step S106 will be described later with reference to FIGS.
  • Step S108 The signal generator 120 modulates in a pattern that suppresses temperature rise in the X-phase upper stage and the Y-phase lower stage.
  • Y-phase is, for example, U-phase, V-phase or W-phase. Processing ends. Detailed processing of step S108 will be described later with reference to FIGS.
  • FIG. 22 is a flow chart showing a protection waveform switching method.
  • 23 and 24 are diagrams showing a switching method of the protection waveform. 22 to 24 show the switching method of the protection waveform when the U phase is used as an example of the X phase.
  • Step S202 The signal generator 120 determines whether the temperatures T_3 to T_6 are equal to or lower than the threshold T_Thr1. When the signal generator 120 determines that the temperatures T_3 to T_6 are not equal to or lower than the threshold value T_Thr1 (step S202: No), the process proceeds to step S206. When the signal generator 120 determines that the temperatures T_3 to T_6 are equal to or lower than the threshold T_Thr1 (step S202: Yes), the process proceeds to step S204.
  • Step S204 The signal generator 120 modulates with four protection patterns. Specifically, the signal generator 120 performs modulation with (i) waveform example 9; Processing ends.
  • Step S206 The signal generator 120 determines whether the temperatures T_5 to T_6 are equal to or lower than the threshold T_Thr2. When the signal generator 120 determines that the temperatures T_5 to T_6 are not equal to or lower than the threshold value T_Thr2 (step S206: No), the process proceeds to step S210. When the signal generator 120 determines that the temperatures T_5 to T_6 are equal to or lower than the threshold T_Thr2 (step S206: Yes), the process proceeds to step S208.
  • Step S208 The signal generator 120 modulates between the three protection patterns and the four protection patterns. Modulation in between the 3 guard pattern and the 4 guard pattern will be described later with reference to FIG. Processing ends.
  • Step S210 The signal generator 120 determines whether the temperatures T_3 to T_5 are equal to or lower than the threshold T_Thr3. When the signal generator 120 determines that the temperatures T_3 to T_5 are not equal to or lower than the threshold value T_Thr3 (step S210: No), the process proceeds to step S214. When the signal generator 120 determines that the temperatures T_3 to T_5 are equal to or lower than the threshold T_Thr3 (step S210: Yes), the process proceeds to step S212.
  • Step S212 The signal generator 120 modulates with three protection patterns. Specifically, the signal generation unit 120 selects the arms (or (Semiconductor switching elements) are modulated with a pattern that can protect them. Processing ends.
  • Step S214 The signal generator 120 determines whether the temperatures T_4 to T_5 are equal to or lower than the threshold T_Thr4. When the signal generator 120 determines that the temperatures T_4 to T_5 are not equal to or lower than the threshold value T_Thr4 (step S214: No), the process proceeds to step S218. When the signal generator 120 determines that the temperatures T_4 to T_5 are equal to or lower than the threshold value T_Thr4 (step S214: Yes), the process proceeds to step S216.
  • Step S216 The signal generator 120 modulates between the two protection patterns and the three protection patterns. Modulation in between the 2 guard pattern and the 3 guard pattern will be described later with reference to FIG. Processing ends.
  • Step S218 The signal generator 120 modulates with two protection patterns. Specifically, the signal generator 120 generates (a) waveform example 1, (c) waveform example 3, (e) waveform example 5, (f) waveform example 6, (i) waveform example 9, and (j) waveform example 10. Of these, modulation is performed with a pattern that can protect arms (semiconductor switching elements) whose temperatures are T_3 and T_4. Processing ends.
  • step S208 shown in FIG. 22 will be described with reference to FIG. That is, a description will be given of the processing in the case of performing modulation between the three protection patterns and the four protection patterns.
  • the signal generation unit 120 determines the positions of the three arms (semiconductor switching elements) with the highest temperature, excluding UH (first semiconductor switching element Up) and UL (second semiconductor switching element Un).
  • upper three arms semiconductor switching elements with higher temperatures excluding UH (first semiconductor switching element Up) and UL (second semiconductor switching element Un)
  • the order of the temperatures of the top three arms does not matter.
  • the order of the temperatures of the upper three arms may be VH (first semiconductor switching element Vp), VL (second semiconductor switching element Vn), and WH (first semiconductor switching element Wp), or VH (first semiconductor switching element Wp).
  • the order of semiconductor switching element Vp), WH (first semiconductor switching element Wp) and VL (second semiconductor switching element Vn) is also acceptable.
  • the order of the temperatures of the top three arms is similarly irrelevant.
  • signal generation unit 120 determines that the upper three arms are VH (first semiconductor switching element Vp), VL (second semiconductor switching element Vn), and WL (second semiconductor switching element Wn), signal generation unit 120 modulates with (f) waveform example 6;
  • step S216 shown in FIG. 22 will be described with reference to FIG. In other words, a description will be given of processing in the case of performing modulation between the two protection patterns and the three protection patterns.
  • the signal generation unit 120 determines the positions of the upper two arms (semiconductor switching elements) with the highest temperature, excluding UH (first semiconductor switching element Up) and UL (second semiconductor switching element Un).
  • UH first semiconductor switching element Up
  • UL second semiconductor switching element Un
  • the order of the temperatures of the upper two arms does not matter.
  • the order of the temperatures of the upper two arms may be VL (second semiconductor switching element Vn) and WL (second semiconductor switching element Wn), or WL (second semiconductor switching element Wn) and VL (second semiconductor switching element Wn).
  • the order of the semiconductor switching elements Vn) may also be used.
  • the order of the temperatures of the top three arms is similarly irrelevant.
  • the signal generation unit 120 determines the position of the arm (semiconductor switching element) with the third highest temperature, excluding UH (first semiconductor switching element Up) and UL (second semiconductor switching element Un).
  • UH first semiconductor switching element Up
  • UL second semiconductor switching element Un
  • a signal When the positions of the upper two arms are VL (second semiconductor switching element Vn) and WL (second semiconductor switching element Vn), and the arm with the third highest temperature is WH (first semiconductor switching element Wp), a signal
  • the generation unit 120 determines that (a) in the waveform example 1, the pattern in which 330 degrees to 330+30 ⁇ (T_Thr4 ⁇ (T_4 ⁇ T_5))/T_Thr4 degrees is applied to the first fixed ON period, the signal generation unit 120 modulate. Processing ends.
  • a signal If the generating unit 120 determines, (e) in the waveform example 5, the pattern in which 330 degrees to 330+30 ⁇ (T_Thr4 ⁇ (T_4 ⁇ T_5))/T_Thr4 degrees is applied to the first fixed ON period, and the signal generating unit 120 modulate.
  • a signal If the generating unit 120 determines, (e) in the waveform example 5, the pattern in which 150 degrees to 150+30 ⁇ (T_Thr4 ⁇ (T_4 ⁇ T_5))/T_Thr4 degrees is applied to the second fixed ON period, and the signal generating unit 120 modulate.
  • a signal If the generating unit 120 determines, (i) in waveform example 9, the signal generating unit 120 modulates with a pattern in which 180 degrees to 180+30 ⁇ (T_Thr4 ⁇ (T_4 ⁇ T_5))/T_Thr4 degrees is applied to the second ON fixed period. I do.
  • a signal When the positions of the upper two arms are VL (second semiconductor switching element Vn) and WH (first semiconductor switching element Wp), and the arm with the third highest temperature is VH (first semiconductor switching element Vp), a signal
  • the generating unit 120 determines, (i) in the waveform example 9, the pattern in which 150 degrees to 150+30 ⁇ (T_Thr4 ⁇ (T_4 ⁇ T_5))/T_Thr4 degrees is applied to the first fixed ON period, and the signal generating unit 120 modulate.
  • the generation unit 120 determines, (j) in waveform example 10, the signal generation unit 120 modulates with a pattern in which 0 degrees to 0+30 ⁇ (T_Thr4 ⁇ (T_4 ⁇ T_5))/T_Thr4 degrees is applied to the second ON fixed period. I do.
  • the protection operation mode includes the first selective protection operation mode that protects the first semiconductor switching element and the second semiconductor switching element of one phase.
  • k is a natural number of 2n ⁇ 3 or less
  • first semiconductor switching elements or second semiconductor switching elements It includes a plurality of k protection modes of operation to protect the switching elements. Selection of k protection operation modes is performed based on the temperature information.
  • FIG. 25 is a table showing the relationship between waveform examples and switching loss.
  • UH represents the switching loss of the U-phase first semiconductor switching element Up.
  • UL represents the switching loss of the U-phase second semiconductor switching element Un.
  • VH represents the switching loss of the V-phase first semiconductor switching element Vp.
  • VL represents the switching loss of the V-phase second semiconductor switching element Vn.
  • WH represents the switching loss of the W-phase first semiconductor switching element Wp.
  • WL represents the switching loss of the W-phase second semiconductor switching element Wn.
  • UH is 0.32 and VL is 0.32.
  • VH is 0.32
  • VL is 0.32.
  • the waveform examples 13 to 29 are waveform examples capable of protecting the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn.
  • a waveform capable of protecting a first semiconductor switching element (eg Up) of a certain phase (eg U phase) and a second semiconductor switching element (eg Vn) of another phase (eg V phase) is referred to as a UH_VL protection waveform.
  • This waveform example corresponds to the case where the former first fixed ON period and the latter second fixed ON period are continuous.
  • FIG. 26A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 26B is a diagram showing switching losses.
  • waveform example 13 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 150 degrees.
  • waveform example 13 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 degrees and at an electrical angle of 150 to 360 degrees.
  • the high-side-on application period T3 is at an electrical angle of 60 degrees to 150 degrees.
  • the low side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees and at an electrical angle of 150 to 360 electrical degrees.
  • the first fixed ON period T1 includes the first fixed ON period T1u.
  • the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees.
  • the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
  • the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
  • the second fixed ON period T2v is from an electrical angle of 0 degrees to an electrical angle of 60 degrees and from an electrical angle of 330 degrees to an electrical angle of 360 degrees.
  • the second fixed ON period T2w is from 150 electrical degrees to 210 electrical degrees.
  • the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 13, the first fixed ON period T1u is 120 degrees, but there is no first fixed ON period T1v and no first fixed ON period T1w. That is, in waveform example 13, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 26B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
  • the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w.
  • the second fixed ON period T2v is 90 degrees
  • the second fixed ON period T2u is 120 degrees
  • the second fixed ON period T2w is 60 degrees. That is, in waveform example 13, the second fixed ON period T2v is longer than the second fixed ON period T2w. Therefore, as shown in FIG. 26B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than that of the W-phase.
  • waveform example 13 As described above with reference to FIGS. 26A and 26B , in waveform example 13, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 13, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn.
  • FIG. 27A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 27B is a diagram showing switching losses.
  • waveform example 14 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 180 degrees.
  • waveform example 14 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 degrees to 60 degrees and at an electrical angle of 180 degrees to 360 degrees.
  • the high-side-on application period T3 is at an electrical angle of 60 degrees to 180 degrees.
  • the low side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees and at an electrical angle of 180 to 360 electrical degrees.
  • the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v.
  • the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees.
  • the first fixed ON period T1v is between 150 electrical degrees and 180 electrical degrees.
  • the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
  • the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
  • the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees.
  • the second fixed ON period T2w is from 180 electrical degrees to 210 electrical degrees.
  • the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 14, the first fixed ON period T1u is 90 degrees, the first fixed ON period T1v is 30 degrees, and there is no first fixed ON period T1w. That is, in Waveform Example 14, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 27B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
  • the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w.
  • the second fixed ON period T2v is 90 degrees
  • the second fixed ON period T2u is 120 degrees
  • the second fixed ON period T2w is 30 degrees. That is, in waveform example 14, the second fixed ON period T2v is longer than the second fixed ON period T2w. Therefore, as shown in FIG. 27B, the switching loss of the V-phase second semiconductor switching element Un (L (low side)) is smaller than that of the W-phase.
  • waveform example 14 As described above with reference to FIGS. 27A and 27B, in waveform example 14, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved.
  • the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
  • FIG. 28A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 28B is a diagram showing switching losses.
  • waveform example 15 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 210 degrees.
  • waveform example 15 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 degrees and at an electrical angle of 210 to 360 degrees.
  • the high-side-on application period T3 is at an electrical angle of 60 degrees to 210 electrical degrees.
  • the low side-on application period is T4 at an electrical angle of 0 to 60 electrical degrees and at an electrical angle of 210 to 360 electrical degrees.
  • the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v.
  • the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees.
  • the first fixed ON period T1v is between 150 electrical degrees and 210 electrical degrees.
  • the second fixed ON period T2 includes a second fixed ON period T2u and a second fixed ON period T2v.
  • the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
  • the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees.
  • the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 15, the first fixed ON period T1u is 90 degrees, the first fixed ON period T1v is 60 degrees, and there is no first fixed ON period T1w. That is, in waveform example 15, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 28B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
  • the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w.
  • the second fixed ON period T2v is 90 degrees
  • the second fixed ON period T2u is 120 degrees
  • waveform example 15 As described above with reference to FIGS. 28A and 28B , in waveform example 15, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 15, the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
  • FIG. 29A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 29B is a diagram showing switching losses.
  • waveform example 16 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 240 degrees.
  • waveform example 16 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 degree to 60 electrical degrees and at an electrical angle of 240 degrees to 360 electrical degrees.
  • the high-side-on application period T3 is at an electrical angle of 60 degrees to 240 electrical degrees.
  • the low side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees and at an electrical angle of 240 to 360 electrical degrees.
  • the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v.
  • the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees.
  • the first fixed ON period T1v is from 150 electrical degrees to 240 electrical degrees.
  • the second fixed ON period T2 includes a second fixed ON period T2u and a second fixed ON period T2v.
  • the second fixed ON period T2u is from 240 electrical degrees to 330 electrical degrees.
  • the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees.
  • the first fixed ON period T1u differs from the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 16, the first fixed ON period T1u is 90 degrees, but there is no first fixed ON period T1w. That is, in waveform example 16, the first fixed ON period T1u is longer than the first fixed ON period T1w. In waveform example 16, the first fixed ON period T1u and the first fixed ON period T1v are equal. Therefore, as shown in FIG. 29B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than that of the W-phase.
  • the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in waveform example 16, the second fixed ON period T2v is 90 degrees, but there is no second fixed ON period T2w. That is, in waveform example 16, the second fixed ON period T2v is longer than the second fixed ON period T2w. In waveform example 16, the second fixed ON period T2u is equal to the second fixed ON period T2v. Therefore, as shown in FIG. 29B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than that of the W-phase.
  • waveform example 16 As described above with reference to FIGS. 29A and 29B , in waveform example 16, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 16, the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
  • FIG. 30A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 30B is a diagram showing switching losses.
  • waveform example 17 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 270 degrees.
  • waveform example 17 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 degree to 60 electrical degrees and at an electrical angle of 270 degrees to 360 electrical degrees.
  • the high-side-on application period T3 is at an electrical angle of 60 degrees to 270 electrical degrees.
  • the low-side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees and at an electrical angle of 270 to 360 electrical degrees.
  • the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v.
  • the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees.
  • the first fixed ON period T1v is from 150 electrical degrees to 270 electrical degrees.
  • the second fixed ON period T2 includes a second fixed ON period T2u and a second fixed ON period T2v.
  • the second fixed ON period T2u is from 270 electrical degrees to 330 electrical degrees.
  • the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees.
  • the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 17, the first fixed ON period T1u is 90 degrees, the first fixed ON period T1v is 120 degrees, and there is no first fixed ON period T1w. That is, in waveform example 17, the first fixed ON period T1u is longer than the first fixed ON period T1w. Therefore, as shown in FIG. 30B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than that of the W-phase.
  • the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w.
  • the second fixed ON period T2v is 90 degrees
  • the second fixed ON period T2u is 60 degrees
  • waveform example 17 As described above with reference to FIGS. 30A and 30B , in waveform example 17, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 17, the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
  • FIG. 31A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 31B is a diagram showing switching losses.
  • waveform example 18 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 300 degrees.
  • waveform example 18 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 electrical degrees and at an electrical angle of 300 to 360 electrical degrees.
  • the high-side-on application period T3 is at an electrical angle of 60 degrees to 300 electrical degrees.
  • the low side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees and at an electrical angle of 300 to 360 electrical degrees.
  • the first fixed ON period T1 includes the first fixed ON period T1u.
  • the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees.
  • the first fixed ON period T1v is from 150 electrical degrees to 270 electrical degrees.
  • the first fixed ON period T1w is from 270 electrical degrees to 300 electrical degrees.
  • the second fixed ON period T2 includes a second fixed ON period T2u and a second fixed ON period T2v.
  • the second fixed ON period T2u is between 300 electrical degrees and 330 electrical degrees.
  • the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees.
  • the first fixed ON period T1u is different from the first fixed ON period T1v and the first fixed ON period T1w.
  • the first fixed ON period T1u is 90 degrees
  • the first fixed ON period T1v is 120 degrees
  • the first fixed ON period T1w is 30 degrees. That is, in waveform example 18, the first fixed ON period T1u is longer than the first fixed ON period T1w. Therefore, as shown in FIG. 31B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than that of the W-phase.
  • the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w.
  • the second fixed ON period T2v is 90 degrees
  • the second fixed ON period T2u is 30 degrees
  • waveform example 18 As described above with reference to FIGS. 31A and 31B, in waveform example 18, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 18, the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
  • waveform example 18 as shown in FIG. 31B, the heat generated by the U-phase second semiconductor switching element Un, the V-phase first semiconductor switching element Vp, and the W-phase first semiconductor switching element Wp can be suppressed at the same time.
  • FIG. 32A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 32B is a diagram showing switching losses.
  • waveform example 19 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 330 degrees.
  • waveform example 19 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 electrical degrees and at an electrical angle of 330 to 360 electrical degrees.
  • the high-side-on application period T3 is at an electrical angle of 60 degrees to 330 electrical degrees.
  • the low side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees and at an electrical angle of 330 to 360 electrical degrees.
  • the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w.
  • the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees.
  • the first fixed ON period T1v is from 150 electrical degrees to 270 electrical degrees.
  • the first fixed ON period T1w is from 270 electrical degrees to 330 electrical degrees.
  • the second fixed ON period T2 includes the second fixed ON period T2v.
  • the second fixed ON period T2v is from 0 electrical angle to 60 electrical degrees and from 330 electrical degrees to 360 electrical degrees.
  • the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 19, the first fixed ON period T1u is 90 degrees, the first fixed ON period T1v is 120 degrees, and the first fixed ON period T1w is 60 degrees. That is, in waveform example 19, the first fixed ON period T1u is longer than the first fixed ON period T1w. Therefore, as shown in FIG. 32B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than that of the W-phase.
  • the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in Waveform Example 19, the second fixed ON period T2v is 90 degrees, whereas the second fixed ON period T2u and the second fixed ON period T2w are absent. That is, in Waveform Example 19, the second fixed ON period T2v is longer than the second fixed ON period T2u and the second fixed ON period T2w. Therefore, as shown in FIG. 32B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
  • waveform example 19 As described above with reference to FIGS. 32A and 32B , in waveform example 19, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 19, the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
  • FIG. 33A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 33B is a diagram showing switching losses.
  • waveform example 20 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 300 degrees to 330 degrees.
  • the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 electrical degrees, 150 to 300 electrical degrees, and 330 to 360 electrical degrees.
  • the high side-on application period T3 occurs at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 300 degrees to 330 degrees.
  • the low side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees, 150 to 300 electrical degrees, and 330 to 360 electrical degrees.
  • the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1w.
  • the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees.
  • the first fixed ON period T1w is between 300 electrical degrees and 330 electrical degrees.
  • the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
  • the second fixed ON period T2u is from 210 electrical degrees to 300 electrical degrees.
  • the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees.
  • the second fixed ON period T2w is from 150 electrical degrees to 210 electrical degrees.
  • the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 20, the first fixed ON period T1u is 90 degrees, but the first fixed ON period T1v is absent and the first fixed ON period T1w is 30 degrees. That is, in waveform example 20, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 33B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
  • the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w.
  • the second fixed ON period T2v is 90 degrees
  • the second fixed ON period T2u is 90 degrees
  • the second fixed ON period T2w is 60 degrees. That is, in waveform example 20, the second fixed ON period T2v is longer than the second fixed ON period T2w. Therefore, as shown in FIG. 33B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than that of the W-phase.
  • waveform example 20 As described above with reference to FIGS. 33A and 33B, in waveform example 20 as well as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved.
  • waveform example 20 it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn.
  • FIG. 34A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 34B is a diagram showing switching losses.
  • waveform example 21 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 270 degrees to 330 degrees.
  • the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 electrical degrees, 150 to 270 electrical degrees, and 330 to 360 electrical degrees.
  • the high side-on application period T3 occurs at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 270 degrees to 330 degrees.
  • the low side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees, 150 to 270 electrical degrees, and 330 to 360 electrical degrees.
  • the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1w.
  • the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees.
  • the first fixed ON period T1w is from 270 electrical degrees to 330 electrical degrees.
  • the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
  • the second fixed ON period T2u is from 210 electrical degrees to 270 electrical degrees.
  • the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees.
  • the second fixed ON period T2w is between 150 electrical degrees and 210 electrical degrees.
  • the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 21, the first fixed ON period T1u is 90 degrees, but the first fixed ON period T1v is absent and the first fixed ON period T1w is 60 degrees. That is, in waveform example 21, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 34B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
  • the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w.
  • the second fixed ON period T2v is 90 degrees
  • the second fixed ON period T2u is 60 degrees
  • the second fixed ON period T2w is 60 degrees. That is, in waveform example 21, the second fixed ON period T2v is longer than the second fixed ON period T2u and the second fixed ON period T2w. Therefore, as shown in FIG. 34B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
  • waveform example 21 As described above with reference to FIGS. 34A and 34B , in waveform example 21, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 21, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn.
  • FIG. 35A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 35B is a diagram showing switching losses.
  • waveform example 22 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 240 degrees to 330 degrees.
  • the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 electrical degrees, 150 to 240 electrical degrees, and 330 to 360 electrical degrees. waveform.
  • the high side-on application period T3 occurs at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 240 degrees to 330 degrees.
  • the low-side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees, 150 to 240 electrical degrees, and 330 to 360 electrical degrees.
  • the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w.
  • the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees.
  • the first fixed ON period T1v is between 240 electrical degrees and 270 electrical degrees.
  • the first fixed ON period T1w is from 270 electrical degrees to 330 electrical degrees.
  • the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
  • the second fixed ON period T2u is from 210 electrical degrees to 240 electrical degrees.
  • the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees.
  • the second fixed ON period T2w is between 150 electrical degrees and 210 electrical degrees.
  • the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 22, the first fixed ON period T1u is 90 degrees, the first fixed ON period T1v is 30 degrees, and the first fixed ON period T1w is 60 degrees. That is, in waveform example 22, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 35B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
  • the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w.
  • the second fixed ON period T2v is 90 degrees
  • the second fixed ON period T2u is 30 degrees
  • the second fixed ON period T2w is 60 degrees. That is, in waveform example 22, the second fixed ON period T2v is longer than the second fixed ON period T2u and the second fixed ON period T2w. Therefore, as shown in FIG. 35B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
  • waveform example 22 As described above with reference to FIGS. 35A and 35B , in waveform example 22, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 22, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn.
  • the U-phase second semiconductor switching element Un As shown in FIG. 35B, the V-phase first semiconductor switching element Vp, the W-phase first semiconductor switching element Wp, and the W-phase semiconductor switching element Wp Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
  • FIG. 36A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 36B is a diagram showing switching losses.
  • waveform example 23 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 210 degrees to 330 degrees.
  • the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 electrical degrees, 150 to 210 electrical degrees, and 330 to 360 electrical degrees. waveform.
  • the high side-on application period T3 occurs at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 210 degrees to 330 degrees.
  • the low side-on application period T4 is at the electrical angle of 0 to 60 electrical degrees, the electrical angle of 150 to 210 electrical degrees, and the electrical angle of 330 to 360 electrical degrees.
  • the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w.
  • the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees.
  • the first fixed ON period T1v is between 210 electrical degrees and 270 electrical degrees.
  • the first fixed ON period T1u is from 270 electrical degrees to 330 electrical degrees.
  • the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
  • the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees.
  • the second fixed ON period T2w is from 150 electrical degrees to 210 electrical degrees.
  • the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 23, the first fixed ON period T1u is 90 degrees, while the first fixed ON period T1v and the first fixed ON period T1w are 60 degrees. That is, in waveform example 23, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 36B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
  • the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in waveform example 23, the second fixed ON period T2v is 90 degrees, whereas the second fixed ON period T2u is absent and the second fixed ON period T2w is 60 degrees. That is, in waveform example 23, the second fixed ON period T2v is longer than the second fixed ON period T2w. Therefore, as shown in FIG. 36B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
  • waveform example 23 As described above with reference to FIGS. 36A and 36B, in waveform example 23, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 23, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn.
  • waveform example 23 as shown in FIG. 36B, the heat generated by the V-phase first semiconductor switching element Vp, the W-phase first semiconductor switching element Wp, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
  • FIG. 37A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 37B is a diagram showing switching losses.
  • waveform example 24 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 180 degrees to 330 degrees.
  • the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 electrical degrees, 150 to 180 electrical degrees, and 330 to 360 electrical degrees.
  • the high-side-on application period T3 is at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 180 degrees to 330 degrees.
  • the low side-on application period T4 is at an electrical angle of 0 to 60 electrical degrees, 150 to 180 electrical degrees, and 330 to 360 electrical degrees.
  • the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w.
  • the first ON fixed period T1u is from 60 electrical degrees to 150 electrical degrees.
  • the first fixed ON period T1v is from 180 degrees to 270 degrees in electrical angle.
  • the first fixed ON period T1w is from 270 electrical degrees to 330 electrical degrees.
  • the second fixed ON period T2 includes a second fixed ON period T2v and a second fixed ON period T2w.
  • the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees.
  • the second fixed ON period T2w is between 150 electrical degrees and 180 electrical degrees.
  • the first fixed ON period T1u differs from the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 24, the first fixed ON period T1u is 90 degrees, while the first fixed ON period T1w is 60 degrees. That is, in waveform example 24, the first fixed ON period T1u is longer than the first fixed ON period T1w. Note that the first fixed ON period T1u and the first fixed ON period T1v are the same. Therefore, as shown in FIG. 37B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than that of the W-phase.
  • the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in waveform example 24, the second fixed ON period T2v is 90 degrees, while the second fixed ON period T2w is 30 degrees. That is, in waveform example 24, the second fixed ON period T2v is longer than the second fixed ON period T2w. Therefore, as shown in FIG. 37B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than that of the W-phase.
  • waveform example 24 As described above with reference to FIGS. 37A and 37B, in waveform example 24, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved.
  • the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
  • waveform example 24 as shown in FIG. 37B, the heat generated by the V-phase first semiconductor switching element Vp, the W-phase first semiconductor switching element Wp, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
  • FIG. 38A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 38B is a diagram showing switching losses.
  • waveform example 25 the output voltage of any one phase is fixed to 1 in a certain electrical angle section, and the output voltage of any one phase is fixed to 1 in another electrical angle section, depending on the electrical angle. is fixed to 0. Specifically, in waveform example 25, the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 150 degrees, from 210 degrees to 240 degrees, and from 270 degrees to 330 degrees. waveform. In addition, waveform example 25 is any of the electrical angle of 0 to 60 electrical degrees, 150 to 210 electrical degrees, 240 to 270 electrical degrees, and 330 to 360 electrical degrees. It is a waveform in which the output of one phase is fixed to 0. In waveform example 25, the high-side-on application period T3 occurs at an electrical angle of 60 to 150 electrical degrees, 210 to 240 electrical degrees, and 270 to 330 electrical degrees. In addition, in waveform example 25, the low side This is the ON application period T4.
  • the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w.
  • the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees.
  • the first fixed ON period T1v is between 210 electrical degrees and 240 electrical degrees.
  • the first fixed ON period T1w is from 270 electrical degrees to 330 electrical degrees.
  • the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
  • the second fixed ON period T2u is from 240 electrical degrees to 270 electrical degrees.
  • the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees.
  • the second fixed ON period T2w is from 150 electrical degrees to 210 electrical degrees.
  • the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 25, the first fixed ON period T1u is 90 degrees, the first fixed ON period T1v is 30 degrees, and the first fixed ON period T1w is 60 degrees. That is, in waveform example 25, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 38B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
  • the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w.
  • the second fixed ON period T2v is 90 degrees
  • the second fixed ON period T2u is 30 degrees
  • the second fixed ON period T2w is 60 degrees. That is, in waveform example 25, the second fixed ON period T2v is longer than the second fixed ON period T2u and the second fixed ON period T2w. Therefore, as shown in FIG. 38B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
  • waveform example 25 As described above with reference to FIGS. 38A and 38B , in waveform example 25, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In the waveform example 25, the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
  • the U-phase second semiconductor switching element Un the V-phase first semiconductor switching element Vp, the W-phase first semiconductor switching element Wp, and the W-phase semiconductor switching element Wp Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
  • FIG. 39A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 39B is a diagram showing switching losses.
  • waveform example 26 the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, in waveform example 26, the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 150 degrees, from 195 degrees to 240 degrees, and from 285 degrees to 330 degrees. waveform. In addition, waveform example 26 is any of the electrical angles of 0 to 60 electrical degrees, 150 to 195 electrical degrees, 240 to 285 electrical degrees, and 330 to 360 electrical degrees. It is a waveform in which the output of one phase is fixed to 0. In waveform example 26, the high-side-on application period T3 is at an electrical angle of 60 to 150 electrical degrees, 195 to 240 electrical degrees, and 285 to 330 electrical degrees. Further, in waveform example 26, the low side This is the ON application period T4.
  • the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w.
  • the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees.
  • the first fixed ON period T1v is between an electrical angle of 195 degrees and an electrical angle of 240 degrees.
  • the first fixed ON period T1w is between an electrical angle of 285 degrees and an electrical angle of 330 degrees.
  • the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
  • the second fixed ON period T2u is from 240 electrical degrees to 285 electrical degrees.
  • the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees.
  • the second fixed ON period T2w is from 150 electrical degrees to 195 electrical degrees.
  • the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 26, the first fixed ON period T1u is 90 degrees, while the first fixed ON period T1v and the first fixed ON period T1w are 45 degrees. That is, in waveform example 26, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 39B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
  • the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w.
  • the second fixed ON period T2v is 90 degrees, while the second fixed ON period T2u and the second fixed ON period T2w are 45 degrees. That is, in waveform example 26, the second fixed ON period T2v is longer than the second fixed ON period T2u and the second fixed ON period T2w. Therefore, as shown in FIG. 39B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
  • waveform example 26 As described above with reference to FIGS. 39A and 39B, in waveform example 26, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved.
  • the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
  • the U-phase second semiconductor switching element Un the V-phase first semiconductor switching element Vp, the W-phase first semiconductor switching element Wp, and the W-phase Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
  • FIG. 40A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 40B is a diagram showing switching losses.
  • waveform example 27 the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, in waveform example 27, the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 150 degrees, from 180 degrees to 240 degrees, and from 300 degrees to 330 degrees. waveform. Further, waveform example 27 is any of the electrical angle of 0 to 60 electrical degrees, the electrical angle of 150 to 180 electrical degrees, the electrical angle of 240 to 300 electrical degrees, and the electrical angle of 330 to 360 electrical degrees. It is a waveform in which the output of one phase is fixed to 0. In waveform example 27, the high-side-on application period T3 occurs at an electrical angle of 60 to 150 electrical degrees, 180 to 240 electrical degrees, and 300 to 330 electrical degrees. Further, in waveform example 27, the low side This is the ON application period T4.
  • the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w.
  • the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees.
  • the first fixed ON period T1v is from 180 electrical degrees to 240 electrical degrees.
  • the first fixed ON period T1w is between 300 electrical degrees and 330 electrical degrees.
  • the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
  • the second fixed ON period T2u is from 240 electrical degrees to 300 electrical degrees.
  • the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees.
  • the second fixed ON period T2w is between 150 electrical degrees and 180 electrical degrees.
  • the first fixed ON period T1u is different from the first fixed ON period T1v and the first fixed ON period T1w.
  • the first fixed ON period T1u is 90 degrees
  • the first fixed ON period T1v is 60 degrees
  • the first fixed ON period T1w is 30 degrees. That is, in waveform example 27, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 40B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
  • the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w.
  • the second fixed ON period T2v is 90 degrees
  • the second fixed ON period T2u is 60 degrees
  • the second fixed ON period T2w is 30 degrees. That is, in waveform example 27, the second fixed ON period T2v is longer than the second fixed ON period T2u and the second fixed ON period T2w. Therefore, as shown in FIG. 40B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
  • waveform example 27 As described above with reference to FIGS. 40A and 40B, in waveform example 27, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 27, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn.
  • the U-phase second semiconductor switching element Un the V-phase first semiconductor switching element Vp, the W-phase first semiconductor switching element Wp, and the W-phase Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
  • FIG. 41A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 41B is a diagram showing switching losses.
  • waveform example 28 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 210 degrees to 270 degrees.
  • the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 electrical degrees, 150 to 210 electrical degrees, and 270 to 360 electrical degrees.
  • the high side-on application period T3 occurs at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 210 degrees to 270 degrees.
  • the low side-on application period T4 is at an electrical angle of 0 to 60 electrical degrees, 150 to 210 electrical degrees, and 270 to 360 electrical degrees.
  • the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v.
  • the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees.
  • the first fixed ON period T1v is between 210 electrical degrees and 270 electrical degrees.
  • the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
  • the second fixed ON period T2u is from 270 electrical degrees to 330 electrical degrees.
  • the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees.
  • the second fixed ON period T2w is from 150 electrical degrees to 210 electrical degrees.
  • the first fixed ON period T1u is different from the first fixed ON period T1v and the first fixed ON period T1w.
  • the first fixed ON period T1u is 90 degrees
  • the first fixed ON period T1v is 60 degrees
  • the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w.
  • the second fixed ON period T2v is 90 degrees, while the second fixed ON period T2u and the second fixed ON period T2w are 60 degrees. That is, in waveform example 28, the second fixed ON period T2v is longer than the second fixed ON period T2u and the second fixed ON period T2w. Therefore, as shown in FIG. 41B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
  • waveform example 28 As described above with reference to FIGS. 41A and 41B , in waveform example 28, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved.
  • the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
  • waveform example 28 as shown in FIG. 41B, the heat generated by the U-phase second semiconductor switching element Un, the V-phase first semiconductor switching element Vp, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
  • FIG. 42A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 42B is a diagram showing switching losses.
  • waveform example 29 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 210 degrees and at an electrical angle of 270 degrees to 330 degrees.
  • the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 electrical degrees, 210 to 270 electrical degrees, and 330 to 360 electrical degrees.
  • the high-side-on application period T3 occurs at an electrical angle of 60 degrees to 210 degrees and at an electrical angle of 270 degrees to 330 degrees.
  • the low side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees, 210 to 270 electrical degrees, and 330 to 360 electrical degrees.
  • the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w.
  • the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees.
  • the first fixed ON period T1v is between 150 electrical degrees and 210 electrical degrees.
  • the first fixed ON period T1w is from 270 electrical degrees to 330 electrical degrees.
  • the second fixed ON period T2 includes a second fixed ON period T2u and a second fixed ON period T2v.
  • the second fixed ON period T2u is from 210 electrical degrees to 270 electrical degrees.
  • the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees.
  • the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 29, the first fixed ON period T1u is 90 degrees, while the first fixed ON period T1v and the first fixed ON period T1w are 60 degrees. That is, in waveform example 29, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 42B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
  • the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w.
  • the second fixed ON period T2v is 90 degrees
  • the second fixed ON period T2u is 60 degrees
  • waveform example 29 As described above with reference to FIGS. 42A and 42B , in waveform example 29, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved.
  • the waveform example 29 it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn.
  • the first fixed ON period is longer than the first fixed ON period of the other phases.
  • the first fixed ON period of the phase having a longer ON period and the second fixed ON period of the phase having a longer second fixed ON period than the second fixed ON period of the other phase are both longer than ⁇ /n and 2 ⁇ /n or less be.
  • it is 1.5 ⁇ /n to 2 ⁇ /n.
  • heat generation can be effectively suppressed.
  • the lower limit may be slightly deviated from ⁇ /n.
  • the upper limit may deviate slightly from 2 ⁇ /n.
  • the second fixed ON period of the phase with the longer ON fixed period is both 2 ⁇ /n.
  • the first fixed ON period of the phase whose first fixed ON period is longer than the first fixed ON period of the other phase and the second fixed ON period of the phase whose second fixed ON period is longer than the second fixed ON period of the other phase ON fixed period is not continuous with each other.
  • the first fixed ON period of one phase and the second fixed ON period of the other phase are mutually different. Contiguous.
  • the U-phase first fixed ON period T1u and the V-phase second fixed ON period T2v are continuous with each other.
  • the sum of the first fixed ON period of one phase and the second fixed ON period of the other phase is 3 ⁇ /n.
  • the first fixed ON period T1u of the U phase is 90 degrees
  • the second fixed ON period T2v of the V phase is 90 degrees.
  • the sum with the on-fixed period T2v is 180 degrees (3 ⁇ /n). Note that the total may deviate slightly from 3 ⁇ /n.
  • the first fixed ON period of one phase and the second fixed ON period of the other phase are each 3 ⁇ /(2n).
  • the U-phase first fixed ON period T1u and the V-phase second fixed ON period T2v are 90 degrees (3 ⁇ /(2n)). Therefore, in waveform examples 13 to 29, when a current continuously flows through the first semiconductor switching element of a phase in which a stall occurs and the second semiconductor switching element of another phase and the temperature rises, the stall escapes. By performing this operation when starting the operation, heat generation of the semiconductor switching element whose temperature has risen under the stall can be suppressed, and the temperature can be quickly lowered, so that the reliability of the inverter is improved.
  • FIG. 43 is a diagram showing switching loss.
  • the second fixed ON period is applied at an electrical angle of 0 to 60 electrical degrees and from 330 to 360 electrical degrees
  • the first fixed period is applied at an electrical angle of 60 to 150 electrical degrees.
  • the ON fixed period is applied, the switching loss of the first semiconductor switching element Up (UH) is 0.32.
  • the switching loss of the second semiconductor switching element Vn(VL) is 0.32.
  • the fixed period on the high side is 90 degrees.
  • the switching loss of the first semiconductor switching element Up(UH) is 0.39.
  • the switching loss of the second semiconductor switching element Vn(VL) is 0.25.
  • the fixed period on the high side is 80 degrees.
  • the second fixed ON period When the second fixed ON period is applied at an electrical angle of 0 to 80 electrical degrees and from 330 to 360 electrical degrees, and the first fixed ON period is applied at an electrical angle of 80 to 150 electrical degrees.
  • the switching loss of the first semiconductor switching element Up (UH) is 0.47.
  • the switching loss of the second semiconductor switching element Vn(VL) is 0.18.
  • the fixed period on the high side is 70 degrees.
  • the switching loss of the first semiconductor switching element Up (UH) is 0.56.
  • the switching loss of the second semiconductor switching element Vn(VL) is 0.13.
  • the fixed period on the high side is 60 degrees.
  • both the first fixed ON period T1u and the second fixed ON period T2u are longer than ⁇ /3 (60 degrees) and 2 ⁇ /3 (120 degrees) or less. Preferably. More preferably, it is longer than 7 ⁇ /18 (70 degrees) and 2 ⁇ /3 (120 degrees) or less.
  • FIG. 44 is a diagram for explaining switching of the UH_VL protection waveform.
  • the waveform of the output voltage and the switching loss are, from the left, (n) waveform example 26 (FIGS. 39A and 39B), (o) waveform example 27 (FIGS. 40A and 40B), (d) waveform example 16 (FIGS. 29A and 29B).
  • Waveform example 26 shown in the left diagram is a waveform example in which the first fixed ON period T1v, the first fixed ON period T1w, the second fixed ON period T2u, and the second fixed ON period T2w are made equal.
  • this is an example of waveforms in which periods other than the first fixed ON period T1u and the second fixed ON period T2v are made uniform.
  • Waveform example 27 shown in the middle diagram is a waveform example in which the first fixed ON period T1v and the second fixed ON period T2u are extended. In other words, this is an example of waveforms in which the U-phase and V-phase are emphasized.
  • Waveform example 16 shown in the right figure is a waveform example in which the first fixed ON period T1v and the second fixed ON period T2u are further extended from (o) Waveform example 27. In other words, this is an example of waveforms in which the U-phase and V-phase are emphasized.
  • the first fixed ON period T1v and the second fixed ON period T2u become longer as the diagram shifts to the right. Therefore, the switching loss of the V-phase first semiconductor switching element Vp (high side) and the U-phase second semiconductor switching element Un (low side) decreases as the diagram shifts to the right.
  • FIG. 45 is a diagram for explaining switching of the UH_VL protection waveform.
  • the output voltage waveform and switching loss correspond to (n) waveform example 26 (FIGS. 39A and 39B) and (m) waveform example 25 (FIGS. 38A and 38B) in order from the left.
  • Waveform example 26 shown in the left diagram is a waveform example in which the first fixed ON period T1v, the first fixed ON period T1w, the second fixed ON period T2u, and the second fixed ON period T2w are made equal.
  • this is an example of waveforms in which periods other than the first fixed ON period T1u and the second fixed ON period T2v are made uniform.
  • Waveform example 25 shown in the right figure is a waveform example in which the first fixed ON period T1w and the second fixed ON period T2w are extended. That is, it is an example of a waveform in which the W phase is emphasized.
  • the first fixed ON period T1w and the second fixed ON period T2w become longer as the diagram shifts to the right. Therefore, the switching loss of the W-phase first semiconductor switching element Wp (high side) and the W-phase second semiconductor switching element Wn (low side) decreases as the drawing shifts to the right side.
  • FIG. 46 is a diagram for explaining switching of the UH_VL protection waveform.
  • the waveform of the output voltage and the switching loss are, from the left, (g) waveform example 19 (FIGS. 32A and 32B), (n) waveform example 26 (FIGS. 39A and 39B), (a) waveform example 13 (FIGS. 26A and 26B).
  • Waveform example 26 shown in the middle diagram is a waveform example in which the first fixed ON period T1v, the first fixed ON period T1w, the second fixed ON period T2v, and the second fixed ON period T2w are equalized. That is, it is a waveform example in which the first fixed ON period T1u and the period other than the first fixed ON period T1u are made uniform.
  • FIG. 47 is a flow chart showing a protection waveform switching method.
  • 48 and 49 are diagrams showing a method of switching guard waveforms. 47 to 49 show the switching method of the protection waveform when the U phase is used as an example of the X phase and the V phase is used as an example of the Y phase.
  • Step S502 The signal generator 120 determines whether the temperatures T_3 to T_6 are equal to or lower than the threshold T_Thr5. When the signal generator 120 determines that the temperatures T_3 to T_6 are not equal to or lower than the threshold value T_Thr5 (step S502: No), the process proceeds to step S506. When the signal generator 120 determines that the temperatures T_3 to T_6 are equal to or lower than the threshold value T_Thr5 (step S502: Yes), the process proceeds to step S504.
  • Step S504 The signal generator 120 modulates with four protection patterns. Specifically, the signal generator 120 performs modulation with (i) waveform example 21 . Processing ends.
  • Step S506 The signal generator 120 determines whether the temperatures T_5 to T_6 are equal to or lower than the threshold T_Thr6. When the signal generator 120 determines that the temperatures T_5 to T_6 are not equal to or lower than the threshold value T_Thr6 (step S506: No), the process proceeds to step S510. When the signal generator 120 determines that the temperatures T_5 to T_6 are equal to or lower than the threshold T_Thr6 (step S506: Yes), the process proceeds to step S508.
  • Step S508 The signal generator 120 modulates between the three protection patterns and the four protection patterns. Modulation in between the 3 guard pattern and the 4 guard pattern is described below with reference to FIG. Processing ends.
  • Step S510 The signal generator 120 determines whether the temperatures T_3 to T_5 are equal to or lower than the threshold T_Thr7. When the signal generator 120 determines that the temperatures T_3 to T_5 are not equal to or lower than the threshold value T_Thr7 (step S510: No), the process proceeds to step S514. When the signal generator 120 determines that the temperatures T_3 to T_5 are equal to or lower than the threshold T_Thr7 (step S510: Yes), the process proceeds to step S512.
  • Step S512 The signal generator 120 modulates with three protection patterns. Specifically, the signal generation unit 120 selects the arms (i) waveform example 21, (k) waveform example 23, (p) waveform example 28, and (q) waveform example 29 whose temperatures are T_3, T_4, and T_5. (Semiconductor switching elements) are modulated with a pattern that can protect them. Processing ends.
  • Step S514 The signal generator 120 determines whether the temperatures T_4 to T_5 are equal to or lower than the threshold T_Thr8. When the signal generator 120 determines that the temperatures T_4 to T_5 are not equal to or lower than the threshold T_Thr8 (step S514: No), the process proceeds to step S518. When the signal generator 120 determines that the temperatures T_4 to T_5 are equal to or lower than the threshold T_Thr8 (step S514: Yes), the process proceeds to step S516.
  • Step S516 The signal generator 120 modulates between the two protection patterns and the three protection patterns. Modulation in between two guard patterns and three guard patterns is described below with reference to FIG. Processing ends.
  • Step S518 The signal generator 120 modulates with two protection patterns. Specifically, the signal generator 120 generates (a) waveform example 13, (c) waveform example 15, (e) waveform example 17, (g) waveform example 19, (i) waveform example 21, and (p) waveform example 28. Of these, modulation is performed with a pattern that can protect arms (semiconductor switching elements) whose temperatures are T_3 and T_4. Processing ends.
  • step S508 shown in FIG. 47 will be described with reference to FIG. That is, a description will be given of the processing in the case of performing modulation between the three protection patterns and the four protection patterns.
  • the signal generation unit 120 determines the positions of the three arms (semiconductor switching elements) with the highest temperature, excluding UH (first semiconductor switching element Up) and VL (second semiconductor switching element Vn).
  • UH first semiconductor switching element Up
  • VL second semiconductor switching element Vn
  • upper three arms semiconductor switching elements with higher temperatures excluding UH (first semiconductor switching element Up) and UL (second semiconductor switching element Un)
  • the order of the temperatures of the top three arms does not matter.
  • the order of the temperatures of the upper three arms may be UL (second semiconductor switching element Un), WH (first semiconductor switching element Wp), and WL (second semiconductor switching element Wn), or UL (second semiconductor switching element Wn).
  • the order of semiconductor switching element Un), WL (second semiconductor switching element Wn), and WH (first semiconductor switching element Wp) is also acceptable.
  • the order of the temperatures of the top three arms is similarly irrelevant.
  • signal generation unit 120 determines that the three arms with the highest temperature are UL (second semiconductor switching element Un), VH (first semiconductor switching element Vp), and WL (second semiconductor switching element Wn), (p )
  • 195 degrees to 195 + 15 x (T_Thr6 - (T_5 - T_6))/T_Thr6 degrees is the first ON fixed period
  • 240 degrees to 240 + 45 x (T_Thr6 - (T_5 - T_6))/T_Thr6 is the second ON period.
  • the signal generation unit 120 performs modulation with a pattern in which 285 degrees to 285+45 ⁇ (T_Thr6-(T_5-T_6))/T_Thr6 degrees is applied to the first ON fixed period.
  • signal generation unit 120 determines that the three arms with the highest temperature are UL (second semiconductor switching element Un), VH (first semiconductor switching element Vp), and WH (first semiconductor switching element Wp), (q )
  • 150 degrees to 150 + 45 x (T_Thr6 - (T_5 - T_6)) / T_Thr6 is the second ON fixed period
  • 210 degrees to 210 + 30 x (T_Thr6 - (T_5 - T_6)) / T_Thr6 is the first ON
  • the signal generation unit 120 performs modulation with a pattern in which 270 degrees to 270+15 ⁇ (T_Thr6-(T_5-T_6))/T_Thr6 degrees is applied to the second ON fixed period.
  • step S516 shown in FIG. 47 will be described with reference to FIG. In other words, a description will be given of processing in the case of performing modulation between the two protection patterns and the three protection patterns.
  • process 1 when the positions of the two arms with the highest temperature and the priority of both are UL>WL and the arm with temperature T_5 is VH, process 1 is performed.
  • the signal generator 120 performs modulation with a pattern obtained by applying 210 degrees to 210+60 ⁇ (T_Thr8-(T_4-T_5))/T_Thr8 degrees in (a) waveform example 13 to the first ON fixed period.
  • process 1 When the position of the two arms with the highest temperature and the priority of both are UL>WL and the arm with the temperature of T_5 is WH, process 1 is performed.
  • the signal generator 120 performs modulation with a pattern obtained by applying 270 degrees to 270+60 ⁇ (T_Thr8-(T_4-T_5))/T_Thr8 degrees in (a) waveform example 13 to the first ON fixed period.
  • process 1 When the position of the two arms with the highest temperature and the priority of both are UL ⁇ WL and the arm with temperature T_5 is VH, process 1 is performed.
  • the signal generator 120 performs modulation with a pattern obtained by applying 210 degrees to 210+60 ⁇ (T_Thr8-(T_4-T_5))/T_Thr8 degrees in (a) waveform example 13 to the first ON fixed period.
  • process 2 If the position of the two arms with the highest temperature and the priority of both are UL ⁇ WL and the arm with temperature T_5 is WH, process 2 is performed.
  • the signal generator 120 performs modulation with a pattern obtained by applying 270 degrees to 270+60 ⁇ (T_Thr8 ⁇ (T_4 ⁇ T_5))/T_Thr8 degrees in (a) waveform example 13 to the first ON fixed period.
  • process 3 is performed.
  • (a) in waveform example 13 150 degrees to 150 + 60 x (T_Thr8 - (T_4 - T_5)) / T_Thr8 degrees, 270 degrees to 270 + 60 x (T_Thr8 - (T_4 - T_5)) / T_Thr8 degrees are the first
  • the signal generating section 120 performs modulation with the pattern applied to the ON-fixed period.
  • process 2 When the position of the two arms with the highest temperature and the priority of both are UL>WH and the arm with the temperature of T_5 is VL, process 2 is performed.
  • the signal generator 120 performs modulation with a pattern obtained by applying 270 degrees to 270+60 ⁇ (T_Thr8 ⁇ (T_4 ⁇ T_5))/T_Thr8 degrees in (a) waveform example 13 to the first ON fixed period.
  • process 4 When the position of the two arms with the highest temperature and the priority of both are UL>VH and the arm with temperature T_5 is WH, process 4 is performed.
  • the signal generator 120 modulates with a pattern obtained by applying 270 degrees to 270+60 ⁇ (T_Thr8-(T_4-T_5))/T_Thr8 degrees in (c) waveform example 15 to the first ON fixed period.
  • process 5 is performed.
  • (c) in waveform example 15 150 degrees to 150+60 ⁇ (T_Thr8 ⁇ (T_4 ⁇ T_5))/T_Thr8 degrees is the second ON fixed period, 210 degrees to 210+60 ⁇ (T_Thr8 ⁇ (T_4 ⁇ T_5))
  • the signal generator 120 performs modulation with a pattern in which /T_Thr8 is applied to the first fixed ON period.
  • process 6 is performed.
  • process 6 (e) in waveform example 17, 210 degrees to 210+60 ⁇ (T_Thr8 ⁇ (T_4 ⁇ T_5))/T_Thr8 degrees is the second ON fixed period, 270 degrees to 270+60 ⁇ (T_Thr8 ⁇ (T_4 ⁇ T_5))
  • the signal generator 120 performs modulation with a pattern in which /T_Thr8 is applied to the first fixed ON period.
  • process 7 When the position of the two arms with the highest temperature and the priority of both are UL ⁇ VH, and the arm with the temperature T_5 is WL, process 7 is performed.
  • the signal generator 120 modulates with a pattern obtained by applying 150 degrees to 150+60 ⁇ (T_Thr8-(T_4-T_5))/T_Thr8 degrees in (e) waveform example 17 to the second ON fixed period.
  • process 7 When the position of the two arms with the highest temperature and the priority of both are VH>WL, and the arm with the temperature of T_5 is WL, process 7 is performed.
  • the signal generator 120 modulates with a pattern obtained by applying 150 degrees to 150+60 ⁇ (T_Thr8-(T_4-T_5))/T_Thr8 degrees in (e) waveform example 17 to the second ON fixed period.
  • process 8 If the position of the two arms with the highest temperature and the priority of both are VH>WL, and if the arm whose temperature is T_5 is WH, then process 8 is performed.
  • process 8 (e) in waveform example 17, 150 degrees to 150+60 ⁇ (T_Thr8 ⁇ (T_4 ⁇ T_5))/T_Thr8 degrees is the second ON fixed period, 270 degrees to 270+60 ⁇ (T_Thr8 ⁇ (T_4 ⁇ T_5))
  • the signal generator 120 performs modulation with a pattern in which /T_Thr8 is applied to the first fixed ON period.
  • process 9 is performed.
  • the signal generator 120 modulates with a pattern obtained by applying 210 degrees to 210+60 ⁇ (T_Thr8-(T_4-T_5))/T_Thr8 degrees in (g) waveform example 19 to the second ON fixed period.
  • process 10 When the position of the two arms with the highest temperature and the priority of both are VH>WH and the arm with the temperature of T_5 is WL, process 10 is performed.
  • the signal generator 120 modulates with a pattern obtained by applying 150 degrees to 150+60 ⁇ (T_Thr8 ⁇ (T_4 ⁇ T_5))/T_Thr8 degrees in (g) waveform example 19 to the second ON fixed period.
  • process 9 If the position of the two arms with the highest temperature and the priority of both are VH ⁇ WH, and if the arm whose temperature is T_5 is UL, process 9 is performed.
  • the signal generator 120 modulates with a pattern obtained by applying 210 degrees to 210+60 ⁇ (T_Thr8-(T_4-T_5))/T_Thr8 degrees in (g) waveform example 19 to the second ON fixed period.
  • process 10 When the position of the two arms with the highest temperature and the priority of both are VH ⁇ WH, and the arm with the temperature of T_5 is WL, process 10 is performed.
  • the signal generator 120 modulates with a pattern obtained by applying 150 degrees to 150+60 ⁇ (T_Thr8 ⁇ (T_4 ⁇ T_5))/T_Thr8 degrees in (g) waveform example 19 to the second ON fixed period.
  • process 11 is performed.
  • the signal generator 120 performs modulation with a pattern in which 150 degrees to 150+60 ⁇ (T_Thr8-(T_4-T_5))/T_Thr8 degrees is applied to the first ON fixed period.
  • process 12 is performed.
  • the signal generator 120 (i) modulates the waveform example 21 .
  • process 12 If the position of the two arms with the highest temperature and the priority of both are WH>WL, and if the arm whose temperature is T_5 is UL, process 12 is performed. In process 12 , the signal generator 120 (i) modulates the waveform example 21 .
  • process 13 is performed.
  • the signal generator 120 performs modulation with a pattern in which 210 degrees to 210+60 ⁇ (T_Thr8-(T_4-T_5))/T_Thr8 degrees is applied to the first ON fixed period.
  • process 12 If the position of the two arms with the highest temperature and the priority of both are WH ⁇ WL, and if the arm whose temperature is T_5 is UL, process 12 is performed. In process 12 , the signal generator 120 (i) modulates the waveform example 21 .
  • process 14 is performed.
  • the signal generator 120 performs modulation with (p) waveform example 28 .
  • process 15 If the position of the two arms with the highest temperature and the priority of both are VH ⁇ WL, and if the arm whose temperature is T_5 is WH, process 15 is performed.
  • the signal generator 120 performs modulation with a pattern obtained by applying 270 degrees to 270+60 ⁇ (T_Thr8 ⁇ (T_4 ⁇ T_5))/T_Thr8 degrees in (p) waveform example 28 to the first ON fixed period.
  • the protection operation mode is the second selective protection operation that protects the first semiconductor switching element of one phase and the second semiconductor switching element of another phase. Including mode.
  • the first fixed ON period of one phase and the second fixed ON period of another phase are continuous.
  • k (k is 2n ⁇ A natural number of 3 or less) includes a plurality of k protection operation modes for protecting the first semiconductor switching elements or the second semiconductor switching elements, and the k protection operation modes are selected based on the temperature information. Therefore, when a current continuously flows through the first semiconductor switch of a certain phase and the second semiconductor switch of another phase due to a stall and the temperature rises, this operation must be performed when the stall is released and the operation is started.
  • the motor drive circuit 100 has a plurality of operation modes with different PWM duty waveforms, and has a function of switching between the plurality of operation modes during power conversion. have. At least one of the plurality of operating modes is a protected operating mode.
  • the protection operation mode has a plurality of protection operation patterns in which the ratio of at least one of the first fixed ON period and the second fixed ON period occupied by each phase differs during one cycle of the AC output. Therefore, various protection modes can be supported. For example, in addition to the normal mode (one type), it is possible to centrally protect each phase (multiple types).
  • a plurality of protection operation modes and a plurality of protection operation patterns are switched based on temperature information of at least one of the first semiconductor switching element and the second semiconductor switching element.
  • the temperature information is, for example, temperatures acquired by the six temperature sensors 20 of each semiconductor switching element.
  • the temperature sensor 20 may be arranged in the vicinity of some of the semiconductor switching elements, and the temperature of the semiconductor switching elements where the temperature sensor 20 is not arranged may be estimated by calculation.
  • the environmental temperature may be monitored and the temperature may be estimated using the values of a current sensor and a voltage sensor (not shown) installed in the motor drive circuit 100 .
  • the ambient temperature is, for example, the ambient temperature, the temperature of the substrate, and the temperature of the cooling water. Cooling water is a liquid for cooling motor drive circuit 100 .
  • Switching between a plurality of protection operation modes and a plurality of protection operation patterns is performed based on temperature information of at least one of the first semiconductor switching element and the second semiconductor switching element, whereby the semiconductor switching element with a high temperature is selectively switched. It is possible to suppress heat generation, promote heat dissipation, and improve the reliability of the power converter.
  • the protection operation mode has at least four types of protection operation patterns. Therefore, various protection modes can be supported. For example, in addition to the normal mode (one type), it is possible to centrally protect each phase (multiple types).
  • FIG. 50A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 50B is a diagram showing switching losses.
  • waveform example 30 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 90 degrees to 210 electrical degrees.
  • waveform example 30 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 to 90 degrees and at an electrical angle of 210 to 360 degrees.
  • the high-side-on application period T3 is at an electrical angle of 90 degrees to 210 electrical degrees.
  • the low side-on application period T4 occurs at an electrical angle of 0 to 90 electrical degrees and at an electrical angle of 210 to 360 electrical degrees.
  • the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v.
  • the first fixed ON period T1u is from 90 electrical degrees to 150 electrical degrees.
  • the first fixed ON period T1v is between an electrical angle of 150 degrees and an electrical angle of 210 degrees.
  • the second fixed ON period T2 includes a second fixed ON period T2u and a second fixed ON period T2v.
  • the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
  • the second fixed ON period T2v is from 0 to 90 electrical degrees and from 330 to 360 electrical degrees.
  • the first fixed ON period T1u differs from the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 30, the first fixed ON period T1u is 60 degrees, but there is no first fixed ON period T1w. That is, in waveform example 30, the first fixed ON period T1u is longer than the first fixed ON period T1w. The first fixed ON period T1v is the same as the first fixed ON period T1u. Therefore, as shown in FIG. 50B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than that of the W-phase.
  • the second fixed ON period T2u is different from the second fixed ON period T2u and the second fixed ON period T2w.
  • the second fixed ON period T2u is 120 degrees, but there is no second fixed ON period T2w. That is, in waveform example 30, the second fixed ON period T2u is longer than the second fixed ON period T2w.
  • the second fixed ON period T2v is the same as the second fixed ON period T2u. Therefore, as shown in FIG. 50B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than that of the W-phase.
  • waveform example 30 As described above with reference to FIGS. 50A and 50B , in waveform example 30, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 30, the heat generation of the U-phase second semiconductor switching element Un and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
  • the heat generation of the U-phase first semiconductor switching element Up and the V-phase first semiconductor switching element Vp can be suppressed at the same time.
  • FIG. 51A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 51B is a diagram showing switching loss.
  • the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0.
  • the waveform example 31 is a waveform in which the output of any one phase is fixed to 1 in the electrical angle of 45 degrees to 135 electrical degrees and in the electrical angle of 180 degrees to 210 electrical degrees.
  • the output of any one phase is fixed to 0 at an electrical angle of 0 to 45 electrical degrees, 135 to 180 electrical degrees, and 210 to 360 electrical degrees.
  • the high-side-on application period T3 occurs at an electrical angle of 45 degrees to 135 degrees and at an electrical angle of 180 degrees to 210 degrees.
  • the low side-on application period T4 occurs at an electrical angle of 0 to 45 electrical degrees, 135 to 180 electrical degrees, and 210 to 360 electrical degrees.
  • the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v.
  • the first fixed ON period T1u is from an electrical angle of 45 degrees to an electrical angle of 135 degrees.
  • the first fixed ON period T1v is from 180 degrees to 210 degrees in electrical angle.
  • the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
  • the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
  • the second fixed ON period T2v is from an electrical angle of 0 degrees to an electrical angle of 45 degrees and from an electrical angle of 330 degrees to an electrical angle of 360 degrees.
  • the second fixed ON period T2w is from 135 electrical degrees to 180 electrical degrees.
  • the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 31, the first fixed ON period T1u is 90 degrees, while the first fixed ON period T1v and the first fixed ON period T1w are 30 degrees. That is, in waveform example 31, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 51B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
  • the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w.
  • the second fixed ON period T2u is 120 degrees
  • the second fixed ON period T2v is 75 degrees
  • the second fixed ON period T2w is 45 degrees. That is, in waveform example 31, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 51B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
  • Waveform Example 31 As described above with reference to FIGS. 51A and 51B , in Waveform Example 31, as in Waveform Example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 31, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un.
  • waveform example 31 as shown in FIG. 51B, the heat generated by the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
  • FIG. 52A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 52B is a diagram showing switching losses.
  • waveform example 32 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 120 degrees and at an electrical angle of 150 degrees to 210 degrees.
  • the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 electrical degrees, 120 to 150 electrical degrees, and 210 to 360 electrical degrees.
  • the high-side-on application period T3 occurs at an electrical angle of 60 degrees to 120 degrees and at an electrical angle of 150 degrees to 210 degrees.
  • the low side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees, 120 to 150 electrical degrees, and 210 to 360 electrical degrees.
  • the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v.
  • the first fixed ON period T1u is from 60 electrical degrees to 120 electrical degrees.
  • the first fixed ON period T1v is between 150 electrical degrees and 210 electrical degrees.
  • the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
  • the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
  • the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees.
  • the second fixed ON period T2w is between 120 electrical degrees and 150 electrical degrees.
  • the first fixed ON period T1u differs from the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 32, the first fixed ON period T1u is 60 degrees, but there is no first fixed ON period T1w. That is, in waveform example 32, the first fixed ON period T1u is longer than the first fixed ON period T1w. The first fixed ON period T1v is the same as the first fixed ON period T1u. Therefore, as shown in FIG. 52B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than that of the W-phase.
  • the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w.
  • the second fixed ON period T2u is 120 degrees
  • the second fixed ON period T2v is 90 degrees
  • the second fixed ON period T2w is 30 degrees. That is, in waveform example 32, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 52B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
  • waveform example 32 As described above with reference to FIGS. 52A and 52B , in waveform example 32, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 32, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un.
  • waveform example 32 as shown in FIG. 52B, the heat generated by the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
  • FIG. 53A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 53B is a diagram showing switching losses.
  • the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0.
  • the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 120 degrees, from 180 degrees to 210 degrees, and from 330 degrees to 360 degrees.
  • the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 electrical degrees, 120 to 180 electrical degrees, and 210 to 330 electrical degrees. waveform.
  • the high side-on application period T3 is at an electrical angle of 60 to 120 electrical degrees, 180 to 210 electrical degrees, and 330 to 360 electrical degrees. Further, in waveform example 33, the low side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees, 120 to 180 electrical degrees, and 210 to 330 electrical degrees.
  • the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w.
  • the first fixed ON period T1u is from 60 electrical degrees to 120 electrical degrees.
  • the first fixed ON period T1v is from 180 degrees to 210 degrees in electrical angle.
  • the first fixed ON period T1w is from 330 electrical degrees to 360 electrical degrees.
  • the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
  • the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
  • the second fixed ON period T2v is from 0 electrical angle to 60 electrical degrees.
  • the second fixed ON period T2w is from 120 electrical degrees to 180 electrical degrees.
  • the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w.
  • the first fixed ON period T1u is 60 degrees, while the first fixed ON period T1v and the first fixed ON period T1w are 30 degrees. That is, in waveform example 33, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 53B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
  • the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w.
  • the second fixed ON period T2u is 120 degrees, while the second fixed ON period T2v and the second fixed ON period T2w are 60 degrees. That is, in waveform example 33, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 53B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
  • waveform example 33 As described above with reference to FIGS. 53A and 53B , in waveform example 33, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 33, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un.
  • the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
  • FIG. 54A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 54B is a diagram showing switching losses.
  • waveform example 34 the output voltage of any one phase is fixed to 1 in a certain electrical angle section, and the output voltage of any one phase is fixed to 1 in another electrical angle section, depending on the electrical angle. is fixed to 0. More specifically, waveform example 34 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 75 degrees to 105 degrees and at an electrical angle of 150 degrees to 240 degrees. In waveform example 34, the output of any one phase is fixed to 0 at an electrical angle of 0 to 75 electrical degrees, 105 to 150 electrical degrees, and 240 to 360 electrical degrees. waveform.
  • the high-side-on application period T3 occurs at an electrical angle of 75 degrees to 105 degrees and at an electrical angle of 150 degrees to 240 degrees.
  • the low side-on application period T4 occurs at an electrical angle of 105 degrees to 150 degrees and at an electrical angle of 240 degrees to 360 degrees.
  • the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v.
  • the first fixed ON period T1u is from 75 electrical degrees to 105 electrical degrees.
  • the first fixed ON period T1v is from 150 electrical degrees to 240 electrical degrees.
  • the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
  • the second fixed ON period T2u is from 240 electrical degrees to 330 electrical degrees.
  • the second fixed ON period T2v is from an electrical angle of 0 degrees to an electrical angle of 75 degrees and from an electrical angle of 330 degrees to an electrical angle of 360 degrees.
  • the second fixed ON period T2w is from 105 electrical degrees to 150 electrical degrees.
  • the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases.
  • the first fixed ON period T1v is 90 degrees
  • the first fixed ON period T1u is 30 degrees
  • the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w.
  • the second fixed ON period T2v is 105 degrees
  • the second fixed ON period T2u is 90 degrees
  • the second fixed ON period T2w is 45 degrees. That is, in waveform example 34, the second fixed ON period T2v is longer than the second fixed ON period T2u and the second fixed ON period T2w. Therefore, as shown in FIG. 54B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
  • waveform example 34 As described above with reference to FIGS. 54A and 54B , in waveform example 34, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 34, the heat generation of the V-phase first semiconductor switching element Vp and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
  • waveform example 34 as shown in FIG. 54B, the heat generated by the U-phase first semiconductor switching element Up, the U-phase second semiconductor switching element Un, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
  • FIG. 55A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 55B is a diagram showing switching losses.
  • the output voltage of any one phase is fixed to 1 in a certain electrical angle section, and the output voltage of any one phase is fixed to 1 in another electrical angle section, depending on the electrical angle. is fixed to 0.
  • the output of any one phase is fixed to 1 at an electrical angle of 75 degrees to 105 degrees, from 150 degrees to 210 degrees, and from 330 degrees to 360 degrees.
  • the output of any one phase is fixed to 0 at an electrical angle of 0 to 75 electrical degrees, 105 to 150 electrical degrees, and 210 to 330 electrical degrees. waveform.
  • the high-side-on application period T3 is at an electrical angle of 75 degrees to 105 degrees, an electrical angle of 150 degrees to 210 degrees, and an electrical angle of 330 degrees to 360 degrees.
  • the low side-on application period T4 occurs at an electrical angle of 0 to 75 electrical degrees, 105 to 150 electrical degrees, and 210 to 330 electrical degrees.
  • the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w.
  • the first fixed ON period T1u is from 75 electrical degrees to 105 electrical degrees.
  • the first fixed ON period T1v is from 150 electrical degrees to 210 electrical degrees.
  • the first fixed ON period T1w is from 330 electrical degrees to 360 electrical degrees.
  • the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
  • the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
  • the second fixed ON period T2v is from 0 electrical angle to 75 electrical degrees.
  • the second fixed ON period T2w is from 105 electrical degrees to 150 electrical degrees.
  • the first fixed ON period T1v differs from the first fixed ON period T1u and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 35, the first fixed ON period T1v is 60 degrees, while the first fixed ON period T1u and the first fixed ON period T1w are 30 degrees. That is, in waveform example 35, the first fixed ON period T1v is longer than the first fixed ON period T1u and the first fixed ON period T1w. Therefore, as shown in FIG. 55B, the switching loss of the V-phase first semiconductor switching element Vp (H (high side)) is smaller than those of the U-phase and W-phase.
  • the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w.
  • the second fixed ON period T2u is 120 degrees
  • the second fixed ON period T2v is 75 degrees
  • the second fixed ON period T2w is 45 degrees. That is, in waveform example 35, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 55B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
  • waveform example 35 As described above with reference to FIGS. 55A and 55B , in waveform example 35 as well as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved.
  • the heat generation of the V-phase first semiconductor switching element Vp and the U-phase second semiconductor switching element Un can be suppressed at the same time.
  • FIG. 56A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 56B is a diagram showing switching losses.
  • waveform example 36 the output voltage of any one phase is fixed to 1 in a certain electrical angle section, and the output voltage of any one phase is fixed to 1 in another electrical angle section, depending on the electrical angle. is fixed to 0. More specifically, waveform example 36 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 150 degrees to 240 degrees and at an electrical angle of 330 degrees to 360 degrees. Waveform example 36 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 degree to 150 electrical degrees and at an electrical angle of 240 degrees to 330 electrical degrees.
  • the high side-on application period T3 occurs at an electrical angle of 150 degrees to 240 degrees and at an electrical angle of 330 degrees to 360 degrees. Further, in waveform example 36, the low side-on application period T4 occurs at an electrical angle of 0 to 150 electrical degrees and at an electrical angle of 240 to 330 electrical degrees.
  • the first fixed ON period T1 includes a first fixed ON period T1v and a first fixed ON period T1w.
  • the first fixed ON period T1v is from 150 electrical degrees to 240 electrical degrees.
  • the first fixed ON period T1w is between 330 electrical degrees and 360 electrical degrees.
  • the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
  • the second fixed ON period T2u is from 240 electrical degrees to 330 electrical degrees.
  • the second fixed ON period T2v is from 0 electrical angle to 90 electrical degrees.
  • the second fixed ON period T2w is from 90 electrical degrees to 150 electrical degrees.
  • the first fixed ON period T1v differs from the first fixed ON period T1u and the first fixed ON period T1w.
  • the first fixed ON period T1v is 90 degrees
  • the first fixed ON period T1u is absent
  • the first fixed ON period T1w is 30 degrees. That is, in waveform example 36, the first fixed ON period T1v is longer than the first fixed ON period T1u and the first fixed ON period T1w. Therefore, as shown in FIG. 56B, the switching loss of the V-phase first semiconductor switching element Vp (H (high side)) is smaller than those of the U-phase and W-phase.
  • the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w.
  • the second fixed ON period T2u is 90 degrees, while the second fixed ON period T2w is 60 degrees. That is, in waveform example 36, the second fixed ON period T2u is longer than the second fixed ON period T2w.
  • the second fixed ON period T2v is the same as the second fixed ON period T2u. Therefore, as shown in FIG. 56B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than that of the W-phase.
  • waveform example 36 As described above with reference to FIGS. 56A and 56B , in waveform example 36, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 36, it is possible to simultaneously suppress the heat generation of the V-phase first semiconductor switching element Vp and the U-phase second semiconductor switching element Un.
  • waveform example 36 as shown in FIG. 56B, the heat generated by the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
  • FIG. 57A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 57B is a diagram showing switching losses.
  • waveform example 37 As shown in FIG. 57A, in waveform example 37, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0.
  • waveform example 37 is a waveform in which the output of any one phase is fixed to 1 in the electrical angle of 0 to 30 electrical degrees, the electrical angle of 150 to 210 electrical degrees, and the electrical angle of 330 to 360 electrical degrees. is.
  • Waveform example 37 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 30 degrees to 150 degrees and at an electrical angle of 210 degrees to 330 degrees.
  • the high-side-on application period T3 occurs at an electrical angle of 0 to 30 electrical degrees, from 150 to 210 electrical degrees, and from 330 to 360 electrical degrees.
  • the low-side-on application period T4 occurs at an electrical angle of 30 degrees to 150 degrees and at an electrical angle of 210 degrees to 330 degrees.
  • the first fixed ON period T1 includes a first fixed ON period T1v and a first fixed ON period T1w.
  • the first fixed ON period T1v is from 150 electrical degrees to 210 electrical degrees.
  • the first fixed ON period T1w is from an electrical angle of 0 degree to an electrical angle of 30 degrees and from an electrical angle of 330 degrees to an electrical angle of 360 degrees.
  • the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
  • the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
  • the second fixed ON period T2v is from 30 electrical degrees to 90 electrical degrees.
  • the second fixed ON period T2w is from 90 electrical degrees to 150 electrical degrees.
  • the first fixed ON period T1v differs from the first fixed ON period T1u in the U phase among the three phases. Specifically, in waveform example 37, the first fixed ON period T1v is 60 degrees, but there is no first fixed ON period T1u. That is, in waveform example 37, the first fixed ON period T1v is longer than the first fixed ON period T1u.
  • the first fixed ON period T1w is the same as the first fixed ON period T1v. Therefore, as shown in FIG. 57B, the switching loss of the V-phase first semiconductor switching element Up (H (high side)) is smaller than that of the U-phase.
  • the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w.
  • the second fixed ON period T2u is 120 degrees, while the second fixed ON period T2v and the second fixed ON period T2w are 60 degrees. That is, in waveform example 37, the second fixed on period T2u is longer than the second fixed on period T2v and the second fixed on period T2w. Therefore, as shown in FIG. 57B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
  • waveform example 37 As described above with reference to FIGS. 57A and 57B , in waveform example 37, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 37, it is possible to simultaneously suppress the heat generation of the V-phase first semiconductor switching element Vp and the U-phase second semiconductor switching element Un.
  • waveform example 37 as shown in FIG. 57B, the heat generated by the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
  • FIG. 58A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 58B is a diagram showing switching losses.
  • waveform example 38 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 45 degrees to 135 degrees and at an electrical angle of 150 degrees to 240 degrees.
  • waveform example 38 the output of any one phase is fixed to 0 at an electrical angle of 0 to 45 electrical degrees, 135 to 150 electrical degrees, and 240 to 360 electrical degrees. waveform.
  • the high-side-on application period T3 occurs at an electrical angle of 45 degrees to 135 degrees and at an electrical angle of 150 degrees to 240 degrees. Further, in waveform example 38, the low side-on application period T4 occurs at an electrical angle of 0 to 45 electrical degrees, 135 to 150 electrical degrees, and 240 to 360 electrical degrees.
  • the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v.
  • the first fixed ON period T1u is from 45 electrical degrees to 135 electrical degrees.
  • the first fixed ON period T1v is from 150 electrical degrees to 240 electrical degrees.
  • the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
  • the second fixed ON period T2u is from 240 electrical degrees to 330 electrical degrees.
  • the second fixed ON period T2v is from an electrical angle of 0 degree to an electrical angle of 45 degrees and from an electrical angle of 330 degrees to an electrical angle of 360 degrees.
  • the second fixed ON period T2w is from 135 electrical degrees to 150 electrical degrees.
  • the first fixed ON period T1u differs from the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 38, the first fixed ON period T1u is 90 degrees, but there is no first fixed ON period T1w. That is, in waveform example 38, the first fixed ON period T1u is longer than the first fixed ON period T1w. The first fixed ON period T1v is the same as the first fixed ON period T1u. Therefore, as shown in FIG. 58B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than that of the W-phase.
  • the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w.
  • the second fixed ON period T2u is 90 degrees
  • the second fixed ON period T2v is 75 degrees
  • the second fixed ON period T2w is 15 degrees. That is, in waveform example 38, the second fixed on period T2u is longer than the second fixed on period T2v and the second fixed on period T2w. Therefore, as shown in FIG. 58B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
  • waveform example 38 As described above with reference to FIGS. 58A and 58B , in waveform example 38, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 38, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un.
  • waveform example 38 as shown in FIG. 58B, the heat generated by the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
  • FIG. 59A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 59B is a diagram showing switching losses.
  • the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0.
  • the output of any one phase is fixed to 1 at an electrical angle of 45 degrees to 135 degrees, from 150 degrees to 210 degrees and from 330 degrees to 360 degrees.
  • the output of any one phase is fixed to 0 at an electrical angle of 0 to 45 electrical degrees, 135 to 150 electrical degrees, and 210 to 330 electrical degrees. waveform.
  • the high-side-on application period T3 is at an electrical angle of 45 degrees to 135 degrees, at an electrical angle of 150 degrees to 210 degrees, and at an electrical angle of 330 degrees to 360 degrees.
  • the low side-on application period T4 occurs at an electrical angle of 0 to 45 electrical degrees, 135 to 150 electrical degrees, and 210 to 330 electrical degrees.
  • the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w.
  • the first fixed ON period T1u is from 45 electrical degrees to 135 electrical degrees.
  • the first fixed ON period T1v is from 150 electrical degrees to 210 electrical degrees.
  • the first fixed ON period T1w is from 330 electrical degrees to 360 electrical degrees.
  • the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
  • the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
  • the second fixed ON period T2v is from 0 electrical angle to 45 electrical degrees.
  • the second fixed ON period T2w is from 135 electrical degrees to 150 electrical degrees.
  • the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases.
  • the first fixed ON period T1u is 90 degrees
  • the first fixed ON period T1v is 60 degrees
  • the first fixed ON period T1w is 30 degrees. That is, in waveform example 39, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 59B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
  • the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w.
  • the second fixed ON period T2u is 120 degrees
  • the second fixed ON period T2v is 45 degrees
  • the second fixed ON period T2w is 15 degrees. That is, in Waveform Example 39, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 59B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
  • waveform example 39 As described above with reference to FIGS. 59A and 59B , in waveform example 39, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 39, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un.
  • the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
  • FIG. 60A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 60B is a diagram showing switching losses.
  • the output voltage of any one phase is fixed to 1 in a certain electrical angle section according to the electrical angle, and the output voltage of any one phase is fixed to 1 in another electrical angle section. is fixed to 0.
  • the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 120 degrees, from 150 degrees to 240 degrees, and from 330 degrees to 360 degrees.
  • the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 degrees, 120 to 150 electrical degrees, and 240 to 330 electrical degrees. waveform.
  • the high-side-on application period T3 is at an electrical angle of 60 to 120 electrical degrees, 150 to 240 electrical degrees, and 330 to 360 electrical degrees.
  • the low side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees, 120 to 150 electrical degrees, and 240 to 330 electrical degrees.
  • the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w.
  • the first fixed ON period T1u is from 60 electrical degrees to 120 electrical degrees.
  • the first fixed ON period T1v is from 150 electrical degrees to 240 electrical degrees.
  • the first fixed ON period T1w is from 330 electrical degrees to 360 electrical degrees.
  • the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
  • the second fixed ON period T2u is from 240 electrical degrees to 330 electrical degrees.
  • the second fixed ON period T2v is from 0 electrical angle to 60 electrical degrees.
  • the second fixed ON period T2w is between 120 electrical degrees and 150 electrical degrees.
  • the first fixed ON period T1v in the V phase among the three phases, is different from the first fixed ON period T1u and the first fixed ON period T1w.
  • the first fixed ON period T1v is 90 degrees
  • the first fixed ON period T1u is 60 degrees
  • the first fixed ON period T1w is 30 degrees. That is, in waveform example 40, the first fixed ON period T1v is longer than the first fixed ON period T1u and the first fixed ON period T1w. Therefore, as shown in FIG. 60B, the switching loss of the U-phase first semiconductor switching element Vp (H (high side)) is smaller than those of the U-phase and W-phase.
  • the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w.
  • the second fixed ON period T2u is 90 degrees
  • the second fixed ON period T2v is 60 degrees
  • the second fixed ON period T2w is 30 degrees. That is, in waveform example 40, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 60B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
  • waveform example 40 As described above with reference to FIGS. 60A and 60B , in waveform example 40 as well as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved.
  • the heat generation of the V-phase first semiconductor switching element Vp and the U-phase second semiconductor switching element Un can be suppressed at the same time.
  • the U-phase first semiconductor switching element Up the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
  • FIG. 61A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 61B is a diagram showing switching losses.
  • waveform example 41 the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0.
  • the waveform example 41 is any of the electrical angles of 0 to 30 electrical degrees, 60 to 120 electrical degrees, 150 to 210 electrical degrees, and 330 to 360 electrical degrees. or is a waveform in which the output of one phase is fixed at 1.
  • the output of any one phase is fixed to 0 at an electrical angle of 30 degrees to 60 degrees, from 120 degrees to 150 degrees and from 210 degrees to 330 degrees. waveform.
  • high side ON is applied at an electrical angle of 0 to 30 electrical degrees, from 60 to 120 electrical degrees, from 150 to 210 electrical degrees, and from 330 to 360 electrical degrees. It is period T3. Further, in waveform example 41, the low side-on application period T4 is at an electrical angle of 30 to 60 electrical degrees, 120 to 150 electrical degrees, and 210 to 330 electrical degrees.
  • the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w.
  • the first fixed ON period T1u is from 60 electrical degrees to 120 electrical degrees.
  • the first fixed ON period T1v is from 150 electrical degrees to 210 electrical degrees.
  • the first fixed ON period T1w is from an electrical angle of 0 degrees to an electrical angle of 30 degrees and from an electrical angle of 330 degrees to an electrical angle of 360 degrees.
  • the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
  • the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
  • the second fixed ON period T2v is between 30 electrical degrees and 60 electrical degrees.
  • the second fixed ON period T2w is from 120 electrical degrees to 150 electrical degrees.
  • the first fixed ON period T1u, the first fixed ON period T1v, and the first fixed ON period T1v are the same. Specifically, in waveform example 41, the first fixed ON period T1u, the first fixed ON period T1u, the first fixed ON period T1v, and the first fixed ON period T1v are 60 degrees.
  • the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w.
  • the second fixed ON period T2u is 120 degrees, while the second fixed ON period T2v and the second fixed ON period T2w are 30 degrees. That is, in waveform example 41, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 61B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
  • waveform example 41 As described above with reference to FIGS. 61A and 61B, in waveform example 41, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 41, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un.
  • the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
  • FIG. 62A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 62B is a diagram showing switching losses.
  • the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0.
  • the output of any one phase is fixed to 1 at an electrical angle of 75 degrees to 105 degrees, from 150 degrees to 270 degrees, and from 330 degrees to 360 degrees.
  • the output of any one phase is fixed to 0 at an electrical angle of 0 to 75 electrical degrees, 105 to 150 electrical degrees, and 270 to 330 electrical degrees. waveform.
  • the high-side-on application period T3 is at an electrical angle of 75 degrees to 105 degrees, an electrical angle of 150 degrees to 270 degrees, and an electrical angle of 330 degrees to 360 degrees.
  • the low side-on application period T4 occurs at an electrical angle of 0 to 75 electrical degrees, 105 to 150 electrical degrees, and 270 to 330 electrical degrees.
  • the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w.
  • the first fixed ON period T1u is from 75 electrical degrees to 105 electrical degrees.
  • the first fixed ON period T1v is from 150 electrical degrees to 270 electrical degrees.
  • the first fixed ON period T1w is from 330 electrical degrees to 360 electrical degrees.
  • the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
  • the second fixed ON period T2u is from 270 degrees to 330 degrees in electrical angle.
  • the second fixed ON period T2v is from 0 electrical angle to 75 electrical degrees.
  • the second fixed ON period T2w is from 105 electrical degrees to 150 electrical degrees.
  • the first fixed ON period T1v differs from the first fixed ON period T1u and the first fixed ON period T1w.
  • the first fixed ON period T1v is 120 degrees, while the first fixed ON period T1u and the first fixed ON period T1w are 30 degrees. That is, in waveform example 42, the first fixed ON period T1v is longer than the first fixed ON period T1u and the first fixed ON period T1w. Therefore, as shown in FIG. 62B, the switching loss of the V-phase first semiconductor switching element Up (H (high side)) is smaller than those of the U-phase and W-phase.
  • the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w.
  • the second fixed ON period T2v is 75 degrees
  • the second fixed ON period T2u is 60 degrees
  • the second fixed ON period T2w is 45 degrees. That is, in waveform example 42, the second fixed ON period T2v is longer than the second fixed ON period T2u and the second fixed ON period T2w. Therefore, as shown in FIG. 62B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
  • waveform example 42 As described above with reference to FIGS. 62A and 62B , in waveform example 42, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 42, the heat generation of the V-phase first semiconductor switching element Vp and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
  • waveform example 42 as shown in FIG. 62B, the U-phase first semiconductor switching element Up, the U-phase second semiconductor switching element Un, the W-phase first semiconductor switching element Wp, and the W-phase semiconductor switching element Wp Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
  • FIG. 63A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 63B is a diagram showing switching losses.
  • waveform example 43 the output voltage of any one phase is fixed to 1 in a certain electrical angle section, and the output voltage of any one phase is fixed to 1 in another electrical angle section, depending on the electrical angle. is fixed to 0.
  • the waveform example 43 is any of the electrical angles of 0 to 30 electrical degrees, 75 to 105 electrical degrees, 150 to 240 electrical degrees, and 330 to 360 electrical degrees. or is a waveform in which the output of one phase is fixed at 1.
  • the output of any one phase is fixed to 0 at an electrical angle of 30 degrees to 75 degrees, from 105 degrees to 150 degrees, and from 240 degrees to 330 degrees. waveform.
  • high side ON is applied at an electrical angle of 0 to 30 electrical degrees, from 75 to 105 electrical degrees, from 150 to 240 electrical degrees, and from 330 to 360 electrical degrees. It is period T3. Further, in waveform example 43, the low side-on application period T4 occurs at an electrical angle of 30 to 75 electrical degrees, 105 to 150 electrical degrees, and 240 to 330 electrical degrees.
  • the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w.
  • the first fixed ON period T1u is from 75 electrical degrees to 105 electrical degrees.
  • the first fixed ON period T1v is from 150 electrical degrees to 240 electrical degrees.
  • the first fixed ON period T1w is from an electrical angle of 0 degrees to an electrical angle of 30 degrees and from an electrical angle of 330 degrees to an electrical angle of 360 degrees.
  • the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
  • the second fixed ON period T2u is from 240 degrees to 330 degrees in electrical angle.
  • the second fixed ON period T2v is from 30 electrical degrees to 75 electrical degrees.
  • the second fixed ON period T2w is from 105 electrical degrees to 150 electrical degrees.
  • the first fixed ON period T1v differs from the first fixed ON period T1u and the first fixed ON period T1w.
  • the first fixed ON period T1v is 90 degrees
  • the first fixed ON period T1u is 30 degrees
  • the first fixed ON period T1w is 60 degrees. That is, in waveform example 43, the first fixed ON period T1v is longer than the first fixed ON period T1u and the first fixed ON period T1w. Therefore, as shown in FIG. 63B, the switching loss of the V-phase first semiconductor switching element Vp (H (high side)) is smaller than those of the U-phase and W-phase.
  • the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w.
  • the second fixed ON period T2u is 90 degrees, while the second fixed ON period T2v and the second fixed ON period T2w are 45 degrees. That is, in waveform example 43, the second fixed on period T2u is longer than the second fixed on period T2v and the second fixed on period T2w. Therefore, as shown in FIG. 63B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
  • waveform example 43 As described above with reference to FIGS. 63A and 63B , in waveform example 43, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In the waveform example 43, the heat generation of the V-phase first semiconductor switching element Vp and the U-phase second semiconductor switching element Un can be suppressed at the same time.
  • waveform example 43 as shown in FIG. 63B, the U-phase first semiconductor switching element Up, the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
  • FIG. 64A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 64B is a diagram showing switching losses.
  • the output voltage of any one phase is fixed to 1 in a certain electrical angle section according to the electrical angle, and the output voltage of any one phase is fixed to 1 in another electrical angle section. is fixed to 0.
  • the output of any one phase is fixed to 1 at an electrical angle of 0 to 30 degrees, from 150 to 270 electrical degrees, and from 330 to 360 electrical degrees.
  • Waveform example 44 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 30 degrees to 150 degrees and at an electrical angle of 270 degrees to 330 degrees.
  • the high-side-on application period T3 occurs at an electrical angle of 0 to 30 electrical degrees, 150 to 270 electrical degrees, and 330 to 360 electrical degrees. Further, in waveform example 44, the low side-on application period T4 occurs at an electrical angle of 30 degrees to 150 degrees and at an electrical angle of 270 degrees to 330 degrees.
  • the first fixed ON period T1 includes a first fixed ON period T1v and a first fixed ON period T1w.
  • the first fixed ON period T1v is from 150 electrical degrees to 270 electrical degrees.
  • the first fixed ON period T1w is from 0 electrical angle to 30 electrical degrees and from 330 electrical degrees to 360 electrical degrees.
  • the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
  • the second fixed ON period T2u is from 270 degrees to 330 degrees in electrical angle.
  • the second ON fixed period T2v is from 30 electrical degrees to 90 electrical degrees.
  • the second fixed ON period T2w is from 90 electrical degrees to 150 electrical degrees.
  • the first fixed ON period T1v differs from the first fixed ON period T1u and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 44, the first fixed ON period T1v is 120 degrees, whereas the first fixed ON period T1u is absent and the first fixed ON period T1w is 60 degrees. That is, in waveform example 44, the first fixed ON period T1v is longer than the first fixed ON period T1u and the first fixed ON period T1w. Therefore, as shown in FIG. 64B, the switching loss of the V-phase first semiconductor switching element Vp (H (high side)) is smaller than those of the U-phase and W-phase.
  • the second fixed ON period T2u, the second fixed ON period T2v, and the second fixed ON period T2w are the same. Specifically, in waveform example 44, the second fixed ON period T2u, the second fixed ON period T2v, and the second fixed ON period T2w are 60 degrees.
  • waveform example 44 As described above with reference to FIGS. 64A and 64B, in waveform example 44, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 44, it is possible to simultaneously suppress the heat generation of the V-phase first semiconductor switching element Vp and the U-phase second semiconductor switching element Un.
  • waveform example 44 as shown in FIG. 64B, the heat generated by the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
  • FIG. 65A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 65B is a diagram showing switching losses.
  • waveform example 45 the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, in waveform example 45, the output of any one phase is fixed to 1 at an electrical angle of 0 to 30 degrees, from 150 to 240 electrical degrees, and from 300 to 360 electrical degrees. waveform. Waveform example 45 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 30 degrees to 150 degrees and at an electrical angle of 240 degrees to 300 degrees.
  • the high-side-on application period T3 occurs at an electrical angle of 0 to 30 electrical degrees, 150 to 240 electrical degrees, and 300 to 360 electrical degrees. Further, in waveform example 45, the low-side-on application period T4 occurs at an electrical angle of 30 degrees to 150 electrical degrees and at an electrical angle of 240 degrees to 300 electrical degrees.
  • the first fixed ON period T1 includes a first fixed ON period T1v and a first fixed ON period T1w.
  • the first fixed ON period T1v is from 150 electrical degrees to 240 electrical degrees.
  • the first fixed ON period T1w is from an electrical angle of 0 degrees to an electrical angle of 30 degrees and from an electrical angle of 300 degrees to an electrical angle of 360 degrees.
  • the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
  • the second fixed ON period T2u is from 240 electrical degrees to 300 electrical degrees.
  • the second fixed ON period T2v is from 30 electrical degrees to 90 electrical degrees.
  • the second fixed ON period T2w is from 90 electrical degrees to 150 electrical degrees.
  • the first fixed ON period T1v differs from the first fixed ON period T1u and the first fixed ON period T1w.
  • the first fixed ON period T1v is 90 degrees, but there is no first fixed ON period T1u. That is, in waveform example 45, the first fixed ON period T1v is longer than the first fixed ON period T1u.
  • the first fixed ON period T1w is the same as the first fixed ON period T1v. Therefore, as shown in FIG. 65B, the switching loss of the V-phase first semiconductor switching element Up (H (high side)) is smaller than that of the W-phase.
  • the second fixed ON period T2u, the second fixed ON period T2v, and the second fixed ON period T2w are the same. Specifically, in waveform example 45, the second fixed ON period T2u, the second fixed ON period T2v, and the second fixed ON period T2w are 60 degrees.
  • waveform example 45 As described above with reference to FIGS. 65A and 65B , in waveform example 45, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In the waveform example 45, the heat generation of the V-phase first semiconductor switching element Vp and the U-phase second semiconductor switching element Un can be suppressed at the same time.
  • waveform example 45 as shown in FIG. 65B, the heat generated by the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
  • FIG. 66A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
  • FIG. 66B is a diagram showing switching losses.
  • waveform example 46 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 90 degrees to 270 electrical degrees.
  • waveform example 46 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 to 90 degrees and at an electrical angle of 270 to 360 degrees.
  • the high-side-on application period T3 is at an electrical angle of 90 degrees to 270 electrical degrees.
  • the low side-on application period T4 occurs at an electrical angle of 0 to 90 electrical degrees and at an electrical angle of 270 to 360 electrical degrees.
  • the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v.
  • the first fixed ON period T1u is from 90 electrical degrees to 150 electrical degrees.
  • the first fixed ON period T1v is from 150 electrical degrees to 270 electrical degrees.
  • the second fixed ON period T2 includes a second fixed ON period T2u and a second fixed ON period T2v.
  • the second fixed ON period T2u is from 270 electrical degrees to 330 electrical degrees.
  • the second fixed ON period T2v is from 0 to 90 electrical degrees and from 330 to 360 electrical degrees.
  • the first fixed ON period T1v differs from the first fixed ON period T1u and the first fixed ON period T1w in the V phase among the three phases. Specifically, in waveform example 46, the first fixed ON period T1v is 120 degrees, the first fixed ON period T1u is 60 degrees, and there is no first fixed ON period T1w. That is, in the waveform example 46, the first fixed ON period T1v is longer than the first fixed ON period T1u and the first fixed ON period T1w. Therefore, as shown in FIG. 66B, the switching loss of the U-phase first semiconductor switching element Vp (H (high side)) is smaller than those of the U-phase and W-phase.
  • the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w.
  • the second fixed ON period T2v is 120 degrees
  • the second fixed ON period T2u is 60 degrees
  • waveform example 46 As described above with reference to FIGS. 66A and 66B , in waveform example 46, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In the waveform example 46, the heat generation of the V-phase first semiconductor switching element Vp and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
  • FIGS. 1 to 66B The embodiments of the present invention have been described above with reference to the drawings (FIGS. 1 to 66B).
  • the present invention is not limited to the above-described embodiments, and can be implemented in various aspects without departing from the gist of the present invention.
  • the drawings schematically show each component mainly, and the thickness, length, number, etc. of each component illustrated are different from the actual ones due to the convenience of drawing. .
  • the material, shape, dimensions, etc. of each component shown in the above embodiment are examples and are not particularly limited, and various changes are possible within a range that does not substantially deviate from the effects of the present invention. be.
  • the motor drive circuit 100 (power converter) described with reference to FIGS. 1 to 66B outputs a three-phase AC output, but the present invention is not limited to this.
  • the motor drive circuit 100 may output AC outputs of five or more phases.
  • the motor drive circuit 100 may drive the 5-phase motor M by outputting a 5-phase AC output.
  • the present invention can be suitably used for power converters and motor modules.

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  • Inverter Devices (AREA)
  • Ac-Ac Conversion (AREA)

Abstract

This power converter converts DC power into AC power of n phases. The power converter comprises: n-number of output terminals; a first power supply terminal; a second power supply terminal; and n-number of serial bodies. During one period of AC outputs of the n phases, at least one phase of the AC outputs has a protective operation mode having at least one of a first on-fixed period during which a first semiconductor switching element is set to ON in a fixed manner and a second on-fixed period during which a second semiconductor switching element set to ON in a fixed manner. In the protective operation mode, in at least one of the n phases, the first on-fixed period is different from that of one of the other phases, or the second on-fixed period is different from that of one of the other phases.

Description

電力変換器およびモータモジュールPower converter and motor module
　本発明は、電力変換器およびモータモジュールに関する。 The present invention relates to power converters and motor modules.
　３相のモータを駆動するモータ制御装置が知られている（例えば特許文献１）。特許文献１に記載のモータ制御装置では、３相電圧の各相電圧を２π／３またはπ／３に固定することによって、スイッチング素子の温度上昇を抑制している。 A motor control device that drives a three-phase motor is known (for example, Patent Document 1). In the motor control device described in Patent Document 1, the temperature rise of the switching element is suppressed by fixing each phase voltage of the three-phase voltage to 2π/3 or π/3.
特開２００５－２２９７１４号公報JP 2005-229714 A
　しかしながら、特許文献１に記載のモータ制御装置では、ハイサイド側の、スイッチング素子を均等に温度上昇の抑制、または、ロウサイド側のスイッチング素子を均等に温度上昇の抑制、あるいは、全てのスイッチング素子を均等に温度上昇の抑制をすることしかできない。したがって、特定の相の特定の半導体スイッチング素子を保護することができない。 However, in the motor control device described in Patent Document 1, the temperature rise of switching elements on the high side is evenly suppressed, the temperature rise of switching elements on the low side is evenly suppressed, or all switching elements are suppressed. It is only possible to uniformly suppress the temperature rise. Therefore, it is not possible to protect specific semiconductor switching elements of specific phases.
　本発明は上記課題に鑑みてなされたものであり、その目的はある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子の発熱を同時に抑えることで、電力変換器の昇温を抑制し信頼性を高めることができる電力変換器およびモータモジュールを提供することにある。 The present invention has been made in view of the above problems, and its object is to simultaneously suppress the heat generation of the first semiconductor switching element of a certain phase and the heat generation of the second semiconductor switching element of a certain phase, thereby suppressing the temperature rise of the power converter. An object of the present invention is to provide a power converter and a motor module capable of suppressing and improving reliability.
　本発明の例示的な電力変換器は、直流電力をｎ相の交流電力に変換する。前記電力変換器は、ｎ個の出力端子と、第１電源端子と、第２電源端子と、ｎ個の直列体とを備える。前記ｎ個の出力端子は、ｎ相の出力電圧とｎ相の出力電流とを出力する。前記第１電源端子には、第１の電圧が印加される。前記第２電源端子には、前記第１の電圧よりも低い第２の電圧が印加される。前記ｎ個の直列体は、２つの半導体スイッチング素子が直列に接続されている。ｎは、交流出力の相数であって、３以上の奇数である。前記ｎ個の直列体は、互いに並列に接続されている。前記ｎ個の直列体の各々は、一端が前記第１電源端子に接続されている。前記ｎ個の直列体の各々は、他端が前記第２電源端子に接続されている。前記ｎ個の直列体の各々は、第１半導体スイッチング素子と、第２半導体スイッチング素子とを有する。前記第１半導体スイッチング素子は、前記第１電源端子に接続される。前記第２半導体スイッチング素子は、前記第２電源端子に接続される。前記第１半導体スイッチング素子と前記第２半導体スイッチング素子とは接続点において接続されている。前記ｎ個の直列体の各々における前記接続点が、前記ｎ個の出力端子に接続されている。前記第１半導体スイッチング素子は、前記交流出力の周波数よりも高い周波数でオンとオフとが切り替えられる。前記第２半導体スイッチング素子は、前記交流出力の周波数よりも高い周波数でオンとオフとが切り替えられる。ｎ相の交流出力の１周期の間に、前記交流出力のうち少なくとも１相が、前記第１半導体スイッチング素子がオンに固定される第１オン固定期間と、前記第２半導体スイッチング素子がオンに固定される第２オン固定期間との少なくとも一方を有する保護動作モードを有する。前記保護動作モードにおいて、ｎ相のうち少なくとも１相において、前記第１オン固定期間が、他のいずれか１相の前記第１オン固定期間と異なるか、または前記第２オン固定期間が、他のいずれか１相の前記第２オン固定期間と異なる。 An exemplary power converter of the present invention converts DC power into n-phase AC power. The power converter includes n output terminals, a first power terminal, a second power terminal, and n series bodies. The n output terminals output n-phase output voltages and n-phase output currents. A first voltage is applied to the first power supply terminal. A second voltage lower than the first voltage is applied to the second power supply terminal. The n series bodies are formed by connecting two semiconductor switching elements in series. n is the number of AC output phases and is an odd number of 3 or more. The n series bodies are connected in parallel with each other. One end of each of the n series bodies is connected to the first power supply terminal. Each of the n series bodies has the other end connected to the second power supply terminal. Each of the n series bodies has a first semiconductor switching element and a second semiconductor switching element. The first semiconductor switching element is connected to the first power terminal. The second semiconductor switching element is connected to the second power terminal. The first semiconductor switching element and the second semiconductor switching element are connected at a connection point. The connection points in each of the n series bodies are connected to the n output terminals. The first semiconductor switching element is switched on and off at a frequency higher than the frequency of the AC output. The second semiconductor switching element is switched on and off at a frequency higher than the frequency of the AC output. During one cycle of the n-phase AC output, at least one phase of the AC output has a first fixed ON period during which the first semiconductor switching element is fixed ON and the second semiconductor switching element is ON. It has a protection mode of operation having at least one of a fixed second ON fixed period. In the protection operation mode, in at least one of the n phases, the first fixed ON period is different from the first fixed ON period of any one of the other phases, or the second fixed ON period is different from the first fixed ON period of any other phase. is different from the second on-fixed period of any one phase.
　本発明の例示的なモータモジュールは、上記に記載の電力変換器と、モータとを備える。前記モータには、前記電力変換器の出力が入力される。 An exemplary motor module of the present invention includes the power converter described above and a motor. The output of the power converter is input to the motor.
　例示的な本発明によればある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子の発熱を同時に抑えることで、電力変換器の昇温を抑制し信頼性を高めることができる。 According to the exemplary present invention, by simultaneously suppressing the heat generation of the first semiconductor switching element of a certain phase and the heat generation of the second semiconductor switching element of a certain phase, it is possible to suppress the temperature rise of the power converter and improve the reliability. .
図１は、本発明の実施形態に係るモータモジュールのブロック図である。FIG. 1 is a block diagram of a motor module according to an embodiment of the invention. 図２は、インバータ部を示す回路図である。FIG. 2 is a circuit diagram showing an inverter section. 図３Ａは、出力電圧を示す図である。FIG. 3A is a diagram showing the output voltage. 図３Ｂは、スイッチング損失を示す図である。FIG. 3B is a diagram showing switching losses. 図４は、波形例とスイッチング損失との関係を示す表である。FIG. 4 is a table showing the relationship between waveform examples and switching loss. 図５Ａは、出力電圧を示す図である。FIG. 5A is a diagram showing the output voltage. 図５Ｂは、スイッチング損失を示す図である。FIG. 5B is a diagram showing switching losses. 図６Ａは、出力電圧を示す図である。FIG. 6A is a diagram showing the output voltage. 図６Ｂは、スイッチング損失を示す図である。FIG. 6B is a diagram showing switching losses. 図７Ａは、出力電圧を示す図である。FIG. 7A is a diagram showing the output voltage. 図７Ｂは、スイッチング損失を示す図である。FIG. 7B is a diagram showing switching losses. 図８Ａは、出力電圧を示す図である。FIG. 8A is a diagram showing the output voltage. 図８Ｂは、スイッチング損失を示す図である。FIG. 8B is a diagram showing switching losses. 図９Ａは、出力電圧を示す図である。FIG. 9A is a diagram showing the output voltage. 図９Ｂは、スイッチング損失を示す図である。FIG. 9B is a diagram showing switching losses. 図１０Ａは、出力電圧を示す図である。FIG. 10A is a diagram showing the output voltage. 図１０Ｂは、スイッチング損失を示す図である。FIG. 10B is a diagram showing switching losses. 図１１Ａは、出力電圧を示す図である。FIG. 11A is a diagram showing output voltages. 図１１Ｂは、スイッチング損失を示す図である。FIG. 11B is a diagram showing switching loss. 図１２Ａは、出力電圧を示す図である。FIG. 12A is a diagram showing the output voltage. 図１２Ｂは、スイッチング損失を示す図である。FIG. 12B is a diagram showing switching losses. 図１３Ａは、出力電圧を示す図である。FIG. 13A is a diagram showing the output voltage. 図１３Ｂは、スイッチング損失を示す図である。FIG. 13B is a diagram showing switching losses. 図１４Ａは、出力電圧を示す図である。FIG. 14A is a diagram showing the output voltage. 図１４Ｂは、スイッチング損失を示す図である。FIG. 14B is a diagram showing switching losses. 図１５Ａは、出力電圧を示す図である。FIG. 15A is a diagram showing output voltages. 図１５Ｂは、スイッチング損失を示す図である。FIG. 15B is a diagram showing switching losses. 図１６は、スイッチング損失を示す図である。FIG. 16 is a diagram showing switching loss. 図１７は、ＵＨ＿ＵＬ保護波形の切り替えを説明するための図である。FIG. 17 is a diagram for explaining switching of the UH_UL protection waveform. 図１８は、ＵＨ＿ＵＬ保護波形の切り替えを説明するための図である。FIG. 18 is a diagram for explaining switching of the UH_UL protection waveform. 図１９は、スイッチング損失を示す図である。FIG. 19 is a diagram showing switching loss. 図２０は、ＵＨ＿ＵＬ保護波形の切り替えを説明するための図である。FIG. 20 is a diagram for explaining switching of the UH_UL protection waveform. 図２１は、保護波形の切替方法を示すフローチャートである。FIG. 21 is a flow chart showing a protection waveform switching method. 図２２は、保護波形の切替方法を示すフローチャートである。FIG. 22 is a flow chart showing a protection waveform switching method. 図２３は、保護波形の切替方法を示す図である。FIG. 23 is a diagram showing a method of switching guard waveforms. 図２４は、保護波形の切替方法を示す図である。FIG. 24 is a diagram showing a method of switching guard waveforms. 図２５は、波形例とスイッチング損失との関係を示す表である。FIG. 25 is a table showing the relationship between waveform examples and switching loss. 図２６Ａは、出力電圧を示す図である。FIG. 26A is a diagram showing the output voltage. 図２６Ｂは、スイッチング損失を示す図である。FIG. 26B is a diagram showing switching loss. 図２７Ａは、出力電圧を示す図である。FIG. 27A is a diagram showing the output voltage. 図２７Ｂは、スイッチング損失を示す図である。FIG. 27B is a diagram showing switching losses. 図２８Ａは、出力電圧を示す図である。FIG. 28A is a diagram showing the output voltage. 図２８Ｂは、スイッチング損失を示す図である。FIG. 28B is a diagram showing switching losses. 図２９Ａは、出力電圧を示す図である。FIG. 29A is a diagram showing the output voltage. 図２９Ｂは、スイッチング損失を示す図である。FIG. 29B is a diagram showing switching losses. 図３０Ａは、出力電圧を示す図である。FIG. 30A is a diagram showing the output voltage. 図３０Ｂは、スイッチング損失を示す図である。FIG. 30B is a diagram showing switching losses. 図３１Ａは、出力電圧を示す図である。FIG. 31A is a diagram showing the output voltage. 図３１Ｂは、スイッチング損失を示す図である。FIG. 31B is a diagram showing switching losses. 図３２Ａは、出力電圧を示す図である。FIG. 32A is a diagram showing the output voltage. 図３２Ｂは、スイッチング損失を示す図である。FIG. 32B is a diagram showing switching losses. 図３３Ａは、出力電圧を示す図である。FIG. 33A is a diagram showing the output voltage. 図３３Ｂは、スイッチング損失を示す図である。FIG. 33B is a diagram showing switching losses. 図３４Ａは、出力電圧を示す図である。FIG. 34A is a diagram showing the output voltage. 図３４Ｂは、スイッチング損失を示す図である。FIG. 34B is a diagram showing switching losses. 図３５Ａは、出力電圧を示す図である。FIG. 35A is a diagram showing the output voltage. 図３５Ｂは、スイッチング損失を示す図である。FIG. 35B is a diagram showing switching losses. 図３６Ａは、出力電圧を示す図である。FIG. 36A is a diagram showing the output voltage. 図３６Ｂは、スイッチング損失を示す図である。FIG. 36B is a diagram showing switching losses. 図３７Ａは、出力電圧を示す図である。FIG. 37A is a diagram showing the output voltage. 図３７Ｂは、スイッチング損失を示す図である。FIG. 37B is a diagram showing switching losses. 図３８Ａは、出力電圧を示す図である。FIG. 38A is a diagram showing the output voltage. 図３８Ｂは、スイッチング損失を示す図である。FIG. 38B is a diagram showing switching losses. 図３９Ａは、出力電圧を示す図である。FIG. 39A is a diagram showing the output voltage. 図３９Ｂは、スイッチング損失を示す図である。FIG. 39B is a diagram showing switching losses. 図４０Ａは、出力電圧を示す図である。FIG. 40A is a diagram showing the output voltage. 図４０Ｂは、スイッチング損失を示す図である。FIG. 40B is a diagram showing switching losses. 図４１Ａは、出力電圧を示す図である。FIG. 41A is a diagram showing the output voltage. 図４１Ｂは、スイッチング損失を示す図である。FIG. 41B is a diagram showing switching losses. 図４２Ａは、出力電圧を示す図である。FIG. 42A is a diagram showing the output voltage. 図４２Ｂは、スイッチング損失を示す図である。FIG. 42B is a diagram showing switching losses. 図４３は、スイッチング損失を示す図である。FIG. 43 is a diagram showing switching loss. 図４４は、ＵＨ＿ＶＬ保護波形の切り替えを説明するための図である。FIG. 44 is a diagram for explaining switching of the UH_VL protection waveform. 図４５は、ＵＨ＿ＶＬ保護波形の切り替えを説明するための図である。FIG. 45 is a diagram for explaining switching of the UH_VL protection waveform. 図４６は、ＵＨ＿ＶＬ保護波形の切り替えを説明するための図である。FIG. 46 is a diagram for explaining switching of the UH_VL protection waveform. 図４７は、保護波形の切替方法を示すフローチャートである。FIG. 47 is a flow chart showing a protection waveform switching method. 図４８は、保護波形の切替方法を示す図である。FIG. 48 is a diagram showing a method of switching guard waveforms. 図４９は、保護波形の切替方法を示す図である。FIG. 49 is a diagram showing a method of switching guard waveforms. 図５０Ａは、出力電圧を示す図である。FIG. 50A is a diagram showing the output voltage. 図５０Ｂは、スイッチング損失を示す図である。FIG. 50B is a diagram showing switching losses. 図５１Ａは、出力電圧を示す図である。FIG. 51A is a diagram showing output voltages. 図５１Ｂは、スイッチング損失を示す図である。FIG. 51B is a diagram showing switching loss. 図５２Ａは、出力電圧を示す図である。FIG. 52A is a diagram showing the output voltage. 図５２Ｂは、スイッチング損失を示す図である。FIG. 52B is a diagram showing switching losses. 図５３Ａは、出力電圧を示す図である。FIG. 53A is a diagram showing the output voltage. 図５３Ｂは、スイッチング損失を示す図である。FIG. 53B is a diagram showing switching losses. 図５４Ａは、出力電圧を示す図である。FIG. 54A is a diagram showing the output voltage. 図５４Ｂは、スイッチング損失を示す図である。FIG. 54B is a diagram showing switching losses. 図５５Ａは、出力電圧を示す図である。FIG. 55A is a diagram showing the output voltage. 図５５Ｂは、スイッチング損失を示す図である。FIG. 55B is a diagram showing switching losses. 図５６Ａは、出力電圧を示す図である。FIG. 56A is a diagram showing the output voltage. 図５６Ｂは、スイッチング損失を示す図である。FIG. 56B is a diagram showing switching losses. 図５７Ａは、出力電圧を示す図である。FIG. 57A is a diagram showing the output voltage. 図５７Ｂは、スイッチング損失を示す図である。FIG. 57B is a diagram showing switching losses. 図５８Ａは、出力電圧を示す図である。FIG. 58A is a diagram showing the output voltage. 図５８Ｂは、スイッチング損失を示す図である。FIG. 58B is a diagram showing switching losses. 図５９Ａは、出力電圧を示す図である。FIG. 59A is a diagram showing the output voltage. 図５９Ｂは、スイッチング損失を示す図である。FIG. 59B is a diagram showing switching losses. 図６０Ａは、出力電圧を示す図である。FIG. 60A is a diagram showing the output voltage. 図６０Ｂは、スイッチング損失を示す図である。FIG. 60B is a diagram showing switching losses. 図６１Ａは、出力電圧を示す図である。FIG. 61A is a diagram showing the output voltage. 図６１Ｂは、スイッチング損失を示す図である。FIG. 61B is a diagram showing switching losses. 図６２Ａは、出力電圧を示す図である。FIG. 62A is a diagram showing the output voltage. 図６２Ｂは、スイッチング損失を示す図である。FIG. 62B is a diagram showing switching losses. 図６３Ａは、出力電圧を示す図である。FIG. 63A is a diagram showing the output voltage. 図６３Ｂは、スイッチング損失を示す図である。FIG. 63B is a diagram showing switching losses. 図６４Ａは、出力電圧を示す図である。FIG. 64A is a diagram showing the output voltage. 図６４Ｂは、スイッチング損失を示す図である。FIG. 64B is a diagram showing switching losses. 図６５Ａは、出力電圧を示す図である。FIG. 65A is a diagram showing the output voltage. 図６５Ｂは、スイッチング損失を示す図である。FIG. 65B is a diagram showing switching losses. 図６６Ａは、出力電圧を示す図である。FIG. 66A is a diagram showing the output voltage. 図６６Ｂは、スイッチング損失を示す図である。FIG. 66B is a diagram showing switching losses.
　以下、本発明の実施形態について、図面を参照しながら説明する。なお、図中、同一または相当部分については同一の参照符号を付して説明を繰り返さない。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.
　図１および図２を参照して、本発明の実施形態に係るモータモジュール２００について説明する。図１は、本発明の実施形態に係るモータモジュール２００のブロック図である。図２は、インバータ部１１０を示す回路図である。 A motor module 200 according to an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram of a motor module 200 according to an embodiment of the invention. FIG. 2 is a circuit diagram showing the inverter section 110. As shown in FIG.
　図１に示すように、モータモジュール２００は、モータ駆動回路１００と、３相モータＭとを備える。３相モータＭは、モータ駆動回路１００によって駆動される。３相モータＭは、例えば、ブラシレスＤＣモータである。３相モータＭは、Ｕ相、Ｖ相およびＷ相を有する。３相モータＭには、モータ駆動回路１００の出力が入力される。なお、モータ駆動回路１００は、「電力変換器」の一例に相当する。 As shown in FIG. 1, the motor module 200 includes a motor drive circuit 100 and a three-phase motor M. A three-phase motor M is driven by a motor drive circuit 100 . The three-phase motor M is, for example, a brushless DC motor. A three-phase motor M has a U-phase, a V-phase and a W-phase. The output of the motor drive circuit 100 is input to the three-phase motor M. As shown in FIG. Note that the motor drive circuit 100 corresponds to an example of a "power converter".
　モータ駆動回路１００は、３相モータＭの駆動を制御する。モータ駆動回路１００は、インバータ部１１０と、信号生成部１２０とを備える。 The motor drive circuit 100 controls driving of the three-phase motor M. The motor drive circuit 100 includes an inverter section 110 and a signal generation section 120 .
　モータ駆動回路１００は、直流電力をｎ相の交流電力に変換する。ｎは、交流出力の相数であって、３以上の整数である。本実施形態では、モータ駆動回路１００は、直流電力を３相の交流電力に変換する。モータ駆動回路１００は、ｎ個の出力端子１０２を備える。本実施形態では、モータ駆動回路１００は、３つの出力端子１０２を備える。３つの出力端子１０２は、出力端子１０２ｕと、出力端子１０２ｖと、出力端子１０２ｗとを含む。ｎ個の出力端子１０２は、ｎ相の出力電圧とｎ相の出力電流とを出力する。本実施形態では、３つの出力端子１０２は、３相の出力電圧と３相の出力電流とを３相モータＭへ出力する。詳しくは、出力端子１０２ｕは、Ｕ相の出力電圧Ｖｕと、Ｕ相の出力電流Ｉｕとを３相モータＭへ出力する。出力端子１０２ｖは、Ｖ相の出力電圧Ｖｖと、Ｖ相の出力電流Ｉｖとを３相モータＭへ出力する。出力端子１０２ｗは、Ｗ相の出力電圧Ｖｗと、Ｗ相の出力電流Ｉｗとを３相モータＭへ出力する。 The motor drive circuit 100 converts DC power into n-phase AC power. n is the number of AC output phases and is an integer of 3 or more. In this embodiment, the motor drive circuit 100 converts DC power into three-phase AC power. The motor drive circuit 100 has n output terminals 102 . In this embodiment, the motor drive circuit 100 has three output terminals 102 . The three output terminals 102 include an output terminal 102u, an output terminal 102v, and an output terminal 102w. The n output terminals 102 output n-phase output voltages and n-phase output currents. In this embodiment, the three output terminals 102 output three-phase output voltages and three-phase output currents to the three-phase motor M. FIG. More specifically, the output terminal 102u outputs the U-phase output voltage Vu and the U-phase output current Iu to the three-phase motor M. Output terminal 102v outputs V-phase output voltage Vv and V-phase output current Iv to three-phase motor M. FIG. The output terminal 102w outputs the W-phase output voltage Vw and the W-phase output current Iw to the three-phase motor M.
　図２に示すように、モータ駆動回路１００は、第１電源端子Ｐと、第２電源端子Ｎと、コンデンサＣと、ｎ個の直列体１１２と、６つの温度センサ２０とを備える。本実施形態では、モータ駆動回路１００は、第１電源端子Ｐと、第２電源端子Ｎと、コンデンサＣと、３つの直列体１１２と、６つの温度センサ２０とを備える。より具体的には、本実施形態では、モータ駆動回路１００は、インバータ部１１０を備え、インバータ部１１０は、第１電源端子Ｐと、第２電源端子Ｎと、コンデンサＣと、３つの直列体１１２と、６つの温度センサ２０とを備える。インバータ部１１０は、直流電圧源Ｂをさらに備える。なお、直流電圧源Ｂは、インバータ部１１０の外部にあってもよい。 As shown in FIG. 2, the motor drive circuit 100 includes a first power terminal P, a second power terminal N, a capacitor C, n series bodies 112, and six temperature sensors 20. In this embodiment, the motor drive circuit 100 includes a first power terminal P, a second power terminal N, a capacitor C, three series bodies 112 and six temperature sensors 20 . More specifically, in this embodiment, the motor drive circuit 100 includes an inverter section 110. The inverter section 110 includes a first power terminal P, a second power terminal N, a capacitor C, and three series bodies. 112 and six temperature sensors 20 . Inverter section 110 further includes a DC voltage source B. FIG. Note that the DC voltage source B may be provided outside the inverter section 110 .
　第１電源端子Ｐには、第１の電圧Ｖ１が印加される。第１電源端子Ｐは、直流電圧源Ｂに接続されている。 A first voltage V1 is applied to the first power supply terminal P. A first power supply terminal P is connected to a DC voltage source B;
　第２電源端子Ｎには、第２の電圧Ｖ２が印加される。第２電源端子Ｎは、直流電圧源Ｂに接続されている。第２の電圧Ｖ２は、第１の電圧Ｖ１よりも低い。 A second voltage V2 is applied to the second power supply terminal N. A second power supply terminal N is connected to a DC voltage source B. As shown in FIG. The second voltage V2 is lower than the first voltage V1.
　コンデンサＣは、第１電源端子Ｐと第２電源端子Ｎとの間に接続される。 The capacitor C is connected between the first power terminal P and the second power terminal N.
　３つの直列体１１２には、２つの半導体スイッチング素子が直列に接続されている。半導体スイッチング素子は、例えば、ＩＧＢＴ（絶縁ゲートバイポーラトランジスタ）である。なお、半導体スイッチング素子は、電界効果トランジスタのような他のトランジスタであってもよい。３つの直列体１１２は、直列体１１２ｕと、直列体１１２ｖと、直列体１１２ｗとを含む。３つの直列体１１２は、互いに並列に接続されている。３つの直列体１１２の各々は、一端が第１電源端子Ｐに接続されている。３つの直列体１１２の各々は、他端が第２電源端子Ｎに接続されている。これらの半導体スイッチング素子にはそれぞれ、第１電源端子Ｐ側（紙面上側）をカソード、第２電源端子Ｎ側（紙面下側）をアノードとして、整流素子Ｄが並列に接続される。半導体スイッチング素子として電界効果トランジスタを用いる場合には、寄生ダイオードをこの整流素子として用いてもよい。 Two semiconductor switching elements are connected in series to the three series bodies 112 . The semiconductor switching element is, for example, an IGBT (insulated gate bipolar transistor). Note that the semiconductor switching element may be another transistor such as a field effect transistor. The three series bodies 112 include a series body 112u, a series body 112v, and a series body 112w. The three series bodies 112 are connected in parallel with each other. Each of the three series bodies 112 is connected to the first power terminal P at one end. Each of the three series bodies 112 is connected to the second power terminal N at the other end. A rectifying element D is connected in parallel to each of these semiconductor switching elements, with the first power supply terminal P side (upper side of the paper) as a cathode and the second power supply terminal N side (lower side of the paper) as an anode. If a field effect transistor is used as the semiconductor switching element, a parasitic diode may be used as this rectifying element.
　３つの直列体１１２の各々は、第１半導体スイッチング素子と、第２半導体スイッチング素子とを有する。詳しくは、直列体１１２ｕは、第１半導体スイッチング素子Ｕｐと、第２半導体スイッチング素子Ｕｎとを有する。直列体１１２ｖは、第１半導体スイッチング素子Ｖｐと、第２半導体スイッチング素子Ｖｎとを有する。直列体１１２ｗは、第１半導体スイッチング素子Ｗｐと、第２半導体スイッチング素子Ｗｎとを有する。 Each of the three series bodies 112 has a first semiconductor switching element and a second semiconductor switching element. Specifically, the series body 112u has a first semiconductor switching element Up and a second semiconductor switching element Un. Series body 112v has a first semiconductor switching element Vp and a second semiconductor switching element Vn. The series body 112w has a first semiconductor switching element Wp and a second semiconductor switching element Wn.
　第１半導体スイッチング素子Ｕｐ、第１半導体スイッチング素子Ｖｐおよび第１半導体スイッチング素子Ｗｐは、第１電源端子Ｐに接続される。換言すると、第１半導体スイッチング素子Ｕｐ、第１半導体スイッチング素子Ｖｐおよび第１半導体スイッチング素子Ｗｐは、高電圧側の半導体スイッチング素子である。 The first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp are connected to the first power supply terminal P. In other words, the first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp are semiconductor switching elements on the high voltage side.
　第２半導体スイッチング素子Ｕｎ、第２半導体スイッチング素子Ｖｎおよび第２半導体スイッチング素子Ｗｎは、第２電源端子Ｎに接続される。換言すると、第２半導体スイッチング素子Ｕｎ、第２半導体スイッチング素子Ｖｎおよび第２半導体スイッチング素子Ｗｎは、低電圧側の半導体スイッチング素子である。 The second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn are connected to the second power supply terminal N. In other words, the second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn are semiconductor switching elements on the low voltage side.
　第１半導体スイッチング素子と第２半導体スイッチング素子とは接続点１１４において接続されている。詳しくは、第１半導体スイッチング素子Ｕｐと、第２半導体スイッチング素子Ｕｎとは、接続点１１４ｕにおいて接続されている。第１半導体スイッチング素子Ｖｐと、第２半導体スイッチング素子Ｖｎとは、接続点１１４ｖにおいて接続されている。第１半導体スイッチング素子Ｗｐと、第２半導体スイッチング素子Ｗｎとは、接続点１１４ｗにおいて接続されている。 The first semiconductor switching element and the second semiconductor switching element are connected at the connection point 114 . Specifically, the first semiconductor switching element Up and the second semiconductor switching element Un are connected at a connection point 114u. The first semiconductor switching element Vp and the second semiconductor switching element Vn are connected at a connection point 114v. The first semiconductor switching element Wp and the second semiconductor switching element Wn are connected at a connection point 114w.
　３つの直列体１１２の各々における接続点１１４が、３つの出力端子１０２に接続されている。詳しくは、直列体１１２ｕにおける接続点１１４ｕが、出力端子１０２ｕに接続されている。直列体１１２ｖにおける接続点１１４ｖが、出力端子１０２ｖに接続されている。直列体１１２ｗにおける接続点１１４ｗが、出力端子１０２ｗに接続されている。 A connection point 114 in each of the three series bodies 112 is connected to the three output terminals 102 . Specifically, a connection point 114u in the series body 112u is connected to the output terminal 102u. A connection point 114v in the series body 112v is connected to the output terminal 102v. A connection point 114w in the series body 112w is connected to the output terminal 102w.
　第１半導体スイッチング素子Ｕｐ、第１半導体スイッチング素子Ｖｐおよび第１半導体スイッチング素子Ｗｐには、ＰＷＭ信号が入力される。ＰＷＭ信号は、信号生成部１２０から出力される。以下、本明細書において、第１半導体スイッチング素子Ｕｐに入力されるＰＷＭ信号を「ＵｐＰＷＭ信号」と記載することがある。また、第１半導体スイッチング素子Ｖｐに入力されるＰＷＭ信号を「ＶｐＰＷＭ信号」と記載することがある。第１半導体スイッチング素子Ｗｐに入力されるＰＷＭ信号を「ＷｐＰＷＭ信号」と記載することがある。第１半導体スイッチング素子Ｕｐ、第１半導体スイッチング素子Ｖｐおよび第１半導体スイッチング素子Ｗｐは、交流出力の周波数よりも高い周波数でオンとオフとが切り替えられる。例えば、第１半導体スイッチング素子Ｕｐ、第１半導体スイッチング素子Ｖｐおよび第１半導体スイッチング素子Ｗｐは、それぞれ、ＵｐＰＷＭ信号、ＶｐＰＷＭ信号およびＷｐＰＷＭ信号がＨＩＧＨレベルの場合に、オンとなる。一方、第１半導体スイッチング素子Ｕｐ、第１半導体スイッチング素子Ｖｐおよび第１半導体スイッチング素子Ｗｐは、それぞれ、ＵｐＰＷＭ信号、ＶｐＰＷＭ信号およびＷｐＰＷＭ信号がＬＯＷレベルの場合に、オフとなる。 A PWM signal is input to the first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp. A PWM signal is output from the signal generator 120 . Hereinafter, in this specification, the PWM signal input to the first semiconductor switching element Up may be referred to as "UpPWM signal". Also, the PWM signal input to the first semiconductor switching element Vp may be referred to as "Vp PWM signal". A PWM signal input to the first semiconductor switching element Wp may be referred to as a "Wp PWM signal". The first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp are switched on and off at a frequency higher than the frequency of the AC output. For example, the first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp are turned on when the UpPWM signal, the VpPWM signal, and the WpPWM signal are at HIGH level, respectively. On the other hand, the first semiconductor switching element Up, the first semiconductor switching element Vp and the first semiconductor switching element Wp are turned off when the UpPWM signal, the VpPWM signal and the WpPWM signal are at LOW level, respectively.
　第２半導体スイッチング素子Ｕｎ、第２半導体スイッチング素子Ｖｎおよび第２半導体スイッチング素子Ｗｎには、ＰＷＭ信号が入力される。ＰＷＭ信号は、信号生成部１２０から出力される。以下、本明細書において、第２半導体スイッチング素子Ｕｎに入力されるＰＷＭ信号を「ＵｎＰＷＭ信号」と記載することがある。また、第２半導体スイッチング素子Ｖｎに入力されるＰＷＭ信号を「ＶｎＰＷＭ信号」と記載することがある。第２半導体スイッチング素子Ｗｎに入力されるＰＷＭ信号を「ＷｎＰＷＭ信号」と記載することがある。第２半導体スイッチング素子Ｕｎ、第２半導体スイッチング素子Ｖｎおよび第２半導体スイッチング素子Ｗｎは、交流出力の周波数よりも高い周波数でオンとオフとが切り替えられる。例えば、第２半導体スイッチング素子Ｕｎ、第２半導体スイッチング素子Ｖｎおよび第２半導体スイッチング素子Ｗｎは、それぞれ、ＵｎＰＷＭ信号、ＶｎＰＷＭ信号およびＷｎＰＷＭ信号がＨＩＧＨレベルの場合に、オンとなる。一方、第２半導体スイッチング素子Ｕｎ、第２半導体スイッチング素子Ｖｎおよび第２半導体スイッチング素子Ｗｎは、それぞれ、ＵｎＰＷＭ信号、ＶｎＰＷＭ信号およびＷｎＰＷＭ信号がＬＯＷレベルの場合に、オフとなる。 A PWM signal is input to the second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn. A PWM signal is output from the signal generator 120 . Hereinafter, in this specification, the PWM signal input to the second semiconductor switching element Un may be referred to as "UnPWM signal". Also, the PWM signal input to the second semiconductor switching element Vn may be referred to as "Vn PWM signal". A PWM signal input to the second semiconductor switching element Wn may be referred to as a "Wn PWM signal". The second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn are switched on and off at a frequency higher than the frequency of the AC output. For example, the second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn are turned on when the UnPWM signal, the VnPWM signal, and the WnPWM signal are at HIGH level, respectively. On the other hand, the second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn are turned off when the UnPWM signal, the VnPWM signal, and the WnPWM signal are at LOW level, respectively.
　図１に示すように、信号生成部１２０は、キャリア生成部１２２と、電圧指令値生成部１２４と、比較部１２６とを有する。信号生成部１２０は、ＣＰＵ（Ｃｅｎｔｒａｌ　Ｐｒｏｃｅｓｓｉｎｇ　Ｕｎｉｔ）のようなプロセッサー、およびＡＳＩＣ（Ａｐｐｌｉｃａｔｉｏｎ　Ｓｐｅｃｉｆｉｃ　Ｉｎｔｅｇｒａｔｅｄ　Ｃｉｒｃｕｉｔ）等によって構成されるハードウェア回路である。そして、信号生成部１２０のプロセッサーは、記憶装置に記憶されたコンピュータープログラムを実行することによって、キャリア生成部１２２と、電圧指令値生成部１２４と、比較部１２６として機能する。 As shown in FIG. 1, the signal generation section 120 has a carrier generation section 122, a voltage command value generation section 124, and a comparison section 126. The signal generator 120 is a hardware circuit configured by a processor such as a CPU (Central Processing Unit) and an ASIC (Application Specific Integrated Circuit). The processor of signal generation unit 120 functions as carrier generation unit 122, voltage command value generation unit 124, and comparison unit 126 by executing computer programs stored in the storage device.
　信号生成部１２０は、インバータ部１１０を制御する。具体的には、信号生成部１２０は、ＰＷＭ信号を生成してＰＷＭ信号を出力することによって、インバータ部１１０を制御する。より具体的には、信号生成部１２０は、３つの直列体１１２のそれぞれに入力するＰＷＭ信号を生成する。 The signal generation section 120 controls the inverter section 110 . Specifically, the signal generation unit 120 controls the inverter unit 110 by generating a PWM signal and outputting the PWM signal. More specifically, signal generator 120 generates a PWM signal to be input to each of three serial bodies 112 .
　キャリア生成部１２２は、キャリア信号を生成する。キャリア信号は、例えば、三角波である。なお、キャリア信号は、鋸波であってもよい。 The carrier generator 122 generates a carrier signal. A carrier signal is, for example, a triangular wave. Note that the carrier signal may be a sawtooth wave.
　電圧指令値生成部１２４は、電圧指令値を生成する。電圧指令値は、モータ駆動回路１００から出力する電圧値に相当する。すなわち、電圧指令値生成部１２４は、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗに応じた電圧値を電圧指令値として生成する。 The voltage command value generation unit 124 generates a voltage command value. A voltage command value corresponds to a voltage value output from the motor drive circuit 100 . That is, voltage command value generation unit 124 generates voltage values corresponding to output voltage Vu, output voltage Vv, and output voltage Vw as voltage command values.
　比較部１２６は、キャリア信号と、電圧指令値とを比較することによってＰＷＭ信号を生成する。 The comparator 126 generates a PWM signal by comparing the carrier signal and the voltage command value.
　６つの温度センサ２０は、温度センサ２１ｕと、温度センサ２１ｖと、温度センサ２１ｗと、温度センサ２２ｕと、温度センサ２２ｖと、温度センサ２２ｗとを含む。６つの温度センサ２０は、半導体スイッチング素子の近傍に配置される。６つの温度センサ２０は、半導体スイッチング素子の温度を検出する。詳しくは、温度センサ２１ｕは、第１半導体スイッチング素子Ｕｐの近傍に配置される。温度センサ２１ｕは、第１半導体スイッチング素子Ｕｐの温度を検出する。温度センサ２１ｖは、第１半導体スイッチング素子Ｖｐの近傍に配置される。温度センサ２１ｖは、第１半導体スイッチング素子Ｖｐの温度を検出する。温度センサ２１ｗは、第１半導体スイッチング素子Ｗｐの近傍に配置される。温度センサ２１ｗは、第１半導体スイッチング素子Ｗｐの温度を検出する。温度センサ２２ｕは、第２半導体スイッチング素子Ｕｎの近傍に配置される。温度センサ２２ｕは、第２半導体スイッチング素子Ｕｎの温度を検出する。温度センサ２２ｖは、第２半導体スイッチング素子Ｖｎの近傍に配置される。温度センサ２２ｖは、第２半導体スイッチング素子Ｖｎの温度を検出する。温度センサ２２ｗは、第２半導体スイッチング素子Ｗｎの近傍に配置される。温度センサ２２ｗは、第２半導体スイッチング素子Ｗｎの温度を検出する。 The six temperature sensors 20 include a temperature sensor 21u, a temperature sensor 21v, a temperature sensor 21w, a temperature sensor 22u, a temperature sensor 22v, and a temperature sensor 22w. Six temperature sensors 20 are arranged in the vicinity of the semiconductor switching elements. Six temperature sensors 20 detect the temperature of the semiconductor switching elements. Specifically, the temperature sensor 21u is arranged near the first semiconductor switching element Up. The temperature sensor 21u detects the temperature of the first semiconductor switching element Up. The temperature sensor 21v is arranged near the first semiconductor switching element Vp. The temperature sensor 21v detects the temperature of the first semiconductor switching element Vp. The temperature sensor 21w is arranged near the first semiconductor switching element Wp. The temperature sensor 21w detects the temperature of the first semiconductor switching element Wp. The temperature sensor 22u is arranged near the second semiconductor switching element Un. The temperature sensor 22u detects the temperature of the second semiconductor switching element Un. The temperature sensor 22v is arranged near the second semiconductor switching element Vn. Temperature sensor 22v detects the temperature of second semiconductor switching element Vn. The temperature sensor 22w is arranged near the second semiconductor switching element Wn. The temperature sensor 22w detects the temperature of the second semiconductor switching element Wn.
　次に、図３Ａおよび図３Ｂを参照して、出力電圧について説明する。図３Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図３Ｂは、スイッチング損失を示す図である。３相すべてをスイッチングする３相変調の場合のスイッチング素子１つあたりのスイッチング損失を１とした場合の相対値として、各素子のスイッチング損失を表している。図３Ａは、本発明の実施形態に係る出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗの波形例１を示す。 Next, the output voltage will be described with reference to FIGS. 3A and 3B. FIG. 3A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 3B is a diagram showing switching losses. The switching loss of each element is shown as a relative value when the switching loss per switching element is 1 in the case of three-phase modulation in which all three phases are switched. FIG. 3A shows waveform example 1 of the output voltage Vu, the output voltage Vv, and the output voltage Vw according to the embodiment of the present invention.
　図３Ａにおいて、出力電圧Ｖｕを実線で示しており、出力電圧Ｖｖを破線で示しており、出力電圧Ｖｗを一点鎖線で示している。図３Ａの縦軸は入力電圧Ｖ１－Ｖ２で規格化した電圧値を表しており、各相の出力電圧は０～１の範囲の値をとる。出力電圧０とは、出力電圧がＶ２に実質的に一致する状態であり、出力電圧１とは、出力電圧がＶ１に実質的に一致する状態である。またこの値は、ＰＷＭ周期に対する各相の第１半導体スイッチング素子のオン時間の比率であるデューティ値も表している。第２半導体スイッチング素子をスイッチングする場合は、１から縦軸の値を引いたものが、ＰＷＭ周期に対する第２半導体スイッチング素子のオン時間の比率となる。第１半導体スイッチング素子と第２半導体スイッチング素子との両方をスイッチングする場合は、両者が同時にオンすることを防ぐために適当なデッドタイムを設けた上で、相補的にスイッチングを行う。図３Ａの横軸は、モータの電気回転角を表しており、単位は度である。 In FIG. 3A, the output voltage Vu is indicated by a solid line, the output voltage Vv is indicated by a dashed line, and the output voltage Vw is indicated by a dashed line. The vertical axis of FIG. 3A represents the voltage value normalized by the input voltage V1-V2, and the output voltage of each phase takes a value in the range of 0-1. Output voltage 0 is the state in which the output voltage substantially matches V2, and output voltage 1 is the state in which the output voltage substantially matches V1. This value also represents the duty value, which is the ratio of the ON time of the first semiconductor switching element of each phase to the PWM cycle. When switching the second semiconductor switching element, the value obtained by subtracting the value on the vertical axis from 1 is the ratio of the ON time of the second semiconductor switching element to the PWM cycle. When both the first semiconductor switching element and the second semiconductor switching element are switched, complementary switching is performed after providing an appropriate dead time to prevent both from being turned on at the same time. The horizontal axis of FIG. 3A represents the electrical rotation angle of the motor in degrees.
　図３Ａを参照して、本発明の実施形態に係る出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗの波形例１について説明する。 A waveform example 1 of the output voltage Vu, the output voltage Vv, and the output voltage Vw according to the embodiment of the present invention will be described with reference to FIG. 3A.
　図３Ａに示すように、波形例１は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例１は、電気角３０度～電気角１５０度において、いずれか１相の出力が１に固定される波形である。また、電気角０度～電気角３０度および電気角１５０度～電気角３６０度において、いずれか１相の出力が０に固定される波形である。本明細書において、いずれか１相の出力が１に固定される期間を、ハイサイドオン適用期間Ｔ３と記載することがある。また、本明細書において、いずれか１相の出力が０に固定される期間を、ロウサイドオン適用期間Ｔ４と記載することがある。波形例１では、電気角３０度～電気角１５０度において、ハイサイドオン適用期間Ｔ３である。また、波形例１では、電気角０度～電気角３０度および電気角１５０度～電気角３６０度において、ロウサイドオン適用期間Ｔ４である。出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗの２相の差分が正弦波となっていることが好ましい。したがって、出力端子間電圧としては正弦波を出力することができる。その結果、例えばモータを駆動する場合にはノイズおよびトルクムラの少ない動作が可能となる。例えば、２π／ｎずつの位相差を有する正弦波から共通のオフセット波形を差し引くことで、各相の出力電圧波形が得られ、この各相の出力電圧波形を電圧指令値とすることができる。 As shown in FIG. 3A, in waveform example 1, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval according to the electrical angle, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, waveform example 1 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 30 degrees to 150 degrees. Also, the waveform is such that the output of any one phase is fixed to 0 at an electrical angle of 0 to 30 electrical degrees and at an electrical angle of 150 to 360 electrical degrees. In this specification, the period during which the output of any one phase is fixed to 1 may be referred to as a high-side-on application period T3. Also, in this specification, the period during which the output of any one phase is fixed to 0 may be referred to as a low-side-on application period T4. In waveform example 1, the high-side-on application period is T3 at an electrical angle of 30 degrees to 150 electrical degrees. Further, in waveform example 1, the low side-on application period T4 occurs at an electrical angle of 0 to 30 electrical degrees and at an electrical angle of 150 to 360 electrical degrees. It is preferable that the difference between the two phases of the output voltage Vu, the output voltage Vv, and the output voltage Vw is a sine wave. Therefore, a sine wave can be output as the voltage between the output terminals. As a result, for example, when driving a motor, it is possible to operate with little noise and torque unevenness. For example, by subtracting a common offset waveform from sine waves having a phase difference of 2π/n each, an output voltage waveform for each phase can be obtained, and this output voltage waveform for each phase can be used as a voltage command value.
　図３Ａに示すように、ｎ相の交流出力の１周期の間に、交流出力のうち少なくとも１相が、第１オン固定期間Ｔ１と、第２オン固定期間Ｔ２とを有する。第１オン固定期間Ｔ１は、第１半導体スイッチング素子がオンに固定される期間である。第２オン固定期間Ｔ２は、第２半導体スイッチング素子がオンに固定される期間である。 As shown in FIG. 3A, during one cycle of the n-phase AC output, at least one phase of the AC output has a first fixed ON period T1 and a second fixed ON period T2. The first fixed on period T1 is a period in which the first semiconductor switching element is fixed on. The second fixed on period T2 is a period during which the second semiconductor switching element is fixed on.
　波形例１では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｕを含む。第１オン固定期間Ｔ１ｕは、第１半導体スイッチング素子Ｕｐがオンに固定される期間である。波形例１では、電気角３０度～電気角１５０度が第１オン固定期間Ｔ１ｕである。 In Waveform Example 1, the first fixed ON period T1 includes the first fixed ON period T1u. The first fixed on period T1u is a period in which the first semiconductor switching element Up is fixed on. In Waveform Example 1, the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees.
　第１オン固定期間Ｔ１は、ｎ相のうち１相のみの第１半導体スイッチング素子がオン固定となり、ｎ相のうち他の相全てにおいて、第１半導体スイッチング素子または第２半導体スイッチング素子の少なくとも一方がスイッチングする期間を示す。波形例１では、第１オン固定期間Ｔ１ｕにおいて、３相のうちＵ相の第１半導体スイッチング素子Ｕｐのみがオン固定となり、３相のうちＶ相の第１半導体スイッチング素子Ｖｐまたは第２半導体スイッチング素子Ｖｎの少なくとも一方、およびＷ相の第１半導体スイッチング素子Ｗｐまたは第２半導体スイッチング素子Ｗｎの少なくとも一方がスイッチングする。 In the first fixed ON period T1, only one of the n phases of the first semiconductor switching element is fixed on, and in all of the other n phases, at least one of the first semiconductor switching element and the second semiconductor switching element is fixed. indicates the switching period. In waveform example 1, in the first fixed on period T1u, only the U-phase first semiconductor switching element Up of the three phases is fixed on, and the V-phase first semiconductor switching element Vp or the second semiconductor switching element Vp of the three phases is fixed. At least one of the elements Vn and at least one of the W-phase first semiconductor switching element Wp or the second semiconductor switching element Wn switches.
　波形例１では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖと、第２オン固定期間Ｔ２ｗとを含む。波形例１では、電気角２１０度～電気角３３０度が第２オン固定期間Ｔ２ｕである。波形例１では、電気角０度～電気角３０度および電気角３３０度～電気角３６０度が第２オン固定期間Ｔ２ｖである。波形例１では、電気角１５０度～電気角２１０度が第２オン固定期間Ｔ２ｗである。 In Waveform Example 1, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In Waveform Example 1, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In waveform example 1, the second fixed ON period T2v is from 0 electrical angle to 30 electrical degrees and from 330 electrical degrees to 360 electrical degrees. In Waveform Example 1, the second fixed ON period T2w is from 150 electrical degrees to 210 electrical degrees.
　第２オン固定期間Ｔ２は、ｎ相のうち１相のみの第２半導体スイッチング素子がオン固定となり、ｎ相のうち他の相全てにおいて、第１半導体スイッチング素子または第２半導体スイッチング素子の少なくとも一方がスイッチングする期間を示す。波形例１では、第２オン固定期間Ｔ２ｕにおいて、３相のうちＵ相の第２半導体スイッチング素子Ｕｎのみがオン固定となり、３相のうちＶ相の第１半導体スイッチング素子Ｖｐまたは第２半導体スイッチング素子Ｖｎの少なくとも一方、およびＷ相の第１半導体スイッチング素子Ｗｐまたは第２半導体スイッチング素子Ｗｎの少なくとも一方がスイッチングする。波形例１では、第２オン固定期間Ｔ２ｖにおいて、３相のうちＶ相の第２半導体スイッチング素子Ｖｎのみがオン固定となり、３相のうちＵ相の第１半導体スイッチング素子Ｕｐまたは第２半導体スイッチング素子Ｕｎの少なくとも一方、およびＷ相の第１半導体スイッチング素子Ｗｐまたは第２半導体スイッチング素子Ｗｎの少なくとも一方がスイッチングする。波形例１では、第２オン固定期間Ｔ２ｗにおいて、３相のうちＷ相の第２半導体スイッチング素子Ｗｎのみがオン固定となり、３相のうちＵ相の第１半導体スイッチング素子Ｕｐまたは第２半導体スイッチング素子Ｕｎの少なくとも一方、およびＶ相の第１半導体スイッチング素子Ｖｐまたは第２半導体スイッチング素子Ｖｎの少なくとも一方がスイッチングする。 In the second fixed on period T2, only one of the n phases of the second semiconductor switching element is fixed on, and at least one of the first semiconductor switching element and the second semiconductor switching element is set in all the other phases of the n phases. indicates the switching period. In waveform example 1, in the second fixed on period T2u, only the U-phase second semiconductor switching element Un among the three phases is fixed on, and the V-phase first semiconductor switching element Vp or the second semiconductor switching element Vp among the three phases is fixed. At least one of the elements Vn and at least one of the W-phase first semiconductor switching element Wp or the second semiconductor switching element Wn switches. In the waveform example 1, only the V-phase second semiconductor switching element Vn of the three phases is fixed on during the second fixed ON period T2v, and the U-phase first semiconductor switching element Up or the second semiconductor switching element Vn of the three phases is fixed. At least one of the elements Un and at least one of the W-phase first semiconductor switching element Wp or second semiconductor switching element Wn switches. In waveform example 1, only the W-phase second semiconductor switching element Wn among the three phases is fixed to the ON state during the second fixed ON period T2w, and the U-phase first semiconductor switching element Up or the second semiconductor switching element Wn among the three phases is turned ON. At least one of the elements Un and at least one of the V-phase first semiconductor switching element Vp or second semiconductor switching element Vn switches.
　交流出力の１周期は複数の期間に分割され、複数の期間はそれぞれ、いずれかの相の第１オン固定期間またはいずれかの相の第２オン固定期間である。詳しくは、波形例１では、電気角０度～電気角３０度が第２オン固定期間Ｔ２ｖである。波形例１では、電気角３０度～電気角１５０度が第１オン固定期間Ｔ１ｕである。波形例１では、電気角１５０度～電気角２１０度が第２オン固定期間Ｔ２ｗである。波形例１では、電気角２１０度～電気角３３０度が第２オン固定期間Ｔ２ｕである。波形例１では、電気角３３０度～電気角３６０度が第２オン固定期間Ｔ２ｖである。したがって、常に一相のスイッチングを停止するので、効果的な昇温抑制が可能となり、インバータの信頼性が高まる。 　One cycle of the AC output is divided into a plurality of periods, and each of the plurality of periods is the first fixed ON period of one of the phases or the second fixed ON period of one of the phases. Specifically, in Waveform Example 1, the second fixed ON period T2v is between an electrical angle of 0 degree and an electrical angle of 30 degrees. In Waveform Example 1, the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees. In Waveform Example 1, the second fixed ON period T2w is from 150 electrical degrees to 210 electrical degrees. In Waveform Example 1, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In Waveform Example 1, the second fixed ON period T2v is from 330 electrical degrees to 360 electrical degrees. Therefore, since the switching of one phase is always stopped, temperature rise can be effectively suppressed, and the reliability of the inverter is enhanced.
　モータ駆動回路１００は、保護動作モードを有する。保護動作モードは、第１オン固定期間Ｔ１と第２オン固定期間Ｔ２との少なくとも一方を有する。保護動作モードにおいて、ｎ相のうち少なくとも１相において、第１オン固定期間Ｔ１が、他のいずれか１相の第１オン固定期間Ｔ１と異なるか、または、第２オン固定期間Ｔ２が、他のいずれか１相の第２オン固定期間Ｔ２と異なる。他のいずれか１相が第１オン固定期間Ｔ１および第２オン固定期間Ｔ２を有さない場合もこれに含まれる。 The motor drive circuit 100 has a protection operation mode. The protection operation mode has at least one of the first fixed ON period T1 and the second fixed ON period T2. In the protection operation mode, in at least one of the n phases, the first fixed ON period T1 is different from the first fixed ON period T1 of any one of the other phases, or the second fixed ON period T2 is different from the first fixed ON period T1 of any other phase. is different from the second on-fixed period T2 of any one phase. This also includes the case where any other phase does not have the first fixed ON period T1 and the second fixed ON period T2.
　波形例１では、３相のうちＵ相において、第１オン固定期間Ｔ１ｕが、第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗと異なる。詳しくは、波形例１では、第１オン固定期間Ｔ１ｕが１２０度であるのに対し、第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗは無い。すなわち、波形例１では、第１オン固定期間Ｔ１ｕが第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗよりも長い。したがって、図３Ｂに示すように、Ｕ相の第１半導体スイッチング素子Ｕｐ（Ｈ（ハイサイド））のスイッチング損失がＶ相およびＷ相に比べて小さくなっている。 In waveform example 1, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 1, the first fixed ON period T1u is 120 degrees, but there is no first fixed ON period T1v and no first fixed ON period T1w. That is, in Waveform Example 1, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 3B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
　波形例１では、３相のうちＵ相において、第２オン固定期間Ｔ２ｕが、第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗと異なる。詳しくは、波形例１では、第２オン固定期間Ｔ２ｕが１２０度であるのに対し、第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗは６０度である。すなわち、波形例１では、第２オン固定期間Ｔ２ｕが第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗよりも長い。したがって、図３Ｂに示すように、Ｕ相の第２半導体スイッチング素子Ｕｎ（Ｌ（ロウサイド））のスイッチング損失がＶ相およびＷ相に比べて小さくなっている。 In waveform example 1, the second fixed ON period T2u differs from the second fixed ON period T2v and the second fixed ON period T2w in the U phase among the three phases. Specifically, in Waveform Example 1, the second fixed ON period T2u is 120 degrees, while the second fixed ON period T2v and the second fixed ON period T2w are 60 degrees. That is, in Waveform Example 1, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 3B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
　以上、図１～図３Ｂを参照して説明したように、波形例１では、保護動作モードにおいて、ｎ相のうち少なくとも１相において、第１オン固定期間Ｔ１が、他の相の第１オン固定期間Ｔ１と異なる。したがって、他の相の第１オン固定期間Ｔ１よりも長い第１オン固定期間を有する相の第１半導体スイッチング素子の発熱を抑制することができる。また、ｎ相のうち少なくとも１相において、第２オン固定期間Ｔ２が、他の相の第２オン固定期間Ｔ２と異なる。したがって、他の相の第２オン固定期間Ｔ２よりも長い第２オン固定期間を有する相の第２半導体スイッチング素子の発熱を抑制することができる。また特に、波形例１では、少なくとも１相において、第１オン固定期間Ｔ１が、他の相の第１オン固定期間Ｔ１と異なり、かつ少なくとも１相において、第２オン固定期間Ｔ２が、他の相の第２オン固定期間Ｔ２と異なる。したがって、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。例えば、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子とが、近傍に発熱部品が存在する、あるいは放熱効率の悪い位置に配置されている、等の原因により、スイッチング動作により温度上昇が起こりやすい場合、波形例１の手法によってこれら２つの素子のスイッチング発熱を抑制することで、これら２素子が過度に温度上昇することを防ぎ、電力変換器（インバータ）の信頼性を高めることができる。波形例１では、Ｕ相の第１半導体スイッチング素子Ｕｐと、Ｕ相の第２半導体スイッチング素子Ｕｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 1 to 3B, in the waveform example 1, in the protection operation mode, in at least one of the n phases, the first fixed ON period T1 is set to the first ON period of the other phases. It differs from the fixed period T1. Therefore, heat generation of the first semiconductor switching element of the phase having the first fixed ON period longer than the first fixed ON period T1 of the other phase can be suppressed. Moreover, in at least one of the n phases, the second fixed ON period T2 is different from the second fixed ON periods T2 of the other phases. Therefore, heat generation of the second semiconductor switching element of the phase having the second fixed ON period longer than the second fixed ON period T2 of the other phase can be suppressed. In particular, in Waveform Example 1, in at least one phase, the first fixed ON period T1 is different from the first fixed ON periods T1 of other phases, and in at least one phase, the second fixed ON period T2 is different from that of the other phase. It is different from the second on-fixed period T2 of the phase. Therefore, by simultaneously suppressing the heat generation of the first semiconductor switching element of a certain phase and the heat generation of the second semiconductor switching element of a certain phase, temperature rise of the power converter (inverter) can be suppressed and reliability can be improved. For example, the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase may have heat-generating components in their vicinity, or may be arranged in positions with poor heat dissipation efficiency. If the temperature rise is likely to occur due to the power converter (inverter), the switching heat generation of these two elements can be suppressed using the method of Waveform Example 1 to prevent the temperature of these two elements from rising excessively and improve the reliability of the power converter (inverter). can be enhanced. In waveform example 1, the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un can be suppressed at the same time.
　また、波形例１では、図３Ｂに示すように、Ｖ相の第２オン固定期間Ｔ２ｖおよびＷ相の第２オン固定期間Ｔ２ｗを設けることにより、Ｖ相の第２半導体スイッチング素子Ｖｎと、Ｗ相の第２半導体スイッチング素子Ｗｎとの発熱についても同時に抑えることができる。このため、Ｕ相が最も温度上昇しやすく、続いて他の相の第２半導体スイッチング素子が温度上昇しやすい環境にある場合、これらの素子の過熱を防止し信頼性を高める。 Further, in the waveform example 1, as shown in FIG. 3B, by providing the V-phase second fixed ON period T2v and the W-phase second fixed ON period T2w, the V-phase second semiconductor switching element Vn and the W Heat generation with the second semiconductor switching element Wn of the phase can also be suppressed at the same time. Therefore, when the temperature of the U phase is most likely to rise and the temperature of the second semiconductor switching elements of the other phases is likely to rise next, overheating of these elements is prevented to improve reliability.
　また、いずれか１相の第１オン固定期間が他の相の第１オン固定期間よりも長く、且つ、いずれか１相の第２オン固定期間が他の相の第２オン固定期間よりも長い。したがって、冷却水路の問題などで特定の相の温度が問題となる場合、その相の発熱を抑制できるので、インバータの信頼性が高まる。あるいは、ストールが発生してある相の第１半導体スイッチング素子と別の相の第２半導体スイッチング素子に連続的に電流が流れ温度上昇した場合、ストールを脱して動作を開始する際にこの動作を行うことで、ストール下で温度上昇した半導体スイッチング素子の発熱を抑え、速やかに温度を下げることができるので、インバータの信頼性が高まる。 Further, the first fixed ON period of any one phase is longer than the first fixed ON period of the other phase, and the second fixed ON period of any one phase is longer than the second fixed ON period of the other phase. long. Therefore, when the temperature of a specific phase becomes a problem due to a problem in the cooling water passage or the like, the heat generation of that phase can be suppressed, thereby increasing the reliability of the inverter. Alternatively, when a stall occurs and current continuously flows through the first semiconductor switching element of a certain phase and the second semiconductor switching element of another phase and the temperature rises, this operation is performed when exiting the stall and starting operation. By doing so, it is possible to suppress the heat generation of the semiconductor switching elements whose temperature has risen under the stall condition, and to quickly lower the temperature, thereby increasing the reliability of the inverter.
　図４～図１５Ｂを参照して、本発明の実施形態に係る波形例についてさらに説明する。図４は、波形例とスイッチング損失との関係を示す表である。図４において、ＵＨは、Ｕ相の第１半導体スイッチング素子Ｕｐのスイッチング損失を示す。ＵＬは、Ｕ相の第２半導体スイッチング素子Ｕｎのスイッチング損失を示す。ＶＨは、Ｖ相の第１半導体スイッチング素子Ｖｐのスイッチング損失を示す。ＶＬは、Ｖ相の第２半導体スイッチング素子Ｖｎのスイッチング損失を示す。ＷＨは、Ｗ相の第１半導体スイッチング素子Ｗｐのスイッチング損失を示す。ＷＬは、Ｗ相の第２半導体スイッチング素子Ｗｎのスイッチング損失を示す。 Examples of waveforms according to embodiments of the present invention will be further described with reference to FIGS. 4 to 15B. FIG. 4 is a table showing the relationship between waveform examples and switching loss. In FIG. 4, UH represents the switching loss of the U-phase first semiconductor switching element Up. UL represents the switching loss of the U-phase second semiconductor switching element Un. VH represents the switching loss of the V-phase first semiconductor switching element Vp. VL represents the switching loss of the V-phase second semiconductor switching element Vn. WH represents the switching loss of the W-phase first semiconductor switching element Wp. WL represents the switching loss of the W-phase second semiconductor switching element Wn.
　図４に示すように、波形例１～波形例１２では、ＵＨが０．１３であり、ＵＬが０．１３である、すなわち、波形例１～波形例１２では、Ｕ相の第１半導体スイッチング素子ＵｐおよびＵ相の第２半導体スイッチング素子Ｕｎのスイッチング損失が少ない波形例である。つまり、波形例１～波形例１２は、Ｕ相の第１半導体スイッチング素子ＵｐおよびＵ相の第２半導体スイッチング素子Ｕｎを保護できる波形例である。本明細書において、ある相（例えばＵ相）の第１半導体スイッチング素子（例えばＵｐ）および同一相の第２半導体スイッチング素子（例えばＵｎ）を保護できる波形を、ＵＨ＿ＵＬ保護波形と記載することがある。 As shown in FIG. 4, in waveform examples 1 to 12, UH is 0.13 and UL is 0.13. This is a waveform example in which the switching loss of the element Up and the U-phase second semiconductor switching element Un is small. That is, waveform examples 1 to 12 are waveform examples capable of protecting the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un. In this specification, a waveform capable of protecting a first semiconductor switching element (eg Up) of a certain phase (eg U phase) and a second semiconductor switching element (eg Un) of the same phase may be referred to as a UH_UL protection waveform. .
　図５Ａおよび図５Ｂを参照して、波形例２について説明する。図５Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図５Ｂは、スイッチング損失を示す図である。 Waveform example 2 will be described with reference to FIGS. 5A and 5B. FIG. 5A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 5B is a diagram showing switching losses.
　図５Ａに示すように、波形例２は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例２は、電気角０度～電気角１８０度において、いずれか１相の出力が１に固定される波形である。また、波形例２は、電気角１８０度～電気角３６０度において、いずれか１相の出力が０に固定される波形である。波形例２では、電気角０度～電気角１８０度において、ハイサイドオン適用期間Ｔ３である。また、波形例２では、電気角１８０度～電気角３６０度において、ロウサイドオン適用期間Ｔ４である。 As shown in FIG. 5A, in waveform example 2, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. More specifically, waveform example 2 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 0 degree to 180 degrees. Waveform example 2 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 180 degrees to 360 degrees. In waveform example 2, the high-side-on application period T3 is from 0 electrical angle to 180 electrical degrees. In waveform example 2, the low-side-on application period T4 occurs at an electrical angle of 180 degrees to 360 degrees.
　波形例２では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｕと、第１オン固定期間Ｔ１ｖと、第１オン固定期間Ｔ１ｗとを含む。波形例２では、電気角３０度～電気角１５０度が第１オン固定期間Ｔ１ｕである。波形例２では、電気角１５０度～電気角１８０度が第１オン固定期間Ｔ１ｖである。波形例２では、電気角０度～電気角３０度が第１オン固定期間Ｔ１ｗである。 In Waveform Example 2, the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w. In Waveform Example 2, the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees. In Waveform Example 2, the first fixed ON period T1v is between 150 electrical degrees and 180 electrical degrees. In Waveform Example 2, the first ON fixed period T1w is from an electrical angle of 0 degree to an electrical angle of 30 degrees.
　波形例２では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖと、第２オン固定期間Ｔ２ｗとを含む。波形例２では、電気角２１０度～電気角３３０度が第２オン固定期間Ｔ２ｕである。波形例２では、電気角３３０度～電気角３６０度が第２オン固定期間Ｔ２ｖである。波形例２では、電気角１８０度～電気角２１０度が第２オン固定期間Ｔ２ｗである。 In Waveform Example 2, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 2, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In Waveform Example 2, the second fixed ON period T2v is from 330 electrical degrees to 360 electrical degrees. In Waveform Example 2, the second fixed ON period T2w is between 180 electrical degrees and 210 electrical degrees.
　波形例２では、３相のうちＵ相において、第１オン固定期間Ｔ１ｕが、第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗと異なる。詳しくは、波形例２では、第１オン固定期間Ｔ１ｕが１２０度であるのに対し、第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗは３０度である。すなわち、波形例２では、第１オン固定期間Ｔ１ｕが第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗよりも長い。したがって、図５Ｂに示すように、Ｕ相の第１半導体スイッチング素子Ｕｐ（Ｈ（ハイサイド））のスイッチング損失がＶ相およびＷ相に比べて小さくなっている。 In waveform example 2, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 2, the first fixed ON period T1u is 120 degrees, while the first fixed ON period T1v and the first fixed ON period T1w are 30 degrees. That is, in Waveform Example 2, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 5B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
　波形例２では、第２オン固定期間Ｔ２ｕが、第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗと異なる。詳しくは、波形例２では、第２オン固定期間Ｔ２ｕが１２０度であるのに対し、第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗは３０度である。すなわち、波形例２では、第２オン固定期間Ｔ２ｕが第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗよりも長い。したがって、図５Ｂに示すように、Ｕ相の第２半導体スイッチング素子Ｕｎ（Ｌ（ロウサイド））のスイッチング損失がＶ相およびＷ相に比べて小さくなっている。 In waveform example 2, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in Waveform Example 2, the second fixed ON period T2u is 120 degrees, while the second fixed ON period T2v and the second fixed ON period T2w are 30 degrees. That is, in Waveform Example 2, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 5B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
　以上、図５Ａおよび図５Ｂを参照して説明したように、波形例２においても、波形例１と同様に、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。波形例２では、Ｕ相の第１半導体スイッチング素子Ｕｐと、Ｕ相の第２半導体スイッチング素子Ｕｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 5A and 5B, in waveform example 2 as well as in waveform example 1, the heat generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In the waveform example 2, the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un can be suppressed at the same time.
　また、波形例２では、図５Ｂに示すように、Ｖ相の第１半導体スイッチング素子Ｖｐと、Ｖ相の第２半導体スイッチング素子Ｖｎと、Ｗ相の第１半導体スイッチング素子Ｗｐと、Ｗ相の第２半導体スイッチング素子Ｗｎとの発熱についても同時に抑えることができる。なお、波形例２は、発熱の抑制効果のより高い後述する波形例９（図１２）で代用が可能である。 In waveform example 2, as shown in FIG. 5B, the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time. Waveform example 2 can be substituted with waveform example 9 (FIG. 12) described later, which has a higher effect of suppressing heat generation.
　図６Ａおよび図６Ｂを参照して、波形例３について説明する。図６Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図６Ｂは、スイッチング損失を示す図である。 Waveform example 3 will be described with reference to FIGS. 6A and 6B. FIG. 6A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 6B is a diagram showing switching losses.
　図６Ａに示すように、波形例３は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例３は、電気角０度～電気角２１０度および電気角３３０度～電気角３６０度において、いずれか１相の出力が１に固定される波形である。また、波形例３は、電気角２１０度～電気角３３０度において、いずれか１相の出力が０に固定される波形である。波形例３では、電気角０度～電気角２１０度および電気角３３０度～電気角３６０度において、ハイサイドオン適用期間Ｔ３である。また、波形例３では、電気角２１０度～電気角３３０度において、ロウサイドオン適用期間Ｔ４である。 As shown in FIG. 6A, in waveform example 3, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. More specifically, waveform example 3 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 0 to 210 electrical degrees and at an electrical angle of 330 to 360 electrical degrees. Waveform example 3 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 210 degrees to 330 degrees. In waveform example 3, the high-side-on application period T3 occurs at an electrical angle of 0 to 210 electrical degrees and at an electrical angle of 330 to 360 electrical degrees. Further, in waveform example 3, the low-side-on application period is T4 at an electrical angle of 210 degrees to 330 electrical degrees.
　波形例３では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｕと、第１オン固定期間Ｔ１ｖと、第１オン固定期間Ｔ１ｗとを含む。波形例３では、電気角３０度～電気角１５０度が第１オン固定期間Ｔ１ｕである。波形例３では、電気角１５０度～電気角２１０度が第１オン固定期間Ｔ１ｖである。波形例３では、電気角０度～電気角３０度および電気角３３０度～電気角３６０度が第１オン固定期間Ｔ１ｗである。 In Waveform Example 3, the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w. In Waveform Example 3, the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees. In Waveform Example 3, the first fixed ON period T1v is between an electrical angle of 150 degrees and an electrical angle of 210 degrees. In waveform example 3, the first fixed ON period T1w is from an electrical angle of 0 degrees to an electrical angle of 30 degrees and from an electrical angle of 330 degrees to an electrical angle of 360 degrees.
　波形例３では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｕを含む。波形例３では、電気角２１０度～電気角３３０度が第２オン固定期間Ｔ２ｕである。 In Waveform Example 3, the second fixed ON period T2 includes the second fixed ON period T2u. In Waveform Example 3, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
　波形例３では、３相のうちＵ相において、第１オン固定期間Ｔ１ｕが、第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗと異なる。詳しくは、波形例３では、第１オン固定期間Ｔ１ｕが１２０度であるのに対し、第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗは６０度である。すなわち、波形例３では、第１オン固定期間Ｔ１ｕが第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗよりも長い。したがって、図６Ｂに示すように、Ｕ相の第１半導体スイッチング素子Ｕｐ（Ｈ（ハイサイド））のスイッチング損失がＶ相およびＷ相に比べて小さくなっている。 In waveform example 3, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 3, the first fixed ON period T1u is 120 degrees, while the first fixed ON period T1v and the first fixed ON period T1w are 60 degrees. That is, in Waveform Example 3, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 6B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
　波形例３では、第２オン固定期間Ｔ２ｕが、第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗと異なる。詳しくは、波形例３では、第２オン固定期間Ｔ２ｕが１２０度であるのに対し、第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗは無い。すなわち、波形例３では、第２オン固定期間Ｔ２ｕが第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗよりも長い。したがって、図６Ｂに示すように、Ｕ相の第２半導体スイッチング素子Ｕｎ（Ｌ（ロウサイド））のスイッチング損失がＶ相およびＷ相に比べて小さくなっている。 In Waveform Example 3, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in Waveform Example 3, the second fixed ON period T2u is 120 degrees, whereas the second fixed ON period T2v and the second fixed ON period T2w are absent. That is, in Waveform Example 3, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 6B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
　以上、図６Ａおよび図６Ｂを参照して説明したように、波形例３においても、波形例１と同様に、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。波形例３では、Ｕ相の第１半導体スイッチング素子Ｕｐと、Ｕ相の第２半導体スイッチング素子Ｕｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 6A and 6B , in Waveform Example 3, as in Waveform Example 1, the heat generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 3, the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un can be suppressed at the same time.
　また、波形例３では、図６Ｂに示すように、Ｖ相の第１半導体スイッチング素子Ｖｐと、Ｗ相の第１半導体スイッチング素子Ｗｐとの発熱についても同時に抑えることができる。 Further, in Waveform Example 3, as shown in FIG. 6B, the heat generation of the V-phase first semiconductor switching element Vp and the W-phase first semiconductor switching element Wp can be suppressed at the same time.
　図７Ａおよび図７Ｂを参照して、波形例４について説明する。図７Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図７Ｂは、スイッチング損失を示す図である。 Waveform example 4 will be described with reference to FIGS. 7A and 7B. FIG. 7A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 7B is a diagram showing switching losses.
　図７Ａに示すように、波形例４は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例４は、電気角３０度～電気角１８０度において、いずれか１相の出力が１に固定される波形である。また、波形例４は、電気角０度～電気角３０度および電気角１８０度～電気角３６０度において、ずれか１相の出力が０に固定される波形である。波形例４では、電気角３０度～電気角１８０度において、ハイサイドオン適用期間Ｔ３である。また、波形例４では、電気角０度～電気角３０度および電気角１８０度～電気角３６０度において、ロウサイドオン適用期間Ｔ４である。 As shown in FIG. 7A, in waveform example 4, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, waveform example 4 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 30 degrees to 180 degrees. Waveform example 4 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 to 30 degrees and at an electrical angle of 180 to 360 degrees. In Waveform Example 4, the high-side-on application period T3 is at an electrical angle of 30 degrees to 180 degrees. Further, in Waveform Example 4, the low-side-on application period T4 occurs at an electrical angle of 0 to 30 electrical degrees and at an electrical angle of 180 to 360 electrical degrees.
　波形例４では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｕと、第１オン固定期間Ｔ１ｖとを含む。波形例４では、電気角３０度～電気角１５０度が第１オン固定期間Ｔ１ｕである。波形例４では、電気角１５０度～電気角１８０度が第１オン固定期間Ｔ１ｖである。 In Waveform Example 4, the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v. In Waveform Example 4, the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees. In Waveform Example 4, the first fixed ON period T1v is between 150 electrical degrees and 180 electrical degrees.
　波形例４では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖと、第２オン固定期間Ｔ２ｗとを含む。波形例４では、電気角２１０度～電気角３３０度が第２オン固定期間Ｔ２ｕである。波形例４では、電気角０度～電気角３０度および電気角３３０度～電気角３６０度が第２オン固定期間Ｔ２ｖである。波形例４では、電気角１８０度～電気角２１０度が第２オン固定期間Ｔ２ｗである。 In Waveform Example 4, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In Waveform Example 4, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In Waveform Example 4, the second fixed ON period T2v is from an electrical angle of 0 degree to an electrical angle of 30 degrees and from an electrical angle of 330 degrees to an electrical angle of 360 degrees. In Waveform Example 4, the second fixed ON period T2w is between 180 electrical degrees and 210 electrical degrees.
　波形例４では、３相のうちＵ相において、第１オン固定期間Ｔ１ｕが、第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗと異なる。詳しくは、波形例４では、第１オン固定期間Ｔ１ｕが１２０度であるのに対し、第１オン固定期間Ｔ１ｖが３０度であり、第１オン固定期間Ｔ１ｗは無い。すなわち、波形例４では、第１オン固定期間Ｔ１ｕが第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗよりも長い。したがって、図７Ｂに示すように、Ｕ相の第１半導体スイッチング素子Ｕｐ（Ｈ（ハイサイド））のスイッチング損失がＶ相およびＷ相に比べて小さくなっている。 In waveform example 4, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 4, the first fixed ON period T1u is 120 degrees, the first fixed ON period T1v is 30 degrees, and there is no first fixed ON period T1w. That is, in Waveform Example 4, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 7B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
　波形例４では、第２オン固定期間Ｔ２ｕが、第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗと異なる。詳しくは、波形例４では、第２オン固定期間Ｔ２ｕが１２０度であるのに対し、第２オン固定期間Ｔ２ｖは６０度であり、第２オン固定期間Ｔ２ｗは３０度である。すなわち、波形例４では、第２オン固定期間Ｔ２ｕが第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗよりも長い。したがって、図７Ｂに示すように、Ｕ相の第２半導体スイッチング素子Ｕｎ（Ｌ（ロウサイド））のスイッチング損失がＶ相およびＷ相に比べて小さくなっている。 In waveform example 4, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in Waveform Example 4, the second fixed ON period T2u is 120 degrees, the second fixed ON period T2v is 60 degrees, and the second fixed ON period T2w is 30 degrees. That is, in Waveform Example 4, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 7B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
　以上、図７Ａおよび図７Ｂを参照して説明したように、波形例４においても、波形例１と同様に、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。波形例４では、Ｕ相の第１半導体スイッチング素子Ｕｐと、Ｕ相の第２半導体スイッチング素子Ｕｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 7A and 7B, in Waveform Example 4, as in Waveform Example 1, the heat generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 4, the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un can be suppressed at the same time.
　また、波形例４では、図７Ｂに示すように、Ｖ相の第１半導体スイッチング素子Ｖｐと、Ｖ相の第２半導体スイッチング素子Ｖｎと、Ｗ相の第２半導体スイッチング素子Ｗｎとの発熱についても同時に抑えることができる。なお、波形例４は、発熱の抑制効果のより高い後述する波形例６（図９）で代用が可能である。 In waveform example 4, as shown in FIG. 7B, the heat generated by the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, and the W-phase second semiconductor switching element Wn can be suppressed at the same time. Waveform example 4 can be substituted with waveform example 6 (FIG. 9) described later, which has a higher effect of suppressing heat generation.
　図８Ａおよび図８Ｂを参照して、波形例５について説明する。図８Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図８Ｂは、スイッチング損失を示す図である。 Waveform example 5 will be described with reference to FIGS. 8A and 8B. FIG. 8A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 8B is a diagram showing switching losses.
　図８Ａに示すように、波形例５は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例５は、電気角３０度～電気角２１０度において、いずれか１相の出力が１に固定される波形である。また、波形例５は、電気角０度～電気角３０度および電気角２１０度～電気角３６０度において、いずれか１相の出力が０に固定される波形である。波形例５では、電気角３０度～電気角２１０度において、ハイサイドオン適用期間Ｔ３である。また、波形例５では、電気角０度～電気角３０度および電気角２１０度～電気角３６０度において、ロウサイドオン適用期間Ｔ４である。 As shown in FIG. 8A, in waveform example 5, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, waveform example 5 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 30 degrees to 210 degrees. Waveform example 5 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 to 30 electrical degrees and at an electrical angle of 210 to 360 electrical degrees. In waveform example 5, the high-side-on application period T3 is at an electrical angle of 30 degrees to 210 degrees. Further, in Waveform Example 5, the low-side-on application period T4 occurs at an electrical angle of 0 to 30 electrical degrees and at an electrical angle of 210 to 360 electrical degrees.
　波形例５では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｕと、第１オン固定期間Ｔ１ｖとを含む。波形例５では、電気角３０度～電気角１５０度が第１オン固定期間Ｔ１ｕである。波形例５では、電気角１５０度～電気角２１０度が第１オン固定期間Ｔ１ｖである。 In waveform example 5, the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v. In Waveform Example 5, the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees. In Waveform Example 5, the first fixed ON period T1v is between an electrical angle of 150 degrees and an electrical angle of 210 degrees.
　波形例５では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖとを含む。波形例５では、電気角２１０度～電気角３３０度が第２オン固定期間Ｔ２ｕである。波形例５では、電気角０度～電気角３０度および電気角３３０度～電気角３６０度が第２オン固定期間Ｔ２ｖである。 In waveform example 5, the second fixed ON period T2 includes a second fixed ON period T2u and a second fixed ON period T2v. In waveform example 5, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In Waveform Example 5, the second fixed ON period T2v is from 0 electrical angle to 30 electrical degrees and from 330 electrical degrees to 360 electrical degrees.
　波形例５では、３相のうちＵ相において、第１オン固定期間Ｔ１ｕが、第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗと異なる。詳しくは、波形例５では、第１オン固定期間Ｔ１ｕが１２０度であるのに対し、第１オン固定期間Ｔ１ｖは６０度であり、第１オン固定期間Ｔ１ｗは無い。すなわち、波形例５では、第１オン固定期間Ｔ１ｕが第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗよりも長い。したがって、図８Ｂに示すように、Ｕ相の第１半導体スイッチング素子Ｕｐ（Ｈ（ハイサイド））のスイッチング損失がＶ相およびＷ相に比べて小さくなっている。 In waveform example 5, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 5, the first fixed ON period T1u is 120 degrees, the first fixed ON period T1v is 60 degrees, and there is no first fixed ON period T1w. That is, in Waveform Example 5, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 8B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
　波形例５では、第２オン固定期間Ｔ２ｕが、第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗと異なる。詳しくは、波形例５では、第２オン固定期間Ｔ２ｕが１２０度であるのに対し、第２オン固定期間Ｔ２ｖは６０度であり、第２オン固定期間Ｔ２ｗは無い。すなわち、波形例５では、第２オン固定期間Ｔ２ｕが第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗよりも長い。したがって、図８Ｂに示すように、Ｕ相の第２半導体スイッチング素子Ｕｎ（Ｌ（ロウサイド））のスイッチング損失がＶ相およびＷ相に比べて小さくなっている。 In waveform example 5, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in Waveform Example 5, the second fixed ON period T2u is 120 degrees, the second fixed ON period T2v is 60 degrees, and there is no second fixed ON period T2w. That is, in Waveform Example 5, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 8B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
　以上、図８Ａおよび図８Ｂを参照して説明したように、波形例５においても、波形例１と同様に、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。波形例５では、Ｕ相の第１半導体スイッチング素子Ｕｐと、Ｕ相の第２半導体スイッチング素子Ｕｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 8A and 8B, in Waveform Example 5 as well as in Waveform Example 1, the heat generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 5, the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un can be suppressed at the same time.
　また、波形例５では、図８Ｂに示すように、Ｖ相の第１半導体スイッチング素子Ｖｐと、Ｖ相の第２半導体スイッチング素子Ｖｎとの発熱についても同時に抑えることができる。 Further, in Waveform Example 5, as shown in FIG. 8B, the heat generation of the V-phase first semiconductor switching element Vp and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
　図９Ａおよび図９Ｂを参照して、波形例６について説明する。図９Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図９Ｂは、スイッチング損失を示す図である。 Waveform example 6 will be described with reference to FIGS. 9A and 9B. FIG. 9A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 9B is a diagram showing switching losses.
　図９Ａに示すように、波形例６は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例６は、電気角３０度～電気角１５０度および電気角１８０度～電気角２１０度において、いずれか１相の出力が１に固定される波形である。また、波形例６は、電気角０度～電気角３０度、電気角１５０度～電気角１８０度および電気角２１０度～電気角３６０度において、いずれか１相の出力が０に固定される波形である。波形例６では、電気角３０度～電気角１５０度および電気角１８０度～電気角２１０度において、ハイサイドオン適用期間Ｔ３である。また、波形例６では、電気角０度～電気角３０度、電気角１５０度～電気角１８０度および電気角２１０度～電気角３６０度において、ロウサイドオン適用期間Ｔ４である。 As shown in FIG. 9A, in waveform example 6, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, waveform example 6 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 30 degrees to 150 degrees and at an electrical angle of 180 degrees to 210 degrees. In waveform example 6, the output of any one phase is fixed to 0 at an electrical angle of 0 to 30 electrical degrees, 150 to 180 electrical degrees, and 210 to 360 electrical degrees. waveform. In Waveform Example 6, the high-side-on application period T3 occurs at an electrical angle of 30 degrees to 150 degrees and at an electrical angle of 180 degrees to 210 degrees. Further, in Waveform Example 6, the low side-on application period T4 occurs at an electrical angle of 0 to 30 electrical degrees, 150 to 180 electrical degrees, and 210 to 360 electrical degrees.
　波形例６では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｕと、第１オン固定期間Ｔ１ｖとを含む。波形例６では、電気角３０度～電気角１５０度が第１オン固定期間Ｔ１ｕである。波形例６では、電気角１８０度～電気角２１０度が第１オン固定期間Ｔ１ｖである。 In Waveform Example 6, the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v. In Waveform Example 6, the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees. In Waveform Example 6, the first fixed ON period T1v is between an electrical angle of 180 degrees and an electrical angle of 210 degrees.
　波形例６では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖと、第２オン固定期間Ｔ２ｗとを含む。波形例６では、電気角２１０度～電気角３３０度が第２オン固定期間Ｔ２ｕである。波形例６では、電気角３３０度～電気角３６０度と電気角０度～電気角３０度とが第２オン固定期間Ｔ２ｖである。波形例６では、電気角１５０度～電気角１８０度が第２オン固定期間Ｔ２ｗである。 In Waveform Example 6, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 6, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In Waveform Example 6, the second fixed ON period T2v is between an electrical angle of 330 degrees and an electrical angle of 360 degrees and between an electrical angle of 0 degrees and an electrical angle of 30 degrees. In Waveform Example 6, the second fixed ON period T2w is between 150 electrical degrees and 180 electrical degrees.
　波形例６では、３相のうちＵ相において、第１オン固定期間Ｔ１ｕが、第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗと異なる。詳しくは、波形例６では、第１オン固定期間Ｔ１ｕが１２０度であるのに対し、第１オン固定期間Ｔ１ｖが３０度であり、第１オン固定期間Ｔ１ｗは無い。すなわち、波形例６では、第１オン固定期間Ｔ１ｕが第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗよりも長い。したがって、図９Ｂに示すように、Ｕ相の第１半導体スイッチング素子Ｕｐ（Ｈ（ハイサイド））のスイッチング損失がＶ相およびＷ相に比べて小さくなっている。 In waveform example 6, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 6, the first fixed ON period T1u is 120 degrees, the first fixed ON period T1v is 30 degrees, and there is no first fixed ON period T1w. That is, in Waveform Example 6, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 9B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
　波形例６では、第２オン固定期間Ｔ２ｕが、第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗと異なる。詳しくは、波形例６では、第２オン固定期間Ｔ２ｕが１２０度であるのに対し、第２オン固定期間Ｔ２ｖが６０度であり、第２オン固定期間Ｔ２ｗは３０度である。すなわち、波形例６では、第２オン固定期間Ｔ２ｕが第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗよりも長い。したがって、図９Ｂに示すように、Ｕ相の第２半導体スイッチング素子Ｕｎ（Ｌ（ロウサイド））のスイッチング損失がＶ相およびＷ相に比べて小さくなっている。 In waveform example 6, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in Waveform Example 6, the second fixed ON period T2u is 120 degrees, the second fixed ON period T2v is 60 degrees, and the second fixed ON period T2w is 30 degrees. That is, in Waveform Example 6, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 9B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
　以上、図９Ａおよび図９Ｂを参照して説明したように、波形例６においても、波形例１と同様に、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。波形例６では、Ｕ相の第１半導体スイッチング素子Ｕｐと、Ｕ相の第２半導体スイッチング素子Ｕｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 9A and 9B, in Waveform Example 6, as in Waveform Example 1, the heat generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 6, the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un can be suppressed at the same time.
　また、波形例６では、図９Ｂに示すように、Ｖ相の第１半導体スイッチング素子Ｖｐと、Ｖ相の第２半導体スイッチング素子Ｖｎと、Ｗ相の第２半導体スイッチング素子Ｗｎとの発熱についても同時に抑えることができる。 In waveform example 6, as shown in FIG. 9B, the heat generated by the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
　図１０Ａおよび図１０Ｂを参照して、波形例７について説明する。図１０Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図１０Ｂは、スイッチング損失を示す図である。 Waveform example 7 will be described with reference to FIGS. 10A and 10B. FIG. 10A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 10B is a diagram showing switching losses.
　図１０Ａに示すように、波形例７は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例７は、電気角０度～電気角１５０度および電気角１８０度～電気角２１０度において、いずれか１相の出力が１に固定される波形である。また、波形例７は、電気角１５０度～電気角１８０度および電気角２１０度～電気角３６０度において、いずれか１相の出力が０に固定される波形である。波形例７では、電気角０度～電気角１５０度および電気角１８０度～電気角２１０度において、ハイサイドオン適用期間Ｔ３である。また、波形例７では、電気角１５０度～電気角１８０度および電気角２１０度～電気角３６０度において、ロウサイドオン適用期間Ｔ４である。 As shown in FIG. 10A, in waveform example 7, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval according to the electrical angle, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, waveform example 7 is a waveform in which the output of any one phase is fixed to 1 in the electrical angle of 0 to 150 electrical degrees and in the electrical angle of 180 to 210 electrical degrees. Waveform example 7 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 150 degrees to 180 degrees and at an electrical angle of 210 degrees to 360 degrees. In Waveform Example 7, the high-side-on application period T3 occurs at an electrical angle of 0 to 150 electrical degrees and at an electrical angle of 180 to 210 electrical degrees. Further, in Waveform Example 7, the low side-on application period T4 occurs at an electrical angle of 150 degrees to 180 degrees and at an electrical angle of 210 degrees to 360 degrees.
　波形例７では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｕと、第１オン固定期間Ｔ１ｖと、第１オン固定期間Ｔ１ｗとを含む。波形例７では、電気角３０度～電気角１５０度が第１オン固定期間Ｔ１ｕである。波形例７では、電気角１８０度～電気角２１０度が第１オン固定期間Ｔ１ｖである。波形例７では、電気角０度～電気角３０度が第１オン固定期間Ｔ１ｗである。 In Waveform Example 7, the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w. In Waveform Example 7, the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees. In Waveform Example 7, the first fixed ON period T1v is between an electrical angle of 180 degrees and an electrical angle of 210 degrees. In Waveform Example 7, the first ON fixed period T1w is from 0 electrical angle to 30 electrical degrees.
　波形例７では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖと、第２オン固定期間Ｔ２ｗとを含む。波形例７では、電気角２１０度～電気角３３０度が第２オン固定期間Ｔ２ｕである。波形例７では、電気角３３０度～電気角３６０度が第２オン固定期間Ｔ２ｖである。波形例７では、電気角１５０度～電気角１８０度が第２オン固定期間Ｔ２ｗである。 In Waveform Example 7, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In Waveform Example 7, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In Waveform Example 7, the second fixed ON period T2v is between 330 electrical degrees and 360 electrical degrees. In Waveform Example 7, the second fixed ON period T2w is between 150 electrical degrees and 180 electrical degrees.
　波形例７では、３相のうちＵ相において、第１オン固定期間Ｔ１ｕが、第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗと異なる。詳しくは、波形例７では、第１オン固定期間Ｔ１ｕが１２０度であるのに対し、第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗは３０度である。すなわち、波形例７では、第１オン固定期間Ｔ１ｕが第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗよりも長い。したがって、図１０Ｂに示すように、Ｕ相の第１半導体スイッチング素子Ｕｐ（Ｈ（ハイサイド））のスイッチング損失がＶ相およびＷ相に比べて小さくなっている。 In waveform example 7, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 7, the first fixed ON period T1u is 120 degrees, while the first fixed ON period T1v and the first fixed ON period T1w are 30 degrees. That is, in Waveform Example 7, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 10B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
　波形例７では、第２オン固定期間Ｔ２ｕが、第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗと異なる。詳しくは、波形例７では、第２オン固定期間Ｔ２ｕが１２０度であるのに対し、第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗは３０度である。すなわち、波形例７では、第２オン固定期間Ｔ２ｕが第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗよりも長い。したがって、図１０Ｂに示すように、Ｕ相の第２半導体スイッチング素子Ｕｎ（Ｌ（ロウサイド））のスイッチング損失がＶ相およびＷ相に比べて小さくなっている。 In Waveform Example 7, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in Waveform Example 7, the second fixed ON period T2u is 120 degrees, while the second fixed ON period T2v and the second fixed ON period T2w are 30 degrees. That is, in Waveform Example 7, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 10B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
　以上、図１０Ａおよび図１０Ｂを参照して説明したように、波形例７においても、波形例１と同様に、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。波形例７では、Ｕ相の第１半導体スイッチング素子Ｕｐと、Ｕ相の第２半導体スイッチング素子Ｕｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 10A and 10B , in Waveform Example 7, as in Waveform Example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 7, the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un can be suppressed at the same time.
　また、波形例７では、図１０Ｂに示すように、Ｖ相の第１半導体スイッチング素子Ｖｐと、Ｖ相の第２半導体スイッチング素子Ｖｎと、Ｗ相の第１半導体スイッチング素子Ｗｐと、Ｗ相の第２半導体スイッチング素子Ｗｎとの発熱についても同時に抑えることができる。なお、波形例７は、発熱の抑制効果のより高い後述する波形例９（図１２）で代用が可能である。 In waveform example 7, as shown in FIG. 10B, the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time. Waveform example 7 can be substituted with waveform example 9 (FIG. 12), which will be described later and has a higher effect of suppressing heat generation.
　図１１Ａおよび図１１Ｂを参照して、波形例８について説明する。図１１Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図１１Ｂは、スイッチング損失を示す図である。 Waveform example 8 will be described with reference to FIGS. 11A and 11B. FIG. 11A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 11B is a diagram showing switching loss.
　図１１Ａに示すように、波形例８は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例８は、電気角０度～電気角１５０度、電気角１８０度～電気角２１０度および電気角３３０度～電気角３６０度において、いずれか１相の出力が１に固定される波形である。また、波形例８は、電気角１５０度～電気角１８０度および電気角２１０度～電気角３３０度において、いずれか１相の出力が０に固定される波形である。波形例８では、電気角０度～電気角１５０度、電気角１８０度～電気角２１０度および電気角３３０度～電気角３６０度において、ハイサイドオン適用期間Ｔ３である。また、波形例８では、電気角１５０度～電気角１８０度および電気角２１０度～電気角３３０度において、ロウサイドオン適用期間Ｔ４である。 As shown in FIG. 11A, in Waveform Example 8, the output voltage of any one phase is fixed to 1 in a certain electrical angle section according to the electrical angle, and the output voltage of any one phase is fixed to 1 in another electrical angle section. is fixed to 0. Specifically, in waveform example 8, the output of any one phase is fixed to 1 at an electrical angle of 0 to 150 degrees, from 180 to 210 electrical degrees, and from 330 to 360 electrical degrees. waveform. Waveform example 8 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 150 degrees to 180 degrees and at an electrical angle of 210 degrees to 330 degrees. In Waveform Example 8, the high side-on application period T3 is at the electrical angle of 0 to 150 electrical degrees, the electrical angle of 180 to 210 electrical degrees, and the electrical angle of 330 to 360 electrical degrees. Further, in Waveform Example 8, the low side-on application period T4 occurs at an electrical angle of 150 degrees to 180 degrees and at an electrical angle of 210 degrees to 330 degrees.
　波形例８では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｕと、第１オン固定期間Ｔ１ｖと、第１オン固定期間Ｔ１ｗとを含む。波形例８では、電気角３０度～電気角１５０度が第１オン固定期間Ｔ１ｕである。波形例８では、電気角１８０度～電気角２１０度が第１オン固定期間Ｔ１ｖである。波形例８では、電気角０度～電気角３０度および電気角３３０度～電気角３６０度が第１オン固定期間Ｔ１ｗである。 In Waveform Example 8, the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w. In Waveform Example 8, the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees. In Waveform Example 8, the first fixed ON period T1v is between an electrical angle of 180 degrees and an electrical angle of 210 degrees. In Waveform Example 8, the first fixed ON period T1w is from an electrical angle of 0 degrees to an electrical angle of 30 degrees and from an electrical angle of 330 degrees to an electrical angle of 360 degrees.
　波形例８では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｗとを含む。波形例８では、電気角２１０度～電気角３３０度が第２オン固定期間Ｔ２ｕである。波形例８では、電気角１５０度～電気角１８０度が第２オン固定期間Ｔ２ｗである。 In Waveform Example 8, the second fixed ON period T2 includes a second fixed ON period T2u and a second fixed ON period T2w. In Waveform Example 8, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In Waveform Example 8, the second fixed ON period T2w is between 150 electrical degrees and 180 electrical degrees.
　波形例８では、３相のうちＵ相において、第１オン固定期間Ｔ１ｕが、第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗと異なる。詳しくは、波形例８では、第１オン固定期間Ｔ１ｕが１２０度であるのに対し、第１オン固定期間Ｔ１ｖは３０度であり、第１オン固定期間Ｔ１ｗは６０度である。すなわち、波形例８では、第１オン固定期間Ｔ１ｕが第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗよりも長い。したがって、図１１Ｂに示すように、Ｕ相の第１半導体スイッチング素子Ｕｐ（Ｈ（ハイサイド））のスイッチング損失がＶ相およびＷ相に比べて小さくなっている。 In waveform example 8, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 8, the first fixed ON period T1u is 120 degrees, the first fixed ON period T1v is 30 degrees, and the first fixed ON period T1w is 60 degrees. That is, in Waveform Example 8, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 11B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
　波形例８では、第２オン固定期間Ｔ２ｕが、第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗと異なる。詳しくは、波形例８では、第２オン固定期間Ｔ２ｕが１２０度であるのに対し、第２オン固定期間Ｔ２ｖは無く、第２オン固定期間Ｔ２ｗは３０度である。すなわち、波形例８では、第２オン固定期間Ｔ２ｕが第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗよりも長い。したがって、図１１Ｂに示すように、Ｕ相の第２半導体スイッチング素子Ｕｎ（Ｌ（ロウサイド））のスイッチング損失がＶ相およびＷ相に比べて小さくなっている。 In Waveform Example 8, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in Waveform Example 8, the second fixed ON period T2u is 120 degrees, whereas the second fixed ON period T2v is absent and the second fixed ON period T2w is 30 degrees. That is, in Waveform Example 8, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 11B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
　以上、図１１Ａおよび図１１Ｂを参照して説明したように、波形例８においても、波形例１と同様に、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。波形例８では、Ｕ相の第１半導体スイッチング素子Ｕｐと、Ｕ相の第２半導体スイッチング素子Ｕｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 11A and 11B, in Waveform Example 8, as in Waveform Example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 8, the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un can be suppressed at the same time.
　また、波形例８では、図１１Ｂに示すように、Ｖ相の第１半導体スイッチング素子Ｖｐと、Ｗ相の第１半導体スイッチング素子Ｗｐと、Ｗ相の第２半導体スイッチング素子Ｗｎとの発熱についても同時に抑えることができる。 In waveform example 8, as shown in FIG. 11B, the heat generated by the V-phase first semiconductor switching element Vp, the W-phase first semiconductor switching element Wp, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
　図１２Ａおよび図１２Ｂを参照して、波形例９について説明する。図１２Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図１２Ｂは、スイッチング損失を示す図である。 Waveform example 9 will be described with reference to FIGS. 12A and 12B. FIG. 12A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 12B is a diagram showing switching losses.
　図１２Ａに示すように、波形例９は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例９は、電気角３０度～電気角１５０度、電気角１８０度～電気角２１０度および電気角３３０度～電気角３６０度において、いずれか１相の出力が１に固定される波形である。また、波形例９は、電気角０度～電気角３０度、電気角１５０度～電気角１８０度および電気角２１０度～電気角３３０度において、波形例９では、電気角３０度～電気角１５０度、電気角１８０度～電気角２１０度および電気角３３０度～電気角３６０度において、ハイサイドオン適用期間Ｔ３である。また、波形例９では、電気角０度～電気角３０度、電気角１５０度～電気角１８０度および電気角２１０度～電気角３３０度において、ロウサイドオン適用期間Ｔ４である。 As shown in FIG. 12A, in waveform example 9, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, in waveform example 9, the output of any one phase is fixed to 1 at an electrical angle of 30 degrees to 150 degrees, from 180 degrees to 210 degrees, and from 330 degrees to 360 degrees. waveform. Further, waveform example 9 corresponds to an electrical angle of 0 degree to an electrical angle of 30 degrees, an electrical angle of 150 degrees to an electrical angle of 180 degrees, and an electrical angle of 210 degrees to an electrical angle of 330 degrees. 150 degrees, the electrical angle of 180 degrees to 210 degrees, and the electrical angle of 330 degrees to 360 degrees are the high side-on application period T3. Further, in waveform example 9, the low side-on application period T4 occurs at an electrical angle of 0 to 30 electrical degrees, 150 to 180 electrical degrees, and 210 to 330 electrical degrees.
　波形例９では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｕと、第１オン固定期間Ｔ１ｖと、第１オン固定期間Ｔ１ｗとを含む。波形例９では、電気角３０度～電気角１５０度が第１オン固定期間Ｔ１ｕである。波形例９では、電気角１８０度～電気角２１０度が第１オン固定期間Ｔ１ｖである。波形例９では、電気角３３０度～電気角３６０度が第１オン固定期間Ｔ１ｗである。 In Waveform Example 9, the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w. In waveform example 9, the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees. In Waveform Example 9, the first fixed ON period T1v is between an electrical angle of 180 degrees and an electrical angle of 210 degrees. In Waveform Example 9, the first fixed ON period T1w is from 330 electrical degrees to 360 electrical degrees.
　波形例９では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖと、第２オン固定期間Ｔ２ｗとを含む。波形例９では、電気角２１０度～電気角３３０度が第２オン固定期間Ｔ２ｕである。波形例９では、電気角０度～電気角３０度が第２オン固定期間Ｔ２ｖである。波形例９では、電気角１５０度～電気角１８０度が第２オン固定期間Ｔ２ｗである。 In Waveform Example 9, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 9, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In Waveform Example 9, the second fixed ON period T2v is from an electrical angle of 0 degrees to an electrical angle of 30 degrees. In Waveform Example 9, the second fixed ON period T2w is between 150 electrical degrees and 180 electrical degrees.
　波形例９では、３相のうちＵ相において、第１オン固定期間Ｔ１ｕが、第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗと異なる。詳しくは、波形例９では、第１オン固定期間Ｔ１ｕが１２０度であるのに対し、第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗは３０度である。すなわち、波形例９では、第１オン固定期間Ｔ１ｕが第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗよりも長い。したがって、図１２Ｂに示すように、Ｕ相の第１半導体スイッチング素子Ｕｐ（Ｈ（ハイサイド））のスイッチング損失がＶ相およびＷ相に比べて小さくなっている。 In waveform example 9, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 9, the first fixed ON period T1u is 120 degrees, while the first fixed ON period T1v and the first fixed ON period T1w are 30 degrees. That is, in Waveform Example 9, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 12B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
　波形例９では、第２オン固定期間Ｔ２ｕが、第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗと異なる。詳しくは、波形例９では、第２オン固定期間Ｔ２ｕが１２０度であるのに対し、第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗは３０度である。すなわち、波形例９では、第２オン固定期間Ｔ２ｕが第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗよりも長い。したがって、図１２Ｂに示すように、Ｕ相の第２半導体スイッチング素子Ｕｎ（Ｌ（ロウサイド））のスイッチング損失がＶ相およびＷ相に比べて小さくなっている。 In waveform example 9, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in Waveform Example 9, the second fixed ON period T2u is 120 degrees, while the second fixed ON period T2v and the second fixed ON period T2w are 30 degrees. That is, in Waveform Example 9, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 12B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
　以上、図１２Ａおよび図１２Ｂを参照して説明したように、波形例９においても、波形例１と同様に、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。波形例９では、Ｕ相の第１半導体スイッチング素子Ｕｐと、Ｕ相の第２半導体スイッチング素子Ｕｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 12A and 12B, in Waveform Example 9, as in Waveform Example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In the waveform example 9, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un.
　また、波形例９では、図１２Ｂに示すように、Ｖ相の第１半導体スイッチング素子Ｖｐと、Ｖ相の第２半導体スイッチング素子Ｖｎと、Ｗ相の第１半導体スイッチング素子Ｗｐと、Ｗ相の第２半導体スイッチング素子Ｗｎとの発熱についても同時に抑えることができる。 In waveform example 9, as shown in FIG. 12B, the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
　図１３Ａおよび図１３Ｂを参照して、波形例１０について説明する。図１３Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図１３Ｂは、スイッチング損失を示す図である。 A waveform example 10 will be described with reference to FIGS. 13A and 13B. FIG. 13A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 13B is a diagram showing switching losses.
　図１３Ａに示すように、波形例１０は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例１０は、電気角０度～電気角１５０度および電気角３３０度～電気角３６０度において、いずれか１相の出力が１に固定される波形である。また、波形例１０は、電気角１５０度～電気角３３０度において、いずれか１相の出力が０に固定される波形である。波形例１０では、電気角０度～電気角１５０度および電気角３３０度～電気角３６０度において、ハイサイドオン適用期間Ｔ３である。また、波形例１０では、電気角１５０度～電気角３３０度において、ロウサイドオン適用期間Ｔ４である。 As shown in FIG. 13A, in waveform example 10, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. More specifically, waveform example 10 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 0 to 150 electrical degrees and at an electrical angle of 330 to 360 electrical degrees. Waveform example 10 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 150 degrees to 330 degrees. In waveform example 10, the high-side-on application period T3 occurs at an electrical angle of 0 to 150 electrical degrees and at an electrical angle of 330 to 360 electrical degrees. Further, in waveform example 10, the low-side-on application period T4 occurs at an electrical angle of 150 degrees to 330 electrical degrees.
　波形例１０では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｕと、第１オン固定期間Ｔ１ｗとを含む。波形例１０では、電気角３０度～電気角１５０度が第１オン固定期間Ｔ１ｕである。波形例１０では、電気角０度～電気角３０度および電気角３３０度～電気角３６０度が第１オン固定期間Ｔ１ｗである。 In waveform example 10, the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1w. In waveform example 10, the first ON fixed period T1u is from 30 electrical degrees to 150 electrical degrees. In waveform example 10, the first fixed ON period T1w is from an electrical angle of 0 degrees to an electrical angle of 30 degrees and from an electrical angle of 330 degrees to an electrical angle of 360 degrees.
　波形例１０では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｗとを含む。波形例１０では、電気角２１０度～電気角３３０度が第２オン固定期間Ｔ２ｕである。波形例１０では、電気角１５０度～電気角２１０度が第２オン固定期間Ｔ２ｗである。 In waveform example 10, the second fixed ON period T2 includes a second fixed ON period T2u and a second fixed ON period T2w. In waveform example 10, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In waveform example 10, the second fixed ON period T2w is between 150 electrical degrees and 210 electrical degrees.
　波形例１０では、３相のうちＵ相において、第１オン固定期間Ｔ１ｕが、第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗと異なる。詳しくは、波形例１０では、第１オン固定期間Ｔ１ｕが１２０度であるのに対し、第１オン固定期間Ｔ１ｖは無く、第１オン固定期間Ｔ１ｗは６０度である。すなわち、波形例１０では、第１オン固定期間Ｔ１ｕが第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗよりも長い。したがって、図１３Ｂに示すように、Ｕ相の第１半導体スイッチング素子Ｕｐ（Ｈ（ハイサイド））のスイッチング損失がＶ相およびＷ相に比べて小さくなっている。 In waveform example 10, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 10, the first fixed ON period T1u is 120 degrees, whereas the first fixed ON period T1v is absent and the first fixed ON period T1w is 60 degrees. That is, in waveform example 10, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 13B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
　波形例１０では、第２オン固定期間Ｔ２ｕが、第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗと異なる。詳しくは、波形例１０では、第２オン固定期間Ｔ２ｕが１２０度であるのに対し、第２オン固定期間Ｔ２ｖは無く、および第２オン固定期間Ｔ２ｗは６０度である。すなわち、波形例１０では、第２オン固定期間Ｔ２ｕが第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗよりも長い。したがって、図１３Ｂに示すように、Ｕ相の第２半導体スイッチング素子Ｕｎ（Ｌ（ロウサイド））のスイッチング損失がＶ相およびＷ相に比べて小さくなっている。 In waveform example 10, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in Waveform Example 10, the second fixed ON period T2u is 120 degrees, while the second fixed ON period T2v is absent and the second fixed ON period T2w is 60 degrees. That is, in waveform example 10, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 13B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
　以上、図１３Ａおよび図１３Ｂを参照して説明したように、波形例１０においても、波形例１と同様に、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。波形例１０では、Ｕ相の第１半導体スイッチング素子Ｕｐと、Ｕ相の第２半導体スイッチング素子Ｕｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 13A and 13B, in waveform example 10 as well as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 10, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un.
　また、波形例１０では、図１３Ｂに示すように、Ｗ相の第１半導体スイッチング素子Ｗｐと、Ｗ相の第２半導体スイッチング素子Ｗｎとの発熱についても同時に抑えることができる。 Further, in waveform example 10, as shown in FIG. 13B, the heat generation of the W-phase first semiconductor switching element Wp and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
　図１４Ａおよび図１４Ｂを参照して、波形例１１について説明する。図１４Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図１４Ｂは、スイッチング損失を示す図である。 A waveform example 11 will be described with reference to FIGS. 14A and 14B. FIG. 14A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 14B is a diagram showing switching losses.
　図１４Ａに示すように、波形例１１は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例１１は、電気角３０度～電気角２１０度および電気角３３０度～電気角３６０度において、いずれか１相の出力が１に固定される波形である。また、波形例１１は、電気角０度～電気角３０度および電気角２１０度～電気角３３０度において、いずれか１相の出力が０に固定される波形である。波形例１１では、電気角３０度～電気角２１０度および電気角３３０度～電気角３６０度において、ハイサイドオン適用期間Ｔ３である。また、波形例１１では、電気角０度～電気角３０度および電気角２１０度～電気角３３０度において、ロウサイドオン適用期間Ｔ４である。 As shown in FIG. 14A, in waveform example 11, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. More specifically, waveform example 11 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 30 to 210 electrical degrees and at an electrical angle of 330 to 360 electrical degrees. Waveform example 11 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 to 30 degrees and at an electrical angle of 210 to 330 degrees. In waveform example 11, the high side-on application period T3 occurs at an electrical angle of 30 to 210 electrical degrees and at an electrical angle of 330 to 360 electrical degrees. Further, in waveform example 11, the low side-on application period T4 occurs at an electrical angle of 0 to 30 electrical degrees and at an electrical angle of 210 to 330 electrical degrees.
　波形例１１では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｕと、第１オン固定期間Ｔ１ｖと、第１オン固定期間Ｔ１ｗとを含む。波形例１１では、電気角３０度～電気角１５０度が第１オン固定期間Ｔ１ｕである。波形例１１では、電気角１５０度～電気角２１０度が第１オン固定期間Ｔ１ｖである。波形例１１では、電気角３３０度～電気角３６０度が第１オン固定期間Ｔ１ｗである。 In waveform example 11, the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w. In waveform example 11, the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees. In waveform example 11, the first fixed ON period T1v is between 150 electrical degrees and 210 electrical degrees. In waveform example 11, the first fixed ON period T1w is from 330 electrical degrees to 360 electrical degrees.
　波形例１１では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖとを含む。波形例１１では、電気角２１０度～電気角３３０度が第２オン固定期間Ｔ２ｕである。波形例１１では、電気角０度～電気角３０度が第２オン固定期間Ｔ２ｖである。 In waveform example 11, the second fixed ON period T2 includes a second fixed ON period T2u and a second fixed ON period T2v. In waveform example 11, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In waveform example 11, the second fixed ON period T2v is from 0 electrical angle to 30 electrical degrees.
　波形例１１では、３相のうちＵ相において、第１オン固定期間Ｔ１ｕが、第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗと異なる。詳しくは、波形例１１では、第１オン固定期間Ｔ１ｕが１２０度であるのに対し、第１オン固定期間Ｔ１ｖは６０度であり、第１オン固定期間Ｔ１ｗは３０度である。すなわち、波形例１１では、第１オン固定期間Ｔ１ｕが第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗよりも長い。したがって、図１４Ｂに示すように、Ｕ相の第１半導体スイッチング素子Ｕｐ（Ｈ（ハイサイド））のスイッチング損失がＶ相およびＷ相に比べて小さくなっている。 In waveform example 11, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 11, the first fixed ON period T1u is 120 degrees, the first fixed ON period T1v is 60 degrees, and the first fixed ON period T1w is 30 degrees. That is, in waveform example 11, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 14B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
　波形例１１では、第２オン固定期間Ｔ２ｕが、第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗと異なる。詳しくは、波形例１１では、第２オン固定期間Ｔ２ｕが１２０度であるのに対し、第２オン固定期間Ｔ２ｖは、３０度であり、第２オン固定期間Ｔ２ｗは無い。すなわち、波形例１１では、第２オン固定期間Ｔ２ｕが第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗよりも長い。したがって、図１４Ｂに示すように、Ｕ相の第２半導体スイッチング素子Ｕｎ（Ｌ（ロウサイド））のスイッチング損失がＶ相およびＷ相に比べて小さくなっている。 In waveform example 11, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in waveform example 11, the second fixed ON period T2u is 120 degrees, the second fixed ON period T2v is 30 degrees, and there is no second fixed ON period T2w. That is, in waveform example 11, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 14B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
　以上、図１４Ａおよび図１４Ｂを参照して説明したように、波形例１１においても、波形例１と同様に、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。波形例１１では、Ｕ相の第１半導体スイッチング素子Ｕｐと、Ｕ相の第２半導体スイッチング素子Ｕｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 14A and 14B, in waveform example 11, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 11, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un.
　また、波形例１１では、図１４Ｂに示すように、Ｖ相の第１半導体スイッチング素子Ｖｐと、Ｖ相の第２半導体スイッチング素子Ｖｎと、Ｗ相の第１半導体スイッチング素子Ｗｐとの発熱についても同時に抑えることができる。 In waveform example 11, as shown in FIG. 14B, the heat generated by the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, and the W-phase first semiconductor switching element Wp can be suppressed at the same time.
　図１５Ａおよび図１５Ｂを参照して、波形例１２について説明する。図１５Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図１５Ｂは、スイッチング損失を示す図である。 Waveform example 12 will be described with reference to FIGS. 15A and 15B. FIG. 15A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 15B is a diagram showing switching losses.
　図１５Ａに示すように、波形例１２は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例１２は、電気角３０度～電気角１５０度および電気角３３０度～電気角３６０度において、いずれか１相の出力が１に固定される波形である。また、波形例１２は、電気角０度～電気角３０度および電気角１５０度～電気角３３０度において、いずれか１相の出力が０に固定される波形である。波形例１２では、電気角３０度～電気角１５０度および電気角３３０度～電気角３６０度において、ハイサイドオン適用期間Ｔ３である。また、波形例１２では、電気角０度～電気角３０度および電気角１５０度～電気角３３０度において、ロウサイドオン適用期間Ｔ４である。 As shown in FIG. 15A, in waveform example 12, the output voltage of any one phase is fixed to 1 in a certain electrical angle section, and the output voltage of any one phase is fixed to 1 in another electrical angle section. is fixed to 0. Specifically, waveform example 12 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 30 degrees to 150 degrees and at an electrical angle of 330 degrees to 360 degrees. Waveform example 12 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 to 30 electrical degrees and at an electrical angle of 150 to 330 electrical degrees. In waveform example 12, the high side-on application period T3 occurs at an electrical angle of 30 degrees to 150 degrees and at an electrical angle of 330 degrees to 360 degrees. Further, in waveform example 12, the low side-on application period T4 occurs at an electrical angle of 0 to 30 electrical degrees and at an electrical angle of 150 to 330 electrical degrees.
　波形例１２では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｕと、第１オン固定期間Ｔ１ｗとを含む。波形例１２では、電気角３０度～電気角１５０度が第１オン固定期間Ｔ１ｕである。波形例１２では、電気角３３０度～電気角３６０度が第１オン固定期間Ｔ１ｗである。 In waveform example 12, the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1w. In waveform example 12, the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees. In waveform example 12, the first fixed ON period T1w is from 330 electrical degrees to 360 electrical degrees.
　波形例１２では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖと、第２オン固定期間Ｔ２ｗとを含む。波形例１２では、電気角２１０度～電気角３３０度が第２オン固定期間Ｔ２ｕである。波形例１２では、電気角０度～電気角３０度が第２オン固定期間Ｔ２ｖである。波形例１２では、電気角１５０度～電気角２１０度が第２オン固定期間Ｔ２ｗである。 In Waveform Example 12, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 12, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In waveform example 12, the second fixed ON period T2v is from 0 electrical angle to 30 electrical degrees. In waveform example 12, the second fixed ON period T2w is from 150 electrical degrees to 210 electrical degrees.
　波形例１２では、３相のうちＵ相において、第１オン固定期間Ｔ１ｕが、第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗと異なる。詳しくは、波形例１２では、第１オン固定期間Ｔ１ｕが１２０度であるのに対し、第１オン固定期間Ｔ１ｖは無く、第１オン固定期間Ｔ１ｗは３０度である。すなわち、波形例１２では、第１オン固定期間Ｔ１ｕが第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗよりも長い。したがって、図１５Ｂに示すように、Ｕ相の第１半導体スイッチング素子Ｕｐ（Ｈ（ハイサイド））のスイッチング損失がＶ相およびＷ相に比べて小さくなっている。 In waveform example 12, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 12, the first fixed ON period T1u is 120 degrees, whereas the first fixed ON period T1v is absent and the first fixed ON period T1w is 30 degrees. That is, in waveform example 12, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 15B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
　波形例１２では、第２オン固定期間Ｔ２ｕが、第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗと異なる。詳しくは、波形例１２では、第２オン固定期間Ｔ２ｕが１２０度であるのに対し、第２オン固定期間Ｔ２ｖは３０度であり、第２オン固定期間Ｔ２ｗは６０度である。すなわち、波形例１２では、第２オン固定期間Ｔ２ｕが第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗよりも長い。したがって、図１５Ｂに示すように、Ｕ相の第２半導体スイッチング素子Ｕｎ（Ｌ（ロウサイド））のスイッチング損失がＶ相およびＷ相に比べて小さくなっている。 In waveform example 12, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in waveform example 12, the second fixed ON period T2u is 120 degrees, the second fixed ON period T2v is 30 degrees, and the second fixed ON period T2w is 60 degrees. That is, in waveform example 12, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 15B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
　以上、図１５Ａおよび図１５Ｂを参照して説明したように、波形例１２においても、波形例１と同様に、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。波形例１２では、Ｕ相の第１半導体スイッチング素子Ｕｐと、Ｕ相の第２半導体スイッチング素子Ｕｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 15A and 15B , in waveform example 12, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 12, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un.
　また、波形例１２では、図１５Ｂに示すように、Ｖ相の第２半導体スイッチング素子Ｖｎと、Ｗ相の第１半導体スイッチング素子Ｗｐと、Ｗ相の第２半導体スイッチング素子Ｗｎとの発熱についても同時に抑えることができる。 In waveform example 12, as shown in FIG. 15B, the heat generated by the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
　図１６を参照して、Ｕ相の固定期間を変化させた場合のスイッチング損失について説明する。図１６は、スイッチング損失を示す図である。 The switching loss when the fixed period of the U phase is changed will be described with reference to FIG. FIG. 16 is a diagram showing switching loss.
　図１６に示すように、Ｕ相において、ハイサイド側の第１オン固定期間Ｔ１ｕを電気角３０度～電気角１５０度、ロウサイド側の第２オン固定期間Ｔ２ｕを電気角２１０度～電気角３３０度にした場合、スイッチング損失は０．１３となる。つまり、Ｕ相において、ハイサイド側の第１オン固定期間Ｔ１ｕを１２０度、ロウサイド側の第２オン固定期間Ｔ２ｕを１２０度にした場合、スイッチング損失は０．１３となる。 As shown in FIG. 16, in the U phase, the first fixed ON period T1u on the high side is 30 to 150 electrical degrees in electrical angle, and the second fixed ON period T2u on the low side is 210 to 330 electrical degrees in electrical angle. , the switching loss is 0.13. That is, in the U-phase, if the high-side first fixed ON period T1u is 120 degrees and the low-side second fixed ON period T2u is 120 degrees, the switching loss is 0.13.
　Ｕ相において、ハイサイド側の第１オン固定期間Ｔ１ｕを電気角４０度～電気角１４０度、ロウサイド側の第２オン固定期間Ｔ２ｕを電気角２２０度～電気角３３０度にした場合、スイッチング損失は０．２２となる。つまり、Ｕ相において、ハイサイド側の第１オン固定期間Ｔ１ｕを１２０度、ロウサイド側の第２オン固定期間Ｔ２ｕを１００度にした場合、スイッチング損失は０．２２となる。 In the U phase, when the first fixed ON period T1u on the high side is set at an electrical angle of 40 degrees to 140 degrees and the second fixed ON period T2u on the low side is set at an electrical angle of 220 degrees to 330 degrees, the switching loss is is 0.22. That is, in the U-phase, if the high-side first fixed ON period T1u is 120 degrees and the low-side second fixed ON period T2u is 100 degrees, the switching loss is 0.22.
　Ｕ相において、ハイサイド側の第１オン固定期間Ｔ１ｕを電気角５０度～電気角１３０度、ロウサイド側の第２オン固定期間Ｔ２ｕを電気角２３０度～電気角３１０度にした場合、スイッチング損失は０．３５となる。つまり、Ｕ相において、ハイサイド側の第１オン固定期間Ｔ１ｕを８０度、ロウサイド側の第２オン固定期間Ｔ２ｕを１００度にした場合、スイッチング損失は０．２２となる。 In the U phase, when the first fixed ON period T1u on the high side is set at an electrical angle of 50 degrees to 130 degrees, and the second fixed ON period T2u on the low side is set at an electrical angle of 230 degrees to 310 degrees, the switching loss is is 0.35. That is, in the U-phase, if the high-side first fixed ON period T1u is 80 degrees and the low-side second fixed ON period T2u is 100 degrees, the switching loss is 0.22.
　Ｕ相において、ハイサイド側の第１オン固定期間Ｔ１ｕを電気角５０度～電気角１３０度、ロウサイド側の第２オン固定期間Ｔ２ｕを電気角２３０度～電気角３１０度にした場合、スイッチング損失は０．３５となる。つまり、Ｕ相において、ハイサイド側の第１オン固定期間Ｔ１ｕを８０度、ロウサイド側の第２オン固定期間Ｔ２ｕを８０度にした場合、スイッチング損失は０．３５となる。 In the U phase, when the first fixed ON period T1u on the high side is set at an electrical angle of 50 degrees to 130 degrees, and the second fixed ON period T2u on the low side is set at an electrical angle of 230 degrees to 310 degrees, the switching loss is is 0.35. That is, in the U-phase, if the high-side first fixed ON period T1u is 80 degrees and the low-side second fixed ON period T2u is 80 degrees, the switching loss is 0.35.
　Ｕ相において、ハイサイド側の第１オン固定期間Ｔ１ｕを電気角６０度～電気角１２０度、ロウサイド側の第２オン固定期間Ｔ２ｕを電気角２４０度～電気角３００度にした場合、スイッチング損失は０．５０となる。つまり、Ｕ相において、ハイサイド側の第１オン固定期間Ｔ１ｕを６０度、ロウサイド側の第２オン固定期間Ｔ２ｕを６０度にした場合、スイッチング損失は０．５０となる。 In the U phase, when the first fixed ON period T1u on the high side is set at an electrical angle of 60 degrees to 120 degrees and the second fixed ON period T2u on the low side is set at an electrical angle of 240 degrees to 300 degrees, the switching loss is is 0.50. That is, in the U-phase, if the high-side first fixed ON period T1u is 60 degrees and the low-side second fixed ON period T2u is 60 degrees, the switching loss is 0.50.
　以上、図１６を参照して説明したように、第１オン固定期間Ｔ１ｕおよび第２オン固定期間Ｔ２ｕは、共に、π／３（６０度）よりも長く、２π／３（１２０度）以下であることが好ましい。より好ましくは、４π／９（８０度）よりも長く、２π／３（１２０度）以下であることが好ましい。 As described above with reference to FIG. 16, both the first fixed ON period T1u and the second fixed ON period T2u are longer than π/3 (60 degrees) and 2π/3 (120 degrees) or less. Preferably. More preferably, it is longer than 4π/9 (80 degrees) and 2π/3 (120 degrees) or less.
　次に、図１７を参照して、ＵＨ＿ＵＬ保護波形の切り替えについてさらに説明する。図１７は、ＵＨ＿ＵＬ保護波形の切り替えを説明するための図である。 Next, switching of the UH_UL protection waveform will be further described with reference to FIG. FIG. 17 is a diagram for explaining switching of the UH_UL protection waveform.
　図１７において、出力電圧の波形およびスイッチング損失は、左から順に、（ｃ）波形例３（図６Ａおよび図６Ｂ）、（ｉ）波形例９（図１２Ａおよび図１２Ｂ）、（ａ）波形例１（図３Ａおよび図３Ｂ）に相当する。 In FIG. 17, the waveforms of the output voltage and the switching loss are, from the left, (c) waveform example 3 (FIGS. 6A and 6B), (i) waveform example 9 (FIGS. 12A and 12B), (a) waveform example 1 (FIGS. 3A and 3B).
　左の図に示す（ｃ）波形例３は、第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗを延長した波形例である。つまり、ハイサイドの発熱抑制を重視した波形例である。 (c) Waveform example 3 shown in the left diagram is a waveform example in which the first fixed ON period T1v and the first fixed ON period T1w are extended. In other words, this is a waveform example that emphasizes suppression of heat generation on the high side.
　中央の図に示す（ｉ）波形例３は、第１オン固定期間Ｔ１ｖ、第１オン固定期間Ｔ１ｗ、第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗを均等にした波形例である。つまり、第１オン固定期間Ｔ１ｕ、第１オン固定期間Ｔ１ｕ以外を均等にした波形例である。 (i) Waveform example 3 shown in the middle diagram is a waveform example in which the first fixed ON period T1v, the first fixed ON period T1w, the second fixed ON period T2v, and the second fixed ON period T2w are equalized. That is, it is a waveform example in which the first fixed ON period T1u and the period other than the first fixed ON period T1u are made uniform.
　右の図に示す（ａ）波形例１は、第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗを延長した波形例である。つまり、ロウサイドの発熱抑制を重視した波形例である。 (a) Waveform example 1 shown in the right figure is a waveform example in which the second fixed ON period T2v and the second fixed ON period T2w are extended. In other words, this is an example of a waveform that emphasizes suppression of heat generation on the low side.
　左の図に移行するにつれて、第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗは長くなる。したがって、左の図に移行するにつれて、Ｖ相の第１半導体スイッチング素子Ｖｐ（ハイサイド）およびＷ相の第１半導体スイッチング素子Ｗｐ（ハイサイド）のスイッチング損失が減少する。 The first fixed ON period T1v and the first fixed ON period T1w become longer as the diagram shifts to the left. Therefore, the switching losses of the V-phase first semiconductor switching element Vp (high side) and the W-phase first semiconductor switching element Wp (high side) decrease as the diagram shifts to the left.
　一方、右の図に移行するにつれて、第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗは長くなる。したがって、左の図に移行するにつれて、Ｖ相の第２半導体スイッチング素子Ｖｎ（ロウサイド）およびＷ相の第２半導体スイッチング素子Ｗｎ（ロウサイド）のスイッチング損失が減少する。 On the other hand, the second fixed ON period T2v and the second fixed ON period T2w become longer as it shifts to the right figure. Therefore, the switching loss of the V-phase second semiconductor switching element Vn (low side) and the W-phase second semiconductor switching element Wn (low side) decreases as the diagram shifts to the left.
　次に、図１６を参照して、ＵＨ＿ＵＬ保護波形の切り替えについてさらに説明する。図１６は、ＵＨ＿ＵＬ保護波形の切り替えを説明するための図である。 Next, switching of the UH_UL protection waveform will be further described with reference to FIG. FIG. 16 is a diagram for explaining switching of the UH_UL protection waveform.
　図１６において、出力電圧の波形およびスイッチング損失は、左から順に、（ｅ）波形例５（図８Ａおよび図８Ｂ）、（ｉ）波形例９（図１２Ａおよび図１２Ｂ）、（ｊ）波形例１０（図１３Ａおよび図１３Ｂ）に相当する。 In FIG. 16, the waveform of the output voltage and the switching loss are, from left to right, (e) waveform example 5 (FIGS. 8A and 8B), (i) waveform example 9 (FIGS. 12A and 12B), (j) waveform example 10 (FIGS. 13A and 13B).
　左の図に示す（ｅ）波形例５は、第１オン固定期間Ｔ１ｖおよび第２オン固定期間Ｔ２ｖを延長した波形例である。つまり、Ｖ相を重視した波形例である。 (e) Waveform example 5 shown in the left diagram is a waveform example in which the first fixed ON period T1v and the second fixed ON period T2v are extended. In other words, this is an example of a waveform that emphasizes the V phase.
　中央の図に示す（ｉ）波形例９は、第１オン固定期間Ｔ１ｖ、第１オン固定期間Ｔ１ｗ、第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗを均等にした波形例である。つまり、第１オン固定期間Ｔ１ｕ、第１オン固定期間Ｔ１ｕ以外を均等にした波形例である。 (i) Waveform example 9 shown in the middle diagram is a waveform example in which the first fixed ON period T1v, the first fixed ON period T1w, the second fixed ON period T2v, and the second fixed ON period T2w are equalized. That is, it is a waveform example in which the first fixed ON period T1u and the period other than the first fixed ON period T1u are made uniform.
　右の図に示す（ｊ）波形例１０は、第１オン固定期間Ｔ１ｗおよび第２オン固定期間Ｔ２ｗを延長した波形例である。つまり、Ｗ相を重視した波形例である。 (j) Waveform example 10 shown in the right figure is a waveform example in which the first fixed ON period T1w and the second fixed ON period T2w are extended. That is, it is an example of a waveform in which the W phase is emphasized.
　左の図に移行するにつれて、第１オン固定期間Ｔ１ｖおよび第２オン固定期間Ｔ２ｖは長くなる。したがって、左の図に移行するにつれて、Ｖ相の第１半導体スイッチング素子Ｖｐ（ハイサイド）およびＶ相の第２半導体スイッチング素子Ｖｎ（ロウサイド）のスイッチング損失が減少する。 The first fixed ON period T1v and the second fixed ON period T2v become longer as the diagram shifts to the left. Therefore, the switching losses of the V-phase first semiconductor switching element Vp (high side) and the V-phase second semiconductor switching element Vn (low side) decrease as the diagram shifts to the left.
　一方、右の図に移行するにつれて、第１オン固定期間Ｔ１ｗおよび第２オン固定期間Ｔ２ｗは長くなる。したがって、右の図に移行するにつれて、Ｗ相の第１半導体スイッチング素子Ｗｐ（ハイサイド）およびＷ相の第２半導体スイッチング素子Ｗｎ（ロウサイド）のスイッチング損失が減少する。 On the other hand, the first fixed ON period T1w and the second fixed ON period T2w become longer as the figure shifts to the right. Therefore, the switching loss of the W-phase first semiconductor switching element Wp (high side) and the W-phase second semiconductor switching element Wn (low side) decreases as the drawing shifts to the right side.
　次に、図１９を参照して、ＵＨ＿ＵＬ保護波形の切り替えについてさらに説明する。図１９は、スイッチング損失を示す図である。 Next, switching of the UH_UL protection waveform will be further described with reference to FIG. FIG. 19 is a diagram showing switching loss.
　図１９に示すように、（ｆ）波形例６（図９Ａ）、（ｈ）波形例８（図１１Ａ）、（ｋ）波形例１１（図１４Ａ）および（ｌ）波形例１２（図１５Ａ）では、第１半導体スイッチング素子Ｕｐ（ＵＨ）のスイッチング損失および第２半導体スイッチング素子Ｕｎ（ＵＬ）のスイッチング損失は、０．１３である。 As shown in FIG. 19, (f) waveform example 6 (FIG. 9A), (h) waveform example 8 (FIG. 11A), (k) waveform example 11 (FIG. 14A) and (l) waveform example 12 (FIG. 15A) Then, the switching loss of the first semiconductor switching element Up (UH) and the switching loss of the second semiconductor switching element Un (UL) are 0.13.
　（ｆ）波形例６では、第１半導体スイッチング素子Ｕｐ（ＵＨ）および第２半導体スイッチング素子Ｕｎ（ＵＬ）に加えて、さらに第２半導体スイッチング素子Ｖｎ（ＶＬ）のスイッチング損失を０．５７と減少させることができる。 (f) In waveform example 6, in addition to the first semiconductor switching element Up (UH) and the second semiconductor switching element Un (UL), the switching loss of the second semiconductor switching element Vn (VL) is reduced to 0.57. can be made
　（ｈ）波形例８では、第１半導体スイッチング素子Ｕｐ（ＵＨ）および第２半導体スイッチング素子Ｕｎ（ＵＬ）に加えて、さらに第１半導体スイッチング素子Ｗｐ（ＷＨ）のスイッチング損失を０．５７と減少させることができる。 (h) In waveform example 8, in addition to the first semiconductor switching element Up (UH) and the second semiconductor switching element Un (UL), the switching loss of the first semiconductor switching element Wp (WH) is reduced to 0.57. can be made
　（ｋ）波形例１１では、第１半導体スイッチング素子Ｕｐ（ＵＨ）および第２半導体スイッチング素子Ｕｎ（ＵＬ）に加えて、さらに第１半導体スイッチング素子Ｖｐ（ＶＨ）のスイッチング損失が０．５７と減少させることができる。 (k) In waveform example 11, in addition to the first semiconductor switching element Up (UH) and the second semiconductor switching element Un (UL), the switching loss of the first semiconductor switching element Vp (VH) is reduced to 0.57. can be made
　（ｌ）波形例１２では、第１半導体スイッチング素子Ｕｐ（ＵＨ）および第２半導体スイッチング素子Ｕｎ（ＵＬ）に加えて、さらに第２半導体スイッチング素子Ｗｎ（ＷＬ）のスイッチング損失が０．５７と減少させることができる。 (l) In waveform example 12, in addition to the first semiconductor switching element Up (UH) and the second semiconductor switching element Un (UL), the switching loss of the second semiconductor switching element Wn (WL) is reduced to 0.57. can be made
　図２０を参照して、ＵＨ＿ＵＬ保護波形の切り替えについてさらに説明する。図２０は、ＵＨ＿ＵＬ保護波形の切り替えを説明するための図である。 The switching of the UH_UL protection waveform will be further described with reference to FIG. FIG. 20 is a diagram for explaining switching of the UH_UL protection waveform.
　図２０に示す波形図は、（ｉ）波形例９（図１２Ａ）に相当する。 The waveform diagram shown in FIG. 20 corresponds to (i) waveform example 9 (FIG. 12A).
　（ａ）波形例１（図３Ａ）は、（ｉ）波形例９に対して、第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗを延長した波形に相当する。したがって、Ｖ相の第２半導体スイッチング素子Ｖｎ（ＶＬ）およびＷ相の第２半導体スイッチング素子Ｗｎ（ＷＬ）のスイッチング損失が減少する。 (a) Waveform example 1 (FIG. 3A) corresponds to a waveform in which the second fixed ON period T2v and the second fixed ON period T2w are extended with respect to (i) waveform example 9. Therefore, the switching losses of the V-phase second semiconductor switching element Vn (VL) and the W-phase second semiconductor switching element Wn (WL) are reduced.
　（ｃ）波形例３（図６Ａ）は、（ｉ）波形例９に対して、第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗを延長した波形に相当する。したがって、Ｖ相の第１半導体スイッチング素子Ｖｐ（ＶＨ）およびＷ相の第１半導体スイッチング素子Ｗｐ（ＷＨ）のスイッチング損失が減少する。 (c) Waveform example 3 (FIG. 6A) corresponds to a waveform in which the first fixed ON period T1v and the first fixed ON period T1w are extended with respect to (i) waveform example 9. Therefore, the switching losses of the V-phase first semiconductor switching element Vp (VH) and the W-phase first semiconductor switching element Wp (WH) are reduced.
　（ｅ）波形例５（図８Ａ）は、（ｉ）波形例９に対して、第１オン固定期間Ｔ１ｖおよび第２オン固定期間Ｔ２ｖを延長した波形に相当する。したがって、Ｖ相の第１半導体スイッチング素子Ｖｐ（ＶＨ）およびＶ相の第２半導体スイッチング素子Ｖｎ（ＶＬ）のスイッチング損失が減少する。 (e) Waveform example 5 (FIG. 8A) corresponds to a waveform in which the first fixed ON period T1v and the second fixed ON period T2v are extended with respect to (i) waveform example 9. Therefore, the switching losses of the V-phase first semiconductor switching element Vp (VH) and the V-phase second semiconductor switching element Vn (VL) are reduced.
　（ｊ）波形例１０（図１３Ａ）は、（ｉ）波形例９に対して、第１オン固定期間Ｔ１ｗおよび第２オン固定期間Ｔ２ｗを延長した波形に相当する。したがって、Ｗ相の第１半導体スイッチング素子Ｗｐ（ＷＨ）およびＷ相の第２半導体スイッチング素子Ｗｎ（ＷＬ）のスイッチング損失が減少する。 (j) Waveform example 10 (FIG. 13A) corresponds to a waveform in which the first fixed ON period T1w and the second fixed ON period T2w are extended with respect to (i) waveform example 9. Therefore, the switching losses of the W-phase first semiconductor switching element Wp (WH) and the W-phase second semiconductor switching element Wn (WL) are reduced.
　（ｆ）波形例６（図９Ａ）は、（ｉ）波形例９に対して、第２オン固定期間Ｔ２ｖを延長した波形に相当する。したがって、Ｖ相の第２半導体スイッチング素子Ｖｎ（ＶＬ）のスイッチング損失が減少する。 (f) Waveform example 6 (FIG. 9A) corresponds to a waveform obtained by extending the second on-fixed period T2v from (i) waveform example 9. Therefore, the switching loss of the V-phase second semiconductor switching element Vn(VL) is reduced.
　（ｈ）波形例８（図１１Ａ）は、（ｉ）波形例９に対して、第１オン固定期間Ｔ１ｗを延長した波形に相当する。したがって、Ｗ相の第１半導体スイッチング素子Ｗｐ（ＷＨ）のスイッチング損失が減少する。 (h) Waveform example 8 (FIG. 11A) corresponds to a waveform obtained by extending the first fixed ON period T1w with respect to (i) waveform example 9. Therefore, the switching loss of the W-phase first semiconductor switching element Wp(WH) is reduced.
　（ｋ）波形例１１（図１４Ａ）は、（ｉ）波形例９に対して、第１オン固定期間Ｔ１ｖを延長した波形に相当する。したがって、Ｖ相の第１半導体スイッチング素子Ｖｐ（ＶＨ）のスイッチング損失が減少する。 (k) Waveform example 11 (FIG. 14A) corresponds to a waveform obtained by extending the first fixed ON period T1v with respect to (i) waveform example 9. Therefore, the switching loss of the V-phase first semiconductor switching element Vp (VH) is reduced.
　（ｌ）波形例１２（図１５Ａ）は、（ｉ）波形例９に対して、第２オン固定期間Ｔ２ｗを延長した波形に相当する。したがって、Ｗ相の第２半導体スイッチング素子Ｗｎ（ＷＬ）のスイッチング損失が減少する。 (l) Waveform example 12 (FIG. 15A) corresponds to a waveform obtained by extending the second on-fixed period T2w from (i) waveform example 9. Therefore, the switching loss of the W-phase second semiconductor switching element Wn(WL) is reduced.
　図２１を参照して保護波形の切替方法について説明する。図２１は、保護波形の切替方法を示すフローチャートである。 A method of switching the protection waveform will be described with reference to FIG. FIG. 21 is a flow chart showing a protection waveform switching method.
　ステップＳ１０２：、信号生成部１２０は、各アーム（半導体スイッチング素子）の温度Ｔ＿ＵＨ、温度Ｔ＿ＵＬ、温度Ｔ＿ＶＨ、温度Ｔ＿ＶＬ、温度Ｔ＿ＷＨ、温度Ｔ＿ＷＨを取得する。温度Ｔ＿ＵＨは、第１半導体スイッチング素子Ｕｐの温度を示す。温度Ｔ＿ＵＬは、第２半導体スイッチング素子Ｕｎの温度を示す。温度Ｔ＿ＶＨは、第１半導体スイッチング素子Ｖｐの温度を示す。温度Ｔ＿ＶＬは、第２半導体スイッチング素子Ｖｎの温度を示す。温度Ｔ＿ＷＨは、第１半導体スイッチング素子Ｗｐの温度を示す。温度Ｔ＿ＷＬは、第２半導体スイッチング素子Ｗｎの温度を示す。 Step S102: The signal generator 120 acquires the temperature T_UH, temperature T_UL, temperature T_VH, temperature T_VL, temperature T_WH, and temperature T_WH of each arm (semiconductor switching element). A temperature T_UH indicates the temperature of the first semiconductor switching element Up. A temperature T_UL indicates the temperature of the second semiconductor switching element Un. A temperature T_VH indicates the temperature of the first semiconductor switching element Vp. A temperature T_VL indicates the temperature of the second semiconductor switching element Vn. A temperature T_WH indicates the temperature of the first semiconductor switching element Wp. A temperature T_WL indicates the temperature of the second semiconductor switching element Wn.
　そして、信号生成部１２０は、取得した温度Ｔ＿ＵＨ、温度Ｔ＿ＵＬ、温度Ｔ＿ＶＨ、温度Ｔ＿ＶＬ、温度Ｔ＿ＷＨ、温度Ｔ＿ＷＨを、温度が高い順にＴ＿１、Ｔ＿２、Ｔ＿３、Ｔ＿４、Ｔ＿５およびＴ＿６とする。処理は、ステップＳ１０４に進む。 Then, the signal generation unit 120 sets the acquired temperature T_UH, temperature T_UL, temperature T_VH, temperature T_VL, temperature T_WH, and temperature T_WH to T_1, T_2, T_3, T_4, T_5, and T_6 in descending order of temperature. The process proceeds to step S104.
　ステップＳ１０４：信号生成部１２０は、最高温の上アーム（第１半導体スイッチング素子）と、最高温の下アーム（第２半導体スイッチング素子）は同相であるか否かを判定する。最高温の上アーム（第１半導体スイッチング素子）と、最高温の下アーム（第２半導体スイッチング素子）は同相でないと、信号生成部１２０が判定した場合（ステップＳ１０４：Ｎｏ）、処理はステップＳ１０８に進む。最高温の上アーム（第１半導体スイッチング素子）と、最高温の下アーム（第２半導体スイッチング素子）は同相であると、信号生成部１２０が判定した場合（ステップＳ１０４：Ｙｅｓ）、処理はステップＳ１０６に進む。 Step S104: The signal generator 120 determines whether or not the highest temperature upper arm (first semiconductor switching element) and the highest temperature lower arm (second semiconductor switching element) are in phase. When the signal generator 120 determines that the highest temperature upper arm (first semiconductor switching element) and the highest temperature lower arm (second semiconductor switching element) are not in phase (step S104: No), the process proceeds to step S108. proceed to When the signal generator 120 determines that the highest temperature upper arm (first semiconductor switching element) and the highest temperature lower arm (second semiconductor switching element) are in phase (step S104: Yes), the process proceeds to step Proceed to S106.
　ステップＳ１０６：信号生成部１２０は、Ｘ相上下段の温度上昇を抑制するようなパターンで変調を行う。Ｘ相は、例えば、Ｕ相、Ｖ相またはＷ相である。処理は、終了する。ステップＳ１０６の詳細な処理については、図２２～図２４を参照して後述する。 Step S106: The signal generator 120 modulates in a pattern that suppresses temperature rise in the upper and lower stages of the X phase. The X phase is, for example, U phase, V phase or W phase. Processing ends. Detailed processing of step S106 will be described later with reference to FIGS.
　ステップＳ１０８：信号生成部１２０は、Ｘ相上段とＹ相下段の温度上昇を抑制するようなパターンで変調を行う。Ｙ相は、例えば、Ｕ相、Ｖ相またはＷ相である。処理は、終了する。ステップＳ１０８の詳細な処理については、図４７～図４９を参照して後述する。 Step S108: The signal generator 120 modulates in a pattern that suppresses temperature rise in the X-phase upper stage and the Y-phase lower stage. Y-phase is, for example, U-phase, V-phase or W-phase. Processing ends. Detailed processing of step S108 will be described later with reference to FIGS.
　図２２から図２４を参照して図２１に示したステップＳ１０６の詳細な処理について説明する。すなわち、Ｘ相上下段の温度上昇を抑制するようなパターンで変調する場合の処理について説明する。図２２は、保護波形の切替方法を示すフローチャートである。図２３および図２４は、保護波形の切替方法を示す図である。なお、図２２～図２４は、Ｘ相の例としてＵ相を用いた場合の保護波形の切替方法を示している。 The detailed processing of step S106 shown in FIG. 21 will be described with reference to FIGS. 22 to 24. FIG. In other words, a description will be given of processing in the case of modulation in a pattern that suppresses temperature rise in the upper and lower stages of the X phase. FIG. 22 is a flow chart showing a protection waveform switching method. 23 and 24 are diagrams showing a switching method of the protection waveform. 22 to 24 show the switching method of the protection waveform when the U phase is used as an example of the X phase.
　ステップＳ２０２：信号生成部１２０は、温度Ｔ＿３～Ｔ＿６が閾値Ｔ＿Ｔｈｒ１以下であるか否かを判定する。温度Ｔ＿３～Ｔ＿６が閾値Ｔ＿Ｔｈｒ１以下でないと、信号生成部１２０が判定した場合（ステップＳ２０２：Ｎｏ）、処理はステップＳ２０６に進む。温度Ｔ＿３～Ｔ＿６が閾値Ｔ＿Ｔｈｒ１以下であると、信号生成部１２０が判定した場合（ステップＳ２０２：Ｙｅｓ）、処理はステップＳ２０４に進む。 Step S202: The signal generator 120 determines whether the temperatures T_3 to T_6 are equal to or lower than the threshold T_Thr1. When the signal generator 120 determines that the temperatures T_3 to T_6 are not equal to or lower than the threshold value T_Thr1 (step S202: No), the process proceeds to step S206. When the signal generator 120 determines that the temperatures T_3 to T_6 are equal to or lower than the threshold T_Thr1 (step S202: Yes), the process proceeds to step S204.
　ステップＳ２０４：信号生成部１２０は、４つ保護パターンで変調を行う。詳しくは、信号生成部１２０は、（ｉ）波形例９で変調を行う。処理は終了する。 Step S204: The signal generator 120 modulates with four protection patterns. Specifically, the signal generator 120 performs modulation with (i) waveform example 9; Processing ends.
　ステップＳ２０６：信号生成部１２０は、温度Ｔ＿５～Ｔ＿６が閾値Ｔ＿Ｔｈｒ２以下であるか否かを判定する。温度Ｔ＿５～Ｔ＿６が閾値Ｔ＿Ｔｈｒ２以下でないと、信号生成部１２０が判定した場合（ステップＳ２０６：Ｎｏ）、処理はステップＳ２１０に進む。温度Ｔ＿５～Ｔ＿６が閾値Ｔ＿Ｔｈｒ２以下であると、信号生成部１２０が判定した場合（ステップＳ２０６：Ｙｅｓ）、処理はステップＳ２０８に進む。 Step S206: The signal generator 120 determines whether the temperatures T_5 to T_6 are equal to or lower than the threshold T_Thr2. When the signal generator 120 determines that the temperatures T_5 to T_6 are not equal to or lower than the threshold value T_Thr2 (step S206: No), the process proceeds to step S210. When the signal generator 120 determines that the temperatures T_5 to T_6 are equal to or lower than the threshold T_Thr2 (step S206: Yes), the process proceeds to step S208.
　ステップＳ２０８：信号生成部１２０は、３つ保護パターンと４つ保護パターンとの中間で変調を行う。３つ保護パターンと４つ保護パターンとの中間で変調については、図２３を参照して後述する。処理は終了する。 Step S208: The signal generator 120 modulates between the three protection patterns and the four protection patterns. Modulation in between the 3 guard pattern and the 4 guard pattern will be described later with reference to FIG. Processing ends.
　ステップＳ２１０：信号生成部１２０は、温度Ｔ＿３～Ｔ＿５が閾値Ｔ＿Ｔｈｒ３以下であるか否かを判定する。温度Ｔ＿３～Ｔ＿５が閾値Ｔ＿Ｔｈｒ３以下でないと、信号生成部１２０が判定した場合（ステップＳ２１０：Ｎｏ）、処理はステップＳ２１４に進む。温度Ｔ＿３～Ｔ＿５が閾値Ｔ＿Ｔｈｒ３以下であると、信号生成部１２０が判定した場合（ステップＳ２１０：Ｙｅｓ）、処理はステップＳ２１２に進む。 Step S210: The signal generator 120 determines whether the temperatures T_3 to T_5 are equal to or lower than the threshold T_Thr3. When the signal generator 120 determines that the temperatures T_3 to T_5 are not equal to or lower than the threshold value T_Thr3 (step S210: No), the process proceeds to step S214. When the signal generator 120 determines that the temperatures T_3 to T_5 are equal to or lower than the threshold T_Thr3 (step S210: Yes), the process proceeds to step S212.
　ステップＳ２１２：信号生成部１２０は、３つ保護パターンで変調を行う。詳しくは、信号生成部１２０は、（ｋ）波形例１１、（ｆ）波形例６、（ｈ）波形例８、（ｌ）波形例１２のうち、温度がＴ＿３、Ｔ＿４、Ｔ＿５となるアーム（半導体スイッチング素子）を保護できるパターンで変調を行う。処理は終了する。 Step S212: The signal generator 120 modulates with three protection patterns. Specifically, the signal generation unit 120 selects the arms (or (Semiconductor switching elements) are modulated with a pattern that can protect them. Processing ends.
　ステップＳ２１４：信号生成部１２０は、温度Ｔ＿４～Ｔ＿５が閾値Ｔ＿Ｔｈｒ４以下であるか否かを判定する。温度Ｔ＿４～Ｔ＿５が閾値Ｔ＿Ｔｈｒ４以下でないと、信号生成部１２０が判定した場合（ステップＳ２１４：Ｎｏ）、処理はステップＳ２１８に進む。温度Ｔ＿４～Ｔ＿５が閾値Ｔ＿Ｔｈｒ４以下であると、信号生成部１２０が判定した場合（ステップＳ２１４：Ｙｅｓ）、処理はステップＳ２１６に進む。 Step S214: The signal generator 120 determines whether the temperatures T_4 to T_5 are equal to or lower than the threshold T_Thr4. When the signal generator 120 determines that the temperatures T_4 to T_5 are not equal to or lower than the threshold value T_Thr4 (step S214: No), the process proceeds to step S218. When the signal generator 120 determines that the temperatures T_4 to T_5 are equal to or lower than the threshold value T_Thr4 (step S214: Yes), the process proceeds to step S216.
　ステップＳ２１６：信号生成部１２０は、２つ保護パターンと３つ保護パターンとの中間で変調を行う。２つ保護パターンと３つ保護パターンとの中間で変調については、図２４を参照して後述する。処理は終了する。 Step S216: The signal generator 120 modulates between the two protection patterns and the three protection patterns. Modulation in between the 2 guard pattern and the 3 guard pattern will be described later with reference to FIG. Processing ends.
　ステップＳ２１８：信号生成部１２０は、２つ保護パターンで変調を行う。詳しくは、信号生成部１２０は、（ａ）波形例１、（ｃ）波形例３、（ｅ）波形例５、（ｆ）波形例６、（ｉ）波形例９および（ｊ）波形例１０のうち、温度がＴ＿３、Ｔ＿４となるアーム（半導体スイッチング素子）を保護できるパターンで変調を行う。処理は終了する。 Step S218: The signal generator 120 modulates with two protection patterns. Specifically, the signal generator 120 generates (a) waveform example 1, (c) waveform example 3, (e) waveform example 5, (f) waveform example 6, (i) waveform example 9, and (j) waveform example 10. Of these, modulation is performed with a pattern that can protect arms (semiconductor switching elements) whose temperatures are T_3 and T_4. Processing ends.
　次に、図２３を参照して図２２に示したステップＳ２０８の詳細な処理について説明する。すなわち、３つ保護パターンと４つ保護パターンとの中間で変調を行う場合の処理について説明する。 Next, the detailed processing of step S208 shown in FIG. 22 will be described with reference to FIG. That is, a description will be given of the processing in the case of performing modulation between the three protection patterns and the four protection patterns.
　信号生成部１２０は、ＵＨ（第１半導体スイッチング素子Ｕｐ）およびＵＬ（第２半導体スイッチング素子Ｕｎ）を除いて温度の高い上位３アーム（半導体スイッチング素子）の位置を判定する。以下、図２３の説明において、「ＵＨ（第１半導体スイッチング素子Ｕｐ）およびＵＬ（第２半導体スイッチング素子Ｕｎ）を除いて温度の高い上位３アーム（半導体スイッチング素子）」を、単に「上位３アーム」と記載することがある。なお、上位３アームの温度の順番は問わない。例えば、上位３アームの温度の順番が、ＶＨ（第１半導体スイッチング素子Ｖｐ）、ＶＬ（第２半導体スイッチング素子Ｖｎ）およびＷＨ（第１半導体スイッチング素子Ｗｐ）の順でもよいし、ＶＨ（第１半導体スイッチング素子Ｖｐ）、ＷＨ（第１半導体スイッチング素子Ｗｐ）およびＶＬ（第２半導体スイッチング素子Ｖｎ）の順でもよい。以下、同様の記載についても同様に上位３アームの温度の順番は問わない。 The signal generation unit 120 determines the positions of the three arms (semiconductor switching elements) with the highest temperature, excluding UH (first semiconductor switching element Up) and UL (second semiconductor switching element Un). Hereinafter, in the description of FIG. 23, "upper three arms (semiconductor switching elements) with higher temperatures excluding UH (first semiconductor switching element Up) and UL (second semiconductor switching element Un)" will simply be referred to as "upper three arms ” may be stated. Note that the order of the temperatures of the top three arms does not matter. For example, the order of the temperatures of the upper three arms may be VH (first semiconductor switching element Vp), VL (second semiconductor switching element Vn), and WH (first semiconductor switching element Wp), or VH (first semiconductor switching element Wp). The order of semiconductor switching element Vp), WH (first semiconductor switching element Wp) and VL (second semiconductor switching element Vn) is also acceptable. In the same description below, the order of the temperatures of the top three arms is similarly irrelevant.
　信号生成部１２０が、上位３アームがＶＨ（第１半導体スイッチング素子Ｖｐ）、ＶＬ（第２半導体スイッチング素子Ｖｎ）およびＷＨ（第１半導体スイッチング素子Ｗｐ）であると判定した場合、（ｋ）波形例１１において、１５０度～１５０＋３０×（Ｔ＿Ｔｈｒ２－（Ｔ＿５－Ｔ＿６））／Ｔ＿Ｔｈｒ２度を第１オン固定期間、３３０度～３３０＋３０×（Ｔ＿Ｔｈｒ２－（Ｔ＿５－Ｔ＿６））／Ｔ＿Ｔｈｒ２度を第２オン固定期間に適用したパターンで、信号生成部１２０は変調を行う。 When signal generation unit 120 determines that the upper three arms are VH (first semiconductor switching element Vp), VL (second semiconductor switching element Vn), and WH (first semiconductor switching element Wp), (k) waveform In Example 11, 150 degrees to 150+30×(T_Thr2−(T_5−T_6))/T_Thr2 degrees is the first fixed ON period, and 330 degrees to 330+30×(T_Thr2−(T_5−T_6))/T_Thr2 degrees is the second fixed ON period. The signal generator 120 modulates with the pattern applied to the period.
　信号生成部１２０が、上位３アームがＶＨ（第１半導体スイッチング素子Ｖｐ）、ＶＬ（第２半導体スイッチング素子Ｖｎ）およびＷＬ（第２半導体スイッチング素子Ｗｎ）であると判定した場合、信号生成部１２０は、（ｆ）波形例６で変調を行う。 When signal generation unit 120 determines that the upper three arms are VH (first semiconductor switching element Vp), VL (second semiconductor switching element Vn), and WL (second semiconductor switching element Wn), signal generation unit 120 modulates with (f) waveform example 6;
　信号生成部１２０が、上位３アームがＶＨ（第１半導体スイッチング素子Ｖｐ）、ＶＬ（第２半導体スイッチング素子Ｖｎ）およびＷＨ（第１半導体スイッチング素子Ｗｐ）であると判定した場合、（ｈ）波形例８において、０度～０＋３０×（Ｔ＿Ｔｈｒ２－（Ｔ＿５－Ｔ＿６））／Ｔ＿Ｔｈｒ２度を第１オン固定期間、３３０度～３３０＋３０×（Ｔ＿Ｔｈｒ２－（Ｔ＿５－Ｔ＿６））／Ｔ＿Ｔｈｒ２を第２オン固定期間に適用したパターンで、信号生成部１２０は変調を行う。 When signal generation unit 120 determines that the upper three arms are VH (first semiconductor switching element Vp), VL (second semiconductor switching element Vn), and WH (first semiconductor switching element Wp), (h) waveform In Example 8, 0 degrees to 0+30×(T_Thr2−(T_5−T_6))/T_Thr2 degrees is the first fixed ON period, and 330 degrees to 330+30×(T_Thr2−(T_5−T_6))/T_Thr2 is the second fixed ON period. The signal generator 120 modulates with the pattern applied to .
　信号生成部１２０が、上位３アームがＶＨ（第１半導体スイッチング素子Ｖｐ）、ＶＬ（第２半導体スイッチング素子Ｖｎ）およびＷＬ（第２半導体スイッチング素子Ｗｎ）であると判定した場合、（ｌ）波形例１２において、０度～０＋３０×（Ｔ＿Ｔｈｒ２－（Ｔ＿５－Ｔ＿６））／Ｔ＿Ｔｈｒ２度を第１オン固定期間、３３０度～３３０＋３０×（Ｔ＿Ｔｈｒ２－（Ｔ＿５－Ｔ＿６））／Ｔ＿Ｔｈｒ２度を第２オン固定期間に適用したパターンで、信号生成部１２０は変調を行う。 When signal generation unit 120 determines that the upper three arms are VH (first semiconductor switching element Vp), VL (second semiconductor switching element Vn), and WL (second semiconductor switching element Wn), (l) waveform In Example 12, 0 degrees to 0+30×(T_Thr2−(T_5−T_6))/T_Thr2 degrees is the first fixed ON period, and 330 degrees to 330+30×(T_Thr2−(T_5−T_6))/T_Thr2 degrees is the second fixed ON period. The signal generator 120 modulates with the pattern applied to the period.
　次に、図２４を参照して図２２に示したステップＳ２１６の詳細な処理について説明する。すなわち、２つ保護パターンと３つ保護パターンとの中間で変調を行う場合の処理について説明する。 Next, the detailed processing of step S216 shown in FIG. 22 will be described with reference to FIG. In other words, a description will be given of processing in the case of performing modulation between the two protection patterns and the three protection patterns.
　信号生成部１２０は、ＵＨ（第１半導体スイッチング素子Ｕｐ）およびＵＬ（第２半導体スイッチング素子Ｕｎ）を除いて温度の高い上位２アーム（半導体スイッチング素子）の位置を判定する。以下、図２４の説明において、「ＵＨ（第１半導体スイッチング素子Ｕｐ）およびＵＬ（第２半導体スイッチング素子Ｕｎ）を除いて温度の高い上位２アーム（半導体スイッチング素子）」を、単に「上位２アーム」と記載することがある。なお、上位２アームの温度の順番は問わない。例えば、上位２アームの温度の順番が、ＶＬ（第２半導体スイッチング素子Ｖｎ）およびＷＬ（第２半導体スイッチング素子Ｗｎ）の順でもよいし、ＷＬ（第２半導体スイッチング素子Ｗｎ）およびＶＬ（第２半導体スイッチング素子Ｖｎ）の順でもよい。以下、同様の記載についても同様に上位３アームの温度の順番は問わない。 The signal generation unit 120 determines the positions of the upper two arms (semiconductor switching elements) with the highest temperature, excluding UH (first semiconductor switching element Up) and UL (second semiconductor switching element Un). Hereinafter, in the description of FIG. 24, "upper two arms (semiconductor switching elements) with higher temperatures excluding UH (first semiconductor switching element Up) and UL (second semiconductor switching element Un)" will simply be referred to as "upper two arms ” may be stated. Note that the order of the temperatures of the upper two arms does not matter. For example, the order of the temperatures of the upper two arms may be VL (second semiconductor switching element Vn) and WL (second semiconductor switching element Wn), or WL (second semiconductor switching element Wn) and VL (second semiconductor switching element Wn). The order of the semiconductor switching elements Vn) may also be used. In the same description below, the order of the temperatures of the top three arms is similarly irrelevant.
　さらに、信号生成部１２０は、ＵＨ（第１半導体スイッチング素子Ｕｐ）およびＵＬ（第２半導体スイッチング素子Ｕｎ）を除いて上位３番目に高温のアーム（半導体スイッチング素子）の位置を判定する。以下、図２４の説明において、「ＵＨ（第１半導体スイッチング素子Ｕｐ）およびＵＬ（第２半導体スイッチング素子Ｕｎ）を除いて上位３番目に高温のアーム（半導体スイッチング素子）」を、単に「上位３番目に高温のアーム」と記載することがある。 Furthermore, the signal generation unit 120 determines the position of the arm (semiconductor switching element) with the third highest temperature, excluding UH (first semiconductor switching element Up) and UL (second semiconductor switching element Un). Hereinafter, in the description of FIG. 24, "upper third hot arm (semiconductor switching element) excluding UH (first semiconductor switching element Up) and UL (second semiconductor switching element Un)" is simply referred to as "upper three It is sometimes described as "the arm with the highest temperature".
　上位２アームの位置がＶＬ（第２半導体スイッチング素子Ｖｎ）およびＷＬ（第２半導体スイッチング素子Ｖｎ）、かつ、上位３番目に高温のアームがＶＨ（第１半導体スイッチング素子Ｖｐ）であると、信号生成部１２０が判定した場合、（ａ）波形例１において、１８０度～１８０＋３０×（Ｔ＿Ｔｈｒ４－（Ｔ＿４－Ｔ＿５））／Ｔ＿Ｔｈｒ４度を第１オン固定期間に適用したパターンで、信号生成部１２０は変調を行う。処理は終了する。 When the positions of the upper two arms are VL (second semiconductor switching element Vn) and WL (second semiconductor switching element Vn), and the arm with the third highest temperature is VH (first semiconductor switching element Vp), a signal When the generation unit 120 determines that (a) in the waveform example 1, the pattern in which 180 degrees to 180+30×(T_Thr4−(T_4−T_5))/T_Thr4 degrees is applied to the first fixed ON period, the signal generation unit 120 modulate. Processing ends.
　上位２アームの位置がＶＬ（第２半導体スイッチング素子Ｖｎ）およびＷＬ（第２半導体スイッチング素子Ｖｎ）、かつ、上位３番目に高温のアームがＷＨ（第１半導体スイッチング素子Ｗｐ）であると、信号生成部１２０が判定した場合、（ａ）波形例１において、３３０度～３３０＋３０×（Ｔ＿Ｔｈｒ４－（Ｔ＿４－Ｔ＿５））／Ｔ＿Ｔｈｒ４度を第１オン固定期間に適用したパターンで、信号生成部１２０は変調を行う。処理は終了する。 When the positions of the upper two arms are VL (second semiconductor switching element Vn) and WL (second semiconductor switching element Vn), and the arm with the third highest temperature is WH (first semiconductor switching element Wp), a signal When the generation unit 120 determines that (a) in the waveform example 1, the pattern in which 330 degrees to 330+30×(T_Thr4−(T_4−T_5))/T_Thr4 degrees is applied to the first fixed ON period, the signal generation unit 120 modulate. Processing ends.
　上位２アームの位置がＶＨ（第１半導体スイッチング素子Ｖｐ）およびＷＨ（第１半導体スイッチング素子Ｗｐ）、かつ、上位３番目に高温のアームがＶＬ（第２半導体スイッチング素子Ｖｎ）であると、信号生成部１２０が判定した場合、（ｃ）波形例３において、０度～０＋３０×（Ｔ＿Ｔｈｒ４－（Ｔ＿４－Ｔ＿５））／Ｔ＿Ｔｈｒ４度を第２オン固定期間に適用したパターンで、信号生成部１２０は変調を行う。 When the positions of the upper two arms are VH (first semiconductor switching element Vp) and WH (first semiconductor switching element Wp), and the arm with the third highest temperature is VL (second semiconductor switching element Vn), a signal When the generation unit 120 determines that (c) in the waveform example 3, the pattern in which 0 degrees to 0+30×(T_Thr4−(T_4−T_5))/T_Thr4 degrees is applied to the second fixed ON period, the signal generation unit 120 modulate.
　上位２アームの位置がＶＨ（第１半導体スイッチング素子Ｖｐ）およびＷＨ（第１半導体スイッチング素子Ｗｐ）、かつ、上位３番目に高温のアームがＷＬ（第２半導体スイッチング素子Ｗｎ）であると、信号生成部１２０が判定した場合、（ｃ）波形例３において、１５０度～１５０＋３０×（Ｔ＿Ｔｈｒ４－（Ｔ＿４－Ｔ＿５））／Ｔ＿Ｔｈｒ４度を第２オン固定期間に適用したパターンで、信号生成部１２０は変調を行う。 When the positions of the upper two arms are VH (first semiconductor switching element Vp) and WH (first semiconductor switching element Wp), and the arm with the third highest temperature is WL (second semiconductor switching element Wn), a signal When the generating unit 120 determines that (c) in the waveform example 3, the pattern in which 150 degrees to 150+30×(T_Thr4−(T_4−T_5))/T_Thr4 degrees is applied to the second fixed ON period, the signal generating unit 120 modulate.
　上位２アームの位置がＶＨ（第１半導体スイッチング素子Ｖｐ）およびＶＬ（第２半導体スイッチング素子Ｖｎ）、かつ、上位３番目に高温のアームがＷＨ（第１半導体スイッチング素子Ｗｐ）であると、信号生成部１２０が判定した場合、（ｅ）波形例５において、３３０度～３３０＋３０×（Ｔ＿Ｔｈｒ４－（Ｔ＿４－Ｔ＿５））／Ｔ＿Ｔｈｒ４度を第１オン固定期間に適用したパターンで、信号生成部１２０は変調を行う。 When the positions of the upper two arms are VH (first semiconductor switching element Vp) and VL (second semiconductor switching element Vn), and the arm with the third highest temperature is WH (first semiconductor switching element Wp), a signal If the generating unit 120 determines, (e) in the waveform example 5, the pattern in which 330 degrees to 330+30×(T_Thr4−(T_4−T_5))/T_Thr4 degrees is applied to the first fixed ON period, and the signal generating unit 120 modulate.
　上位２アームの位置がＶＨ（第１半導体スイッチング素子Ｖｐ）およびＶＬ（第２半導体スイッチング素子Ｖｎ）、かつ、上位３番目に高温のアームがＷＬ（第２半導体スイッチング素子Ｗｎ）であると、信号生成部１２０が判定した場合、（ｅ）波形例５において、１５０度～１５０＋３０×（Ｔ＿Ｔｈｒ４－（Ｔ＿４－Ｔ＿５））／Ｔ＿Ｔｈｒ４度を第２オン固定期間に適用したパターンで、信号生成部１２０は変調を行う。 When the positions of the upper two arms are VH (first semiconductor switching element Vp) and VL (second semiconductor switching element Vn), and the arm with the third highest temperature is WL (second semiconductor switching element Wn), a signal If the generating unit 120 determines, (e) in the waveform example 5, the pattern in which 150 degrees to 150+30×(T_Thr4−(T_4−T_5))/T_Thr4 degrees is applied to the second fixed ON period, and the signal generating unit 120 modulate.
　上位２アームの位置がＶＨ（第１半導体スイッチング素子Ｖｐ）およびＷＬ（第２半導体スイッチング素子Ｗｎ）、かつ、上位３番目に高温のアームがＷＨ（第１半導体スイッチング素子Ｗｐ）であると、信号生成部１２０が判定した場合、（ｆ）波形例６において、３３０度～３３０＋６０×（Ｔ＿Ｔｈｒ４－（Ｔ＿４－Ｔ＿５））／Ｔ＿Ｔｈｒ４度を第１オン固定期間に適用したパターンで、信号生成部１２０は変調を行う。但し、上限が３６０度をＤ度だけ超える場合、（ｆ）波形例６において第１オン固定期間を適用する区間は、０度～Ｄ度及び３３０度～３６０度とする。 When the positions of the upper two arms are VH (first semiconductor switching element Vp) and WL (second semiconductor switching element Wn), and the arm with the third highest temperature is WH (first semiconductor switching element Wp), a signal When the generation unit 120 determines that (f) in the waveform example 6, the pattern in which 330 degrees to 330+60×(T_Thr4−(T_4−T_5))/T_Thr4 degrees is applied to the first fixed ON period, the signal generation unit 120 modulate. However, if the upper limit exceeds 360 degrees by D degrees, the sections to which the first fixed ON period is applied in (f) waveform example 6 are 0 degrees to D degrees and 330 degrees to 360 degrees.
　上位２アームの位置がＶＨ（第１半導体スイッチング素子Ｖｐ）およびＷＬ（第２半導体スイッチング素子Ｗｎ）、かつ、上位３番目に高温のアームがＶＬ（第２半導体スイッチング素子Ｖｎ）であると、信号生成部１２０が判定した場合、信号生成部１２０は、（ｆ）波形例６で変調を行う。処理は終了する。 When the positions of the upper two arms are VH (first semiconductor switching element Vp) and WL (second semiconductor switching element Wn), and the arm with the third highest temperature is VL (second semiconductor switching element Vn), a signal If the generation unit 120 determines, the signal generation unit 120 modulates with (f) waveform example 6 . Processing ends.
　上位２アームの位置がＶＬ（第２半導体スイッチング素子Ｖｎ）およびＷＨ（第１半導体スイッチング素子Ｗｐ）、かつ、上位３番目に高温のアームがＷＬ（第２半導体スイッチング素子Ｗｎ）であると、信号生成部１２０判定した場合、（ｉ）波形例９において、１８０度～１８０＋３０×（Ｔ＿Ｔｈｒ４－（Ｔ＿４－Ｔ＿５））／Ｔ＿Ｔｈｒ４度を第２オン固定期間に適用したパターンで、信号生成部１２０は変調を行う。 When the positions of the upper two arms are VL (second semiconductor switching element Vn) and WH (first semiconductor switching element Wp), and the arm with the third highest temperature is WL (second semiconductor switching element Wn), a signal If the generating unit 120 determines, (i) in waveform example 9, the signal generating unit 120 modulates with a pattern in which 180 degrees to 180+30×(T_Thr4−(T_4−T_5))/T_Thr4 degrees is applied to the second ON fixed period. I do.
　上位２アームの位置がＶＬ（第２半導体スイッチング素子Ｖｎ）およびＷＨ（第１半導体スイッチング素子Ｗｐ）、かつ、上位３番目に高温のアームがＶＨ（第１半導体スイッチング素子Ｖｐ）であると、信号生成部１２０が判定した場合、（ｉ）波形例９において、１５０度～１５０＋３０×（Ｔ＿Ｔｈｒ４－（Ｔ＿４－Ｔ＿５））／Ｔ＿Ｔｈｒ４度を第１オン固定期間に適用したパターンで、信号生成部１２０は変調を行う。 When the positions of the upper two arms are VL (second semiconductor switching element Vn) and WH (first semiconductor switching element Wp), and the arm with the third highest temperature is VH (first semiconductor switching element Vp), a signal When the generating unit 120 determines, (i) in the waveform example 9, the pattern in which 150 degrees to 150+30×(T_Thr4−(T_4−T_5))/T_Thr4 degrees is applied to the first fixed ON period, and the signal generating unit 120 modulate.
　上位２アームの位置がＷＨ（第１半導体スイッチング素子Ｗｐ）およびＷＬ（第２半導体スイッチング素子Ｗｎ）、かつ、上位３番目に高温のアームがＶＬ（第２半導体スイッチング素子Ｖｎ）であると、信号生成部１２０判定した場合、（ｊ）波形例１０において、０度～０＋３０×（Ｔ＿Ｔｈｒ４－（Ｔ＿４－Ｔ＿５））／Ｔ＿Ｔｈｒ４度を第２オン固定期間に適用したパターンで、信号生成部１２０は変調を行う。 When the positions of the upper two arms are WH (first semiconductor switching element Wp) and WL (second semiconductor switching element Wn), and the arm with the third highest temperature is VL (second semiconductor switching element Vn), a signal If the generation unit 120 determines, (j) in waveform example 10, the signal generation unit 120 modulates with a pattern in which 0 degrees to 0+30×(T_Thr4−(T_4−T_5))/T_Thr4 degrees is applied to the second ON fixed period. I do.
　上位２アームの位置がＷＨ（第１半導体スイッチング素子Ｗｐ）およびＷＬ（第２半導体スイッチング素子Ｗｎ）、かつ、上位３番目に高温のアームがＶＨ（第１半導体スイッチング素子Ｖｐ）であると、信号生成部１２０が判定した場合、（ｊ）波形例１０において、１８０度～１８０＋３０×（Ｔ＿Ｔｈｒ４－（Ｔ＿４－Ｔ＿５））／Ｔ＿Ｔｈｒ４度を第１オン固定期間に適用したパターンで、信号生成部１２０は変調を行う。 When the positions of the upper two arms are WH (first semiconductor switching element Wp) and WL (second semiconductor switching element Wn), and the arm with the third highest temperature is VH (first semiconductor switching element Vp), a signal When the generation unit 120 determines that (j) in waveform example 10, the pattern in which 180 degrees to 180+30×(T_Thr4−(T_4−T_5))/T_Thr4 degrees is applied to the first fixed ON period, the signal generation unit 120 modulate.
　以上、図２１～図２４を参照して説明したように、保護動作モードは、１つの相の第１半導体スイッチング素子と第２半導体スイッチング素子とを保護する第１選択保護動作モードを含む、第１選択保護動作モードは、１つの相以外の相の第１半導体スイッチング素子と第２半導体スイッチング素子のうち、ｋ個（ｋは２ｎ－３以下の自然数）の第１半導体スイッチング素子または第２半導体スイッチング素子を保護する、複数のｋ個保護動作モードを含む。温度情報に基づいて、ｋ個保護動作モードの選択を行う。したがって、冷却水路の問題などで特定の相の温度が問題となる場合、特定の相の温度が問題となる場合、特定の１相の第１半導体スイッチング素子と第２半導体スイッチング素子との昇温を最大限に抑制しながら、他の半導体スイッチング素子も温度状況に応じて必要な半導体スイッチング素子の昇温を抑制することで、インバータの信頼性が高まる。 As described above with reference to FIGS. 21 to 24, the protection operation mode includes the first selective protection operation mode that protects the first semiconductor switching element and the second semiconductor switching element of one phase. In the one-selection protection operation mode, among the first semiconductor switching elements and the second semiconductor switching elements of phases other than one phase, k (k is a natural number of 2n−3 or less) first semiconductor switching elements or second semiconductor switching elements It includes a plurality of k protection modes of operation to protect the switching elements. Selection of k protection operation modes is performed based on the temperature information. Therefore, if the temperature of a specific phase becomes a problem due to a problem in the cooling water passage, etc., if the temperature of the specific phase becomes a problem, the temperature rise of the first semiconductor switching element and the second semiconductor switching element of a specific phase While suppressing to the maximum extent possible, other semiconductor switching elements also suppress the temperature rise of necessary semiconductor switching elements in accordance with the temperature conditions, thereby increasing the reliability of the inverter.
　図２５～図４２Ｂを参照して、本発明の実施形態に係る波形例についてさらに説明する。図２５は、波形例とスイッチング損失との関係を示す表である。図２５において、ＵＨは、Ｕ相の第１半導体スイッチング素子Ｕｐのスイッチング損失を示す。ＵＬは、Ｕ相の第２半導体スイッチング素子Ｕｎのスイッチング損失を示す。ＶＨは、Ｖ相の第１半導体スイッチング素子Ｖｐのスイッチング損失を示す。ＶＬは、Ｖ相の第２半導体スイッチング素子Ｖｎのスイッチング損失を示す。ＷＨは、Ｗ相の第１半導体スイッチング素子Ｗｐのスイッチング損失を示す。ＷＬは、Ｗ相の第２半導体スイッチング素子Ｗｎのスイッチング損失を示す。 Waveform examples according to embodiments of the present invention will be further described with reference to FIGS. 25 to 42B. FIG. 25 is a table showing the relationship between waveform examples and switching loss. In FIG. 25, UH represents the switching loss of the U-phase first semiconductor switching element Up. UL represents the switching loss of the U-phase second semiconductor switching element Un. VH represents the switching loss of the V-phase first semiconductor switching element Vp. VL represents the switching loss of the V-phase second semiconductor switching element Vn. WH represents the switching loss of the W-phase first semiconductor switching element Wp. WL represents the switching loss of the W-phase second semiconductor switching element Wn.
　図２５に示すように、波形例１３～波形例２９では、ＵＨが０．３２であり、ＶＬが０．３２である、すなわち、波形例１３～波形例２９では、Ｕ相の第１半導体スイッチング素子ＵｐおよびＶ相の第２半導体スイッチング素子Ｖｎのスイッチング損失が少ない波形例である。つまり、波形例１３～波形例２９は、Ｕ相の第１半導体スイッチング素子ＵｐおよびＶ相の第２半導体スイッチング素子Ｖｎを保護できる波形例である。本明細書において、ある相（例えばＵ相）の第１半導体スイッチング素子（例えばＵｐ）および他の相（例えばＶ相）の第２半導体スイッチング素子（例えばＶｎ）を保護できる波形を、ＵＨ＿ＶＬ保護波形と記載することがある。これの波形例は、前者の第１オン固定期間と後者の第２オン固定期間とが連続する場合に相当する。 As shown in FIG. 25, in waveform examples 13 to 29, UH is 0.32 and VL is 0.32. This is an example of a waveform in which the switching loss of the element Up and the V-phase second semiconductor switching element Vn is small. That is, the waveform examples 13 to 29 are waveform examples capable of protecting the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn. In this specification, a waveform capable of protecting a first semiconductor switching element (eg Up) of a certain phase (eg U phase) and a second semiconductor switching element (eg Vn) of another phase (eg V phase) is referred to as a UH_VL protection waveform. is sometimes described. This waveform example corresponds to the case where the former first fixed ON period and the latter second fixed ON period are continuous.
　図２６Ａおよび図２６Ｂを参照して、波形例１３について説明する。図２６Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図２６Ｂは、スイッチング損失を示す図である。 Waveform example 13 will be described with reference to FIGS. 26A and 26B. FIG. 26A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 26B is a diagram showing switching losses.
　図２６Ａに示すように、波形例１３は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例１３は、電気角６０度～電気角１５０度において、いずれか１相の出力が１に固定される波形である。また、波形例１３は、電気角０度～電気角６０度および電気角１５０度～電気角３６０度において、いずれか１相の出力が０に固定される波形である。波形例１３では、電気角６０度～電気角１５０度において、ハイサイドオン適用期間Ｔ３である。また、波形例１３では、電気角０度～電気角６０度および電気角１５０度～電気角３６０度において、ロウサイドオン適用期間Ｔ４である。 As shown in FIG. 26A, in waveform example 13, the output voltage of any one phase is fixed to 1 in a certain electrical angle section, and the output voltage of any one phase is fixed to 1 in another electrical angle section. is fixed to 0. Specifically, waveform example 13 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 150 degrees. Waveform example 13 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 degrees and at an electrical angle of 150 to 360 degrees. In waveform example 13, the high-side-on application period T3 is at an electrical angle of 60 degrees to 150 degrees. Further, in waveform example 13, the low side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees and at an electrical angle of 150 to 360 electrical degrees.
　波形例１３では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｕを含む。波形例１３では、電気角６０度～電気角１５０度が第１オン固定期間Ｔ１ｕである。 In waveform example 13, the first fixed ON period T1 includes the first fixed ON period T1u. In waveform example 13, the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees.
　波形例１３では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖと、第２オン固定期間Ｔ２ｗとを含む。波形例１３では、電気角２１０度～電気角３３０度が第２オン固定期間Ｔ２ｕである。波形例１３では、電気角０度～電気角６０度および電気角３３０度～電気角３６０度が第２オン固定期間Ｔ２ｖである。波形例１３では、電気角１５０度～電気角２１０度が第２オン固定期間Ｔ２ｗである。 In Waveform Example 13, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 13, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In waveform example 13, the second fixed ON period T2v is from an electrical angle of 0 degrees to an electrical angle of 60 degrees and from an electrical angle of 330 degrees to an electrical angle of 360 degrees. In waveform example 13, the second fixed ON period T2w is from 150 electrical degrees to 210 electrical degrees.
　波形例１３では、３相のうちＵ相において、第１オン固定期間Ｔ１ｕが、第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗと異なる。詳しくは、波形例１３では、第１オン固定期間Ｔ１ｕが１２０度であるのに対し、第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗは無い。すなわち、波形例１３では、第１オン固定期間Ｔ１ｕが第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗよりも長い。したがって、図２６Ｂに示すように、Ｕ相の第１半導体スイッチング素子Ｕｐ（Ｈ（ハイサイド））のスイッチング損失がＶ相およびＷ相に比べて小さくなっている。 In waveform example 13, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 13, the first fixed ON period T1u is 120 degrees, but there is no first fixed ON period T1v and no first fixed ON period T1w. That is, in waveform example 13, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 26B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
　波形例１３では、第２オン固定期間Ｔ２ｖが、第２オン固定期間Ｔ２ｕおよび第２オン固定期間Ｔ２ｗと異なる。詳しくは、波形例１３では、第２オン固定期間Ｔ２ｖが９０度であるのに対し、第２オン固定期間Ｔ２ｕは１２０度であり、第２オン固定期間Ｔ２ｗは６０度である。すなわち、波形例１３では、第２オン固定期間Ｔ２ｖが第２オン固定期間Ｔ２ｗよりも長い。したがって、図２６Ｂに示すように、Ｖ相の第２半導体スイッチング素子Ｖｎ（Ｌ（ロウサイド））のスイッチング損失がＷ相に比べて小さくなっている。 In waveform example 13, the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in waveform example 13, the second fixed ON period T2v is 90 degrees, the second fixed ON period T2u is 120 degrees, and the second fixed ON period T2w is 60 degrees. That is, in waveform example 13, the second fixed ON period T2v is longer than the second fixed ON period T2w. Therefore, as shown in FIG. 26B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than that of the W-phase.
　以上、図２６Ａおよび図２６Ｂを参照して説明したように、波形例１３においても、波形例１と同様に、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。波形例１３では、Ｕ相の第１半導体スイッチング素子Ｕｐと、Ｖ相の第２半導体スイッチング素子Ｖｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 26A and 26B , in waveform example 13, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 13, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn.
　また、波形例１３では、図２６Ｂに示すように、Ｕ相の第２半導体スイッチング素子Ｕｎと、Ｗ相の第２半導体スイッチング素子Ｗｎとの発熱についても同時に抑えることができる。 Further, in waveform example 13, as shown in FIG. 26B, the heat generation of the U-phase second semiconductor switching element Un and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
　図２７Ａおよび図２７Ｂを参照して、波形例１４について説明する。図２７Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図２７Ｂは、スイッチング損失を示す図である。 Waveform example 14 will be described with reference to FIGS. 27A and 27B. FIG. 27A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 27B is a diagram showing switching losses.
　図２７Ａに示すように、波形例１４は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例１４は、電気角６０度～電気角１８０度において、いずれか１相の出力が１に固定される波形である。また、波形例１４は、電気角０度～電気角６０度および電気角１８０度～電気角３６０度において、いずれか１相の出力が０に固定される波形である。波形例１４では、電気角６０度～電気角１８０度において、ハイサイドオン適用期間Ｔ３である。また、波形例１４では、電気角０度～電気角６０度および電気角１８０度～電気角３６０度において、ロウサイドオン適用期間Ｔ４である。 As shown in FIG. 27A, in waveform example 14, according to the electrical angle, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, waveform example 14 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 180 degrees. Waveform example 14 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 degrees to 60 degrees and at an electrical angle of 180 degrees to 360 degrees. In waveform example 14, the high-side-on application period T3 is at an electrical angle of 60 degrees to 180 degrees. Further, in Waveform Example 14, the low side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees and at an electrical angle of 180 to 360 electrical degrees.
　波形例１４では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｕと、第１オン固定期間Ｔ１ｖとを含む。波形例１４では、電気角６０度～電気角１５０度が第１オン固定期間Ｔ１ｕである。波形例１４では、電気角１５０度～電気角１８０度が第１オン固定期間Ｔ１ｖである。 In Waveform Example 14, the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v. In waveform example 14, the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees. In waveform example 14, the first fixed ON period T1v is between 150 electrical degrees and 180 electrical degrees.
　波形例１４では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖと、第２オン固定期間Ｔ２ｗとを含む。波形例１４では、電気角２１０度～電気角３３０度が第２オン固定期間Ｔ２ｕである。波形例１４では、電気角０度～電気角６０度および電気角３３０度～電気角３６０度が第２オン固定期間Ｔ２ｖである。波形例１４では、電気角１８０度～電気角２１０度が第２オン固定期間Ｔ２ｗである。 In Waveform Example 14, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 14, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In waveform example 14, the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees. In Waveform Example 14, the second fixed ON period T2w is from 180 electrical degrees to 210 electrical degrees.
　波形例１４では、３相のうちＵ相において、第１オン固定期間Ｔ１ｕが、第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗと異なる。詳しくは、波形例１４では、第１オン固定期間Ｔ１ｕが９０度であるのに対し、第１オン固定期間Ｔ１ｖが３０度であり、第１オン固定期間Ｔ１ｗは無い。すなわち、波形例１４では、第１オン固定期間Ｔ１ｕが第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗよりも長い。したがって、図２７Ｂに示すように、Ｕ相の第１半導体スイッチング素子Ｕｐ（Ｈ（ハイサイド））のスイッチング損失がＶ相およびＷ相に比べて小さくなっている。 In waveform example 14, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 14, the first fixed ON period T1u is 90 degrees, the first fixed ON period T1v is 30 degrees, and there is no first fixed ON period T1w. That is, in Waveform Example 14, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 27B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
　波形例１４では、第２オン固定期間Ｔ２ｖが、第２オン固定期間Ｔ２ｕおよび第２オン固定期間Ｔ２ｗと異なる。詳しくは、波形例１４では、第２オン固定期間Ｔ２ｖが９０度であるのに対し、第２オン固定期間Ｔ２ｕは１２０度であり、第２オン固定期間Ｔ２ｗは３０度である。すなわち、波形例１４では、第２オン固定期間Ｔ２ｖが第２オン固定期間Ｔ２ｗよりも長い。したがって、図２７Ｂに示すように、Ｖ相の第２半導体スイッチング素子Ｕｎ（Ｌ（ロウサイド））のスイッチング損失がＷ相に比べて小さくなっている。 In waveform example 14, the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in Waveform Example 14, the second fixed ON period T2v is 90 degrees, the second fixed ON period T2u is 120 degrees, and the second fixed ON period T2w is 30 degrees. That is, in waveform example 14, the second fixed ON period T2v is longer than the second fixed ON period T2w. Therefore, as shown in FIG. 27B, the switching loss of the V-phase second semiconductor switching element Un (L (low side)) is smaller than that of the W-phase.
　以上、図２７Ａおよび図２７Ｂを参照して説明したように、波形例１４においても、波形例１と同様に、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。波形例１４では、Ｕ相の第１半導体スイッチング素子Ｕｐと、Ｖ相の第２半導体スイッチング素子Ｖｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 27A and 27B, in waveform example 14, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 14, the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
　また、波形例１４では、図２７Ｂに示すように、Ｕ相の第２半導体スイッチング素子Ｕｎと、Ｖ相の第１半導体スイッチング素子Ｖｐと、Ｗ相の第２半導体スイッチング素子Ｗｎとの発熱についても同時に抑えることができる。 In waveform example 14, as shown in FIG. 27B, the heat generated by the U-phase second semiconductor switching element Un, the V-phase first semiconductor switching element Vp, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
　図２８Ａおよび図２８Ｂを参照して、波形例１５について説明する。図２８Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図２８Ｂは、スイッチング損失を示す図である。 Waveform example 15 will be described with reference to FIGS. 28A and 28B. FIG. 28A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 28B is a diagram showing switching losses.
　図２８Ａに示すように、波形例１５は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例１５は、電気角６０度～電気角２１０度において、いずれか１相の出力が１に固定される波形である。また、波形例１５は、電気角０度～電気角６０度および電気角２１０度～電気角３６０度において、いずれか１相の出力が０に固定される波形である。波形例１５では、電気角６０度～電気角２１０度において、ハイサイドオン適用期間Ｔ３である。また、波形例１５では、電気角０度～電気角６０度および電気角２１０度～電気角３６０度において、ロウサイドオン適用期間Ｔ４である。 As shown in FIG. 28A , in waveform example 15, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, waveform example 15 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 210 degrees. Waveform example 15 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 degrees and at an electrical angle of 210 to 360 degrees. In waveform example 15, the high-side-on application period T3 is at an electrical angle of 60 degrees to 210 electrical degrees. In waveform example 15, the low side-on application period is T4 at an electrical angle of 0 to 60 electrical degrees and at an electrical angle of 210 to 360 electrical degrees.
　波形例１５では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｕと、第１オン固定期間Ｔ１ｖとを含む。波形例１５では、電気角６０度～電気角１５０度が第１オン固定期間Ｔ１ｕである。波形例１５では、電気角１５０度～電気角２１０度が第１オン固定期間Ｔ１ｖである。 In Waveform Example 15, the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v. In waveform example 15, the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees. In waveform example 15, the first fixed ON period T1v is between 150 electrical degrees and 210 electrical degrees.
　波形例１５では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖとを含む。波形例１５では、電気角２１０度～電気角３３０度が第２オン固定期間Ｔ２ｕである。波形例１５では、電気角０度～電気角６０度および電気角３３０度～電気角３６０度が第２オン固定期間Ｔ２ｖである。 In Waveform Example 15, the second fixed ON period T2 includes a second fixed ON period T2u and a second fixed ON period T2v. In waveform example 15, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In waveform example 15, the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees.
　波形例１５では、３相のうちＵ相において、第１オン固定期間Ｔ１ｕが、第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗと異なる。詳しくは、波形例１５では、第１オン固定期間Ｔ１ｕが９０度であるのに対し、第１オン固定期間Ｔ１ｖは６０度であり、第１オン固定期間Ｔ１ｗは無い。すなわち、波形例１５では、第１オン固定期間Ｔ１ｕが第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗよりも長い。したがって、図２８Ｂに示すように、Ｕ相の第１半導体スイッチング素子Ｕｐ（Ｈ（ハイサイド））のスイッチング損失がＶ相およびＷ相に比べて小さくなっている。 In waveform example 15, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 15, the first fixed ON period T1u is 90 degrees, the first fixed ON period T1v is 60 degrees, and there is no first fixed ON period T1w. That is, in waveform example 15, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 28B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
　波形例１５では、第２オン固定期間Ｔ２ｖが、第２オン固定期間Ｔ２ｕおよび第２オン固定期間Ｔ２ｗと異なる。詳しくは、波形例１５では、第２オン固定期間Ｔ２ｖが９０度であるのに対し、第２オン固定期間Ｔ２ｕは１２０度であり、第２オン固定期間Ｔ２ｗは無い。すなわち、波形例１５では、第２オン固定期間Ｔ２ｖが第２オン固定期間Ｔ２ｗよりも長い。したがって、図２８Ｂに示すように、Ｖ相の第２半導体スイッチング素子Ｖｎ（Ｌ（ロウサイド））のスイッチング損失がＷ相に比べて小さくなっている。 In waveform example 15, the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in waveform example 15, the second fixed ON period T2v is 90 degrees, the second fixed ON period T2u is 120 degrees, and there is no second fixed ON period T2w. That is, in waveform example 15, the second fixed ON period T2v is longer than the second fixed ON period T2w. Therefore, as shown in FIG. 28B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than that of the W-phase.
　以上、図２８Ａおよび図２８Ｂを参照して説明したように、波形例１５においても、波形例１と同様に、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。波形例１５では、Ｕ相の第１半導体スイッチング素子Ｕｐと、Ｖ相の第２半導体スイッチング素子Ｖｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 28A and 28B , in waveform example 15, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 15, the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
　また、波形例１５では、図２８Ｂに示すように、Ｕ相の第２半導体スイッチング素子Ｕｎと、Ｖ相の第１半導体スイッチング素子Ｖｐとの発熱についても同時に抑えることができる。 Further, in waveform example 15, as shown in FIG. 28B, the heat generation of the U-phase second semiconductor switching element Un and the V-phase first semiconductor switching element Vp can be suppressed at the same time.
　図２９Ａおよび図２９Ｂを参照して、波形例１６について説明する。図２９Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図２９Ｂは、スイッチング損失を示す図である。 Waveform example 16 will be described with reference to FIGS. 29A and 29B. FIG. 29A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 29B is a diagram showing switching losses.
　図２９Ａに示すように、波形例１６は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例１６は、電気角６０度～電気角２４０度において、いずれか１相の出力が１に固定される波形である。また、波形例１６は、電気角０度～電気角６０度および電気角２４０度～電気角３６０度において、いずれか１相の出力が０に固定される波形である。波形例１６では、電気角６０度～電気角２４０度において、ハイサイドオン適用期間Ｔ３である。また、波形例１６では、電気角０度～電気角６０度および電気角２４０度～電気角３６０度において、ロウサイドオン適用期間Ｔ４である。 As shown in FIG. 29A, in waveform example 16, according to the electrical angle, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, waveform example 16 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 240 degrees. Waveform example 16 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 degree to 60 electrical degrees and at an electrical angle of 240 degrees to 360 electrical degrees. In waveform example 16, the high-side-on application period T3 is at an electrical angle of 60 degrees to 240 electrical degrees. Further, in waveform example 16, the low side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees and at an electrical angle of 240 to 360 electrical degrees.
　波形例１６では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｕと、第１オン固定期間Ｔ１ｖとを含む。波形例１６では、電気角６０度～電気角１５０度が第１オン固定期間Ｔ１ｕである。波形例１６では、電気角１５０度～電気角２４０度が第１オン固定期間Ｔ１ｖである。 In Waveform Example 16, the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v. In waveform example 16, the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees. In waveform example 16, the first fixed ON period T1v is from 150 electrical degrees to 240 electrical degrees.
　波形例１６では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖとを含む。波形例１６では、電気角２４０度～電気角３３０度が第２オン固定期間Ｔ２ｕである。波形例１６では、電気角０度～電気角６０度および電気角３３０度～電気角３６０度が第２オン固定期間Ｔ２ｖである。 In Waveform Example 16, the second fixed ON period T2 includes a second fixed ON period T2u and a second fixed ON period T2v. In waveform example 16, the second fixed ON period T2u is from 240 electrical degrees to 330 electrical degrees. In waveform example 16, the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees.
　波形例１６では、３相のうちＵ相において、第１オン固定期間Ｔ１ｕが、第１オン固定期間Ｔ１ｗと異なる。詳しくは、波形例１６では、第１オン固定期間Ｔ１ｕが９０度であるのに対し、第１オン固定期間Ｔ１ｗは無い。すなわち、波形例１６では、第１オン固定期間Ｔ１ｕが第１オン固定期間Ｔ１ｗよりも長い。なお、波形例１６では、第１オン固定期間Ｔ１ｕと、第１オン固定期間Ｔ１ｖとは等しい。したがって、図２９Ｂに示すように、Ｕ相の第１半導体スイッチング素子Ｕｐ（Ｈ（ハイサイド））のスイッチング損失がＷ相に比べて小さくなっている。 In waveform example 16, the first fixed ON period T1u differs from the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 16, the first fixed ON period T1u is 90 degrees, but there is no first fixed ON period T1w. That is, in waveform example 16, the first fixed ON period T1u is longer than the first fixed ON period T1w. In waveform example 16, the first fixed ON period T1u and the first fixed ON period T1v are equal. Therefore, as shown in FIG. 29B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than that of the W-phase.
　波形例１６では、第２オン固定期間Ｔ２ｖが、第２オン固定期間Ｔ２ｕおよび第２オン固定期間Ｔ２ｗと異なる。詳しくは、波形例１６では、第２オン固定期間Ｔ２ｖが９０度であるのに対し、第２オン固定期間Ｔ２ｗは無い。すなわち、波形例１６では、第２オン固定期間Ｔ２ｖが第２オン固定期間Ｔ２ｗよりも長い。なお、波形例１６では、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖとは等しい。したがって、図２９Ｂに示すように、Ｖ相の第２半導体スイッチング素子Ｖｎ（Ｌ（ロウサイド））のスイッチング損失がＷ相に比べて小さくなっている。 In waveform example 16, the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in waveform example 16, the second fixed ON period T2v is 90 degrees, but there is no second fixed ON period T2w. That is, in waveform example 16, the second fixed ON period T2v is longer than the second fixed ON period T2w. In waveform example 16, the second fixed ON period T2u is equal to the second fixed ON period T2v. Therefore, as shown in FIG. 29B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than that of the W-phase.
　以上、図２９Ａおよび図２９Ｂを参照して説明したように、波形例１６においても、波形例１と同様に、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。波形例１６では、Ｕ相の第１半導体スイッチング素子Ｕｐと、Ｖ相の第２半導体スイッチング素子Ｖｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 29A and 29B , in waveform example 16, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 16, the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
　また、波形例１６では、図２９Ｂに示すように、Ｕ相の第２半導体スイッチング素子Ｕｎと、Ｖ相の第１半導体スイッチング素子Ｖｐとの発熱についても同時に抑えることができる。 Further, in waveform example 16, as shown in FIG. 29B, the heat generation of the U-phase second semiconductor switching element Un and the V-phase first semiconductor switching element Vp can be suppressed at the same time.
　図３０Ａおよび図３０Ｂを参照して、波形例１７について説明する。図３０Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図３０Ｂは、スイッチング損失を示す図である。 Waveform example 17 will be described with reference to FIGS. 30A and 30B. FIG. 30A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 30B is a diagram showing switching losses.
　図３０Ａに示すように、波形例１７は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例１７は、電気角６０度～電気角２７０度において、いずれか１相の出力が１に固定される波形である。また、波形例１７は、電気角０度～電気角６０度および電気角２７０度～電気角３６０度において、いずれか１相の出力が０に固定される波形である。波形例１７では、電気角６０度～電気角２７０度において、ハイサイドオン適用期間Ｔ３である。また、波形例１７では、電気角０度～電気角６０度および電気角２７０度～電気角３６０度において、ロウサイドオン適用期間Ｔ４である。 As shown in FIG. 30A, in waveform example 17, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, waveform example 17 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 270 degrees. Waveform example 17 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 degree to 60 electrical degrees and at an electrical angle of 270 degrees to 360 electrical degrees. In waveform example 17, the high-side-on application period T3 is at an electrical angle of 60 degrees to 270 electrical degrees. Further, in waveform example 17, the low-side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees and at an electrical angle of 270 to 360 electrical degrees.
　波形例１７では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｕと、第１オン固定期間Ｔ１ｖとを含む。波形例１７では、電気角６０度～電気角１５０度が第１オン固定期間Ｔ１ｕである。波形例１７では、電気角１５０度～電気角２７０度が第１オン固定期間Ｔ１ｖである。 In Waveform Example 17, the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v. In waveform example 17, the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees. In waveform example 17, the first fixed ON period T1v is from 150 electrical degrees to 270 electrical degrees.
　波形例１７では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖとを含む。波形例１７では、電気角２７０度～電気角３３０度が第２オン固定期間Ｔ２ｕである。波形例１７では、電気角０度～電気角６０度および電気角３３０度～電気角３６０度が第２オン固定期間Ｔ２ｖである。 In waveform example 17, the second fixed ON period T2 includes a second fixed ON period T2u and a second fixed ON period T2v. In waveform example 17, the second fixed ON period T2u is from 270 electrical degrees to 330 electrical degrees. In waveform example 17, the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees.
　波形例１７では、３相のうちＵ相において、第１オン固定期間Ｔ１ｕが、第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗと異なる。詳しくは、波形例１７では、第１オン固定期間Ｔ１ｕが９０度であるのに対し、第１オン固定期間Ｔ１ｖは１２０度であり、第１オン固定期間Ｔ１ｗは無い。すなわち、波形例１７では、第１オン固定期間Ｔ１ｕが第１オン固定期間Ｔ１ｗよりも長い。したがって、図３０Ｂに示すように、Ｕ相の第１半導体スイッチング素子Ｕｐ（Ｈ（ハイサイド））のスイッチング損失がＷ相に比べて小さくなっている。 In waveform example 17, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 17, the first fixed ON period T1u is 90 degrees, the first fixed ON period T1v is 120 degrees, and there is no first fixed ON period T1w. That is, in waveform example 17, the first fixed ON period T1u is longer than the first fixed ON period T1w. Therefore, as shown in FIG. 30B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than that of the W-phase.
　波形例１７では、第２オン固定期間Ｔ２ｖが、第２オン固定期間Ｔ２ｕおよび第２オン固定期間Ｔ２ｗと異なる。詳しくは、波形例１７では、第２オン固定期間Ｔ２ｖが９０度であるのに対し、第２オン固定期間Ｔ２ｕは６０度であり、第２オン固定期間Ｔ２ｗは無い。すなわち、波形例１７では、第２オン固定期間Ｔ２ｖが第２オン固定期間Ｔ２ｕおよび第２オン固定期間Ｔ２ｗよりも長い。したがって、図３０Ｂに示すように、Ｖ相の第２半導体スイッチング素子Ｖｎ（Ｌ（ロウサイド））のスイッチング損失がＵ相およびＷ相に比べて小さくなっている。 In waveform example 17, the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in Waveform Example 17, the second fixed ON period T2v is 90 degrees, the second fixed ON period T2u is 60 degrees, and there is no second fixed ON period T2w. That is, in Waveform Example 17, the second fixed ON period T2v is longer than the second fixed ON period T2u and the second fixed ON period T2w. Therefore, as shown in FIG. 30B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
　以上、図３０Ａおよび図３０Ｂを参照して説明したように、波形例１７においても、波形例１と同様に、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。波形例１７では、Ｕ相の第１半導体スイッチング素子Ｕｐと、Ｖ相の第２半導体スイッチング素子Ｖｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 30A and 30B , in waveform example 17, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 17, the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
　また、波形例１７では、図３０Ｂに示すように、Ｕ相の第２半導体スイッチング素子Ｕｎと、Ｖ相の第１半導体スイッチング素子Ｖｐとの発熱についても同時に抑えることができる。 Further, in waveform example 17, as shown in FIG. 30B, the heat generation of the U-phase second semiconductor switching element Un and the V-phase first semiconductor switching element Vp can be suppressed at the same time.
　図３１Ａおよび図３１Ｂを参照して、波形例１８について説明する。図３１Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図３１Ｂは、スイッチング損失を示す図である。 Waveform example 18 will be described with reference to FIGS. 31A and 31B. FIG. 31A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 31B is a diagram showing switching losses.
　図３１Ａに示すように、波形例１８は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例１８は、電気角６０度～電気角３００度において、いずれか１相の出力が１に固定される波形である。また、波形例１８は、電気角０度～電気角６０度および電気角３００度～電気角３６０度において、いずれか１相の出力が０に固定される波形である。波形例１８では、電気角６０度～電気角３００度において、ハイサイドオン適用期間Ｔ３である。また、波形例１８では、電気角０度～電気角６０度および電気角３００度～電気角３６０度において、ロウサイドオン適用期間Ｔ４である。 As shown in FIG. 31A, in waveform example 18, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, waveform example 18 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 300 degrees. Waveform example 18 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 electrical degrees and at an electrical angle of 300 to 360 electrical degrees. In waveform example 18, the high-side-on application period T3 is at an electrical angle of 60 degrees to 300 electrical degrees. Further, in waveform example 18, the low side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees and at an electrical angle of 300 to 360 electrical degrees.
　波形例１８では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｕを含む。波形例１８では、電気角６０度～電気角１５０度が第１オン固定期間Ｔ１ｕである。波形例１８では、電気角１５０度～電気角２７０度が第１オン固定期間Ｔ１ｖである。波形例１８では、電気角２７０度～電気角３００度が第１オン固定期間Ｔ１ｗである。 In waveform example 18, the first fixed ON period T1 includes the first fixed ON period T1u. In waveform example 18, the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees. In waveform example 18, the first fixed ON period T1v is from 150 electrical degrees to 270 electrical degrees. In waveform example 18, the first fixed ON period T1w is from 270 electrical degrees to 300 electrical degrees.
　波形例１８では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖとを含む。波形例１８では、電気角３００度～電気角３３０度が第２オン固定期間Ｔ２ｕである。波形例１８では、電気角０度～電気角６０度および電気角３３０度～電気角３６０度が第２オン固定期間Ｔ２ｖである。 In Waveform Example 18, the second fixed ON period T2 includes a second fixed ON period T2u and a second fixed ON period T2v. In waveform example 18, the second fixed ON period T2u is between 300 electrical degrees and 330 electrical degrees. In waveform example 18, the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees.
　波形例１８では、３相のうちＵ相において、第１オン固定期間Ｔ１ｕが、第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗと異なる。詳しくは、波形例１８では、第１オン固定期間Ｔ１ｕが９０度であるのに対し、第１オン固定期間Ｔ１ｖは、１２０度であり、第１オン固定期間Ｔ１ｗは３０度である。すなわち、波形例１８では、第１オン固定期間Ｔ１ｕが第１オン固定期間Ｔ１ｗよりも長い。したがって、図３１Ｂに示すように、Ｕ相の第１半導体スイッチング素子Ｕｐ（Ｈ（ハイサイド））のスイッチング損失がＷ相に比べて小さくなっている。 In waveform example 18, in the U phase among the three phases, the first fixed ON period T1u is different from the first fixed ON period T1v and the first fixed ON period T1w. Specifically, in waveform example 18, the first fixed ON period T1u is 90 degrees, the first fixed ON period T1v is 120 degrees, and the first fixed ON period T1w is 30 degrees. That is, in waveform example 18, the first fixed ON period T1u is longer than the first fixed ON period T1w. Therefore, as shown in FIG. 31B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than that of the W-phase.
　波形例１８では、第２オン固定期間Ｔ２ｖが、第２オン固定期間Ｔ２ｕおよび第２オン固定期間Ｔ２ｗと異なる。詳しくは、波形例１８では、第２オン固定期間Ｔ２ｖが９０度であるのに対し、第２オン固定期間Ｔ２ｕは３０度であり、第２オン固定期間Ｔ２ｗは無い。すなわち、波形例１８では、第２オン固定期間Ｔ２ｖが第２オン固定期間Ｔ２ｕおよび第２オン固定期間Ｔ２ｗよりも長い。したがって、図３１Ｂに示すように、Ｖ相の第２半導体スイッチング素子Ｖｎ（Ｌ（ロウサイド））のスイッチング損失がＵ相およびＷ相に比べて小さくなっている。 In waveform example 18, the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in Waveform Example 18, the second fixed ON period T2v is 90 degrees, the second fixed ON period T2u is 30 degrees, and there is no second fixed ON period T2w. That is, in Waveform Example 18, the second fixed ON period T2v is longer than the second fixed ON period T2u and the second fixed ON period T2w. Therefore, as shown in FIG. 31B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
　以上、図３１Ａおよび図３１Ｂを参照して説明したように、波形例１８においても、波形例１と同様に、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。波形例１８では、Ｕ相の第１半導体スイッチング素子Ｕｐと、Ｖ相の第２半導体スイッチング素子Ｖｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 31A and 31B, in waveform example 18, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 18, the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
　また、波形例１８では、図３１Ｂに示すように、Ｕ相の第２半導体スイッチング素子Ｕｎと、Ｖ相の第１半導体スイッチング素子Ｖｐと、Ｗ相の第１半導体スイッチング素子Ｗｐとの発熱についても同時に抑えることができる。 In waveform example 18, as shown in FIG. 31B, the heat generated by the U-phase second semiconductor switching element Un, the V-phase first semiconductor switching element Vp, and the W-phase first semiconductor switching element Wp can be suppressed at the same time.
　図３２Ａおよび図３２Ｂを参照して、波形例１９について説明する。図３２Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図３２Ｂは、スイッチング損失を示す図である。 Waveform example 19 will be described with reference to FIGS. 32A and 32B. FIG. 32A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 32B is a diagram showing switching losses.
　図３２Ａに示すように、波形例１９は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例１９は、電気角６０度～電気角３３０度において、いずれか１相の出力が１に固定される波形である。また、波形例１９は、電気角０度～電気角６０度および電気角３３０度～電気角３６０度において、いずれか１相の出力が０に固定される波形である。波形例１９では、電気角６０度～電気角３３０度において、ハイサイドオン適用期間Ｔ３である。また、波形例１９では、電気角０度～電気角６０度および電気角３３０度～電気角３６０度において、ロウサイドオン適用期間Ｔ４である。 As shown in FIG. 32A , in waveform example 19, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, waveform example 19 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 330 degrees. Waveform example 19 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 electrical degrees and at an electrical angle of 330 to 360 electrical degrees. In waveform example 19, the high-side-on application period T3 is at an electrical angle of 60 degrees to 330 electrical degrees. Further, in waveform example 19, the low side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees and at an electrical angle of 330 to 360 electrical degrees.
　波形例１９では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｕと、第１オン固定期間Ｔ１ｖと、第１オン固定期間Ｔ１ｗとを含む。波形例１９では、電気角６０度～電気角１５０度が第１オン固定期間Ｔ１ｕである。波形例１９では、電気角１５０度～電気角２７０度が第１オン固定期間Ｔ１ｖである。波形例１９では、電気角２７０度～電気角３３０度が第１オン固定期間Ｔ１ｗである。 In Waveform Example 19, the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w. In waveform example 19, the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees. In waveform example 19, the first fixed ON period T1v is from 150 electrical degrees to 270 electrical degrees. In Waveform Example 19, the first fixed ON period T1w is from 270 electrical degrees to 330 electrical degrees.
　波形例１９では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｖを含む。波形例１９では、波形例１９では、電気角０度～電気角６０度および電気角３３０度～電気角３６０度が第２オン固定期間Ｔ２ｖである。 In waveform example 19, the second fixed ON period T2 includes the second fixed ON period T2v. In waveform example 19, the second fixed ON period T2v is from 0 electrical angle to 60 electrical degrees and from 330 electrical degrees to 360 electrical degrees.
　波形例１９では、３相のうちＵ相において、第１オン固定期間Ｔ１ｕが、第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗと異なる。詳しくは、波形例１９では、第１オン固定期間Ｔ１ｕが９０度であるのに対し、第１オン固定期間Ｔ１ｖは１２０度であり、第１オン固定期間Ｔ１ｗは６０度である。すなわち、波形例１９では、第１オン固定期間Ｔ１ｕが第１オン固定期間Ｔ１ｗよりも長い。したがって、図３２Ｂに示すように、Ｕ相の第１半導体スイッチング素子Ｕｐ（Ｈ（ハイサイド））のスイッチング損失がＷ相に比べて小さくなっている。 In waveform example 19, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 19, the first fixed ON period T1u is 90 degrees, the first fixed ON period T1v is 120 degrees, and the first fixed ON period T1w is 60 degrees. That is, in waveform example 19, the first fixed ON period T1u is longer than the first fixed ON period T1w. Therefore, as shown in FIG. 32B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than that of the W-phase.
　波形例１９では、第２オン固定期間Ｔ２ｖが、第２オン固定期間Ｔ２ｕおよび第２オン固定期間Ｔ２ｗと異なる。詳しくは、波形例１９では、第２オン固定期間Ｔ２ｖが９０度であるのに対し、第２オン固定期間Ｔ２ｕおよび第２オン固定期間Ｔ２ｗは無い。すなわち、波形例１９では、第２オン固定期間Ｔ２ｖが第２オン固定期間Ｔ２ｕおよび第２オン固定期間Ｔ２ｗよりも長い。したがって、図３２Ｂに示すように、Ｖ相の第２半導体スイッチング素子Ｖｎ（Ｌ（ロウサイド））のスイッチング損失がＵ相およびＷ相に比べて小さくなっている。 In waveform example 19, the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in Waveform Example 19, the second fixed ON period T2v is 90 degrees, whereas the second fixed ON period T2u and the second fixed ON period T2w are absent. That is, in Waveform Example 19, the second fixed ON period T2v is longer than the second fixed ON period T2u and the second fixed ON period T2w. Therefore, as shown in FIG. 32B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
　以上、図３２Ａおよび図３２Ｂを参照して説明したように、波形例１９においても、波形例１と同様に、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。波形例１９では、Ｕ相の第１半導体スイッチング素子Ｕｐと、Ｖ相の第２半導体スイッチング素子Ｖｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 32A and 32B , in waveform example 19, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 19, the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
　また、波形例１９では、図３２Ｂに示すように、Ｖ相の第１半導体スイッチング素子Ｖｐと、Ｗ相の第１半導体スイッチング素子Ｗｐとの発熱についても同時に抑えることができる。 Further, in waveform example 19, as shown in FIG. 32B, the heat generation of the V-phase first semiconductor switching element Vp and the W-phase first semiconductor switching element Wp can be suppressed at the same time.
　図３３Ａおよび図３３Ｂを参照して、波形例２０について説明する。図３３Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図３３Ｂは、スイッチング損失を示す図である。 A waveform example 20 will be described with reference to FIGS. 33A and 33B. FIG. 33A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 33B is a diagram showing switching losses.
　図３３Ａに示すように、波形例２０は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例２０は、電気角６０度～電気角１５０度および電気角３００度～電気角３３０度において、いずれか１相の出力が１に固定される波形である。また、波形例２０は、電気角０度～電気角６０度、電気角１５０度～電気角３００度および電気角３３０度～電気角３６０度において、いずれか１相の出力が０に固定される波形である。波形例２０では、電気角６０度～電気角１５０度および電気角３００度～電気角３３０度において、ハイサイドオン適用期間Ｔ３である。また、波形例２０では、電気角０度～電気角６０度、電気角１５０度～電気角３００度および電気角３３０度～電気角３６０度において、ロウサイドオン適用期間Ｔ４である。 As shown in FIG. 33A, in waveform example 20, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, waveform example 20 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 300 degrees to 330 degrees. In waveform example 20, the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 electrical degrees, 150 to 300 electrical degrees, and 330 to 360 electrical degrees. waveform. In waveform example 20, the high side-on application period T3 occurs at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 300 degrees to 330 degrees. Further, in waveform example 20, the low side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees, 150 to 300 electrical degrees, and 330 to 360 electrical degrees.
　波形例２０では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｕと、第１オン固定期間Ｔ１ｗとを含む。波形例２０では、電気角６０度～電気角１５０度が第１オン固定期間Ｔ１ｕである。波形例２０では、電気角３００度～電気角３３０度が第１オン固定期間Ｔ１ｗである。 In waveform example 20, the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1w. In waveform example 20, the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees. In waveform example 20, the first fixed ON period T1w is between 300 electrical degrees and 330 electrical degrees.
　波形例２０では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖと、第２オン固定期間Ｔ２ｗとを含む。波形例２０では、電気角２１０度～電気角３００度が第２オン固定期間Ｔ２ｕである。波形例２０では、電気角０度～電気角６０度および電気角３３０度～電気角３６０度が第２オン固定期間Ｔ２ｖである。波形例２０では、電気角１５０度～電気角２１０度が第２オン固定期間Ｔ２ｗである。 In waveform example 20, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 20, the second fixed ON period T2u is from 210 electrical degrees to 300 electrical degrees. In waveform example 20, the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees. In waveform example 20, the second fixed ON period T2w is from 150 electrical degrees to 210 electrical degrees.
　波形例２０では、３相のうちＵ相において、第１オン固定期間Ｔ１ｕが、第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗと異なる。詳しくは、波形例２０では、第１オン固定期間Ｔ１ｕが９０度であるのに対し、第１オン固定期間Ｔ１ｖは無く、第１オン固定期間Ｔ１ｗは３０度である。すなわち、波形例２０では、第１オン固定期間Ｔ１ｕが第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗよりも長い。したがって、図３３Ｂに示すように、Ｕ相の第１半導体スイッチング素子Ｕｐ（Ｈ（ハイサイド））のスイッチング損失がＶ相およびＷ相に比べて小さくなっている。 In waveform example 20, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 20, the first fixed ON period T1u is 90 degrees, but the first fixed ON period T1v is absent and the first fixed ON period T1w is 30 degrees. That is, in waveform example 20, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 33B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
　波形例２０では、第２オン固定期間Ｔ２ｖが、第２オン固定期間Ｔ２ｕおよび第２オン固定期間Ｔ２ｗと異なる。詳しくは、波形例２０では、第２オン固定期間Ｔ２ｖが９０度であるのに対し、第２オン固定期間Ｔ２ｕは９０度であり、第２オン固定期間Ｔ２ｗは６０度である。すなわち、波形例２０では、第２オン固定期間Ｔ２ｖが第２オン固定期間Ｔ２ｗよりも長い。したがって、図３３Ｂに示すように、Ｖ相の第２半導体スイッチング素子Ｖｎ（Ｌ（ロウサイド））のスイッチング損失がＷ相に比べて小さくなっている。 In waveform example 20, the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in waveform example 20, the second fixed ON period T2v is 90 degrees, the second fixed ON period T2u is 90 degrees, and the second fixed ON period T2w is 60 degrees. That is, in waveform example 20, the second fixed ON period T2v is longer than the second fixed ON period T2w. Therefore, as shown in FIG. 33B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than that of the W-phase.
　以上、図３３Ａおよび図３３Ｂを参照して説明したように、波形例２０においても、波形例１と同様に、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。波形例２０では、Ｕ相の第１半導体スイッチング素子Ｕｐと、Ｖ相の第２半導体スイッチング素子Ｖｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 33A and 33B, in waveform example 20 as well as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 20, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn.
　また、波形例２０では、図３３Ｂに示すように、Ｕ相の第２半導体スイッチング素子Ｕｎと、Ｗ相の第１半導体スイッチング素子Ｗｐと、Ｗ相の第２半導体スイッチング素子Ｗｎとの発熱についても同時に抑えることができる。 In waveform example 20, as shown in FIG. 33B, the heat generated by the U-phase second semiconductor switching element Un, the W-phase first semiconductor switching element Wp, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
　図３４Ａおよび図３４Ｂを参照して、波形例２１について説明する。図３４Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図３４Ｂは、スイッチング損失を示す図である。 A waveform example 21 will be described with reference to FIGS. 34A and 34B. FIG. 34A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 34B is a diagram showing switching losses.
　図３４Ａに示すように、波形例２１は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例２１は、電気角６０度～電気角１５０度および電気角２７０度～電気角３３０度において、いずれか１相の出力が１に固定される波形である。また、波形例２１は、電気角０度～電気角６０度、電気角１５０度～電気角２７０度および電気角３３０度～電気角３６０度において、いずれか１相の出力が０に固定される波形である。波形例２１では、電気角６０度～電気角１５０度および電気角２７０度～電気角３３０度において、ハイサイドオン適用期間Ｔ３である。また、波形例２１では、電気角０度～電気角６０度、電気角１５０度～電気角２７０度および電気角３３０度～電気角３６０度において、ロウサイドオン適用期間Ｔ４である。 As shown in FIG. 34A, in waveform example 21, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, waveform example 21 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 270 degrees to 330 degrees. In waveform example 21, the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 electrical degrees, 150 to 270 electrical degrees, and 330 to 360 electrical degrees. waveform. In waveform example 21, the high side-on application period T3 occurs at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 270 degrees to 330 degrees. Further, in waveform example 21, the low side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees, 150 to 270 electrical degrees, and 330 to 360 electrical degrees.
　波形例２１では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｕと、第１オン固定期間Ｔ１ｗとを含む。波形例２１では、電気角６０度～電気角１５０度が第１オン固定期間Ｔ１ｕである。波形例２１では、電気角２７０度～電気角３３０度が第１オン固定期間Ｔ１ｗである。 In waveform example 21, the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1w. In waveform example 21, the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees. In waveform example 21, the first fixed ON period T1w is from 270 electrical degrees to 330 electrical degrees.
　波形例２１では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖと、第２オン固定期間Ｔ２ｗとを含む。波形例２１では、電気角２１０度～電気角２７０度が第２オン固定期間Ｔ２ｕである。波形例２１では、電気角０度～電気角６０度および電気角３３０度～電気角３６０度が第２オン固定期間Ｔ２ｖである。波形例２１では、電気角１５０度～電気角２１０度が第２オン固定期間Ｔ２ｗである。 In waveform example 21, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 21, the second fixed ON period T2u is from 210 electrical degrees to 270 electrical degrees. In waveform example 21, the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees. In waveform example 21, the second fixed ON period T2w is between 150 electrical degrees and 210 electrical degrees.
　波形例２１では、３相のうちＵ相において、第１オン固定期間Ｔ１ｕが、第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗと異なる。詳しくは、波形例２１では、第１オン固定期間Ｔ１ｕが９０度であるのに対し、第１オン固定期間Ｔ１ｖは無く、第１オン固定期間Ｔ１ｗは６０度である。すなわち、波形例２１では、第１オン固定期間Ｔ１ｕが第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗよりも長い。したがって、図３４Ｂに示すように、Ｕ相の第１半導体スイッチング素子Ｕｐ（Ｈ（ハイサイド））のスイッチング損失がＶ相およびＷ相に比べて小さくなっている。 In waveform example 21, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 21, the first fixed ON period T1u is 90 degrees, but the first fixed ON period T1v is absent and the first fixed ON period T1w is 60 degrees. That is, in waveform example 21, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 34B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
　波形例２１では、第２オン固定期間Ｔ２ｖが、第２オン固定期間Ｔ２ｕおよび第２オン固定期間Ｔ２ｗと異なる。詳しくは、波形例２１では、第２オン固定期間Ｔ２ｖが９０度であるのに対し、第２オン固定期間Ｔ２ｕは６０度であり、第２オン固定期間Ｔ２ｗは６０度である。すなわち、波形例２１では、第２オン固定期間Ｔ２ｖが第２オン固定期間Ｔ２ｕおよび第２オン固定期間Ｔ２ｗよりも長い。したがって、図３４Ｂに示すように、Ｖ相の第２半導体スイッチング素子Ｖｎ（Ｌ（ロウサイド））のスイッチング損失がＵ相およびＷ相に比べて小さくなっている。 In waveform example 21, the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in waveform example 21, the second fixed ON period T2v is 90 degrees, the second fixed ON period T2u is 60 degrees, and the second fixed ON period T2w is 60 degrees. That is, in waveform example 21, the second fixed ON period T2v is longer than the second fixed ON period T2u and the second fixed ON period T2w. Therefore, as shown in FIG. 34B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
　以上、図３４Ａおよび図３４Ｂを参照して説明したように、波形例２１においても、波形例１と同様に、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。波形例２１では、Ｕ相の第１半導体スイッチング素子Ｕｐと、Ｖ相の第２半導体スイッチング素子Ｖｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 34A and 34B , in waveform example 21, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 21, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn.
　また、波形例２１では、図３４Ｂに示すように、Ｕ相の第２半導体スイッチング素子Ｕｎと、Ｗ相の第１半導体スイッチング素子Ｗｐと、Ｗ相の第２半導体スイッチング素子Ｗｎとの発熱についても同時に抑えることができる。 In waveform example 21, as shown in FIG. 34B, the heat generated by the U-phase second semiconductor switching element Un, the W-phase first semiconductor switching element Wp, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
　図３５Ａおよび図３５Ｂを参照して、波形例２２について説明する。図３５Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図３５Ｂは、スイッチング損失を示す図である。 A waveform example 22 will be described with reference to FIGS. 35A and 35B. FIG. 35A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 35B is a diagram showing switching losses.
　図３５Ａに示すように、波形例２２は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例２２は、電気角６０度～電気角１５０度および電気角２４０度～電気角３３０度において、いずれか１相の出力が１に固定される波形である。また、波形例２２は、電気角０度～電気角６０度、電気角１５０度～電気角２４０度および電気角３３０度～電気角３６０度において、いずれか１相の出力が０に固定される波形である。波形例２２では、電気角６０度～電気角１５０度および電気角２４０度～電気角３３０度において、ハイサイドオン適用期間Ｔ３である。また、波形例２２では、電気角０度～電気角６０度、電気角１５０度～電気角２４０度および電気角３３０度～電気角３６０度において、ロウサイドオン適用期間Ｔ４である。 As shown in FIG. 35A, in waveform example 22, the output voltage of any one phase is fixed to 1 in a certain electrical angle section, and the output voltage of any one phase is fixed to 1 in another electrical angle section, depending on the electrical angle. is fixed to 0. Specifically, waveform example 22 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 240 degrees to 330 degrees. In waveform example 22, the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 electrical degrees, 150 to 240 electrical degrees, and 330 to 360 electrical degrees. waveform. In waveform example 22, the high side-on application period T3 occurs at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 240 degrees to 330 degrees. In waveform example 22, the low-side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees, 150 to 240 electrical degrees, and 330 to 360 electrical degrees.
　波形例２２では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｕと、第１オン固定期間Ｔ１ｖ、第１オン固定期間Ｔ１ｗとを含む。波形例２２では、電気角６０度～電気角１５０度が第１オン固定期間Ｔ１ｕである。波形例２２では、電気角２４０度～電気角２７０度が第１オン固定期間Ｔ１ｖである。波形例２２では、電気角２７０度～電気角３３０度が第１オン固定期間Ｔ１ｗである。 In waveform example 22, the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w. In waveform example 22, the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees. In waveform example 22, the first fixed ON period T1v is between 240 electrical degrees and 270 electrical degrees. In waveform example 22, the first fixed ON period T1w is from 270 electrical degrees to 330 electrical degrees.
　波形例２２では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖと、第２オン固定期間Ｔ２ｗとを含む。波形例２２では、電気角２１０度～電気角２４０度が第２オン固定期間Ｔ２ｕである。波形例２２では、電気角０度～電気角６０度および電気角３３０度～電気角３６０度が第２オン固定期間Ｔ２ｖである。波形例２２では、電気角１５０度～電気角２１０度が第２オン固定期間Ｔ２ｗである。 In waveform example 22, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 22, the second fixed ON period T2u is from 210 electrical degrees to 240 electrical degrees. In waveform example 22, the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees. In waveform example 22, the second fixed ON period T2w is between 150 electrical degrees and 210 electrical degrees.
　波形例２２では、３相のうちＵ相において、第１オン固定期間Ｔ１ｕが、第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗと異なる。詳しくは、波形例２２では、第１オン固定期間Ｔ１ｕが９０度であるのに対し、第１オン固定期間Ｔ１ｖは３０度であり、第１オン固定期間Ｔ１ｗは６０度である。すなわち、波形例２２では、第１オン固定期間Ｔ１ｕが第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗよりも長い。したがって、図３５Ｂに示すように、Ｕ相の第１半導体スイッチング素子Ｕｐ（Ｈ（ハイサイド））のスイッチング損失がＶ相およびＷ相に比べて小さくなっている。 In waveform example 22, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 22, the first fixed ON period T1u is 90 degrees, the first fixed ON period T1v is 30 degrees, and the first fixed ON period T1w is 60 degrees. That is, in waveform example 22, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 35B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
　波形例２２では、第２オン固定期間Ｔ２ｖが、第２オン固定期間Ｔ２ｕおよび第２オン固定期間Ｔ２ｗと異なる。詳しくは、波形例２２では、第２オン固定期間Ｔ２ｖが９０度であるのに対し、第２オン固定期間Ｔ２ｕは３０度であり、第２オン固定期間Ｔ２ｗは６０度である。すなわち、波形例２２では、第２オン固定期間Ｔ２ｖが第２オン固定期間Ｔ２ｕおよび第２オン固定期間Ｔ２ｗよりも長い。したがって、図３５Ｂに示すように、Ｖ相の第２半導体スイッチング素子Ｖｎ（Ｌ（ロウサイド））のスイッチング損失がＵ相およびＷ相に比べて小さくなっている。 In waveform example 22, the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in waveform example 22, the second fixed ON period T2v is 90 degrees, the second fixed ON period T2u is 30 degrees, and the second fixed ON period T2w is 60 degrees. That is, in waveform example 22, the second fixed ON period T2v is longer than the second fixed ON period T2u and the second fixed ON period T2w. Therefore, as shown in FIG. 35B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
　以上、図３５Ａおよび図３５Ｂを参照して説明したように、波形例２２においても、波形例１と同様に、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。波形例２２では、Ｕ相の第１半導体スイッチング素子Ｕｐと、Ｖ相の第２半導体スイッチング素子Ｖｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 35A and 35B , in waveform example 22, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 22, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn.
　また、波形例２２では、図３５Ｂに示すように、Ｕ相の第２半導体スイッチング素子Ｕｎと、Ｖ相の第１半導体スイッチング素子Ｖｐと、Ｗ相の第１半導体スイッチング素子Ｗｐと、Ｗ相の第２半導体スイッチング素子Ｗｎとの発熱についても同時に抑えることができる。 In waveform example 22, as shown in FIG. 35B, the U-phase second semiconductor switching element Un, the V-phase first semiconductor switching element Vp, the W-phase first semiconductor switching element Wp, and the W-phase semiconductor switching element Wp Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
　図３６Ａおよび図３６Ｂを参照して、波形例２３について説明する。図３６Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図３６Ｂは、スイッチング損失を示す図である。 A waveform example 23 will be described with reference to FIGS. 36A and 36B. FIG. 36A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 36B is a diagram showing switching losses.
　図３６Ａに示すように、波形例２３は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例２３は、電気角６０度～電気角１５０度および電気角２１０度～電気角３３０度において、いずれか１相の出力が１に固定される波形である。また、波形例２３は、電気角０度～電気角６０度、電気角１５０度～電気角２１０度および電気角３３０度～電気角３６０度において、いずれか１相の出力が０に固定される波形である。波形例２３では、電気角６０度～電気角１５０度および電気角２１０度～電気角３３０度において、ハイサイドオン適用期間Ｔ３である。また、波形例２３では、電気角０度～電気角６０度、電気角１５０度～電気角２１０度および電気角３３０度～電気角３６０度において、ロウサイドオン適用期間Ｔ４である。 As shown in FIG. 36A, in waveform example 23, the output voltage of any one phase is fixed to 1 in a certain electrical angle section, and the output voltage of any one phase is fixed to 1 in another electrical angle section, depending on the electrical angle. is fixed to 0. Specifically, waveform example 23 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 210 degrees to 330 degrees. In waveform example 23, the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 electrical degrees, 150 to 210 electrical degrees, and 330 to 360 electrical degrees. waveform. In waveform example 23, the high side-on application period T3 occurs at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 210 degrees to 330 degrees. Further, in waveform example 23, the low side-on application period T4 is at the electrical angle of 0 to 60 electrical degrees, the electrical angle of 150 to 210 electrical degrees, and the electrical angle of 330 to 360 electrical degrees.
　波形例２３では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｕと、第１オン固定期間Ｔ１ｖと、第１オン固定期間Ｔ１ｗとを含む。波形例２３では、電気角６０度～電気角１５０度が第１オン固定期間Ｔ１ｕである。波形例２３では、電気角２１０度～電気角２７０度が第１オン固定期間Ｔ１ｖである。波形例２３では、電気角２７０度～電気角３３０度が第１オン固定期間Ｔ１ｕである。 In waveform example 23, the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w. In waveform example 23, the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees. In waveform example 23, the first fixed ON period T1v is between 210 electrical degrees and 270 electrical degrees. In waveform example 23, the first fixed ON period T1u is from 270 electrical degrees to 330 electrical degrees.
　波形例２３では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖと、第２オン固定期間Ｔ２ｗとを含む。波形例２３では、電気角０度～電気角６０度および電気角３３０度～電気角３６０度が第２オン固定期間Ｔ２ｖである。波形例２３では、電気角１５０度～電気角２１０度が第２オン固定期間Ｔ２ｗである。 In waveform example 23, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 23, the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees. In waveform example 23, the second fixed ON period T2w is from 150 electrical degrees to 210 electrical degrees.
　波形例２３では、３相のうちＵ相において、第１オン固定期間Ｔ１ｕが、第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗと異なる。詳しくは、波形例２３では、第１オン固定期間Ｔ１ｕが９０度であるのに対し、第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗは６０度である。すなわち、波形例２３では、第１オン固定期間Ｔ１ｕが第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗよりも長い。したがって、図３６Ｂに示すように、Ｕ相の第１半導体スイッチング素子Ｕｐ（Ｈ（ハイサイド））のスイッチング損失がＶ相およびＷ相に比べて小さくなっている。 In waveform example 23, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 23, the first fixed ON period T1u is 90 degrees, while the first fixed ON period T1v and the first fixed ON period T1w are 60 degrees. That is, in waveform example 23, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 36B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
　波形例２３では、第２オン固定期間Ｔ２ｖが、第２オン固定期間Ｔ２ｕおよび第２オン固定期間Ｔ２ｗと異なる。詳しくは、波形例２３では、第２オン固定期間Ｔ２ｖが９０度であるのに対し、第２オン固定期間Ｔ２ｕは無く、第２オン固定期間Ｔ２ｗは６０度である。すなわち、波形例２３では、第２オン固定期間Ｔ２ｖが第２オン固定期間Ｔ２ｗよりも長い。したがって、図３６Ｂに示すように、Ｖ相の第２半導体スイッチング素子Ｖｎ（Ｌ（ロウサイド））のスイッチング損失がＵ相およびＷ相に比べて小さくなっている。 In waveform example 23, the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in waveform example 23, the second fixed ON period T2v is 90 degrees, whereas the second fixed ON period T2u is absent and the second fixed ON period T2w is 60 degrees. That is, in waveform example 23, the second fixed ON period T2v is longer than the second fixed ON period T2w. Therefore, as shown in FIG. 36B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
　以上、図３６Ａおよび図３６Ｂを参照して説明したように、波形例２３においても、波形例１と同様に、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。波形例２３では、Ｕ相の第１半導体スイッチング素子Ｕｐと、Ｖ相の第２半導体スイッチング素子Ｖｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 36A and 36B, in waveform example 23, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 23, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn.
　また、波形例２３では、図３６Ｂに示すように、Ｖ相の第１半導体スイッチング素子Ｖｐと、Ｗ相の第１半導体スイッチング素子Ｗｐと、Ｗ相の第２半導体スイッチング素子Ｗｎとの発熱についても同時に抑えることができる。 In waveform example 23, as shown in FIG. 36B, the heat generated by the V-phase first semiconductor switching element Vp, the W-phase first semiconductor switching element Wp, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
　図３７Ａおよび図３７Ｂを参照して、波形例２４について説明する。図３７Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図３７Ｂは、スイッチング損失を示す図である。 Waveform example 24 will be described with reference to FIGS. 37A and 37B. FIG. 37A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 37B is a diagram showing switching losses.
　図３７Ａに示すように、波形例２４は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例２４は、電気角６０度～電気角１５０度および電気角１８０度～電気角３３０度において、いずれか１相の出力が１に固定される波形である。また、波形例２４は、電気角０度～電気角６０度、電気角１５０度～電気角１８０度および電気角３３０度～電気角３６０度において、いずれか１相の出力が０に固定される波形である。波形例２４では、電気角６０度～電気角１５０度および電気角１８０度～電気角３３０度において、ハイサイドオン適用期間Ｔ３である。また、波形例２４では、電気角０度～電気角６０度、電気角１５０度～電気角１８０度および電気角３３０度～電気角３６０度において、ロウサイドオン適用期間Ｔ４である。 As shown in FIG. 37A, in waveform example 24, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, waveform example 24 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 180 degrees to 330 degrees. In waveform example 24, the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 electrical degrees, 150 to 180 electrical degrees, and 330 to 360 electrical degrees. waveform. In waveform example 24, the high-side-on application period T3 is at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 180 degrees to 330 degrees. Further, in waveform example 24, the low side-on application period T4 is at an electrical angle of 0 to 60 electrical degrees, 150 to 180 electrical degrees, and 330 to 360 electrical degrees.
　波形例２４では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｕと、第１オン固定期間Ｔ１ｖと、第１オン固定期間Ｔ１ｗとを含む。波形例２４では、電気角６０度～電気角１５０度が第１オン固定期間Ｔ１ｕである。波形例２４では、電気角１８０度～電気角２７０度が第１オン固定期間Ｔ１ｖである。波形例２４では、電気角２７０度～電気角３３０度が第１オン固定期間Ｔ１ｗである。 In Waveform Example 24, the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w. In waveform example 24, the first ON fixed period T1u is from 60 electrical degrees to 150 electrical degrees. In waveform example 24, the first fixed ON period T1v is from 180 degrees to 270 degrees in electrical angle. In waveform example 24, the first fixed ON period T1w is from 270 electrical degrees to 330 electrical degrees.
　波形例２４では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｖと、第２オン固定期間Ｔ２ｗとを含む。波形例２４では、電気角０度～電気角６０度および電気角３３０度～電気角３６０度が第２オン固定期間Ｔ２ｖである。波形例２４では、電気角１５０度～電気角１８０度が第２オン固定期間Ｔ２ｗである。 In waveform example 24, the second fixed ON period T2 includes a second fixed ON period T2v and a second fixed ON period T2w. In waveform example 24, the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees. In waveform example 24, the second fixed ON period T2w is between 150 electrical degrees and 180 electrical degrees.
　波形例２４では、３相のうちＵ相において、第１オン固定期間Ｔ１ｕが、第１オン固定期間Ｔ１ｗと異なる。詳しくは、波形例２４では、第１オン固定期間Ｔ１ｕが９０度であるのに対し、第１オン固定期間Ｔ１ｗは６０度である。すなわち、波形例２４では、第１オン固定期間Ｔ１ｕが第１オン固定期間Ｔ１ｗよりも長い。なお、第１オン固定期間Ｔ１ｕと、第１オン固定期間Ｔ１ｖとは同じである。したがって、図３７Ｂに示すように、Ｕ相の第１半導体スイッチング素子Ｕｐ（Ｈ（ハイサイド））のスイッチング損失がＷ相に比べて小さくなっている。 In waveform example 24, the first fixed ON period T1u differs from the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 24, the first fixed ON period T1u is 90 degrees, while the first fixed ON period T1w is 60 degrees. That is, in waveform example 24, the first fixed ON period T1u is longer than the first fixed ON period T1w. Note that the first fixed ON period T1u and the first fixed ON period T1v are the same. Therefore, as shown in FIG. 37B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than that of the W-phase.
　波形例２４では、第２オン固定期間Ｔ２ｖが、第２オン固定期間Ｔ２ｕおよび第２オン固定期間Ｔ２ｗと異なる。詳しくは、波形例２４では、第２オン固定期間Ｔ２ｖが９０度であるのに対し、第２オン固定期間Ｔ２ｗは３０度である。すなわち、波形例２４では、第２オン固定期間Ｔ２ｖが第２オン固定期間Ｔ２ｗよりも長い。したがって、図３７Ｂに示すように、Ｖ相の第２半導体スイッチング素子Ｖｎ（Ｌ（ロウサイド））のスイッチング損失がＷ相に比べて小さくなっている。 In waveform example 24, the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in waveform example 24, the second fixed ON period T2v is 90 degrees, while the second fixed ON period T2w is 30 degrees. That is, in waveform example 24, the second fixed ON period T2v is longer than the second fixed ON period T2w. Therefore, as shown in FIG. 37B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than that of the W-phase.
　以上、図３７Ａおよび図３７Ｂを参照して説明したように、波形例２４においても、波形例１と同様に、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。波形例２４では、Ｕ相の第１半導体スイッチング素子Ｕｐと、Ｖ相の第２半導体スイッチング素子Ｖｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 37A and 37B, in waveform example 24, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In the waveform example 24, the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
　また、波形例２４では、図３７Ｂに示すように、Ｖ相の第１半導体スイッチング素子Ｖｐと、Ｗ相の第１半導体スイッチング素子Ｗｐと、Ｗ相の第２半導体スイッチング素子Ｗｎとの発熱についても同時に抑えることができる。 In waveform example 24, as shown in FIG. 37B, the heat generated by the V-phase first semiconductor switching element Vp, the W-phase first semiconductor switching element Wp, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
　図３８Ａおよび図３８Ｂを参照して、波形例２５について説明する。図３８Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図３８Ｂは、スイッチング損失を示す図である。 A waveform example 25 will be described with reference to FIGS. 38A and 38B. FIG. 38A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 38B is a diagram showing switching losses.
　図３８Ａに示すように、波形例２５は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例２５は、電気角６０度～電気角１５０度、電気角２１０度～電気角２４０度および電気角２７０度～電気角３３０度において、いずれか１相の出力が１に固定される波形である。また、波形例２５は、電気角０度～電気角６０度、電気角１５０度～電気角２１０度、電気角２４０度～電気角２７０度および電気角３３０度～電気角３６０度において、いずれか１相の出力が０に固定される波形である。波形例２５では、電気角６０度～電気角１５０度、電気角２１０度～電気角２４０度および電気角２７０度～電気角３３０度において、ハイサイドオン適用期間Ｔ３である。また、波形例２５では、電気角０度～電気角６０度、電気角１５０度～電気角２１０度、電気角２４０度～電気角２７０度および電気角３３０度～電気角３６０度において、ロウサイドオン適用期間Ｔ４である。 As shown in FIG. 38A, in waveform example 25, the output voltage of any one phase is fixed to 1 in a certain electrical angle section, and the output voltage of any one phase is fixed to 1 in another electrical angle section, depending on the electrical angle. is fixed to 0. Specifically, in waveform example 25, the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 150 degrees, from 210 degrees to 240 degrees, and from 270 degrees to 330 degrees. waveform. In addition, waveform example 25 is any of the electrical angle of 0 to 60 electrical degrees, 150 to 210 electrical degrees, 240 to 270 electrical degrees, and 330 to 360 electrical degrees. It is a waveform in which the output of one phase is fixed to 0. In waveform example 25, the high-side-on application period T3 occurs at an electrical angle of 60 to 150 electrical degrees, 210 to 240 electrical degrees, and 270 to 330 electrical degrees. In addition, in waveform example 25, the low side This is the ON application period T4.
　波形例２５では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｕと、第１オン固定期間Ｔ１ｖと、第１オン固定期間Ｔ１ｗとを含む。波形例２５では、電気角６０度～電気角１５０度が第１オン固定期間Ｔ１ｕである。波形例２５では、電気角２１０度～電気角２４０度が第１オン固定期間Ｔ１ｖである。波形例２５では、電気角２７０度～電気角３３０度が第１オン固定期間Ｔ１ｗである。 In waveform example 25, the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w. In waveform example 25, the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees. In waveform example 25, the first fixed ON period T1v is between 210 electrical degrees and 240 electrical degrees. In waveform example 25, the first fixed ON period T1w is from 270 electrical degrees to 330 electrical degrees.
　波形例２５では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖと、第２オン固定期間Ｔ２ｗとを含む。波形例２５では、電気角２４０度～電気角２７０度が第２オン固定期間Ｔ２ｕである。波形例２５では、電気角０度～電気角６０度および電気角３３０度～電気角３６０度が第２オン固定期間Ｔ２ｖである。波形例２５では、電気角１５０度～電気角２１０度が第２オン固定期間Ｔ２ｗである。 In waveform example 25, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 25, the second fixed ON period T2u is from 240 electrical degrees to 270 electrical degrees. In waveform example 25, the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees. In waveform example 25, the second fixed ON period T2w is from 150 electrical degrees to 210 electrical degrees.
　波形例２５では、３相のうちＵ相において、第１オン固定期間Ｔ１ｕが、第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗと異なる。詳しくは、波形例２５では、第１オン固定期間Ｔ１ｕが９０度であるのに対し、第１オン固定期間Ｔ１ｖは３０度であり、第１オン固定期間Ｔ１ｗは６０度である。すなわち、波形例２５では、第１オン固定期間Ｔ１ｕが第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗよりも長い。したがって、図３８Ｂに示すように、Ｕ相の第１半導体スイッチング素子Ｕｐ（Ｈ（ハイサイド））のスイッチング損失がＶ相およびＷ相に比べて小さくなっている。 In waveform example 25, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 25, the first fixed ON period T1u is 90 degrees, the first fixed ON period T1v is 30 degrees, and the first fixed ON period T1w is 60 degrees. That is, in waveform example 25, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 38B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
　波形例２５では、第２オン固定期間Ｔ２ｖが、第２オン固定期間Ｔ２ｕおよび第２オン固定期間Ｔ２ｗと異なる。詳しくは、波形例２５では、第２オン固定期間Ｔ２ｖが９０度であるのに対し、第２オン固定期間Ｔ２ｕは３０度であり、第２オン固定期間Ｔ２ｗは６０度である。すなわち、波形例２５では、第２オン固定期間Ｔ２ｖが第２オン固定期間Ｔ２ｕおよび第２オン固定期間Ｔ２ｗよりも長い。したがって、図３８Ｂに示すように、Ｖ相の第２半導体スイッチング素子Ｖｎ（Ｌ（ロウサイド））のスイッチング損失がＵ相およびＷ相に比べて小さくなっている。 In waveform example 25, the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in waveform example 25, the second fixed ON period T2v is 90 degrees, the second fixed ON period T2u is 30 degrees, and the second fixed ON period T2w is 60 degrees. That is, in waveform example 25, the second fixed ON period T2v is longer than the second fixed ON period T2u and the second fixed ON period T2w. Therefore, as shown in FIG. 38B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
　以上、図３８Ａおよび図３８Ｂを参照して説明したように、波形例２５においても、波形例１と同様に、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。波形例２５では、Ｕ相の第１半導体スイッチング素子Ｕｐと、Ｖ相の第２半導体スイッチング素子Ｖｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 38A and 38B , in waveform example 25, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In the waveform example 25, the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
　また、波形例２５では、図３８Ｂに示すように、Ｕ相の第２半導体スイッチング素子Ｕｎと、Ｖ相の第１半導体スイッチング素子Ｖｐと、Ｗ相の第１半導体スイッチング素子Ｗｐと、Ｗ相の第２半導体スイッチング素子Ｗｎとの発熱についても同時に抑えることができる。 In waveform example 25, as shown in FIG. 38B, the U-phase second semiconductor switching element Un, the V-phase first semiconductor switching element Vp, the W-phase first semiconductor switching element Wp, and the W-phase semiconductor switching element Wp Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
　図３９Ａおよび図３９Ｂを参照して、波形例２６について説明する。図３９Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図３９Ｂは、スイッチング損失を示す図である。 A waveform example 26 will be described with reference to FIGS. 39A and 39B. FIG. 39A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 39B is a diagram showing switching losses.
　図３９Ａに示すように、波形例２６は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例２６は、電気角６０度～電気角１５０度、電気角１９５度～電気角２４０度および電気角２８５度～電気角３３０度において、いずれか１相の出力が１に固定される波形である。また、波形例２６は、電気角０度～電気角６０度、電気角１５０度～電気角１９５度、電気角２４０度～電気角２８５度および電気角３３０度～電気角３６０度において、いずれか１相の出力が０に固定される波形である。波形例２６では、電気角６０度～電気角１５０度、電気角１９５度～電気角２４０度および電気角２８５度～電気角３３０度において、ハイサイドオン適用期間Ｔ３である。また、波形例２６では、電気角０度～電気角６０度、電気角１５０度～電気角１９５度、電気角２４０度～電気角２８５度および電気角３３０度～電気角３６０度において、ロウサイドオン適用期間Ｔ４である。 As shown in FIG. 39A, in waveform example 26, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, in waveform example 26, the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 150 degrees, from 195 degrees to 240 degrees, and from 285 degrees to 330 degrees. waveform. In addition, waveform example 26 is any of the electrical angles of 0 to 60 electrical degrees, 150 to 195 electrical degrees, 240 to 285 electrical degrees, and 330 to 360 electrical degrees. It is a waveform in which the output of one phase is fixed to 0. In waveform example 26, the high-side-on application period T3 is at an electrical angle of 60 to 150 electrical degrees, 195 to 240 electrical degrees, and 285 to 330 electrical degrees. Further, in waveform example 26, the low side This is the ON application period T4.
　波形例２６では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｕと、第１オン固定期間Ｔ１ｖと、第１オン固定期間Ｔ１ｗとを含む。波形例２６では、電気角６０度～電気角１５０度が第１オン固定期間Ｔ１ｕである。波形例２６では、電気角１９５度～電気角２４０度が第１オン固定期間Ｔ１ｖである。波形例２６では、電気角２８５度～電気角３３０度が第１オン固定期間Ｔ１ｗである。 In waveform example 26, the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w. In waveform example 26, the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees. In waveform example 26, the first fixed ON period T1v is between an electrical angle of 195 degrees and an electrical angle of 240 degrees. In waveform example 26, the first fixed ON period T1w is between an electrical angle of 285 degrees and an electrical angle of 330 degrees.
　波形例２６では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖと、第２オン固定期間Ｔ２ｗとを含む。波形例２６では、電気角２４０度～電気角２８５度が第２オン固定期間Ｔ２ｕである。波形例２６では、電気角０度～電気角６０度および電気角３３０度～電気角３６０度が第２オン固定期間Ｔ２ｖである。波形例２６では、電気角１５０度～電気角１９５度が第２オン固定期間Ｔ２ｗである。 In waveform example 26, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 26, the second fixed ON period T2u is from 240 electrical degrees to 285 electrical degrees. In waveform example 26, the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees. In waveform example 26, the second fixed ON period T2w is from 150 electrical degrees to 195 electrical degrees.
　波形例２６では、３相のうちＵ相において、第１オン固定期間Ｔ１ｕが、第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗと異なる。詳しくは、波形例２６では、第１オン固定期間Ｔ１ｕが９０度であるのに対し、第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗは４５度である。すなわち、波形例２６では、第１オン固定期間Ｔ１ｕが第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗよりも長い。したがって、図３９Ｂに示すように、Ｕ相の第１半導体スイッチング素子Ｕｐ（Ｈ（ハイサイド））のスイッチング損失がＶ相およびＷ相に比べて小さくなっている。 In waveform example 26, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 26, the first fixed ON period T1u is 90 degrees, while the first fixed ON period T1v and the first fixed ON period T1w are 45 degrees. That is, in waveform example 26, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 39B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
　波形例２６では、第２オン固定期間Ｔ２ｖが、第２オン固定期間Ｔ２ｕおよび第２オン固定期間Ｔ２ｗと異なる。詳しくは、波形例２６では、第２オン固定期間Ｔ２ｖが９０度であるのに対し、第２オン固定期間Ｔ２ｕおよび第２オン固定期間Ｔ２ｗは４５度である。すなわち、波形例２６では、第２オン固定期間Ｔ２ｖが第２オン固定期間Ｔ２ｕおよび第２オン固定期間Ｔ２ｗよりも長い。したがって、図３９Ｂに示すように、Ｖ相の第２半導体スイッチング素子Ｖｎ（Ｌ（ロウサイド））のスイッチング損失がＵ相およびＷ相に比べて小さくなっている。 In waveform example 26, the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in waveform example 26, the second fixed ON period T2v is 90 degrees, while the second fixed ON period T2u and the second fixed ON period T2w are 45 degrees. That is, in waveform example 26, the second fixed ON period T2v is longer than the second fixed ON period T2u and the second fixed ON period T2w. Therefore, as shown in FIG. 39B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
　以上、図３９Ａおよび図３９Ｂを参照して説明したように、波形例２６においても、波形例１と同様に、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。波形例２６では、Ｕ相の第１半導体スイッチング素子Ｕｐと、Ｖ相の第２半導体スイッチング素子Ｖｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 39A and 39B, in waveform example 26, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In the waveform example 26, the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
　また、波形例２６では、図３９Ｂに示すように、Ｕ相の第２半導体スイッチング素子Ｕｎと、Ｖ相の第１半導体スイッチング素子Ｖｐと、Ｗ相の第１半導体スイッチング素子Ｗｐと、Ｗ相の第２半導体スイッチング素子Ｗｎとの発熱についても同時に抑えることができる。 In waveform example 26, as shown in FIG. 39B, the U-phase second semiconductor switching element Un, the V-phase first semiconductor switching element Vp, the W-phase first semiconductor switching element Wp, and the W-phase Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
　図４０Ａおよび図４０Ｂを参照して、波形例２７について説明する。図４０Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図４０Ｂは、スイッチング損失を示す図である。 A waveform example 27 will be described with reference to FIGS. 40A and 40B. FIG. 40A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 40B is a diagram showing switching losses.
　図４０Ａに示すように、波形例２７は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例２７は、電気角６０度～電気角１５０度、電気角１８０度～電気角２４０度および電気角３００度～電気角３３０度において、いずれか１相の出力が１に固定される波形である。また、波形例２７は、電気角０度～電気角６０度、電気角１５０度～電気角１８０度、電気角２４０度～電気角３００度および電気角３３０度～電気角３６０度において、いずれか１相の出力が０に固定される波形である。波形例２７では、電気角６０度～電気角１５０度、電気角１８０度～電気角２４０度および電気角３００度～電気角３３０度において、ハイサイドオン適用期間Ｔ３である。また、波形例２７では、電気角０度～電気角６０度、電気角１５０度～電気角１８０度、電気角２４０度～電気角３００度および電気角３３０度～電気角３６０度において、ロウサイドオン適用期間Ｔ４である。 As shown in FIG. 40A, in waveform example 27, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, in waveform example 27, the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 150 degrees, from 180 degrees to 240 degrees, and from 300 degrees to 330 degrees. waveform. Further, waveform example 27 is any of the electrical angle of 0 to 60 electrical degrees, the electrical angle of 150 to 180 electrical degrees, the electrical angle of 240 to 300 electrical degrees, and the electrical angle of 330 to 360 electrical degrees. It is a waveform in which the output of one phase is fixed to 0. In waveform example 27, the high-side-on application period T3 occurs at an electrical angle of 60 to 150 electrical degrees, 180 to 240 electrical degrees, and 300 to 330 electrical degrees. Further, in waveform example 27, the low side This is the ON application period T4.
　波形例２７では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｕと、第１オン固定期間Ｔ１ｖと、第１オン固定期間Ｔ１ｗとを含む。波形例２７では、電気角６０度～電気角１５０度が第１オン固定期間Ｔ１ｕである。波形例２７では、電気角１８０度～電気角２４０度が第１オン固定期間Ｔ１ｖである。波形例２７では、電気角３００度～電気角３３０度が第１オン固定期間Ｔ１ｗである。 In waveform example 27, the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w. In waveform example 27, the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees. In waveform example 27, the first fixed ON period T1v is from 180 electrical degrees to 240 electrical degrees. In waveform example 27, the first fixed ON period T1w is between 300 electrical degrees and 330 electrical degrees.
　波形例２７では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖと、第２オン固定期間Ｔ２ｗとを含む。波形例２７では、電気角２４０度～電気角３００度が第２オン固定期間Ｔ２ｕである。波形例２７では、電気角０度～電気角６０度および電気角３３０度～電気角３６０度が第２オン固定期間Ｔ２ｖである。波形例２７では、電気角１５０度～電気角１８０度が第２オン固定期間Ｔ２ｗである。 In waveform example 27, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 27, the second fixed ON period T2u is from 240 electrical degrees to 300 electrical degrees. In waveform example 27, the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees. In waveform example 27, the second fixed ON period T2w is between 150 electrical degrees and 180 electrical degrees.
　波形例２７では、３相のうちＵ相において、第１オン固定期間Ｔ１ｕが、第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗと異なる。詳しくは、波形例２７では、第１オン固定期間Ｔ１ｕが９０度であるのに対し、第１オン固定期間Ｔ１ｖは６０度であり、第１オン固定期間Ｔ１ｗは３０度である。すなわち、波形例２７では、第１オン固定期間Ｔ１ｕが第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗよりも長い。したがって、図４０Ｂに示すように、Ｕ相の第１半導体スイッチング素子Ｕｐ（Ｈ（ハイサイド））のスイッチング損失がＶ相およびＷ相に比べて小さくなっている。 In waveform example 27, in the U phase among the three phases, the first fixed ON period T1u is different from the first fixed ON period T1v and the first fixed ON period T1w. Specifically, in waveform example 27, the first fixed ON period T1u is 90 degrees, the first fixed ON period T1v is 60 degrees, and the first fixed ON period T1w is 30 degrees. That is, in waveform example 27, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 40B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
　波形例２７では、第２オン固定期間Ｔ２ｖが、第２オン固定期間Ｔ２ｕおよび第２オン固定期間Ｔ２ｗと異なる。詳しくは、波形例２７では、第２オン固定期間Ｔ２ｖが９０度であるのに対し、第２オン固定期間Ｔ２ｕは６０度であり、第２オン固定期間Ｔ２ｗは３０度である。すなわち、波形例２７では、第２オン固定期間Ｔ２ｖが第２オン固定期間Ｔ２ｕおよび第２オン固定期間Ｔ２ｗよりも長い。したがって、図４０Ｂに示すように、Ｖ相の第２半導体スイッチング素子Ｖｎ（Ｌ（ロウサイド））のスイッチング損失がＵ相およびＷ相に比べて小さくなっている。 In waveform example 27, the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in waveform example 27, the second fixed ON period T2v is 90 degrees, the second fixed ON period T2u is 60 degrees, and the second fixed ON period T2w is 30 degrees. That is, in waveform example 27, the second fixed ON period T2v is longer than the second fixed ON period T2u and the second fixed ON period T2w. Therefore, as shown in FIG. 40B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
　以上、図４０Ａおよび図４０Ｂを参照して説明したように、波形例２７においても、波形例１と同様に、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。波形例２７では、Ｕ相の第１半導体スイッチング素子Ｕｐと、Ｖ相の第２半導体スイッチング素子Ｖｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 40A and 40B, in waveform example 27, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 27, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn.
　また、波形例２７では、図４０Ｂに示すように、Ｕ相の第２半導体スイッチング素子Ｕｎと、Ｖ相の第１半導体スイッチング素子Ｖｐと、Ｗ相の第１半導体スイッチング素子Ｗｐと、Ｗ相の第２半導体スイッチング素子Ｗｎとの発熱についても同時に抑えることができる。 In waveform example 27, as shown in FIG. 40B, the U-phase second semiconductor switching element Un, the V-phase first semiconductor switching element Vp, the W-phase first semiconductor switching element Wp, and the W-phase Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
　図４１Ａおよび図４１Ｂを参照して、波形例２８について説明する。図４１Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図４１Ｂは、スイッチング損失を示す図である。 A waveform example 28 will be described with reference to FIGS. 41A and 41B. FIG. 41A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 41B is a diagram showing switching losses.
　図４１Ａに示すように、波形例２８は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例２８は、電気角６０度～電気角１５０度および電気角２１０度～電気角２７０度において、いずれか１相の出力が１に固定される波形である。また、波形例２８は、電気角０度～電気角６０度、電気角１５０度～電気角２１０度および電気角２７０度～電気角３６０度において、いずれか１相の出力が０に固定される波形である。波形例２８では、電気角６０度～電気角１５０度および電気角２１０度～電気角２７０度において、ハイサイドオン適用期間Ｔ３である。また、波形例２８では、電気角０度～電気角６０度、電気角１５０度～電気角２１０度および電気角２７０度～電気角３６０度において、ロウサイドオン適用期間Ｔ４である。 As shown in FIG. 41A, in waveform example 28, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. More specifically, waveform example 28 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 210 degrees to 270 degrees. In waveform example 28, the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 electrical degrees, 150 to 210 electrical degrees, and 270 to 360 electrical degrees. waveform. In waveform example 28, the high side-on application period T3 occurs at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 210 degrees to 270 degrees. Further, in waveform example 28, the low side-on application period T4 is at an electrical angle of 0 to 60 electrical degrees, 150 to 210 electrical degrees, and 270 to 360 electrical degrees.
　波形例２８では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｕと、第１オン固定期間Ｔ１ｖとを含む。波形例２８では、電気角６０度～電気角１５０度が第１オン固定期間Ｔ１ｕである。波形例２８では、電気角２１０度～電気角２７０度が第１オン固定期間Ｔ１ｖである。 In waveform example 28, the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v. In waveform example 28, the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees. In waveform example 28, the first fixed ON period T1v is between 210 electrical degrees and 270 electrical degrees.
　波形例２８では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖと、第２オン固定期間Ｔ２ｗとを含む。波形例２８では、電気角２７０度～電気角３３０度が第２オン固定期間Ｔ２ｕである。波形例２８では、電気角０度～電気角６０度および電気角３３０度～電気角３６０度が第２オン固定期間Ｔ２ｖである。波形例２８では、電気角１５０度～電気角２１０度が第２オン固定期間Ｔ２ｗである。 In Waveform Example 28, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 28, the second fixed ON period T2u is from 270 electrical degrees to 330 electrical degrees. In waveform example 28, the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees. In waveform example 28, the second fixed ON period T2w is from 150 electrical degrees to 210 electrical degrees.
　波形例２８では、３相のうちＵ相において、第１オン固定期間Ｔ１ｕが、第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗと異なる。詳しくは、波形例２８では、第１オン固定期間Ｔ１ｕが９０度であるのに対し、第１オン固定期間Ｔ１ｖは６０度であり、第１オン固定期間Ｔ１ｗは無い。すなわち、波形例２８では、第１オン固定期間Ｔ１ｕが第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗよりも長い。したがって、図４１Ｂに示すように、Ｕ相の第１半導体スイッチング素子Ｕｐ（Ｈ（ハイサイド））のスイッチング損失がＶ相およびＷ相に比べて小さくなっている。 In waveform example 28, in the U phase among the three phases, the first fixed ON period T1u is different from the first fixed ON period T1v and the first fixed ON period T1w. Specifically, in waveform example 28, the first fixed ON period T1u is 90 degrees, the first fixed ON period T1v is 60 degrees, and there is no first fixed ON period T1w. That is, in waveform example 28, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 41B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
　波形例２８では、第２オン固定期間Ｔ２ｖが、第２オン固定期間Ｔ２ｕおよび第２オン固定期間Ｔ２ｗと異なる。詳しくは、波形例２８では、第２オン固定期間Ｔ２ｖが９０度であるのに対し、第２オン固定期間Ｔ２ｕおよび第２オン固定期間Ｔ２ｗは６０度である。すなわち、波形例２８では、第２オン固定期間Ｔ２ｖが第２オン固定期間Ｔ２ｕおよび第２オン固定期間Ｔ２ｗよりも長い。したがって、図４１Ｂに示すように、Ｖ相の第２半導体スイッチング素子Ｖｎ（Ｌ（ロウサイド））のスイッチング損失がＵ相およびＷ相に比べて小さくなっている。 In waveform example 28, the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in waveform example 28, the second fixed ON period T2v is 90 degrees, while the second fixed ON period T2u and the second fixed ON period T2w are 60 degrees. That is, in waveform example 28, the second fixed ON period T2v is longer than the second fixed ON period T2u and the second fixed ON period T2w. Therefore, as shown in FIG. 41B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
　以上、図４１Ａおよび図４１Ｂを参照して説明したように、波形例２８においても、波形例１と同様に、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。波形例２８では、Ｕ相の第１半導体スイッチング素子Ｕｐと、Ｖ相の第２半導体スイッチング素子Ｖｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 41A and 41B , in waveform example 28, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In the waveform example 28, the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
　また、波形例２８では、図４１Ｂに示すように、Ｕ相の第２半導体スイッチング素子Ｕｎと、Ｖ相の第１半導体スイッチング素子Ｖｐと、Ｗ相の第２半導体スイッチング素子Ｗｎとの発熱についても同時に抑えることができる。 In waveform example 28, as shown in FIG. 41B, the heat generated by the U-phase second semiconductor switching element Un, the V-phase first semiconductor switching element Vp, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
　図４２Ａおよび図４２Ｂを参照して、波形例２９について説明する。図４２Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図４２Ｂは、スイッチング損失を示す図である。 A waveform example 29 will be described with reference to FIGS. 42A and 42B. FIG. 42A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 42B is a diagram showing switching losses.
　図４２Ａに示すように、波形例２９は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例２９は、電気角６０度～電気角２１０度および電気角２７０度～電気角３３０度において、いずれか１相の出力が１に固定される波形である。また、波形例２９は、電気角０度～電気角６０度、電気角２１０度～電気角２７０度および電気角３３０度～電気角３６０度において、いずれか１相の出力が０に固定される波形である。波形例２９では、電気角６０度～電気角２１０度および電気角２７０度～電気角３３０度において、ハイサイドオン適用期間Ｔ３である。また、波形例２９では、電気角０度～電気角６０度、電気角２１０度～電気角２７０度および電気角３３０度～電気角３６０度において、ロウサイドオン適用期間Ｔ４である。 As shown in FIG. 42A, in waveform example 29, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. More specifically, waveform example 29 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 210 degrees and at an electrical angle of 270 degrees to 330 degrees. In waveform example 29, the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 electrical degrees, 210 to 270 electrical degrees, and 330 to 360 electrical degrees. waveform. In waveform example 29, the high-side-on application period T3 occurs at an electrical angle of 60 degrees to 210 degrees and at an electrical angle of 270 degrees to 330 degrees. Further, in waveform example 29, the low side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees, 210 to 270 electrical degrees, and 330 to 360 electrical degrees.
　波形例２９では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｕと、第１オン固定期間Ｔ１ｖと、第１オン固定期間Ｔ１ｗとを含む。波形例２９では、電気角６０度～電気角１５０度が第１オン固定期間Ｔ１ｕである。波形例２９では、電気角１５０度～電気角２１０度が第１オン固定期間Ｔ１ｖである。波形例２９では、電気角２７０度～電気角３３０度が第１オン固定期間Ｔ１ｗである。 In Waveform Example 29, the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w. In waveform example 29, the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees. In waveform example 29, the first fixed ON period T1v is between 150 electrical degrees and 210 electrical degrees. In waveform example 29, the first fixed ON period T1w is from 270 electrical degrees to 330 electrical degrees.
　波形例２９では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖとを含む。波形例２９では、電気角２１０度～電気角２７０度が第２オン固定期間Ｔ２ｕである。波形例２９では、電気角０度～電気角６０度および電気角３３０度～電気角３６０度が第２オン固定期間Ｔ２ｖである。 In waveform example 29, the second fixed ON period T2 includes a second fixed ON period T2u and a second fixed ON period T2v. In waveform example 29, the second fixed ON period T2u is from 210 electrical degrees to 270 electrical degrees. In waveform example 29, the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees.
　波形例２９では、３相のうちＵ相において、第１オン固定期間Ｔ１ｕが、第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗと異なる。詳しくは、波形例２９では、第１オン固定期間Ｔ１ｕが９０度であるのに対し、第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗは６０度である。すなわち、波形例２９では、第１オン固定期間Ｔ１ｕが第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗよりも長い。したがって、図４２Ｂに示すように、Ｕ相の第１半導体スイッチング素子Ｕｐ（Ｈ（ハイサイド））のスイッチング損失がＶ相およびＷ相に比べて小さくなっている。 In waveform example 29, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 29, the first fixed ON period T1u is 90 degrees, while the first fixed ON period T1v and the first fixed ON period T1w are 60 degrees. That is, in waveform example 29, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 42B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
　波形例２９では、第２オン固定期間Ｔ２ｖが、第２オン固定期間Ｔ２ｕおよび第２オン固定期間Ｔ２ｗと異なる。詳しくは、波形例２９では、第２オン固定期間Ｔ２ｖが９０度であるのに対し、第２オン固定期間Ｔ２ｕは６０度であり、第２オン固定期間Ｔ２ｗは無い。すなわち、波形例２９では、第２オン固定期間Ｔ２ｖが第２オン固定期間Ｔ２ｕおよび第２オン固定期間Ｔ２ｗよりも長い。したがって、図４２Ｂに示すように、Ｖ相の第２半導体スイッチング素子Ｖｎ（Ｌ（ロウサイド））のスイッチング損失がＵ相およびＷ相に比べて小さくなっている。 In waveform example 29, the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in waveform example 29, the second fixed ON period T2v is 90 degrees, the second fixed ON period T2u is 60 degrees, and there is no second fixed ON period T2w. That is, in waveform example 29, the second fixed ON period T2v is longer than the second fixed ON period T2u and the second fixed ON period T2w. Therefore, as shown in FIG. 42B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
　以上、図４２Ａおよび図４２Ｂを参照して説明したように、波形例２９においても、波形例１と同様に、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。波形例２９では、Ｕ相の第１半導体スイッチング素子Ｕｐと、Ｖ相の第２半導体スイッチング素子Ｖｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 42A and 42B , in waveform example 29, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In the waveform example 29, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn.
　また、波形例２９では、図４２Ｂに示すように、Ｕ相の第２半導体スイッチング素子Ｕｎと、Ｖ相の第１半導体スイッチング素子Ｖｐと、Ｗ相の第１半導体スイッチング素子Ｗｐとの発熱についても同時に抑えることができる。 In waveform example 29, as shown in FIG. 42B, the heat generated by the U-phase second semiconductor switching element Un, the V-phase first semiconductor switching element Vp, and the W-phase first semiconductor switching element Wp can be suppressed at the same time.
　以上、図３Ａ、図３Ｂ、図５Ａ～図１５Ｂおよび図２６Ａ～図４２Ｂを参照して説明した波形例１～波形例２９では、他の相の第１オン固定期間よりも第１オン固定期間が長い相の第１オン固定期間および他の相の第２オン固定期間よりも第２オン固定期間が長い相の第２オン固定期間がともに、π／ｎよりも長く、２π／ｎ以下である。好ましくは、１．５π／ｎ～２π／ｎである。これによって、効果的な発熱の抑制ができる。なお、下限はπ／ｎから僅かにずれていてもよい。また、上限は２π／ｎから僅かにずれていてもよい。例えば、波形例１では、第１オン固定期間Ｔ１ｕが、２π／ｎ（＝１２０度）であり、第２オン固定期間Ｔ２ｕが、２π／ｎ（＝１２０度）である。つまり、波形例１～波形例２９では、他の相の第１オン固定期間よりも第１オン固定期間が長い相の第１オン固定期間および他の相の第２オン固定期間よりも第２オン固定期間が長い相の第２オン固定期間がともに、２π／ｎである。また、他の相の第１オン固定期間よりも第１オン固定期間が長い相の第１オン固定期間と他の相の第２オン固定期間よりも第２オン固定期間が長い相の第２オン固定期間とが互いに連続しない。したがって、冷却水路の問題などで特定の相の温度が問題となる場合、その相の発熱を抑制できるので、インバータの信頼性が高まる。あるいは、ストールが発生してある相の第１半導体スイッチング素子と別の相の第２半導体スイッチング素子に連続的に電流が流れ温度上昇した場合、ストールを脱して動作を開始する際にこの動作を行うことで、ストール下で温度上昇した半導体スイッチング素子の発熱を抑え、速やかに温度を下げることができるので、インバータの信頼性が高まる。 In the waveform examples 1 to 29 described above with reference to FIGS. 3A, 3B, 5A to 15B, and 26A to 42B, the first fixed ON period is longer than the first fixed ON period of the other phases. the first fixed ON period of the phase having a longer ON period and the second fixed ON period of the phase having a longer second fixed ON period than the second fixed ON period of the other phase are both longer than π/n and 2π/n or less be. Preferably, it is 1.5π/n to 2π/n. As a result, heat generation can be effectively suppressed. Note that the lower limit may be slightly deviated from π/n. Also, the upper limit may deviate slightly from 2π/n. For example, in waveform example 1, the first fixed ON period T1u is 2π/n (=120 degrees), and the second fixed ON period T2u is 2π/n (=120 degrees). That is, in waveform examples 1 to 29, the first fixed ON period of the phase is longer than the first fixed ON period of the other phase, and the second fixed period is longer than the second fixed ON period of the other phase. The second fixed ON period of the phase with the longer ON fixed period is both 2π/n. Also, the first fixed ON period of the phase whose first fixed ON period is longer than the first fixed ON period of the other phase and the second fixed ON period of the phase whose second fixed ON period is longer than the second fixed ON period of the other phase ON fixed period is not continuous with each other. Therefore, when the temperature of a specific phase becomes a problem due to a problem in the cooling water passage or the like, the heat generation of that phase can be suppressed, thereby increasing the reliability of the inverter. Alternatively, when a stall occurs and current continuously flows through the first semiconductor switching element of a certain phase and the second semiconductor switching element of another phase and the temperature rises, this operation is performed when exiting the stall and starting operation. By doing so, it is possible to suppress the heat generation of the semiconductor switching elements whose temperature has risen under the stall condition, and to quickly lower the temperature, thereby increasing the reliability of the inverter.
　図２６Ａ～図４２Ｂを参照して説明した波形例１３～波形例２９では、ｎ相のうち２相において、一方の相の第１オン固定期間と他方の相の第２オン固定期間とが互いに連続している。例えば、波形例１３では、３相のうちＵ相およびＶ相において、Ｕ相の第１オン固定期間Ｔ１ｕとＶ相の第２オン固定期間Ｔ２ｖとが互いに連続している。一方の相の第１オン固定期間と他方の相の第２オン固定期間との合計が３π／ｎである。例えば、波形例１３では、Ｕ相の第１オン固定期間Ｔ１ｕが９０度であり、Ｖ相の第２オン固定期間Ｔ２ｖが９０度であるため、第１オン固定期間Ｔ１ｕとＶ相の第２オン固定期間Ｔ２ｖとの合計は、１８０度（３π／ｎ）となる。なお、合計は３π／ｎからわずかにずれていてもよい。また、一方の相の第１オン固定期間および他方の相の第２オン固定期間とはそれぞれ３π／（２ｎ）である。例えば、波形例１３では、Ｕ相の第１オン固定期間Ｔ１ｕおよびＶ相の第２オン固定期間Ｔ２ｖは９０度（３π／（２ｎ））である。したがって、波形例１３～波形例２９では、ストールが発生してある相の第１半導体スイッチング素子と別の相の第２半導体スイッチング素子に連続的に電流が流れ温度上昇した場合、ストールを脱して動作を開始する際にこの動作を行うことで、ストール下で温度上昇した半導体スイッングチ素子の発熱を抑え、速やかに温度を下げることができるので、インバータの信頼性が高まる。 In waveform examples 13 to 29 described with reference to FIGS. 26A to 42B, in two of the n phases, the first fixed ON period of one phase and the second fixed ON period of the other phase are mutually different. Contiguous. For example, in waveform example 13, in the U-phase and the V-phase among the three phases, the U-phase first fixed ON period T1u and the V-phase second fixed ON period T2v are continuous with each other. The sum of the first fixed ON period of one phase and the second fixed ON period of the other phase is 3π/n. For example, in waveform example 13, the first fixed ON period T1u of the U phase is 90 degrees, and the second fixed ON period T2v of the V phase is 90 degrees. The sum with the on-fixed period T2v is 180 degrees (3π/n). Note that the total may deviate slightly from 3π/n. Also, the first fixed ON period of one phase and the second fixed ON period of the other phase are each 3π/(2n). For example, in waveform example 13, the U-phase first fixed ON period T1u and the V-phase second fixed ON period T2v are 90 degrees (3π/(2n)). Therefore, in waveform examples 13 to 29, when a current continuously flows through the first semiconductor switching element of a phase in which a stall occurs and the second semiconductor switching element of another phase and the temperature rises, the stall escapes. By performing this operation when starting the operation, heat generation of the semiconductor switching element whose temperature has risen under the stall can be suppressed, and the temperature can be quickly lowered, so that the reliability of the inverter is improved.
　図４３を参照して、Ｕ相の固定期間およびＶ相の固定期間を変化させた場合のスイッチング損失について説明する。図４３は、スイッチング損失を示す図である。 The switching loss when the U-phase fixed period and the V-phase fixed period are changed will be described with reference to FIG. FIG. 43 is a diagram showing switching loss.
　図４３に示すように、電気角０度～電気角６０度および電気角３３０度～電気角３６０度において、第２オン固定期間を適用し、電気角６０度～電気角１５０度において、第１オン固定期間を適用した場合、第１半導体スイッチング素子Ｕｐ（ＵＨ）のスイッチング損失は０．３２となる。また、第２半導体スイッチング素子Ｖｎ（ＶＬ）のスイッチング損失は０．３２となる。このときハイサイド側の固定期間は、９０度である。 As shown in FIG. 43, the second fixed ON period is applied at an electrical angle of 0 to 60 electrical degrees and from 330 to 360 electrical degrees, and the first fixed period is applied at an electrical angle of 60 to 150 electrical degrees. When the ON fixed period is applied, the switching loss of the first semiconductor switching element Up (UH) is 0.32. Also, the switching loss of the second semiconductor switching element Vn(VL) is 0.32. At this time, the fixed period on the high side is 90 degrees.
　電気角０度～電気角７０度および電気角３３０度～電気角３６０度において、第２オン固定期間を適用し、電気角７０度～電気角１５０度において、第１オン固定期間を適用した場合、第１半導体スイッチング素子Ｕｐ（ＵＨ）のスイッチング損失は０．３９となる。また、第２半導体スイッチング素子Ｖｎ（ＶＬ）のスイッチング損失は０．２５となる。このときハイサイド側の固定期間は、８０度である。 When the second fixed ON period is applied at an electrical angle of 0 to 70 electrical degrees and from 330 to 360 electrical degrees, and the first fixed ON period is applied at an electrical angle of 70 to 150 electrical degrees. , the switching loss of the first semiconductor switching element Up(UH) is 0.39. Also, the switching loss of the second semiconductor switching element Vn(VL) is 0.25. At this time, the fixed period on the high side is 80 degrees.
　電気角０度～電気角８０度および電気角３３０度～電気角３６０度において、第２オン固定期間を適用し、電気角８０度～電気角１５０度において、第１オン固定期間を適用した場合、第１半導体スイッチング素子Ｕｐ（ＵＨ）のスイッチング損失は０．４７となる。また、第２半導体スイッチング素子Ｖｎ（ＶＬ）のスイッチング損失は０．１８となる。このときハイサイド側の固定期間は、７０度である。 When the second fixed ON period is applied at an electrical angle of 0 to 80 electrical degrees and from 330 to 360 electrical degrees, and the first fixed ON period is applied at an electrical angle of 80 to 150 electrical degrees. , the switching loss of the first semiconductor switching element Up (UH) is 0.47. Also, the switching loss of the second semiconductor switching element Vn(VL) is 0.18. At this time, the fixed period on the high side is 70 degrees.
　電気角０度～電気角９０度および電気角３３０度～電気角３６０度において、第２オン固定期間を適用し、電気角９０度～電気角１５０度において、第１オン固定期間を適用した場合、第１半導体スイッチング素子Ｕｐ（ＵＨ）のスイッチング損失は０．５６となる。また、第２半導体スイッチング素子Ｖｎ（ＶＬ）のスイッチング損失は０．１３となる。このときハイサイド側の固定期間は、６０度である。 When the second fixed ON period is applied at an electrical angle of 0 to 90 electrical degrees and from 330 to 360 electrical degrees, and the first fixed ON period is applied at an electrical angle of 90 to 150 electrical degrees. , the switching loss of the first semiconductor switching element Up (UH) is 0.56. Also, the switching loss of the second semiconductor switching element Vn(VL) is 0.13. At this time, the fixed period on the high side is 60 degrees.
　以上、図４３を参照して説明したように、第１オン固定期間Ｔ１ｕおよび第２オン固定期間Ｔ２ｕは、共に、π／３（６０度）よりも長く、２π／３（１２０度）以下であることが好ましい。より好ましくは、７π／１８（７０度）よりも長く、２π／３（１２０度）以下であることが好ましい。 As described above with reference to FIG. 43, both the first fixed ON period T1u and the second fixed ON period T2u are longer than π/3 (60 degrees) and 2π/3 (120 degrees) or less. Preferably. More preferably, it is longer than 7π/18 (70 degrees) and 2π/3 (120 degrees) or less.
　次に、図４４を参照して、ＵＨ＿ＶＬ保護波形の切り替えについてさらに説明する。図４４は、ＵＨ＿ＶＬ保護波形の切り替えを説明するための図である。 Next, switching of the UH_VL protection waveform will be further described with reference to FIG. FIG. 44 is a diagram for explaining switching of the UH_VL protection waveform.
　図４４において、出力電圧の波形およびスイッチング損失は、左から順に、（ｎ）波形例２６（図３９Ａおよび図３９Ｂ）、（ｏ）波形例２７（図４０Ａおよび図４０Ｂ）、（ｄ）波形例１６（図２９Ａおよび図２９Ｂ）に相当する。 In FIG. 44, the waveform of the output voltage and the switching loss are, from the left, (n) waveform example 26 (FIGS. 39A and 39B), (o) waveform example 27 (FIGS. 40A and 40B), (d) waveform example 16 (FIGS. 29A and 29B).
　左の図に示す（ｎ）波形例２６は、第１オン固定期間Ｔ１ｖ、第１オン固定期間Ｔ１ｗ、第２オン固定期間Ｔ２ｕおよび第２オン固定期間Ｔ２ｗを均等にした波形例である。つまり、第１オン固定期間Ｔ１ｕ、第２オン固定期間Ｔ２ｖ以外を均等にした波形例である。 (n) Waveform example 26 shown in the left diagram is a waveform example in which the first fixed ON period T1v, the first fixed ON period T1w, the second fixed ON period T2u, and the second fixed ON period T2w are made equal. In other words, this is an example of waveforms in which periods other than the first fixed ON period T1u and the second fixed ON period T2v are made uniform.
　中央の図に示す（ｏ）波形例２７は、第１オン固定期間Ｔ１ｖおよび第２オン固定期間Ｔ２ｕを延長した波形例である。つまり、Ｕ相およびＶ相を重視した波形例である。 (o) Waveform example 27 shown in the middle diagram is a waveform example in which the first fixed ON period T1v and the second fixed ON period T2u are extended. In other words, this is an example of waveforms in which the U-phase and V-phase are emphasized.
　右の図に示す（ｄ）波形例１６は、第１オン固定期間Ｔ１ｖおよび第２オン固定期間Ｔ２ｕを（ｏ）波形例２７よりさらに延長した波形例である。つまり、Ｕ相およびＶ相を重視した波形例である。 (d) Waveform example 16 shown in the right figure is a waveform example in which the first fixed ON period T1v and the second fixed ON period T2u are further extended from (o) Waveform example 27. In other words, this is an example of waveforms in which the U-phase and V-phase are emphasized.
　右の図に移行するにつれて、第１オン固定期間Ｔ１ｖおよび第２オン固定期間Ｔ２ｕは長くなる。したがって、右の図に移行するにつれて、Ｖ相の第１半導体スイッチング素子Ｖｐ（ハイサイド）およびＵ相の第２半導体スイッチング素子Ｕｎ（ロウサイド）のスイッチング損失が減少する。 The first fixed ON period T1v and the second fixed ON period T2u become longer as the diagram shifts to the right. Therefore, the switching loss of the V-phase first semiconductor switching element Vp (high side) and the U-phase second semiconductor switching element Un (low side) decreases as the diagram shifts to the right.
　次に、図４５を参照して、ＵＨ＿ＶＬ保護波形の切り替えについてさらに説明する。図４５は、ＵＨ＿ＶＬ保護波形の切り替えを説明するための図である。 Next, switching of the UH_VL protection waveform will be further described with reference to FIG. FIG. 45 is a diagram for explaining switching of the UH_VL protection waveform.
　図４５において、出力電圧の波形およびスイッチング損失は、左から順に、（ｎ）波形例２６（図３９Ａおよび図３９Ｂ）、（ｍ）波形例２５（図３８Ａおよび図３８Ｂ）に相当する。 In FIG. 45, the output voltage waveform and switching loss correspond to (n) waveform example 26 (FIGS. 39A and 39B) and (m) waveform example 25 (FIGS. 38A and 38B) in order from the left.
　左の図に示す（ｎ）波形例２６は、第１オン固定期間Ｔ１ｖ、第１オン固定期間Ｔ１ｗ、第２オン固定期間Ｔ２ｕおよび第２オン固定期間Ｔ２ｗを均等にした波形例である。つまり、第１オン固定期間Ｔ１ｕ、第２オン固定期間Ｔ２ｖ以外を均等にした波形例である。 (n) Waveform example 26 shown in the left diagram is a waveform example in which the first fixed ON period T1v, the first fixed ON period T1w, the second fixed ON period T2u, and the second fixed ON period T2w are made equal. In other words, this is an example of waveforms in which periods other than the first fixed ON period T1u and the second fixed ON period T2v are made uniform.
　右の図に示す（ｍ）波形例２５は、第１オン固定期間Ｔ１ｗおよび第２オン固定期間Ｔ２ｗを延長した波形例である。つまり、Ｗ相を重視した波形例である。 (m) Waveform example 25 shown in the right figure is a waveform example in which the first fixed ON period T1w and the second fixed ON period T2w are extended. That is, it is an example of a waveform in which the W phase is emphasized.
　右の図に移行するにつれて、第１オン固定期間Ｔ１ｗおよび第２オン固定期間Ｔ２ｗは長くなる。したがって、右の図に移行するにつれて、Ｗ相の第１半導体スイッチング素子Ｗｐ（ハイサイド）およびＷ相の第２半導体スイッチング素子Ｗｎ（ロウサイド）のスイッチング損失が減少する。 The first fixed ON period T1w and the second fixed ON period T2w become longer as the diagram shifts to the right. Therefore, the switching loss of the W-phase first semiconductor switching element Wp (high side) and the W-phase second semiconductor switching element Wn (low side) decreases as the drawing shifts to the right side.
　次に、図４６を参照して、ＵＨ＿ＶＬ保護波形の切り替えについてさらに説明する。図４６は、ＵＨ＿ＶＬ保護波形の切り替えを説明するための図である。 Next, switching of the UH_VL protection waveform will be further described with reference to FIG. FIG. 46 is a diagram for explaining switching of the UH_VL protection waveform.
　図４６において、出力電圧の波形およびスイッチング損失は、左から順に、（ｇ）波形例１９（図３２Ａおよび図３２Ｂ）、（ｎ）波形例２６（図３９Ａおよび図３９Ｂ）、（ａ）波形例１３（図２６Ａおよび図２６Ｂ）に相当する。 In FIG. 46, the waveform of the output voltage and the switching loss are, from the left, (g) waveform example 19 (FIGS. 32A and 32B), (n) waveform example 26 (FIGS. 39A and 39B), (a) waveform example 13 (FIGS. 26A and 26B).
　左の図に示す（ｇ）波形例１９は、（ｎ）波形例２６の第２オン固定期間Ｔ２ｕおよび第２オン固定期間Ｔ２ｗを減らし、第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗを増やした波形例である。つまり、ハイサイドを重視した波形例である。 In (g) waveform example 19 shown in the left diagram, the second fixed on period T2u and the second fixed on period T2w of (n) waveform example 26 are reduced, and the first fixed on period T1v and the first fixed on period T1w are reduced. It is an example of increased waveforms. That is, it is an example of a waveform that emphasizes the high side.
　中央の図に示す（ｎ）波形例２６は、第１オン固定期間Ｔ１ｖ、第１オン固定期間Ｔ１ｗ、第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗを均等にした波形例である。つまり、第１オン固定期間Ｔ１ｕ、第１オン固定期間Ｔ１ｕ以外を均等にした波形例である。 (n) Waveform example 26 shown in the middle diagram is a waveform example in which the first fixed ON period T1v, the first fixed ON period T1w, the second fixed ON period T2v, and the second fixed ON period T2w are equalized. That is, it is a waveform example in which the first fixed ON period T1u and the period other than the first fixed ON period T1u are made uniform.
　右の図に示す（ａ）波形例１３は、（ｎ）波形例２６の第１オン固定期間Ｔ１ｕおよび第１オン固定期間Ｔ１ｗを減らし、第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗを増やした波形例である。つまり、ロウサイドを重視した波形例である。 In (a) waveform example 13 shown in the right diagram, the first fixed ON period T1u and first fixed ON period T1w of (n) waveform example 26 are reduced, and the second fixed ON period T2v and second fixed ON period T2w are reduced. It is an example of increased waveforms. That is, it is an example of a waveform that emphasizes the low side.
　図４７から図４９を参照して図２１に示したステップＳ１８６の詳細な処理について説明する。すなわち、Ｘ相上段とＹ相下段の温度上昇を抑制するようなパターンで変調する場合の処理について説明する。図４７は、保護波形の切替方法を示すフローチャートである。図４８および図４９は、保護波形の切替方法を示す図である。なお、図４７～図４９は、Ｘ相の例としてＵ相を、Ｙ相の例としてＶ相を用いた場合の保護波形の切替方法を示している。 The detailed processing of step S186 shown in FIG. 21 will be described with reference to FIGS. 47 to 49. FIG. In other words, the process of modulating in a pattern that suppresses the temperature rise of the X-phase upper stage and the Y-phase lower stage will be described. FIG. 47 is a flow chart showing a protection waveform switching method. 48 and 49 are diagrams showing a method of switching guard waveforms. 47 to 49 show the switching method of the protection waveform when the U phase is used as an example of the X phase and the V phase is used as an example of the Y phase.
　ステップＳ５０２：信号生成部１２０は、温度Ｔ＿３～Ｔ＿６が閾値Ｔ＿Ｔｈｒ５以下であるか否かを判定する。温度Ｔ＿３～Ｔ＿６が閾値Ｔ＿Ｔｈｒ５以下でないと、信号生成部１２０が判定した場合（ステップＳ５０２：Ｎｏ）、処理はステップＳ５０６に進む。温度Ｔ＿３～Ｔ＿６が閾値Ｔ＿Ｔｈｒ５以下であると、信号生成部１２０が判定した場合（ステップＳ５０２：Ｙｅｓ）、処理はステップＳ５０４に進む。 Step S502: The signal generator 120 determines whether the temperatures T_3 to T_6 are equal to or lower than the threshold T_Thr5. When the signal generator 120 determines that the temperatures T_3 to T_6 are not equal to or lower than the threshold value T_Thr5 (step S502: No), the process proceeds to step S506. When the signal generator 120 determines that the temperatures T_3 to T_6 are equal to or lower than the threshold value T_Thr5 (step S502: Yes), the process proceeds to step S504.
　ステップＳ５０４：信号生成部１２０は、４つ保護パターンで変調を行う。詳しくは、信号生成部１２０は、（ｉ）波形例２１で変調を行う。処理は終了する。 Step S504: The signal generator 120 modulates with four protection patterns. Specifically, the signal generator 120 performs modulation with (i) waveform example 21 . Processing ends.
　ステップＳ５０６：信号生成部１２０は、温度Ｔ＿５～Ｔ＿６が閾値Ｔ＿Ｔｈｒ６以下であるか否かを判定する。温度Ｔ＿５～Ｔ＿６が閾値Ｔ＿Ｔｈｒ６以下でないと、信号生成部１２０が判定した場合（ステップＳ５０６：Ｎｏ）、処理はステップＳ５１０に進む。温度Ｔ＿５～Ｔ＿６が閾値Ｔ＿Ｔｈｒ６以下であると、信号生成部１２０が判定した場合（ステップＳ５０６：Ｙｅｓ）、処理はステップＳ５０８に進む。 Step S506: The signal generator 120 determines whether the temperatures T_5 to T_6 are equal to or lower than the threshold T_Thr6. When the signal generator 120 determines that the temperatures T_5 to T_6 are not equal to or lower than the threshold value T_Thr6 (step S506: No), the process proceeds to step S510. When the signal generator 120 determines that the temperatures T_5 to T_6 are equal to or lower than the threshold T_Thr6 (step S506: Yes), the process proceeds to step S508.
　ステップＳ５０８：信号生成部１２０は、３つ保護パターンと４つ保護パターンとの中間で変調を行う。３つ保護パターンと４つ保護パターンとの中間で変調については、図４８を参照して後述する。処理は終了する。 Step S508: The signal generator 120 modulates between the three protection patterns and the four protection patterns. Modulation in between the 3 guard pattern and the 4 guard pattern is described below with reference to FIG. Processing ends.
　ステップＳ５１０：信号生成部１２０は、温度Ｔ＿３～Ｔ＿５が閾値Ｔ＿Ｔｈｒ７以下であるか否かを判定する。温度Ｔ＿３～Ｔ＿５が閾値Ｔ＿Ｔｈｒ７以下でないと、信号生成部１２０が判定した場合（ステップＳ５１０：Ｎｏ）、処理はステップＳ５１４に進む。温度Ｔ＿３～Ｔ＿５が閾値Ｔ＿Ｔｈｒ７以下であると、信号生成部１２０が判定した場合（ステップＳ５１０：Ｙｅｓ）、処理はステップＳ５１２に進む。 Step S510: The signal generator 120 determines whether the temperatures T_3 to T_5 are equal to or lower than the threshold T_Thr7. When the signal generator 120 determines that the temperatures T_3 to T_5 are not equal to or lower than the threshold value T_Thr7 (step S510: No), the process proceeds to step S514. When the signal generator 120 determines that the temperatures T_3 to T_5 are equal to or lower than the threshold T_Thr7 (step S510: Yes), the process proceeds to step S512.
　ステップＳ５１２：信号生成部１２０は、３つ保護パターンで変調を行う。詳しくは、信号生成部１２０は、（ｉ）波形例２１、（ｋ）波形例２３、（ｐ）波形例２８、（ｑ）波形例２９のうち、温度がＴ＿３、Ｔ＿４、Ｔ＿５となるアーム（半導体スイッチング素子）を保護できるパターンで変調を行う。処理は終了する。 Step S512: The signal generator 120 modulates with three protection patterns. Specifically, the signal generation unit 120 selects the arms (i) waveform example 21, (k) waveform example 23, (p) waveform example 28, and (q) waveform example 29 whose temperatures are T_3, T_4, and T_5. (Semiconductor switching elements) are modulated with a pattern that can protect them. Processing ends.
　ステップＳ５１４：信号生成部１２０は、温度Ｔ＿４～Ｔ＿５が閾値Ｔ＿Ｔｈｒ８以下であるか否かを判定する。温度Ｔ＿４～Ｔ＿５が閾値Ｔ＿Ｔｈｒ８以下でないと、信号生成部１２０が判定した場合（ステップＳ５１４：Ｎｏ）、処理はステップＳ５１８に進む。温度Ｔ＿４～Ｔ＿５が閾値Ｔ＿Ｔｈｒ８以下であると、信号生成部１２０が判定した場合（ステップＳ５１４：Ｙｅｓ）、処理はステップＳ５１６に進む。 Step S514: The signal generator 120 determines whether the temperatures T_4 to T_5 are equal to or lower than the threshold T_Thr8. When the signal generator 120 determines that the temperatures T_4 to T_5 are not equal to or lower than the threshold T_Thr8 (step S514: No), the process proceeds to step S518. When the signal generator 120 determines that the temperatures T_4 to T_5 are equal to or lower than the threshold T_Thr8 (step S514: Yes), the process proceeds to step S516.
　ステップＳ５１６：信号生成部１２０は、２つ保護パターンと３つ保護パターンとの中間で変調を行う。２つ保護パターンと３つ保護パターンとの中間で変調については、図４９を参照して後述する。処理は終了する。 Step S516: The signal generator 120 modulates between the two protection patterns and the three protection patterns. Modulation in between two guard patterns and three guard patterns is described below with reference to FIG. Processing ends.
　ステップＳ５１８：信号生成部１２０は、２つ保護パターンで変調を行う。詳しくは、信号生成部１２０は、（ａ）波形例１３、（ｃ）波形例１５、（ｅ）波形例１７、（ｇ）波形例１９、（ｉ）波形例２１および（ｐ）波形例２８のうち、温度がＴ＿３、Ｔ＿４となるアーム（半導体スイッチング素子）を保護できるパターンで変調を行う。処理は終了する。 Step S518: The signal generator 120 modulates with two protection patterns. Specifically, the signal generator 120 generates (a) waveform example 13, (c) waveform example 15, (e) waveform example 17, (g) waveform example 19, (i) waveform example 21, and (p) waveform example 28. Of these, modulation is performed with a pattern that can protect arms (semiconductor switching elements) whose temperatures are T_3 and T_4. Processing ends.
　次に、図４８を参照して図４７に示したステップＳ５０８の詳細な処理について説明する。すなわち、３つ保護パターンと４つ保護パターンとの中間で変調を行う場合の処理について説明する。 Next, the detailed processing of step S508 shown in FIG. 47 will be described with reference to FIG. That is, a description will be given of the processing in the case of performing modulation between the three protection patterns and the four protection patterns.
　信号生成部１２０は、ＵＨ（第１半導体スイッチング素子Ｕｐ）およびＶＬ（第２半導体スイッチング素子Ｖｎ）を除いて温度の高い上位３アーム（半導体スイッチング素子）の位置を判定する。以下、図４８の説明において、「ＵＨ（第１半導体スイッチング素子Ｕｐ）およびＵＬ（第２半導体スイッチング素子Ｕｎ）を除いて温度の高い上位３アーム（半導体スイッチング素子）」を、単に「上位３アーム」と記載することがある。なお、上位３アームの温度の順番は問わない。例えば、上位３アームの温度の順番が、ＵＬ（第２半導体スイッチング素子Ｕｎ）、ＷＨ（第１半導体スイッチング素子Ｗｐ）およびＷＬ（第２半導体スイッチング素子Ｗｎ）の順でもよいし、ＵＬ（第２半導体スイッチング素子Ｕｎ）、ＷＬ（第２半導体スイッチング素子Ｗｎ）およびＷＨ（第１半導体スイッチング素子Ｗｐ）の順でもよい。以下、同様の記載についても同様に上位３アームの温度の順番は問わない。 The signal generation unit 120 determines the positions of the three arms (semiconductor switching elements) with the highest temperature, excluding UH (first semiconductor switching element Up) and VL (second semiconductor switching element Vn). Hereinafter, in the description of FIG. 48, "upper three arms (semiconductor switching elements) with higher temperatures excluding UH (first semiconductor switching element Up) and UL (second semiconductor switching element Un)" will be simply referred to as "upper three arms ” may be stated. Note that the order of the temperatures of the top three arms does not matter. For example, the order of the temperatures of the upper three arms may be UL (second semiconductor switching element Un), WH (first semiconductor switching element Wp), and WL (second semiconductor switching element Wn), or UL (second semiconductor switching element Wn). The order of semiconductor switching element Un), WL (second semiconductor switching element Wn), and WH (first semiconductor switching element Wp) is also acceptable. In the same description below, the order of the temperatures of the top three arms is similarly irrelevant.
　信号生成部１２０が、最高温の３アームがＵＬ（第２半導体スイッチング素子Ｕｎ）、ＷＨ（第１半導体スイッチング素子Ｗｐ）およびＷＬ（第２半導体スイッチング素子Ｗｎ）であると判定した場合、（ｉ）波形例２１において、１９５度～１９５＋４５×（Ｔ＿Ｔｈｒ６－（Ｔ＿５－Ｔ＿６））／Ｔ＿Ｔｈｒ６度を第１オン固定期間、２７０度～２７０＋１５×（Ｔ＿Ｔｈｒ６－（Ｔ＿５－Ｔ＿６））／Ｔ＿Ｔｈｒ６度を第２オン固定期間に適用したパターンで、信号生成部１２０は変調を行う。 When the signal generation unit 120 determines that the three arms with the highest temperature are UL (second semiconductor switching element Un), WH (first semiconductor switching element Wp), and WL (second semiconductor switching element Wn), (i ) In waveform example 21, 195 degrees to 195 + 45 x (T_Thr6 - (T_5 - T_6)) / T_Thr6 degrees is the first ON fixed period, 270 degrees to 270 + 15 x (T_Thr6 - (T_5 - T_6)) / T_Thr6 degrees is the second The signal generating section 120 performs modulation with the pattern applied to the ON-fixed period.
　信号生成部１２０が、最高温の３アームがＶＨ（第１半導体スイッチング素子Ｖｐ）、ＷＨ（第１半導体スイッチング素子Ｗｐ）およびＷＬ（第２半導体スイッチング素子Ｗｎ）であると判定した場合、（ｋ）波形例２３において、１９５度～１９５＋１５×（Ｔ＿Ｔｈｒ６－（Ｔ＿５－Ｔ＿６））／Ｔ＿Ｔｈｒ６度を第１オン固定期間、２４０度～２４０＋４５×（Ｔ＿Ｔｈｒ６－（Ｔ＿５－Ｔ＿６））／Ｔ＿Ｔｈｒ６度を第２オン固定期間に適用したパターンで、信号生成部１２０は変調を行う。 When signal generation unit 120 determines that the three arms with the highest temperature are VH (first semiconductor switching element Vp), WH (first semiconductor switching element Wp), and WL (second semiconductor switching element Wn), (k ) In waveform example 23, 195 degrees to 195 + 15 x (T_Thr6-(T_5-T_6))/T_Thr6 degrees is the first ON fixed period, and 240 degrees to 240 + 45 x (T_Thr6-(T_5-T_6))/T_Thr6 degrees is the second The signal generating section 120 performs modulation with the pattern applied to the ON-fixed period.
　信号生成部１２０が、最高温の３アームがＵＬ（第２半導体スイッチング素子Ｕｎ）、ＶＨ（第１半導体スイッチング素子Ｖｐ）およびＷＬ（第２半導体スイッチング素子Ｗｎ）であると判定した場合、（ｐ）波形例２８において、１９５度～１９５＋１５×（Ｔ＿Ｔｈｒ６－（Ｔ＿５－Ｔ＿６））／Ｔ＿Ｔｈｒ６度を第１オン固定期間、２４０度～２４０＋４５×（Ｔ＿Ｔｈｒ６－（Ｔ＿５－Ｔ＿６））／Ｔ＿Ｔｈｒ６を第２オン固定期間、２８５度～２８５＋４５×（Ｔ＿Ｔｈｒ６－（Ｔ＿５－Ｔ＿６））／Ｔ＿Ｔｈｒ６度を第１オン固定期間に適用したパターンで、信号生成部１２０は変調を行う。 When signal generation unit 120 determines that the three arms with the highest temperature are UL (second semiconductor switching element Un), VH (first semiconductor switching element Vp), and WL (second semiconductor switching element Wn), (p ) In waveform example 28, 195 degrees to 195 + 15 x (T_Thr6 - (T_5 - T_6))/T_Thr6 degrees is the first ON fixed period, and 240 degrees to 240 + 45 x (T_Thr6 - (T_5 - T_6))/T_Thr6 is the second ON period. The signal generation unit 120 performs modulation with a pattern in which 285 degrees to 285+45×(T_Thr6-(T_5-T_6))/T_Thr6 degrees is applied to the first ON fixed period.
　信号生成部１２０が、最高温の３アームがＵＬ（第２半導体スイッチング素子Ｕｎ）、ＶＨ（第１半導体スイッチング素子Ｖｐ）およびＷＨ（第１半導体スイッチング素子Ｗｐ）であると判定した場合、（ｑ）波形例２９において、１５０度～１５０＋４５×（Ｔ＿Ｔｈｒ６－（Ｔ＿５－Ｔ＿６））／Ｔ＿Ｔｈｒ６度を第２オン固定期間、２１０度～２１０＋３０×（Ｔ＿Ｔｈｒ６－（Ｔ＿５－Ｔ＿６））／Ｔ＿Ｔｈｒ６を第１オン固定期間、２７０度～２７０＋１５×（Ｔ＿Ｔｈｒ６－（Ｔ＿５－Ｔ＿６））／Ｔ＿Ｔｈｒ６度を第２オン固定期間に適用したパターンで、信号生成部１２０は変調を行う。 When signal generation unit 120 determines that the three arms with the highest temperature are UL (second semiconductor switching element Un), VH (first semiconductor switching element Vp), and WH (first semiconductor switching element Wp), (q ) In waveform example 29, 150 degrees to 150 + 45 x (T_Thr6 - (T_5 - T_6)) / T_Thr6 is the second ON fixed period, 210 degrees to 210 + 30 x (T_Thr6 - (T_5 - T_6)) / T_Thr6 is the first ON The signal generation unit 120 performs modulation with a pattern in which 270 degrees to 270+15×(T_Thr6-(T_5-T_6))/T_Thr6 degrees is applied to the second ON fixed period.
　次に、図４９を参照して図４７に示したステップＳ５１６の詳細な処理について説明する。すなわち、２つ保護パターンと３つ保護パターンとの中間で変調を行う場合の処理について説明する。 Next, the detailed processing of step S516 shown in FIG. 47 will be described with reference to FIG. In other words, a description will be given of processing in the case of performing modulation between the two protection patterns and the three protection patterns.
　図４９に示すように、最高温の２アームの位置、および両者の優先度が、ＵＬ＞ＷＬの場合であって、温度がＴ＿５となるアームがＶＨの場合、処理１を行う。処理１では、（ａ）波形例１３において、２１０度～２１０＋６０×（Ｔ＿Ｔｈｒ８－（Ｔ＿４－Ｔ＿５））／Ｔ＿Ｔｈｒ８度を第１オン固定期間に適用したパターンで、信号生成部１２０は変調を行う。 As shown in FIG. 49, when the positions of the two arms with the highest temperature and the priority of both are UL>WL and the arm with temperature T_5 is VH, process 1 is performed. In process 1, the signal generator 120 performs modulation with a pattern obtained by applying 210 degrees to 210+60×(T_Thr8-(T_4-T_5))/T_Thr8 degrees in (a) waveform example 13 to the first ON fixed period.
　最高温の２アームの位置、および両者の優先度が、ＵＬ＞ＷＬの場合であって、温度がＴ＿５となるアームがＷＨの場合、処理１を行う。処理１では、（ａ）波形例１３において、２７０度～２７０＋６０×（Ｔ＿Ｔｈｒ８－（Ｔ＿４－Ｔ＿５））／Ｔ＿Ｔｈｒ８度を第１オン固定期間に適用したパターンで、信号生成部１２０は変調を行う。 When the position of the two arms with the highest temperature and the priority of both are UL>WL and the arm with the temperature of T_5 is WH, process 1 is performed. In process 1, the signal generator 120 performs modulation with a pattern obtained by applying 270 degrees to 270+60×(T_Thr8-(T_4-T_5))/T_Thr8 degrees in (a) waveform example 13 to the first ON fixed period.
　最高温の２アームの位置、および両者の優先度が、ＵＬ＜ＷＬの場合であって、温度がＴ＿５となるアームがＶＨの場合、処理１を行う。処理１では、（ａ）波形例１３において、２１０度～２１０＋６０×（Ｔ＿Ｔｈｒ８－（Ｔ＿４－Ｔ＿５））／Ｔ＿Ｔｈｒ８度を第１オン固定期間に適用したパターンで、信号生成部１２０は変調を行う。 When the position of the two arms with the highest temperature and the priority of both are UL<WL and the arm with temperature T_5 is VH, process 1 is performed. In process 1, the signal generator 120 performs modulation with a pattern obtained by applying 210 degrees to 210+60×(T_Thr8-(T_4-T_5))/T_Thr8 degrees in (a) waveform example 13 to the first ON fixed period.
　最高温の２アームの位置、および両者の優先度が、ＵＬ＜ＷＬの場合であって、温度がＴ＿５となるアームがＷＨの場合、処理２を行う。処理２では、（ａ）波形例１３において、２７０度～２７０＋６０×（Ｔ＿Ｔｈｒ８－（Ｔ＿４－Ｔ＿５））／Ｔ＿Ｔｈｒ８度を第１オン固定期間に適用したパターンで、信号生成部１２０は変調を行う。 If the position of the two arms with the highest temperature and the priority of both are UL<WL and the arm with temperature T_5 is WH, process 2 is performed. In process 2, the signal generator 120 performs modulation with a pattern obtained by applying 270 degrees to 270+60×(T_Thr8−(T_4−T_5))/T_Thr8 degrees in (a) waveform example 13 to the first ON fixed period.
　最高温の２アームの位置、および両者の優先度が、ＵＬ＞ＷＨの場合であって、温度がＴ＿５となるアームがＶＨの場合、処理３を行う。処理３では、（ａ）波形例１３において、１５０度～１５０＋６０×（Ｔ＿Ｔｈｒ８－（Ｔ＿４－Ｔ＿５））／Ｔ＿Ｔｈｒ８度、２７０度～２７０＋６０×（Ｔ＿Ｔｈｒ８－（Ｔ＿４－Ｔ＿５））／Ｔ＿Ｔｈｒ８度を第１オン固定期間に適用したパターンで、信号生成部１２０は変調を行う。 When the position of the two arms with the highest temperature and the priority of both are UL>WH and the arm with temperature T_5 is VH, process 3 is performed. In process 3, (a) in waveform example 13, 150 degrees to 150 + 60 x (T_Thr8 - (T_4 - T_5)) / T_Thr8 degrees, 270 degrees to 270 + 60 x (T_Thr8 - (T_4 - T_5)) / T_Thr8 degrees are the first The signal generating section 120 performs modulation with the pattern applied to the ON-fixed period.
　最高温の２アームの位置、および両者の優先度が、ＵＬ＞ＷＨの場合であって、温度がＴ＿５となるアームがＶＬの場合、処理２を行う。処理２では、（ａ）波形例１３において、２７０度～２７０＋６０×（Ｔ＿Ｔｈｒ８－（Ｔ＿４－Ｔ＿５））／Ｔ＿Ｔｈｒ８度を第１オン固定期間に適用したパターンで、信号生成部１２０は変調を行う。 When the position of the two arms with the highest temperature and the priority of both are UL>WH and the arm with the temperature of T_5 is VL, process 2 is performed. In process 2, the signal generator 120 performs modulation with a pattern obtained by applying 270 degrees to 270+60×(T_Thr8−(T_4−T_5))/T_Thr8 degrees in (a) waveform example 13 to the first ON fixed period.
　最高温の２アームの位置、および両者の優先度が、ＵＬ＞ＶＨの場合であって、温度がＴ＿５となるアームがＷＨの場合、処理４を行う。処理４では、（ｃ）波形例１５において、２７０度～２７０＋６０×（Ｔ＿Ｔｈｒ８－（Ｔ＿４－Ｔ＿５））／Ｔ＿Ｔｈｒ８度を第１オン固定期間に適用したパターンで、信号生成部１２０は変調を行う。 When the position of the two arms with the highest temperature and the priority of both are UL>VH and the arm with temperature T_5 is WH, process 4 is performed. In process 4, the signal generator 120 modulates with a pattern obtained by applying 270 degrees to 270+60×(T_Thr8-(T_4-T_5))/T_Thr8 degrees in (c) waveform example 15 to the first ON fixed period.
　最高温の２アームの位置、および両者の優先度が、ＵＬ＞ＶＨの場合であって、温度がＴ＿５となるアームがＷＬの場合、処理５を行う。処理５では、（ｃ）波形例１５において、１５０度～１５０＋６０×（Ｔ＿Ｔｈｒ８－（Ｔ＿４－Ｔ＿５））／Ｔ＿Ｔｈｒ８度を第２オン固定期間、２１０度～２１０＋６０×（Ｔ＿Ｔｈｒ８－（Ｔ＿４－Ｔ＿５））／Ｔ＿Ｔｈｒ８度を第１オン固定期間に適用したパターンで、信号生成部１２０は変調を行う。 If the position of the two arms with the highest temperature and the priority of both are UL>VH and the arm with temperature T_5 is WL, process 5 is performed. In process 5, (c) in waveform example 15, 150 degrees to 150+60×(T_Thr8−(T_4−T_5))/T_Thr8 degrees is the second ON fixed period, 210 degrees to 210+60×(T_Thr8−(T_4−T_5)) The signal generator 120 performs modulation with a pattern in which /T_Thr8 is applied to the first fixed ON period.
　最高温の２アームの位置、および両者の優先度が、ＵＬ＜ＶＨの場合であって、温度がＴ＿５となるアームがＷＨの場合、処理６を行う。処理６では、（ｅ）波形例１７において、２１０度～２１０＋６０×（Ｔ＿Ｔｈｒ８－（Ｔ＿４－Ｔ＿５））／Ｔ＿Ｔｈｒ８度を第２オン固定期間、２７０度～２７０＋６０×（Ｔ＿Ｔｈｒ８－（Ｔ＿４－Ｔ＿５））／Ｔ＿Ｔｈｒ８度を第１オン固定期間に適用したパターンで、信号生成部１２０は変調を行う。 If the position of the two arms with the highest temperature and the priority of both are UL<VH, and if the arm whose temperature is T_5 is WH, process 6 is performed. In process 6, (e) in waveform example 17, 210 degrees to 210+60×(T_Thr8−(T_4−T_5))/T_Thr8 degrees is the second ON fixed period, 270 degrees to 270+60×(T_Thr8−(T_4−T_5)) The signal generator 120 performs modulation with a pattern in which /T_Thr8 is applied to the first fixed ON period.
　最高温の２アームの位置、および両者の優先度が、ＵＬ＜ＶＨの場合であって、温度がＴ＿５となるアームがＷＬの場合、処理７を行う。処理７では、（ｅ）波形例１７において、１５０度～１５０＋６０×（Ｔ＿Ｔｈｒ８－（Ｔ＿４－Ｔ＿５））／Ｔ＿Ｔｈｒ８度を第２オン固定期間に適用したパターンで、信号生成部１２０は変調を行う。 When the position of the two arms with the highest temperature and the priority of both are UL<VH, and the arm with the temperature T_5 is WL, process 7 is performed. In process 7, the signal generator 120 modulates with a pattern obtained by applying 150 degrees to 150+60×(T_Thr8-(T_4-T_5))/T_Thr8 degrees in (e) waveform example 17 to the second ON fixed period.
　最高温の２アームの位置、および両者の優先度が、ＶＨ＞ＷＬの場合であって、温度がＴ＿５となるアームがＷＬの場合、処理７を行う。処理７では、（ｅ）波形例１７において、１５０度～１５０＋６０×（Ｔ＿Ｔｈｒ８－（Ｔ＿４－Ｔ＿５））／Ｔ＿Ｔｈｒ８度を第２オン固定期間に適用したパターンで、信号生成部１２０は変調を行う。 When the position of the two arms with the highest temperature and the priority of both are VH>WL, and the arm with the temperature of T_5 is WL, process 7 is performed. In process 7, the signal generator 120 modulates with a pattern obtained by applying 150 degrees to 150+60×(T_Thr8-(T_4-T_5))/T_Thr8 degrees in (e) waveform example 17 to the second ON fixed period.
　最高温の２アームの位置、および両者の優先度が、ＶＨ＞ＷＬの場合であって、温度がＴ＿５となるアームがＷＨの場合、処理８を行う。処理８では、（ｅ）波形例１７において、１５０度～１５０＋６０×（Ｔ＿Ｔｈｒ８－（Ｔ＿４－Ｔ＿５））／Ｔ＿Ｔｈｒ８度を第２オン固定期間、２７０度～２７０＋６０×（Ｔ＿Ｔｈｒ８－（Ｔ＿４－Ｔ＿５））／Ｔ＿Ｔｈｒ８度を第１オン固定期間に適用したパターンで、信号生成部１２０は変調を行う。 If the position of the two arms with the highest temperature and the priority of both are VH>WL, and if the arm whose temperature is T_5 is WH, then process 8 is performed. In process 8, (e) in waveform example 17, 150 degrees to 150+60×(T_Thr8−(T_4−T_5))/T_Thr8 degrees is the second ON fixed period, 270 degrees to 270+60×(T_Thr8−(T_4−T_5)) The signal generator 120 performs modulation with a pattern in which /T_Thr8 is applied to the first fixed ON period.
　最高温の２アームの位置、および両者の優先度が、ＶＨ＞ＷＨの場合であって、温度がＴ＿５となるアームがＵＬの場合、処理９を行う。処理９では、（ｇ）波形例１９において、２１０度～２１０＋６０×（Ｔ＿Ｔｈｒ８－（Ｔ＿４－Ｔ＿５））／Ｔ＿Ｔｈｒ８度を第２オン固定期間に適用したパターンで、信号生成部１２０は変調を行う。 When the position of the two arms with the highest temperature and the priority of both are VH>WH and the arm with the temperature of T_5 is UL, process 9 is performed. In process 9, the signal generator 120 modulates with a pattern obtained by applying 210 degrees to 210+60×(T_Thr8-(T_4-T_5))/T_Thr8 degrees in (g) waveform example 19 to the second ON fixed period.
　最高温の２アームの位置、および両者の優先度が、ＶＨ＞ＷＨの場合であって、温度がＴ＿５となるアームがＷＬの場合、処理１０を行う。処理１０では、（ｇ）波形例１９において、１５０度～１５０＋６０×（Ｔ＿Ｔｈｒ８－（Ｔ＿４－Ｔ＿５））／Ｔ＿Ｔｈｒ８度を第２オン固定期間に適用したパターンで、信号生成部１２０は変調を行う。 When the position of the two arms with the highest temperature and the priority of both are VH>WH and the arm with the temperature of T_5 is WL, process 10 is performed. In process 10, the signal generator 120 modulates with a pattern obtained by applying 150 degrees to 150+60×(T_Thr8−(T_4−T_5))/T_Thr8 degrees in (g) waveform example 19 to the second ON fixed period.
　最高温の２アームの位置、および両者の優先度が、ＶＨ＜ＷＨの場合であって、温度がＴ＿５となるアームがＵＬの場合、処理９を行う。処理９では、（ｇ）波形例１９において、２１０度～２１０＋６０×（Ｔ＿Ｔｈｒ８－（Ｔ＿４－Ｔ＿５））／Ｔ＿Ｔｈｒ８度を第２オン固定期間に適用したパターンで、信号生成部１２０は変調を行う。 If the position of the two arms with the highest temperature and the priority of both are VH<WH, and if the arm whose temperature is T_5 is UL, process 9 is performed. In process 9, the signal generator 120 modulates with a pattern obtained by applying 210 degrees to 210+60×(T_Thr8-(T_4-T_5))/T_Thr8 degrees in (g) waveform example 19 to the second ON fixed period.
　最高温の２アームの位置、および両者の優先度が、ＶＨ＜ＷＨの場合であって、温度がＴ＿５となるアームがＷＬの場合、処理１０を行う。処理１０では、（ｇ）波形例１９において、１５０度～１５０＋６０×（Ｔ＿Ｔｈｒ８－（Ｔ＿４－Ｔ＿５））／Ｔ＿Ｔｈｒ８度を第２オン固定期間に適用したパターンで、信号生成部１２０は変調を行う。 When the position of the two arms with the highest temperature and the priority of both are VH<WH, and the arm with the temperature of T_5 is WL, process 10 is performed. In process 10, the signal generator 120 modulates with a pattern obtained by applying 150 degrees to 150+60×(T_Thr8−(T_4−T_5))/T_Thr8 degrees in (g) waveform example 19 to the second ON fixed period.
　最高温の２アームの位置、および両者の優先度が、ＵＬ＜ＷＨの場合であって、温度がＴ＿５となるアームがＶＨの場合、処理１１を行う。処理１１では、（ｉ）波形例２１において、１５０度～１５０＋６０×（Ｔ＿Ｔｈｒ８－（Ｔ＿４－Ｔ＿５））／Ｔ＿Ｔｈｒ８度を第１オン固定期間に適用したパターンで、信号生成部１２０は変調を行う。 If the position of the two arms with the highest temperature and the priority of both are UL<WH and the arm with temperature T_5 is VH, process 11 is performed. In process 11, (i) in waveform example 21, the signal generator 120 performs modulation with a pattern in which 150 degrees to 150+60×(T_Thr8-(T_4-T_5))/T_Thr8 degrees is applied to the first ON fixed period.
　最高温の２アームの位置、および両者の優先度が、ＵＬ＜ＷＨの場合であって、温度がＴ＿５となるアームがＷＬの場合、処理１２を行う。処理１２では、信号生成部１２０は（ｉ）波形例２１で変調を行う。 If the position of the two arms with the highest temperature and the priority of both are UL<WH and the arm with temperature T_5 is WL, process 12 is performed. In process 12 , the signal generator 120 (i) modulates the waveform example 21 .
　最高温の２アームの位置、および両者の優先度が、ＷＨ＞ＷＬの場合であって、温度がＴ＿５となるアームがＵＬの場合、処理１２を行う。処理１２では、信号生成部１２０は（ｉ）波形例２１で変調を行う。 If the position of the two arms with the highest temperature and the priority of both are WH>WL, and if the arm whose temperature is T_5 is UL, process 12 is performed. In process 12 , the signal generator 120 (i) modulates the waveform example 21 .
　最高温の２アームの位置、および両者の優先度が、ＷＨ＞ＷＬの場合であって、温度がＴ＿５となるアームがＶＨの場合、処理１３を行う。処理１３では、（ｉ）波形例２１において、２１０度～２１０＋６０×（Ｔ＿Ｔｈｒ８－（Ｔ＿４－Ｔ＿５））／Ｔ＿Ｔｈｒ８度を第１オン固定期間に適用したパターンで、信号生成部１２０は変調を行う。 If the position of the two arms with the highest temperature and the priority of both are WH>WL, and if the arm whose temperature is T_5 is VH, process 13 is performed. In process 13, (i) in waveform example 21, the signal generator 120 performs modulation with a pattern in which 210 degrees to 210+60×(T_Thr8-(T_4-T_5))/T_Thr8 degrees is applied to the first ON fixed period.
　最高温の２アームの位置、および両者の優先度が、ＷＨ＜ＷＬの場合であって、温度がＴ＿５となるアームがＵＬの場合、処理１２を行う。処理１２では、信号生成部１２０は（ｉ）波形例２１で変調を行う。 If the position of the two arms with the highest temperature and the priority of both are WH<WL, and if the arm whose temperature is T_5 is UL, process 12 is performed. In process 12 , the signal generator 120 (i) modulates the waveform example 21 .
　最高温の２アームの位置、および両者の優先度が、ＶＨ＜ＷＬの場合であって、温度がＴ＿５となるアームがＵＬの場合、処理１４を行う。処理１４では、信号生成部１２０は（ｐ）波形例２８で変調を行う。 If the position of the two arms with the highest temperature and the priority of both are VH<WL and the arm with temperature T_5 is UL, process 14 is performed. In process 14 , the signal generator 120 performs modulation with (p) waveform example 28 .
　最高温の２アームの位置、および両者の優先度が、ＶＨ＜ＷＬの場合であって、温度がＴ＿５となるアームがＷＨの場合、処理１５を行う。処理１５では、（ｐ）波形例２８において、２７０度～２７０＋６０×（Ｔ＿Ｔｈｒ８－（Ｔ＿４－Ｔ＿５））／Ｔ＿Ｔｈｒ８度を第１オン固定期間に適用したパターンで、信号生成部１２０は変調を行う。 If the position of the two arms with the highest temperature and the priority of both are VH<WL, and if the arm whose temperature is T_5 is WH, process 15 is performed. In process 15, the signal generator 120 performs modulation with a pattern obtained by applying 270 degrees to 270+60×(T_Thr8−(T_4−T_5))/T_Thr8 degrees in (p) waveform example 28 to the first ON fixed period.
　以上、図４７～図４９を参照して説明したように、保護動作モードは、１つの相の第１半導体スイッチング素子と、他の相の第２半導体スイッチング素子とを保護する第２選択保護動作モードを含む。１つの相の第１オン固定期間と他の相の第２オン固定期間とが連続している。第２選択保護動作モードは、１つの相の第１半導体スイッチング素子および他の相の第２半導体スイッチング素子以外の第１半導体スイッチング素子および第２半導体スイッチング素子のうち、ｋ個（ｋは２ｎ－３以下の自然数）の第１半導体スイッチング素子または第２半導体スイッチング素子を保護する、複数のｋ個保護動作モードを含み、温度情報に基づいて、ｋ個保護動作モードの選択を行う。したがって、ストールが発生してある相の第１半導体スイッチと別の相の第２半導体スイッチに連続的に電流が流れ温度上昇した場合、ストールを脱して動作を開始する際にこの動作を行うことで、ある相の第１半導体スイッチと別の相の第２半導体スイッチの昇温を最大限に抑制しながら、他の半導体スイッチング素子も温度状況に応じて必要な半導体スイッチング素子の昇温を抑制することで、インバータの信頼性が高まる。 As described above with reference to FIGS. 47 to 49, the protection operation mode is the second selective protection operation that protects the first semiconductor switching element of one phase and the second semiconductor switching element of another phase. Including mode. The first fixed ON period of one phase and the second fixed ON period of another phase are continuous. In the second selective protection operation mode, k (k is 2n− A natural number of 3 or less) includes a plurality of k protection operation modes for protecting the first semiconductor switching elements or the second semiconductor switching elements, and the k protection operation modes are selected based on the temperature information. Therefore, when a current continuously flows through the first semiconductor switch of a certain phase and the second semiconductor switch of another phase due to a stall and the temperature rises, this operation must be performed when the stall is released and the operation is started. Therefore, while suppressing the temperature rise of the first semiconductor switch of a certain phase and the second semiconductor switch of another phase to the maximum, other semiconductor switching elements also suppress the temperature rise of necessary semiconductor switching elements according to the temperature situation. By doing so, the reliability of the inverter is enhanced.
　以上、図１～図４９を参照して説明したように、モータ駆動回路１００は、ＰＷＭデューティ波形が異なる複数の動作モードを有するとともに、電力変換中に前記複数の動作モードの切り替えを行う機能を有する。複数の動作モードのうち少なくとも１つは、保護動作モードである。動作モードの切り替えにより、必要に応じた最適な動作モードを採用することで、電力変換器（インバータ）の昇温を効率的に抑制し信頼性を高めることができる。 As described above with reference to FIGS. 1 to 49, the motor drive circuit 100 has a plurality of operation modes with different PWM duty waveforms, and has a function of switching between the plurality of operation modes during power conversion. have. At least one of the plurality of operating modes is a protected operating mode. By switching the operation mode and adopting the optimum operation mode according to need, it is possible to efficiently suppress the temperature rise of the power converter (inverter) and improve the reliability.
　保護動作モードは、交流出力の１周期の間に、各相が占める第１オン固定期間および第２オン固定期間のうち少なくとも一方の比率が異なる複数の保護動作パターンを有する。したがって、様々な保護モードに対応することができる。例えば、通常モード（１種類）に加え、各相それぞれを中心的に保護する（複数種類）ことが可能となる。 The protection operation mode has a plurality of protection operation patterns in which the ratio of at least one of the first fixed ON period and the second fixed ON period occupied by each phase differs during one cycle of the AC output. Therefore, various protection modes can be supported. For example, in addition to the normal mode (one type), it is possible to centrally protect each phase (multiple types).
　複数の保護動作モードおよび複数の保護動作パターンの切り替えは、第１半導体スイッチング素子または第２半導体スイッチング素子の少なくとも一方の温度情報に基づいて行う。温度情報は、例えば、各半導体スイッチング素子の６つの温度センサ２０が取得した温度である。なお、温度センサ２０を一部の半導体スイッチング素子の近傍に配置し、温度センサ２０が配置されていない半導体スイッチング素子の温度は演算により推定してもよい。あるいは、環境温度をモニタリングし、モータ駆動回路１００に設置した電流センサおよび電圧センサ（図示略）の値を用いて温度を推定してよい。環境温度は、例えば、気温、基板の温度および冷却水の温度である。冷却水は、モータ駆動回路１００を冷却するための液体である。複数の保護動作モードおよび複数の保護動作パターンの切り替えは、第１半導体スイッチング素子または第２半導体スイッチング素子の少なくとも一方の温度情報に基づいて行うことによって、温度が高くなった半導体スイッチング素子を選択的に発熱抑制して放熱を促進し、電力変換器の信頼性を高めることができる。 A plurality of protection operation modes and a plurality of protection operation patterns are switched based on temperature information of at least one of the first semiconductor switching element and the second semiconductor switching element. The temperature information is, for example, temperatures acquired by the six temperature sensors 20 of each semiconductor switching element. Note that the temperature sensor 20 may be arranged in the vicinity of some of the semiconductor switching elements, and the temperature of the semiconductor switching elements where the temperature sensor 20 is not arranged may be estimated by calculation. Alternatively, the environmental temperature may be monitored and the temperature may be estimated using the values of a current sensor and a voltage sensor (not shown) installed in the motor drive circuit 100 . The ambient temperature is, for example, the ambient temperature, the temperature of the substrate, and the temperature of the cooling water. Cooling water is a liquid for cooling motor drive circuit 100 . Switching between a plurality of protection operation modes and a plurality of protection operation patterns is performed based on temperature information of at least one of the first semiconductor switching element and the second semiconductor switching element, whereby the semiconductor switching element with a high temperature is selectively switched. It is possible to suppress heat generation, promote heat dissipation, and improve the reliability of the power converter.
　また、保護動作モードは、少なくとも４種類の保護動作パターンを有する。したがって、様々な保護モードに対応することができる。例えば、通常モード（１種類）に加え、各相それぞれを中心的に保護する（複数種類）ことが可能となる。 Also, the protection operation mode has at least four types of protection operation patterns. Therefore, various protection modes can be supported. For example, in addition to the normal mode (one type), it is possible to centrally protect each phase (multiple types).
　図５０Ａ～図６６Ｂを参照して、他の波形例について説明する。 Other waveform examples will be described with reference to FIGS. 50A to 66B.
　図５０Ａおよび図５０Ｂを参照して、波形例３０について説明する。図５０Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図５０Ｂは、スイッチング損失を示す図である。 A waveform example 30 will be described with reference to FIGS. 50A and 50B. FIG. 50A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 50B is a diagram showing switching losses.
　図５０Ａに示すように、波形例３０は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例３０は、電気角９０度～電気角２１０度において、いずれか１相の出力が１に固定される波形である。また、波形例３０は、電気角０度～電気角９０度および電気角２１０度～電気角３６０度において、いずれか１相の出力が０に固定される波形である。波形例３０では、電気角９０度～電気角２１０度において、ハイサイドオン適用期間Ｔ３である。また、波形例３０では、電気角０度～電気角９０度および電気角２１０度～電気角３６０度において、ロウサイドオン適用期間Ｔ４である。 As shown in FIG. 50A , in waveform example 30, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, waveform example 30 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 90 degrees to 210 electrical degrees. Waveform example 30 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 to 90 degrees and at an electrical angle of 210 to 360 degrees. In the waveform example 30, the high-side-on application period T3 is at an electrical angle of 90 degrees to 210 electrical degrees. Further, in waveform example 30, the low side-on application period T4 occurs at an electrical angle of 0 to 90 electrical degrees and at an electrical angle of 210 to 360 electrical degrees.
　波形例３０では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｕと、第１オン固定期間Ｔ１ｖとを含む。波形例３０では、電気角９０度～電気角１５０度が第１オン固定期間Ｔ１ｕである。波形例３０では、電気角１５０度～電気角２１０度が第１オン固定期間Ｔ１ｖである。 In waveform example 30, the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v. In waveform example 30, the first fixed ON period T1u is from 90 electrical degrees to 150 electrical degrees. In waveform example 30, the first fixed ON period T1v is between an electrical angle of 150 degrees and an electrical angle of 210 degrees.
　波形例３０では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖとを含む。波形例３０では、電気角２１０度～電気角３３０度が第２オン固定期間Ｔ２ｕである。波形例３０では、電気角０度～電気角９０度および電気角３３０度～電気角３６０度が第２オン固定期間Ｔ２ｖである。 In waveform example 30, the second fixed ON period T2 includes a second fixed ON period T2u and a second fixed ON period T2v. In waveform example 30, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In waveform example 30, the second fixed ON period T2v is from 0 to 90 electrical degrees and from 330 to 360 electrical degrees.
　波形例３０では、３相のうちＵ相において、第１オン固定期間Ｔ１ｕが、第１オン固定期間Ｔ１ｗと異なる。詳しくは、波形例３０では、第１オン固定期間Ｔ１ｕが６０度であるのに対し、第１オン固定期間Ｔ１ｗは無い。すなわち、波形例３０では、第１オン固定期間Ｔ１ｕが第１オン固定期間Ｔ１ｗよりも長い。なお、第１オン固定期間Ｔ１ｖは、第１オン固定期間Ｔ１ｕと同じである。したがって、図５０Ｂに示すように、Ｕ相の第１半導体スイッチング素子Ｕｐ（Ｈ（ハイサイド））のスイッチング損失がＷ相に比べて小さくなっている。 In waveform example 30, the first fixed ON period T1u differs from the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 30, the first fixed ON period T1u is 60 degrees, but there is no first fixed ON period T1w. That is, in waveform example 30, the first fixed ON period T1u is longer than the first fixed ON period T1w. The first fixed ON period T1v is the same as the first fixed ON period T1u. Therefore, as shown in FIG. 50B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than that of the W-phase.
　波形例３０では、第２オン固定期間Ｔ２ｕが、第２オン固定期間Ｔ２ｕおよび第２オン固定期間Ｔ２ｗと異なる。詳しくは、波形例３０では、第２オン固定期間Ｔ２ｕが１２０度であるのに対し、第２オン固定期間Ｔ２ｗは無い。すなわち、波形例３０では、第２オン固定期間Ｔ２ｕが第２オン固定期間Ｔ２ｗよりも長い。なお、第２オン固定期間Ｔ２ｖは、第２オン固定期間Ｔ２ｕと同じである。したがって、図５０Ｂに示すように、Ｕ相の第２半導体スイッチング素子Ｕｎ（Ｌ（ロウサイド））のスイッチング損失がＷ相に比べて小さくなっている。 In waveform example 30, the second fixed ON period T2u is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in waveform example 30, the second fixed ON period T2u is 120 degrees, but there is no second fixed ON period T2w. That is, in waveform example 30, the second fixed ON period T2u is longer than the second fixed ON period T2w. The second fixed ON period T2v is the same as the second fixed ON period T2u. Therefore, as shown in FIG. 50B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than that of the W-phase.
　以上、図５０Ａおよび図５０Ｂを参照して説明したように、波形例３０においても、波形例１と同様に、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。波形例３０では、Ｕ相の第２半導体スイッチング素子Ｕｎと、Ｖ相の第２半導体スイッチング素子Ｖｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 50A and 50B , in waveform example 30, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 30, the heat generation of the U-phase second semiconductor switching element Un and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
　また、波形例３０では、図５０Ｂに示すように、Ｕ相の第１半導体スイッチング素子Ｕｐと、Ｖ相の第１半導体スイッチング素子Ｖｐとの発熱についても同時に抑えることができる。 Further, in the waveform example 30, as shown in FIG. 50B, the heat generation of the U-phase first semiconductor switching element Up and the V-phase first semiconductor switching element Vp can be suppressed at the same time.
　図５１Ａおよび図５１Ｂを参照して、波形例３１について説明する。図５１Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図５１Ｂは、スイッチング損失を示す図である。 A waveform example 31 will be described with reference to FIGS. 51A and 51B. FIG. 51A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 51B is a diagram showing switching loss.
　図５１Ａに示すように、波形例３１は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例３１は、電気角４５度～電気角１３５度および電気角１８０度～電気角２１０度において、いずれか１相の出力が１に固定される波形である。また、波形例３１は、電気角０度～電気角４５度、電気角１３５度～電気角１８０度および電気角２１０度～電気角３６０度において、いずれか１相の出力が０に固定される波形である。波形例３１では、電気角４５度～電気角１３５度および電気角１８０度～電気角２１０度において、ハイサイドオン適用期間Ｔ３である。また、波形例３１では、電気角０度～電気角４５度、電気角１３５度～電気角１８０度および電気角２１０度～電気角３６０度において、ロウサイドオン適用期間Ｔ４である。 As shown in FIG. 51A, in waveform example 31, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, the waveform example 31 is a waveform in which the output of any one phase is fixed to 1 in the electrical angle of 45 degrees to 135 electrical degrees and in the electrical angle of 180 degrees to 210 electrical degrees. In waveform example 31, the output of any one phase is fixed to 0 at an electrical angle of 0 to 45 electrical degrees, 135 to 180 electrical degrees, and 210 to 360 electrical degrees. waveform. In waveform example 31, the high-side-on application period T3 occurs at an electrical angle of 45 degrees to 135 degrees and at an electrical angle of 180 degrees to 210 degrees. Further, in waveform example 31, the low side-on application period T4 occurs at an electrical angle of 0 to 45 electrical degrees, 135 to 180 electrical degrees, and 210 to 360 electrical degrees.
　波形例３１では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｕと、第１オン固定期間Ｔ１ｖとを含む。波形例３１では、電気角４５度～電気角１３５度が第１オン固定期間Ｔ１ｕである。波形例３１では、電気角１８０度～電気角２１０度が第１オン固定期間Ｔ１ｖである。 In waveform example 31, the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v. In waveform example 31, the first fixed ON period T1u is from an electrical angle of 45 degrees to an electrical angle of 135 degrees. In waveform example 31, the first fixed ON period T1v is from 180 degrees to 210 degrees in electrical angle.
　波形例３１では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖと、第２オン固定期間Ｔ２ｗとを含む。波形例３１では、電気角２１０度～電気角３３０度が第２オン固定期間Ｔ２ｕである。波形例３１では、電気角０度～電気角４５度および電気角３３０度～電気角３６０度が第２オン固定期間Ｔ２ｖである。波形例３１では、電気角１３５度～電気角１８０度が第２オン固定期間Ｔ２ｗである。 In waveform example 31, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 31, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In waveform example 31, the second fixed ON period T2v is from an electrical angle of 0 degrees to an electrical angle of 45 degrees and from an electrical angle of 330 degrees to an electrical angle of 360 degrees. In waveform example 31, the second fixed ON period T2w is from 135 electrical degrees to 180 electrical degrees.
　波形例３１では、３相のうちＵ相において、第１オン固定期間Ｔ１ｕが、第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗと異なる。詳しくは、波形例３１では、第１オン固定期間Ｔ１ｕが９０度であるのに対し、第１オン固定期間Ｔ１ｖは、および第１オン固定期間Ｔ１ｗは３０度である。すなわち、波形例３１では、第１オン固定期間Ｔ１ｕが第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗよりも長い。したがって、図５１Ｂに示すように、Ｕ相の第１半導体スイッチング素子Ｕｐ（Ｈ（ハイサイド））のスイッチング損失がＶ相およびＷ相に比べて小さくなっている。 In waveform example 31, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 31, the first fixed ON period T1u is 90 degrees, while the first fixed ON period T1v and the first fixed ON period T1w are 30 degrees. That is, in waveform example 31, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 51B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
　波形例３１では、第２オン固定期間Ｔ２ｕが、第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗと異なる。詳しくは、波形例３１では、第２オン固定期間Ｔ２ｕが１２０度であるのに対し、第２オン固定期間Ｔ２ｖは７５度であり、第２オン固定期間Ｔ２ｗは４５度である。すなわち、波形例３１では、第２オン固定期間Ｔ２ｕが第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗよりも長い。したがって、図５１Ｂに示すように、Ｕ相の第２半導体スイッチング素子Ｕｎ（Ｌ（ロウサイド））のスイッチング損失がＶ相およびＷ相に比べて小さくなっている。 In waveform example 31, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in waveform example 31, the second fixed ON period T2u is 120 degrees, the second fixed ON period T2v is 75 degrees, and the second fixed ON period T2w is 45 degrees. That is, in waveform example 31, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 51B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
　以上、図５１Ａおよび図５１Ｂを参照して説明したように、波形例３１においても、波形例１と同様に、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。波形例３１では、Ｕ相の第１半導体スイッチング素子Ｕｐと、Ｕ相の第２半導体スイッチング素子Ｕｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 51A and 51B , in Waveform Example 31, as in Waveform Example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 31, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un.
　また、波形例３１では、図５１Ｂに示すように、Ｖ相の第１半導体スイッチング素子Ｖｐと、Ｖ相の第２半導体スイッチング素子Ｖｎと、Ｗ相の第２半導体スイッチング素子Ｗｎとの発熱についても同時に抑えることができる。 Further, in waveform example 31, as shown in FIG. 51B, the heat generated by the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
　図５２Ａおよび図５２Ｂを参照して、波形例３２について説明する。図５２Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図５２Ｂは、スイッチング損失を示す図である。 A waveform example 32 will be described with reference to FIGS. 52A and 52B. FIG. 52A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 52B is a diagram showing switching losses.
　図５２Ａに示すように、波形例３２は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例３２は、電気角６０度～電気角１２０度および電気角１５０度～電気角２１０度において、いずれか１相の出力が１に固定される波形である。また、波形例３２は、電気角０度～電気角６０度、電気角１２０度～電気角１５０度および電気角２１０度～電気角３６０度において、いずれか１相の出力が０に固定される波形である。波形例３２では、電気角６０度～電気角１２０度および電気角１５０度～電気角２１０度において、ハイサイドオン適用期間Ｔ３である。また、波形例３２では、電気角０度～電気角６０度、電気角１２０度～電気角１５０度および電気角２１０度～電気角３６０度において、ロウサイドオン適用期間Ｔ４である。 As shown in FIG. 52A, in waveform example 32, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. More specifically, waveform example 32 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 120 degrees and at an electrical angle of 150 degrees to 210 degrees. In waveform example 32, the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 electrical degrees, 120 to 150 electrical degrees, and 210 to 360 electrical degrees. waveform. In waveform example 32, the high-side-on application period T3 occurs at an electrical angle of 60 degrees to 120 degrees and at an electrical angle of 150 degrees to 210 degrees. Further, in waveform example 32, the low side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees, 120 to 150 electrical degrees, and 210 to 360 electrical degrees.
　波形例３２では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｕと、第１オン固定期間Ｔ１ｖとを含む。波形例３２では、電気角６０度～電気角１２０度が第１オン固定期間Ｔ１ｕである。波形例３２では、電気角１５０度～電気角２１０度が第１オン固定期間Ｔ１ｖである。 In waveform example 32, the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v. In waveform example 32, the first fixed ON period T1u is from 60 electrical degrees to 120 electrical degrees. In waveform example 32, the first fixed ON period T1v is between 150 electrical degrees and 210 electrical degrees.
　波形例３２では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖと、第２オン固定期間Ｔ２ｗとを含む。波形例３２では、電気角２１０度～電気角３３０度が第２オン固定期間Ｔ２ｕである。波形例３２では、電気角０度～電気角６０度および電気角３３０度～電気角３６０度が第２オン固定期間Ｔ２ｖである。波形例３２では、電気角１２０度～電気角１５０度が第２オン固定期間Ｔ２ｗである。 In waveform example 32, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 32, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In waveform example 32, the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees. In waveform example 32, the second fixed ON period T2w is between 120 electrical degrees and 150 electrical degrees.
　波形例３２では、３相のうちＵ相において、第１オン固定期間Ｔ１ｕが、第１オン固定期間Ｔ１ｗと異なる。詳しくは、波形例３２では、第１オン固定期間Ｔ１ｕが６０度であるのに対し、第１オン固定期間Ｔ１ｗは無い。すなわち、波形例３２では、第１オン固定期間Ｔ１ｕが第１オン固定期間Ｔ１ｗよりも長い。なお、第１オン固定期間Ｔ１ｖは、第１オン固定期間Ｔ１ｕと同じである。したがって、図５２Ｂに示すように、Ｕ相の第１半導体スイッチング素子Ｕｐ（Ｈ（ハイサイド））のスイッチング損失がＷ相に比べて小さくなっている。 In waveform example 32, the first fixed ON period T1u differs from the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 32, the first fixed ON period T1u is 60 degrees, but there is no first fixed ON period T1w. That is, in waveform example 32, the first fixed ON period T1u is longer than the first fixed ON period T1w. The first fixed ON period T1v is the same as the first fixed ON period T1u. Therefore, as shown in FIG. 52B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than that of the W-phase.
　波形例３２では、第２オン固定期間Ｔ２ｕが、第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗと異なる。詳しくは、波形例３２では、第２オン固定期間Ｔ２ｕが１２０度であるのに対し、第２オン固定期間Ｔ２ｖは９０度であり、および第２オン固定期間Ｔ２ｗは３０度である。すなわち、波形例３２では、第２オン固定期間Ｔ２ｕが第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗよりも長い。したがって、図５２Ｂに示すように、Ｕ相の第２半導体スイッチング素子Ｕｎ（Ｌ（ロウサイド））のスイッチング損失がＶ相およびＷ相に比べて小さくなっている。 In waveform example 32, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in waveform example 32, the second fixed ON period T2u is 120 degrees, the second fixed ON period T2v is 90 degrees, and the second fixed ON period T2w is 30 degrees. That is, in waveform example 32, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 52B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
　以上、図５２Ａおよび図５２Ｂを参照して説明したように、波形例３２においても、波形例１と同様に、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。波形例３２では、Ｕ相の第１半導体スイッチング素子Ｕｐと、Ｕ相の第２半導体スイッチング素子Ｕｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 52A and 52B , in waveform example 32, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 32, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un.
　また、波形例３２では、図５２Ｂに示すように、Ｖ相の第１半導体スイッチング素子Ｖｐと、Ｖ相の第２半導体スイッチング素子Ｖｎと、Ｗ相の第２半導体スイッチング素子Ｗｎとの発熱についても同時に抑えることができる。 Further, in waveform example 32, as shown in FIG. 52B, the heat generated by the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
　図５３Ａおよび図５３Ｂを参照して、波形例３３について説明する。図５３Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図５３Ｂは、スイッチング損失を示す図である。 A waveform example 33 will be described with reference to FIGS. 53A and 53B. FIG. 53A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 53B is a diagram showing switching losses.
　図５３Ａに示すように、波形例３３は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例３３は、電気角６０度～電気角１２０度、電気角１８０度～電気角２１０度および電気角３３０度～電気角３６０度において、いずれか１相の出力が１に固定される波形である。また、波形例３３は、電気角０度～電気角６０度、電気角１２０度～電気角１８０度および電気角２１０度～電気角３３０度において、いずれか１相の出力が０に固定される波形である。波形例３３では、電気角６０度～電気角１２０度、電気角１８０度～電気角２１０度および電気角３３０度～電気角３６０度において、ハイサイドオン適用期間Ｔ３である。また、波形例３３では、電気角０度～電気角６０度、電気角１２０度～電気角１８０度および電気角２１０度～電気角３３０度において、ロウサイドオン適用期間Ｔ４である。 As shown in FIG. 53A, in waveform example 33, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, in waveform example 33, the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 120 degrees, from 180 degrees to 210 degrees, and from 330 degrees to 360 degrees. waveform. In waveform example 33, the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 electrical degrees, 120 to 180 electrical degrees, and 210 to 330 electrical degrees. waveform. In waveform example 33, the high side-on application period T3 is at an electrical angle of 60 to 120 electrical degrees, 180 to 210 electrical degrees, and 330 to 360 electrical degrees. Further, in waveform example 33, the low side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees, 120 to 180 electrical degrees, and 210 to 330 electrical degrees.
　波形例３３では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｕと、第１オン固定期間Ｔ１ｖと、第１オン固定期間Ｔ１ｗとを含む。波形例３３では、電気角６０度～電気角１２０度が第１オン固定期間Ｔ１ｕである。波形例３３では、電気角１８０度～電気角２１０度が第１オン固定期間Ｔ１ｖである。波形例３３では、電気角３３０度～電気角３６０度が第１オン固定期間Ｔ１ｗである。 In Waveform Example 33, the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w. In waveform example 33, the first fixed ON period T1u is from 60 electrical degrees to 120 electrical degrees. In waveform example 33, the first fixed ON period T1v is from 180 degrees to 210 degrees in electrical angle. In waveform example 33, the first fixed ON period T1w is from 330 electrical degrees to 360 electrical degrees.
　波形例３３では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖと、第２オン固定期間Ｔ２ｗとを含む。波形例３３では、電気角２１０度～電気角３３０度が第２オン固定期間Ｔ２ｕである。波形例３３では、電気角０度～電気角６０度が第２オン固定期間Ｔ２ｖである。波形例３３では、電気角１２０度～電気角１８０度が第２オン固定期間Ｔ２ｗである。 In waveform example 33, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 33, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In waveform example 33, the second fixed ON period T2v is from 0 electrical angle to 60 electrical degrees. In waveform example 33, the second fixed ON period T2w is from 120 electrical degrees to 180 electrical degrees.
　波形例３３では、３相のうちＵ相において、第１オン固定期間Ｔ１ｕが、第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗと異なる。詳しくは、波形例３３では、第１オン固定期間Ｔ１ｕが６０度であるのに対し、第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗは３０度である。すなわち、波形例３３では、第１オン固定期間Ｔ１ｕが第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗよりも長い。したがって、図５３Ｂに示すように、Ｕ相の第１半導体スイッチング素子Ｕｐ（Ｈ（ハイサイド））のスイッチング損失がＶ相およびＷ相に比べて小さくなっている。 In waveform example 33, in the U phase among the three phases, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w. Specifically, in waveform example 33, the first fixed ON period T1u is 60 degrees, while the first fixed ON period T1v and the first fixed ON period T1w are 30 degrees. That is, in waveform example 33, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 53B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
　波形例３３では、第２オン固定期間Ｔ２ｕが、第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗと異なる。詳しくは、波形例３３では、第２オン固定期間Ｔ２ｕが１２０度であるのに対し、第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗは６０度である。すなわち、波形例３３では、第２オン固定期間Ｔ２ｕが第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗよりも長い。したがって、図５３Ｂに示すように、Ｕ相の第２半導体スイッチング素子Ｕｎ（Ｌ（ロウサイド））のスイッチング損失がＶ相およびＷ相に比べて小さくなっている。 In waveform example 33, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in waveform example 33, the second fixed ON period T2u is 120 degrees, while the second fixed ON period T2v and the second fixed ON period T2w are 60 degrees. That is, in waveform example 33, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 53B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
　以上、図５３Ａおよび図５３Ｂを参照して説明したように、波形例３３においても、波形例１と同様に、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。波形例３３では、Ｕ相の第１半導体スイッチング素子Ｕｐと、Ｕ相の第２半導体スイッチング素子Ｕｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 53A and 53B , in waveform example 33, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 33, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un.
　また、波形例３３では、図５３Ｂに示すように、Ｖ相の第１半導体スイッチング素子Ｖｐと、Ｖ相の第２半導体スイッチング素子Ｖｎと、Ｗ相の第１半導体スイッチング素子Ｗｐと、Ｗ相の第２半導体スイッチング素子Ｗｎとの発熱についても同時に抑えることができる。 In waveform example 33, as shown in FIG. 53B, the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
　図５４Ａおよび図５４Ｂを参照して、波形例３４について説明する。図５４Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図５４Ｂは、スイッチング損失を示す図である。 A waveform example 34 will be described with reference to FIGS. 54A and 54B. FIG. 54A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 54B is a diagram showing switching losses.
　図５４Ａに示すように、波形例３４は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例３４は、電気角７５度～電気角１０５度および電気角１５０度～電気角２４０度において、いずれか１相の出力が１に固定される波形である。また、波形例３４は、電気角０度～電気角７５度、電気角１０５度～電気角１５０度および電気角２４０度～電気角３６０度において、いずれか１相の出力が０に固定される波形である。波形例３４では、電気角７５度～電気角１０５度および電気角１５０度～電気角２４０度において、ハイサイドオン適用期間Ｔ３である。また、波形例３４では、電気角１０５度～電気角１５０度および電気角２４０度～電気角３６０度において、ロウサイドオン適用期間Ｔ４である。 As shown in FIG. 54A, in waveform example 34, the output voltage of any one phase is fixed to 1 in a certain electrical angle section, and the output voltage of any one phase is fixed to 1 in another electrical angle section, depending on the electrical angle. is fixed to 0. More specifically, waveform example 34 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 75 degrees to 105 degrees and at an electrical angle of 150 degrees to 240 degrees. In waveform example 34, the output of any one phase is fixed to 0 at an electrical angle of 0 to 75 electrical degrees, 105 to 150 electrical degrees, and 240 to 360 electrical degrees. waveform. In waveform example 34, the high-side-on application period T3 occurs at an electrical angle of 75 degrees to 105 degrees and at an electrical angle of 150 degrees to 240 degrees. Further, in waveform example 34, the low side-on application period T4 occurs at an electrical angle of 105 degrees to 150 degrees and at an electrical angle of 240 degrees to 360 degrees.
　波形例３４では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｕと、第１オン固定期間Ｔ１ｖとを含む。波形例３４では、電気角７５度～電気角１０５度が第１オン固定期間Ｔ１ｕである。波形例３４では、電気角１５０度～電気角２４０度が第１オン固定期間Ｔ１ｖである。 In waveform example 34, the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v. In waveform example 34, the first fixed ON period T1u is from 75 electrical degrees to 105 electrical degrees. In waveform example 34, the first fixed ON period T1v is from 150 electrical degrees to 240 electrical degrees.
　波形例３４では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖと、第２オン固定期間Ｔ２ｗとを含む。波形例３４では、電気角２４０度～電気角３３０度が第２オン固定期間Ｔ２ｕである。波形例３４では、電気角０度～電気角７５度および電気角３３０度～電気角３６０度が第２オン固定期間Ｔ２ｖである。波形例３４では、電気角１０５度～電気角１５０度が第２オン固定期間Ｔ２ｗである。 In waveform example 34, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 34, the second fixed ON period T2u is from 240 electrical degrees to 330 electrical degrees. In waveform example 34, the second fixed ON period T2v is from an electrical angle of 0 degrees to an electrical angle of 75 degrees and from an electrical angle of 330 degrees to an electrical angle of 360 degrees. In waveform example 34, the second fixed ON period T2w is from 105 electrical degrees to 150 electrical degrees.
　波形例３４では、３相のうちＵ相において、第１オン固定期間Ｔ１ｕが、第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗと異なる。詳しくは、波形例３４では、第１オン固定期間Ｔ１ｖが９０度であるのに対し、第１オン固定期間Ｔ１ｕは３０度であり、第１オン固定期間Ｔ１ｗは無い。すなわち、波形例３４では、第１オン固定期間Ｔ１ｖが第１オン固定期間Ｔ１ｕおよび第１オン固定期間Ｔ１ｗよりも長い。したがって、図５４Ｂに示すように、Ｖ相の第１半導体スイッチング素子Ｖｐ（Ｈ（ハイサイド））のスイッチング損失がＵ相およびＷ相に比べて小さくなっている。 In waveform example 34, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 34, the first fixed ON period T1v is 90 degrees, the first fixed ON period T1u is 30 degrees, and there is no first fixed ON period T1w. That is, in waveform example 34, the first fixed ON period T1v is longer than the first fixed ON period T1u and the first fixed ON period T1w. Therefore, as shown in FIG. 54B, the switching loss of the V-phase first semiconductor switching element Vp (H (high side)) is smaller than those of the U-phase and W-phase.
　波形例３４では、第２オン固定期間Ｔ２ｕが、第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗと異なる。詳しくは、波形例３４では、第２オン固定期間Ｔ２ｖが１０５度であるのに対し、第２オン固定期間Ｔ２ｕが９０度あり、第２オン固定期間Ｔ２ｗは４５度である。すなわち、波形例３４では、第２オン固定期間Ｔ２ｖが第２オン固定期間Ｔ２ｕおよび第２オン固定期間Ｔ２ｗよりも長い。したがって、図５４Ｂに示すように、Ｖ相の第２半導体スイッチング素子Ｖｎ（Ｌ（ロウサイド））のスイッチング損失がＵ相、Ｗ相に比べて小さくなっている。 In waveform example 34, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in waveform example 34, the second fixed ON period T2v is 105 degrees, the second fixed ON period T2u is 90 degrees, and the second fixed ON period T2w is 45 degrees. That is, in waveform example 34, the second fixed ON period T2v is longer than the second fixed ON period T2u and the second fixed ON period T2w. Therefore, as shown in FIG. 54B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
　以上、図５４Ａおよび図５４Ｂを参照して説明したように、波形例３４においても、波形例１と同様に、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。波形例３４では、Ｖ相の第１半導体スイッチング素子Ｖｐと、Ｖ相の第２半導体スイッチング素子Ｖｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 54A and 54B , in waveform example 34, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 34, the heat generation of the V-phase first semiconductor switching element Vp and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
　また、波形例３４では、図５４Ｂに示すように、Ｕ相の第１半導体スイッチング素子Ｕｐと、Ｕ相の第２半導体スイッチング素子Ｕｎと、Ｗ相の第２半導体スイッチング素子Ｗｎとの発熱についても同時に抑えることができる。 In waveform example 34, as shown in FIG. 54B, the heat generated by the U-phase first semiconductor switching element Up, the U-phase second semiconductor switching element Un, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
　図５５Ａおよび図５５Ｂを参照して、波形例３５について説明する。図５５Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図５５Ｂは、スイッチング損失を示す図である。 A waveform example 35 will be described with reference to FIGS. 55A and 55B. FIG. 55A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 55B is a diagram showing switching losses.
　図５５Ａに示すように、波形例３５は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例３５は、電気角７５度～電気角１０５度、電気角１５０度～電気角２１０度および電気角３３０度～電気角３６０度において、いずれか１相の出力が１に固定される波形である。また、波形例３５は、電気角０度～電気角７５度、電気角１０５度～電気角１５０度および電気角２１０度～電気角３３０度において、いずれか１相の出力が０に固定される波形である。波形例３５では、電気角７５度～電気角１０５度、電気角１５０度～電気角２１０度および電気角３３０度～電気角３６０度において、ハイサイドオン適用期間Ｔ３である。また、波形例３５では、電気角０度～電気角７５度、電気角１０５度～電気角１５０度および電気角２１０度～電気角３３０度において、ロウサイドオン適用期間Ｔ４である。 As shown in FIG. 55A, in waveform example 35, the output voltage of any one phase is fixed to 1 in a certain electrical angle section, and the output voltage of any one phase is fixed to 1 in another electrical angle section, depending on the electrical angle. is fixed to 0. Specifically, in waveform example 35, the output of any one phase is fixed to 1 at an electrical angle of 75 degrees to 105 degrees, from 150 degrees to 210 degrees, and from 330 degrees to 360 degrees. waveform. In waveform example 35, the output of any one phase is fixed to 0 at an electrical angle of 0 to 75 electrical degrees, 105 to 150 electrical degrees, and 210 to 330 electrical degrees. waveform. In waveform example 35, the high-side-on application period T3 is at an electrical angle of 75 degrees to 105 degrees, an electrical angle of 150 degrees to 210 degrees, and an electrical angle of 330 degrees to 360 degrees. Further, in waveform example 35, the low side-on application period T4 occurs at an electrical angle of 0 to 75 electrical degrees, 105 to 150 electrical degrees, and 210 to 330 electrical degrees.
　波形例３５では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｕと、第１オン固定期間Ｔ１ｖと、第１オン固定期間Ｔ１ｗとを含む。波形例３５では、電気角７５度～電気角１０５度が第１オン固定期間Ｔ１ｕである。波形例３５では、電気角１５０度～電気角２１０度が第１オン固定期間Ｔ１ｖである。波形例３５では、電気角３３０度～電気角３６０度が第１オン固定期間Ｔ１ｗである。 In Waveform Example 35, the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w. In waveform example 35, the first fixed ON period T1u is from 75 electrical degrees to 105 electrical degrees. In waveform example 35, the first fixed ON period T1v is from 150 electrical degrees to 210 electrical degrees. In waveform example 35, the first fixed ON period T1w is from 330 electrical degrees to 360 electrical degrees.
　波形例３５では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖと、第２オン固定期間Ｔ２ｗとを含む。波形例３５では、電気角２１０度～電気角３３０度が第２オン固定期間Ｔ２ｕである。波形例３５では、電気角０度～電気角７５度が第２オン固定期間Ｔ２ｖである。波形例３５では、電気角１０５度～電気角１５０度が第２オン固定期間Ｔ２ｗである。 In Waveform Example 35, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 35, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In waveform example 35, the second fixed ON period T2v is from 0 electrical angle to 75 electrical degrees. In waveform example 35, the second fixed ON period T2w is from 105 electrical degrees to 150 electrical degrees.
　波形例３５では、３相のうちＵ相において、第１オン固定期間Ｔ１ｖが、第１オン固定期間Ｔ１ｕおよび第１オン固定期間Ｔ１ｗと異なる。詳しくは、波形例３５では、第１オン固定期間Ｔ１ｖが６０度であるのに対し、第１オン固定期間Ｔ１ｕおよび第１オン固定期間Ｔ１ｗは３０度である。すなわち、波形例３５では、第１オン固定期間Ｔ１ｖが第１オン固定期間Ｔ１ｕおよび第１オン固定期間Ｔ１ｗよりも長い。したがって、図５５Ｂに示すように、Ｖ相の第１半導体スイッチング素子Ｖｐ（Ｈ（ハイサイド））のスイッチング損失がＵ相およびＷ相に比べて小さくなっている。 In waveform example 35, the first fixed ON period T1v differs from the first fixed ON period T1u and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 35, the first fixed ON period T1v is 60 degrees, while the first fixed ON period T1u and the first fixed ON period T1w are 30 degrees. That is, in waveform example 35, the first fixed ON period T1v is longer than the first fixed ON period T1u and the first fixed ON period T1w. Therefore, as shown in FIG. 55B, the switching loss of the V-phase first semiconductor switching element Vp (H (high side)) is smaller than those of the U-phase and W-phase.
　波形例３５では、第２オン固定期間Ｔ２ｕが、第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗと異なる。詳しくは、波形例３５では、第２オン固定期間Ｔ２ｕが１２０度であるのに対し、第２オン固定期間Ｔ２ｖは７５度であり、第２オン固定期間Ｔ２ｗは４５度である。すなわち、波形例３５では、第２オン固定期間Ｔ２ｕが第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗよりも長い。したがって、図５５Ｂに示すように、Ｕ相の第２半導体スイッチング素子Ｕｎ（Ｌ（ロウサイド））のスイッチング損失がＶ相、Ｗ相に比べて小さくなっている。 In waveform example 35, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in waveform example 35, the second fixed ON period T2u is 120 degrees, the second fixed ON period T2v is 75 degrees, and the second fixed ON period T2w is 45 degrees. That is, in waveform example 35, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 55B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
　以上、図５５Ａおよび図５５Ｂを参照して説明したように、波形例３５においても、波形例１と同様に、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。波形例３５では、Ｖ相の第１半導体スイッチング素子Ｖｐと、Ｕ相の第２半導体スイッチング素子Ｕｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 55A and 55B , in waveform example 35 as well as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In the waveform example 35, the heat generation of the V-phase first semiconductor switching element Vp and the U-phase second semiconductor switching element Un can be suppressed at the same time.
　また、波形例３５では、図５５Ｂに示すように、Ｕ相の第１半導体スイッチング素子Ｕｐと、Ｖ相の第２半導体スイッチング素子Ｖｎと、Ｗ相の第１半導体スイッチング素子Ｗｐと、Ｗ相の第２半導体スイッチング素子Ｗｎとの発熱についても同時に抑えることができる。 In waveform example 35, as shown in FIG. 55B, the U-phase first semiconductor switching element Up, the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
　図５６Ａおよび図５６Ｂを参照して、波形例３６について説明する。図５６Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図５６Ｂは、スイッチング損失を示す図である。 A waveform example 36 will be described with reference to FIGS. 56A and 56B. FIG. 56A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 56B is a diagram showing switching losses.
　図５６Ａに示すように、波形例３６は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例３６は、電気角１５０度～電気角２４０度および電気角３３０度～電気角３６０度において、いずれか１相の出力が１に固定される波形である。また、波形例３６は、電気角０度～電気角１５０度および電気角２４０度～電気角３３０度において、いずれか１相の出力が０に固定される波形である。波形例３６では、電気角１５０度～電気角２４０度および電気角３３０度～電気角３６０度において、ハイサイドオン適用期間Ｔ３である。また、波形例３６では、電気角０度～電気角１５０度および電気角２４０度～電気角３３０度において、ロウサイドオン適用期間Ｔ４である。 As shown in FIG. 56A , in waveform example 36, the output voltage of any one phase is fixed to 1 in a certain electrical angle section, and the output voltage of any one phase is fixed to 1 in another electrical angle section, depending on the electrical angle. is fixed to 0. More specifically, waveform example 36 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 150 degrees to 240 degrees and at an electrical angle of 330 degrees to 360 degrees. Waveform example 36 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 degree to 150 electrical degrees and at an electrical angle of 240 degrees to 330 electrical degrees. In waveform example 36, the high side-on application period T3 occurs at an electrical angle of 150 degrees to 240 degrees and at an electrical angle of 330 degrees to 360 degrees. Further, in waveform example 36, the low side-on application period T4 occurs at an electrical angle of 0 to 150 electrical degrees and at an electrical angle of 240 to 330 electrical degrees.
　波形例３６では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｖと、第１オン固定期間Ｔ１ｗとを含む。波形例３６では、電気角１５０度～電気角２４０度が第１オン固定期間Ｔ１ｖである。波形例３６では、電気角３３０度～電気角３６０度が第１オン固定期間Ｔ１ｗである。 In waveform example 36, the first fixed ON period T1 includes a first fixed ON period T1v and a first fixed ON period T1w. In waveform example 36, the first fixed ON period T1v is from 150 electrical degrees to 240 electrical degrees. In waveform example 36, the first fixed ON period T1w is between 330 electrical degrees and 360 electrical degrees.
　波形例３６では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖと、第２オン固定期間Ｔ２ｗとを含む。波形例３６では、電気角２４０度～電気角３３０度が第２オン固定期間Ｔ２ｕである。波形例３６では、電気角０度～電気角９０度が第２オン固定期間Ｔ２ｖである。波形例３６では、電気角９０度～電気角１５０度が第２オン固定期間Ｔ２ｗである。 In waveform example 36, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 36, the second fixed ON period T2u is from 240 electrical degrees to 330 electrical degrees. In waveform example 36, the second fixed ON period T2v is from 0 electrical angle to 90 electrical degrees. In waveform example 36, the second fixed ON period T2w is from 90 electrical degrees to 150 electrical degrees.
　波形例３６では、３相のうちＶ相において、第１オン固定期間Ｔ１ｖが、第１オン固定期間Ｔ１ｕおよび第１オン固定期間Ｔ１ｗと異なる。詳しくは、波形例３６では、第１オン固定期間Ｔ１ｖが９０度であるのに対し、第１オン固定期間Ｔ１ｕは無く、第１オン固定期間Ｔ１ｗは３０度である。すなわち、波形例３６では、第１オン固定期間Ｔ１ｖが第１オン固定期間Ｔ１ｕおよび第１オン固定期間Ｔ１ｗよりも長い。したがって、図５６Ｂに示すように、Ｖ相の第１半導体スイッチング素子Ｖｐ（Ｈ（ハイサイド））のスイッチング損失がＵ相およびＷ相に比べて小さくなっている。 In waveform example 36, in the V phase among the three phases, the first fixed ON period T1v differs from the first fixed ON period T1u and the first fixed ON period T1w. Specifically, in waveform example 36, the first fixed ON period T1v is 90 degrees, whereas the first fixed ON period T1u is absent and the first fixed ON period T1w is 30 degrees. That is, in waveform example 36, the first fixed ON period T1v is longer than the first fixed ON period T1u and the first fixed ON period T1w. Therefore, as shown in FIG. 56B, the switching loss of the V-phase first semiconductor switching element Vp (H (high side)) is smaller than those of the U-phase and W-phase.
　波形例３６では、第２オン固定期間Ｔ２ｕが、第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗと異なる。詳しくは、波形例３６では、第２オン固定期間Ｔ２ｕが９０度であるのに対し、第２オン固定期間Ｔ２ｗは６０度である。すなわち、波形例３６では、第２オン固定期間Ｔ２ｕが第２オン固定期間Ｔ２ｗよりも長い。なお、第２オン固定期間Ｔ２ｖは、第２オン固定期間Ｔ２ｕと同じである。したがって、図５６Ｂに示すように、Ｕ相の第２半導体スイッチング素子Ｕｎ（Ｌ（ロウサイド））のスイッチング損失がＷ相に比べて小さくなっている。 In waveform example 36, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in waveform example 36, the second fixed ON period T2u is 90 degrees, while the second fixed ON period T2w is 60 degrees. That is, in waveform example 36, the second fixed ON period T2u is longer than the second fixed ON period T2w. The second fixed ON period T2v is the same as the second fixed ON period T2u. Therefore, as shown in FIG. 56B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than that of the W-phase.
　以上、図５６Ａおよび図５６Ｂを参照して説明したように、波形例３６においても、波形例１と同様に、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。波形例３６では、Ｖ相の第１半導体スイッチング素子Ｖｐと、Ｕ相の第２半導体スイッチング素子Ｕｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 56A and 56B , in waveform example 36, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 36, it is possible to simultaneously suppress the heat generation of the V-phase first semiconductor switching element Vp and the U-phase second semiconductor switching element Un.
　また、波形例３６では、図５６Ｂに示すように、Ｖ相の第２半導体スイッチング素子Ｖｎと、Ｗ相の第１半導体スイッチング素子Ｗｐと、Ｗ相の第２半導体スイッチング素子Ｗｎとの発熱についても同時に抑えることができる。 In waveform example 36, as shown in FIG. 56B, the heat generated by the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
　図５７Ａおよび図５７Ｂを参照して、波形例３７について説明する。図５７Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図５７Ｂは、スイッチング損失を示す図である。 A waveform example 37 will be described with reference to FIGS. 57A and 57B. FIG. 57A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 57B is a diagram showing switching losses.
　図５７Ａに示すように、波形例３７は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例３７は、電気角０度～電気角３０度、電気角１５０度～電気２１０度および電気角３３０度～電気３６０度において、いずれか１相の出力が１に固定される波形である。また、波形例３７は、電気角３０度～電気角１５０度および電気角２１０度～電気角３３０度において、いずれか１相の出力が０に固定される波形である。波形例３７では、電気角０度～電気角３０度、電気角１５０度～電気２１０度および電気角３３０度～電気３６０度において、ハイサイドオン適用期間Ｔ３である。また、波形例３７では、電気角３０度～電気角１５０度および電気角２１０度～電気角３３０度において、ロウサイドオン適用期間Ｔ４である。 As shown in FIG. 57A, in waveform example 37, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, waveform example 37 is a waveform in which the output of any one phase is fixed to 1 in the electrical angle of 0 to 30 electrical degrees, the electrical angle of 150 to 210 electrical degrees, and the electrical angle of 330 to 360 electrical degrees. is. Waveform example 37 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 30 degrees to 150 degrees and at an electrical angle of 210 degrees to 330 degrees. In waveform example 37, the high-side-on application period T3 occurs at an electrical angle of 0 to 30 electrical degrees, from 150 to 210 electrical degrees, and from 330 to 360 electrical degrees. In waveform example 37, the low-side-on application period T4 occurs at an electrical angle of 30 degrees to 150 degrees and at an electrical angle of 210 degrees to 330 degrees.
　波形例３７では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｖと、第１オン固定期間Ｔ１ｗとを含む。波形例３７では、電気角１５０度～電気角２１０度が第１オン固定期間Ｔ１ｖである。波形例３７では、電気角０度～電気角３０度および電気角３３０度～電気角３６０度が第１オン固定期間Ｔ１ｗである。 In waveform example 37, the first fixed ON period T1 includes a first fixed ON period T1v and a first fixed ON period T1w. In waveform example 37, the first fixed ON period T1v is from 150 electrical degrees to 210 electrical degrees. In waveform example 37, the first fixed ON period T1w is from an electrical angle of 0 degree to an electrical angle of 30 degrees and from an electrical angle of 330 degrees to an electrical angle of 360 degrees.
　波形例３７では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖと、第２オン固定期間Ｔ２ｗとを含む。波形例３７では、電気角２１０度～電気角３３０度が第２オン固定期間Ｔ２ｕである。波形例３７では、電気角３０度～電気角９０度が第２オン固定期間Ｔ２ｖである。波形例３７では、電気角９０度～電気角１５０度が第２オン固定期間Ｔ２ｗである。 In Waveform Example 37, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 37, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In waveform example 37, the second fixed ON period T2v is from 30 electrical degrees to 90 electrical degrees. In waveform example 37, the second fixed ON period T2w is from 90 electrical degrees to 150 electrical degrees.
　波形例３７では、３相のうちＵ相において、第１オン固定期間Ｔ１ｖが、第１オン固定期間Ｔ１ｕと異なる。詳しくは、波形例３７では、第１オン固定期間Ｔ１ｖが６０度であるのに対し、第１オン固定期間Ｔ１ｕは無い。すなわち、波形例３７では、第１オン固定期間Ｔ１ｖが第１オン固定期間Ｔ１ｕよりも長い。なお、第１オン固定期間Ｔ１ｗは、第１オン固定期間Ｔ１ｖと同じである。したがって、図５７Ｂに示すように、Ｖ相の第１半導体スイッチング素子Ｕｐ（Ｈ（ハイサイド））のスイッチング損失がＵ相に比べて小さくなっている。 In waveform example 37, the first fixed ON period T1v differs from the first fixed ON period T1u in the U phase among the three phases. Specifically, in waveform example 37, the first fixed ON period T1v is 60 degrees, but there is no first fixed ON period T1u. That is, in waveform example 37, the first fixed ON period T1v is longer than the first fixed ON period T1u. The first fixed ON period T1w is the same as the first fixed ON period T1v. Therefore, as shown in FIG. 57B, the switching loss of the V-phase first semiconductor switching element Up (H (high side)) is smaller than that of the U-phase.
　波形例３７では、第２オン固定期間Ｔ２ｕが、第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗと異なる。詳しくは、波形例３７では、第２オン固定期間Ｔ２ｕが１２０度であるのに対し、第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗは６０度である。すなわち、波形例３７では、第２オン固定期間Ｔ２ｕが第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗよりも長い。したがって、図５７Ｂに示すように、Ｕ相の第２半導体スイッチング素子Ｕｎ（Ｌ（ロウサイド））のスイッチング損失がＶ相、Ｗ相に比べて小さくなっている。 In waveform example 37, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in Waveform Example 37, the second fixed ON period T2u is 120 degrees, while the second fixed ON period T2v and the second fixed ON period T2w are 60 degrees. That is, in waveform example 37, the second fixed on period T2u is longer than the second fixed on period T2v and the second fixed on period T2w. Therefore, as shown in FIG. 57B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
　以上、図５７Ａおよび図５７Ｂを参照して説明したように、波形例３７においても、波形例１と同様に、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。波形例３７では、Ｖ相の第１半導体スイッチング素子Ｖｐと、Ｕ相の第２半導体スイッチング素子Ｕｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 57A and 57B , in waveform example 37, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 37, it is possible to simultaneously suppress the heat generation of the V-phase first semiconductor switching element Vp and the U-phase second semiconductor switching element Un.
　また、波形例３７では、図５７Ｂに示すように、Ｖ相の第２半導体スイッチング素子Ｖｎと、Ｗ相の第１半導体スイッチング素子Ｗｐと、Ｗ相の第２半導体スイッチング素子Ｗｎとの発熱についても同時に抑えることができる。 In waveform example 37, as shown in FIG. 57B, the heat generated by the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
　図５８Ａおよび図５８Ｂを参照して、波形例３８について説明する。図５８Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図５８Ｂは、スイッチング損失を示す図である。 A waveform example 38 will be described with reference to FIGS. 58A and 58B. FIG. 58A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 58B is a diagram showing switching losses.
　図５８Ａに示すように、波形例３８は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例３８は、電気角４５度～電気角１３５度および電気角１５０度～電気角２４０度において、いずれか１相の出力が１に固定される波形である。また、波形例３８は、電気角０度～電気角４５度、電気角１３５度～電気角１５０度および電気角２４０度～電気角３６０度において、いずれか１相の出力が０に固定される波形である。波形例３８では、電気角４５度～電気角１３５度および電気角１５０度～電気角２４０度において、ハイサイドオン適用期間Ｔ３である。また、波形例３８では、電気角０度～電気角４５度、電気角１３５度～電気角１５０度および電気角２４０度～電気角３６０度において、ロウサイドオン適用期間Ｔ４である。 As shown in FIG. 58A , in waveform example 38, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. More specifically, waveform example 38 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 45 degrees to 135 degrees and at an electrical angle of 150 degrees to 240 degrees. In waveform example 38, the output of any one phase is fixed to 0 at an electrical angle of 0 to 45 electrical degrees, 135 to 150 electrical degrees, and 240 to 360 electrical degrees. waveform. In waveform example 38, the high-side-on application period T3 occurs at an electrical angle of 45 degrees to 135 degrees and at an electrical angle of 150 degrees to 240 degrees. Further, in waveform example 38, the low side-on application period T4 occurs at an electrical angle of 0 to 45 electrical degrees, 135 to 150 electrical degrees, and 240 to 360 electrical degrees.
　波形例３８では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｕと、第１オン固定期間Ｔ１ｖとを含む。波形例３８では、電気角４５度～電気角１３５度が第１オン固定期間Ｔ１ｕである。波形例３８では、電気角１５０度～電気角２４０度が第１オン固定期間Ｔ１ｖである。 In waveform example 38, the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v. In waveform example 38, the first fixed ON period T1u is from 45 electrical degrees to 135 electrical degrees. In waveform example 38, the first fixed ON period T1v is from 150 electrical degrees to 240 electrical degrees.
　波形例３８では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖと、第２オン固定期間Ｔ２ｗとを含む。波形例３８では、電気角２４０度～電気角３３０度が第２オン固定期間Ｔ２ｕである。波形例３８では、電気角０度～電気角４５度および電気角３３０度～電気角３６０度が第２オン固定期間Ｔ２ｖである。波形例３８では、電気角１３５度～電気角１５０度が第２オン固定期間Ｔ２ｗである。 In Waveform Example 38, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 38, the second fixed ON period T2u is from 240 electrical degrees to 330 electrical degrees. In waveform example 38, the second fixed ON period T2v is from an electrical angle of 0 degree to an electrical angle of 45 degrees and from an electrical angle of 330 degrees to an electrical angle of 360 degrees. In waveform example 38, the second fixed ON period T2w is from 135 electrical degrees to 150 electrical degrees.
　波形例３８では、３相のうちＵ相において、第１オン固定期間Ｔ１ｕが、第１オン固定期間Ｔ１ｗと異なる。詳しくは、波形例３８では、第１オン固定期間Ｔ１ｕが９０度であるのに対し、第１オン固定期間Ｔ１ｗは無い。すなわち、波形例３８では、第１オン固定期間Ｔ１ｕが第１オン固定期間Ｔ１ｗよりも長い。なお、第１オン固定期間Ｔ１ｖは、第１オン固定期間Ｔ１ｕと同じである。したがって、図５８Ｂに示すように、Ｕ相の第１半導体スイッチング素子Ｕｐ（Ｈ（ハイサイド））のスイッチング損失がＷ相に比べて小さくなっている。 In waveform example 38, the first fixed ON period T1u differs from the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 38, the first fixed ON period T1u is 90 degrees, but there is no first fixed ON period T1w. That is, in waveform example 38, the first fixed ON period T1u is longer than the first fixed ON period T1w. The first fixed ON period T1v is the same as the first fixed ON period T1u. Therefore, as shown in FIG. 58B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than that of the W-phase.
　波形例３８では、第２オン固定期間Ｔ２ｕが、第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗと異なる。詳しくは、波形例３８では、第２オン固定期間Ｔ２ｕが９０度であるのに対し、第２オン固定期間Ｔ２ｖは７５度であり、第２オン固定期間Ｔ２ｗは１５度である。すなわち、波形例３８では、第２オン固定期間Ｔ２ｕが第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗよりも長い。したがって、図５８Ｂに示すように、Ｕ相の第２半導体スイッチング素子Ｕｎ（Ｌ（ロウサイド））のスイッチング損失がＶ相、Ｗ相に比べて小さくなっている。 In waveform example 38, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in waveform example 38, the second fixed ON period T2u is 90 degrees, the second fixed ON period T2v is 75 degrees, and the second fixed ON period T2w is 15 degrees. That is, in waveform example 38, the second fixed on period T2u is longer than the second fixed on period T2v and the second fixed on period T2w. Therefore, as shown in FIG. 58B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
　以上、図５８Ａおよび図５８Ｂを参照して説明したように、波形例３８においても、波形例１と同様に、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。波形例３８では、Ｕ相の第１半導体スイッチング素子Ｕｐと、Ｕ相の第２半導体スイッチング素子Ｕｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 58A and 58B , in waveform example 38, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 38, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un.
　また、波形例３８では、図５８Ｂに示すように、Ｖ相の第１半導体スイッチング素子Ｖｐと、Ｖ相の第２半導体スイッチング素子Ｖｎと、Ｗ相の第２半導体スイッチング素子Ｗｎとの発熱についても同時に抑えることができる。 Further, in waveform example 38, as shown in FIG. 58B, the heat generated by the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
　図５９Ａおよび図５９Ｂを参照して、波形例３９について説明する。図５９Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図５９Ｂは、スイッチング損失を示す図である。 A waveform example 39 will be described with reference to FIGS. 59A and 59B. FIG. 59A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 59B is a diagram showing switching losses.
　図５９Ａに示すように、波形例３９は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例３９は、電気角４５度～電気角１３５度、電気角１５０度～電気角２１０度および電気角３３０度～電気角３６０度において、いずれか１相の出力が１に固定される波形である。また、波形例３９は、電気角０度～電気角４５度、電気角１３５度～電気角１５０度および電気角２１０度～電気角３３０度において、いずれか１相の出力が０に固定される波形である。波形例３９では、電気角４５度～電気角１３５度、電気角１５０度～電気角２１０度および電気角３３０度～電気角３６０度において、ハイサイドオン適用期間Ｔ３である。また、波形例３９では、電気角０度～電気角４５度、電気角１３５度～電気角１５０度および電気角２１０度～電気角３３０度において、ロウサイドオン適用期間Ｔ４である。 As shown in FIG. 59A, in waveform example 39, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, in waveform example 39, the output of any one phase is fixed to 1 at an electrical angle of 45 degrees to 135 degrees, from 150 degrees to 210 degrees and from 330 degrees to 360 degrees. waveform. In waveform example 39, the output of any one phase is fixed to 0 at an electrical angle of 0 to 45 electrical degrees, 135 to 150 electrical degrees, and 210 to 330 electrical degrees. waveform. In waveform example 39, the high-side-on application period T3 is at an electrical angle of 45 degrees to 135 degrees, at an electrical angle of 150 degrees to 210 degrees, and at an electrical angle of 330 degrees to 360 degrees. Further, in waveform example 39, the low side-on application period T4 occurs at an electrical angle of 0 to 45 electrical degrees, 135 to 150 electrical degrees, and 210 to 330 electrical degrees.
　波形例３９では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｕと、第１オン固定期間Ｔ１ｖと、第１オン固定期間Ｔ１ｗとを含む。波形例３９では、電気角４５度～電気角１３５度が第１オン固定期間Ｔ１ｕである。波形例３９では、電気角１５０度～電気角２１０度が第１オン固定期間Ｔ１ｖである。波形例３９では、電気角３３０度～電気角３６０度が第１オン固定期間Ｔ１ｗである。 In Waveform Example 39, the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w. In waveform example 39, the first fixed ON period T1u is from 45 electrical degrees to 135 electrical degrees. In waveform example 39, the first fixed ON period T1v is from 150 electrical degrees to 210 electrical degrees. In waveform example 39, the first fixed ON period T1w is from 330 electrical degrees to 360 electrical degrees.
　波形例３９では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖと、第２オン固定期間Ｔ２ｗとを含む。波形例３９では、電気角２１０度～電気角３３０度が第２オン固定期間Ｔ２ｕである。波形例３９では、電気角０度～電気角４５度が第２オン固定期間Ｔ２ｖである。波形例３９では、電気角１３５度～電気角１５０度が第２オン固定期間Ｔ２ｗである。 In Waveform Example 39, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 39, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In waveform example 39, the second fixed ON period T2v is from 0 electrical angle to 45 electrical degrees. In Waveform Example 39, the second fixed ON period T2w is from 135 electrical degrees to 150 electrical degrees.
　波形例３９では、３相のうちＵ相において、第１オン固定期間Ｔ１ｕが、第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗと異なる。詳しくは、波形例３９では、第１オン固定期間Ｔ１ｕが９０度であるのに対し、第１オン固定期間Ｔ１ｖは６０度であり、第１オン固定期間Ｔ１ｗは３０度である。すなわち、波形例３９では、第１オン固定期間Ｔ１ｕが第１オン固定期間Ｔ１ｖおよび第１オン固定期間Ｔ１ｗよりも長い。したがって、図５９Ｂに示すように、Ｕ相の第１半導体スイッチング素子Ｕｐ（Ｈ（ハイサイド））のスイッチング損失がＶ相およびＷ相に比べて小さくなっている。 In waveform example 39, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 39, the first fixed ON period T1u is 90 degrees, the first fixed ON period T1v is 60 degrees, and the first fixed ON period T1w is 30 degrees. That is, in waveform example 39, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 59B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
　波形例３９では、第２オン固定期間Ｔ２ｕが、第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗと異なる。詳しくは、波形例３９では、第２オン固定期間Ｔ２ｕが１２０度であるのに対し、第２オン固定期間Ｔ２ｖは４５度であり、第２オン固定期間Ｔ２ｗは１５度である。すなわち、波形例３９では、第２オン固定期間Ｔ２ｕが第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗよりも長い。したがって、図５９Ｂに示すように、Ｕ相の第２半導体スイッチング素子Ｕｎ（Ｌ（ロウサイド））のスイッチング損失がＶ相、Ｗ相に比べて小さくなっている。 In waveform example 39, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in Waveform Example 39, the second fixed ON period T2u is 120 degrees, the second fixed ON period T2v is 45 degrees, and the second fixed ON period T2w is 15 degrees. That is, in Waveform Example 39, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 59B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
　以上、図５９Ａおよび図５９Ｂを参照して説明したように、波形例３９においても、波形例１と同様に、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。波形例３９では、Ｕ相の第１半導体スイッチング素子Ｕｐと、Ｕ相の第２半導体スイッチング素子Ｕｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 59A and 59B , in waveform example 39, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 39, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un.
　また、波形例３９では、図５９Ｂに示すように、Ｖ相の第１半導体スイッチング素子Ｖｐと、Ｖ相の第２半導体スイッチング素子Ｖｎと、Ｗ相の第１半導体スイッチング素子Ｗｐと、Ｗ相の第２半導体スイッチング素子Ｗｎとの発熱についても同時に抑えることができる。 In waveform example 39, as shown in FIG. 59B, the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
　図６０Ａおよび図６０Ｂを参照して、波形例４０について説明する。図６０Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図６０Ｂは、スイッチング損失を示す図である。 A waveform example 40 will be described with reference to FIGS. 60A and 60B. FIG. 60A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 60B is a diagram showing switching losses.
　図６０Ａに示すように、波形例４０は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例４０は、電気角６０度～電気角１２０度、電気角１５０度～電気角２４０度および電気角３３０度～電気角３６０度において、いずれか１相の出力が１に固定される波形である。また、波形例４０は、電気角０度～電気角６０度、電気角１２０度～電気角１５０度および電気角２４０度～電気角３３０度において、いずれか１相の出力が０に固定される波形である。波形例４０では、電気角６０度～電気角１２０度、電気角１５０度～電気角２４０度および電気角３３０度～電気角３６０度において、ハイサイドオン適用期間Ｔ３である。また、波形例４０では、電気角０度～電気角６０度、電気角１２０度～電気角１５０度および電気角２４０度～電気角３３０度において、ロウサイドオン適用期間Ｔ４である。 As shown in FIG. 60A, in the waveform example 40, the output voltage of any one phase is fixed to 1 in a certain electrical angle section according to the electrical angle, and the output voltage of any one phase is fixed to 1 in another electrical angle section. is fixed to 0. Specifically, in waveform example 40, the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 120 degrees, from 150 degrees to 240 degrees, and from 330 degrees to 360 degrees. waveform. Further, in waveform example 40, the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 degrees, 120 to 150 electrical degrees, and 240 to 330 electrical degrees. waveform. In waveform example 40, the high-side-on application period T3 is at an electrical angle of 60 to 120 electrical degrees, 150 to 240 electrical degrees, and 330 to 360 electrical degrees. Further, in waveform example 40, the low side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees, 120 to 150 electrical degrees, and 240 to 330 electrical degrees.
　波形例４０では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｕと、第１オン固定期間Ｔ１ｖと、第１オン固定期間Ｔ１ｗとを含む。波形例４０では、電気角６０度～電気角１２０度が第１オン固定期間Ｔ１ｕである。波形例４０では、電気角１５０度～電気角２４０度が第１オン固定期間Ｔ１ｖである。波形例４０では、電気角３３０度～電気角３６０度が第１オン固定期間Ｔ１ｗである。 In waveform example 40, the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w. In waveform example 40, the first fixed ON period T1u is from 60 electrical degrees to 120 electrical degrees. In waveform example 40, the first fixed ON period T1v is from 150 electrical degrees to 240 electrical degrees. In waveform example 40, the first fixed ON period T1w is from 330 electrical degrees to 360 electrical degrees.
　波形例４０では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖと、第２オン固定期間Ｔ２ｗとを含む。波形例４０では、電気角２４０度～電気角３３０度が第２オン固定期間Ｔ２ｕである。波形例４０では、電気角０度～電気角６０度が第２オン固定期間Ｔ２ｖである。波形例４０では、電気角１２０度～電気角１５０度が第２オン固定期間Ｔ２ｗである。 In waveform example 40, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 40, the second fixed ON period T2u is from 240 electrical degrees to 330 electrical degrees. In waveform example 40, the second fixed ON period T2v is from 0 electrical angle to 60 electrical degrees. In the waveform example 40, the second fixed ON period T2w is between 120 electrical degrees and 150 electrical degrees.
　波形例４０では、３相のうちＶ相において、第１オン固定期間Ｔ１ｖが、第１オン固定期間Ｔ１ｕおよび第１オン固定期間Ｔ１ｗと異なる。詳しくは、波形例４０では、第１オン固定期間Ｔ１ｖが９０度であるのに対し、第１オン固定期間Ｔ１ｕが６０度であり、第１オン固定期間Ｔ１ｗは３０度である。すなわち、波形例４０では、第１オン固定期間Ｔ１ｖが第１オン固定期間Ｔ１ｕおよび第１オン固定期間Ｔ１ｗよりも長い。したがって、図６０Ｂに示すように、Ｕ相の第１半導体スイッチング素子Ｖｐ（Ｈ（ハイサイド））のスイッチング損失がＵ相およびＷ相に比べて小さくなっている。 In waveform example 40, in the V phase among the three phases, the first fixed ON period T1v is different from the first fixed ON period T1u and the first fixed ON period T1w. Specifically, in waveform example 40, the first fixed ON period T1v is 90 degrees, the first fixed ON period T1u is 60 degrees, and the first fixed ON period T1w is 30 degrees. That is, in waveform example 40, the first fixed ON period T1v is longer than the first fixed ON period T1u and the first fixed ON period T1w. Therefore, as shown in FIG. 60B, the switching loss of the U-phase first semiconductor switching element Vp (H (high side)) is smaller than those of the U-phase and W-phase.
　波形例４０では、第２オン固定期間Ｔ２ｕが、第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗと異なる。詳しくは、波形例４０では、第２オン固定期間Ｔ２ｕが９０度であるのに対し、第２オン固定期間Ｔ２ｖは６０度、および第２オン固定期間Ｔ２ｗは３０度である。すなわち、波形例４０では、第２オン固定期間Ｔ２ｕが第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗよりも長い。したがって、図６０Ｂに示すように、Ｕ相の第２半導体スイッチング素子Ｕｎ（Ｌ（ロウサイド））のスイッチング損失がＶ相、Ｗ相に比べて小さくなっている。 In waveform example 40, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in waveform example 40, the second fixed ON period T2u is 90 degrees, the second fixed ON period T2v is 60 degrees, and the second fixed ON period T2w is 30 degrees. That is, in waveform example 40, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 60B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
　以上、図６０Ａおよび図６０Ｂを参照して説明したように、波形例４０においても、波形例１と同様に、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。波形例４０では、Ｖ相の第１半導体スイッチング素子Ｖｐと、Ｕ相の第２半導体スイッチング素子Ｕｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 60A and 60B , in waveform example 40 as well as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In the waveform example 40, the heat generation of the V-phase first semiconductor switching element Vp and the U-phase second semiconductor switching element Un can be suppressed at the same time.
　また、波形例４０では、図６０Ｂに示すように、Ｕ相の第１半導体スイッチング素子Ｕｐと、Ｖ相の第２半導体スイッチング素子Ｖｎと、Ｗ相の第１半導体スイッチング素子Ｗｐと、Ｗ相の第２半導体スイッチング素子Ｗｎとの発熱についても同時に抑えることができる。 In waveform example 40, as shown in FIG. 60B, the U-phase first semiconductor switching element Up, the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
　図６１Ａおよび図６１Ｂを参照して、波形例４１について説明する。図６１Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図６１Ｂは、スイッチング損失を示す図である。 A waveform example 41 will be described with reference to FIGS. 61A and 61B. FIG. 61A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 61B is a diagram showing switching losses.
　図６１Ａに示すように、波形例４１は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例４１は、電気角０度～電気角３０度、電気角６０度～電気角１２０度、電気角１５０度～電気角２１０度および電気角３３０度～電気角３６０度において、いずれか１相の出力が１に固定される波形である。また、波形例４１は、電気角３０度～電気角６０度、電気角１２０度～電気角１５０度および電気角２１０度～電気角３３０度において、いずれか１相の出力が０に固定される波形である。波形例４１では、電気角０度～電気角３０度、電気角６０度～電気角１２０度、電気角１５０度～電気角２１０度および電気角３３０度～電気角３６０度において、ハイサイドオン適用期間Ｔ３である。また、波形例４１では、電気角３０度～電気角６０度、電気角１２０度～電気角１５０度および電気角２１０度～電気角３３０度において、ロウサイドオン適用期間Ｔ４である。 As shown in FIG. 61A, in waveform example 41, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, the waveform example 41 is any of the electrical angles of 0 to 30 electrical degrees, 60 to 120 electrical degrees, 150 to 210 electrical degrees, and 330 to 360 electrical degrees. or is a waveform in which the output of one phase is fixed at 1. In waveform example 41, the output of any one phase is fixed to 0 at an electrical angle of 30 degrees to 60 degrees, from 120 degrees to 150 degrees and from 210 degrees to 330 degrees. waveform. In waveform example 41, high side ON is applied at an electrical angle of 0 to 30 electrical degrees, from 60 to 120 electrical degrees, from 150 to 210 electrical degrees, and from 330 to 360 electrical degrees. It is period T3. Further, in waveform example 41, the low side-on application period T4 is at an electrical angle of 30 to 60 electrical degrees, 120 to 150 electrical degrees, and 210 to 330 electrical degrees.
　波形例４１では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｕと、第１オン固定期間Ｔ１ｖと、第１オン固定期間Ｔ１ｗとを含む。波形例４１では、電気角６０度～電気角１２０度が第１オン固定期間Ｔ１ｕである。波形例４１では、電気角１５０度～電気角２１０度が第１オン固定期間Ｔ１ｖである。波形例４１では、電気角０度～電気角３０度および電気角３３０度～電気角３６０度が第１オン固定期間Ｔ１ｗである。 In waveform example 41, the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w. In waveform example 41, the first fixed ON period T1u is from 60 electrical degrees to 120 electrical degrees. In waveform example 41, the first fixed ON period T1v is from 150 electrical degrees to 210 electrical degrees. In waveform example 41, the first fixed ON period T1w is from an electrical angle of 0 degrees to an electrical angle of 30 degrees and from an electrical angle of 330 degrees to an electrical angle of 360 degrees.
　波形例４１では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖと、第２オン固定期間Ｔ２ｗとを含む。波形例４１では、電気角２１０度～電気角３３０度が第２オン固定期間Ｔ２ｕである。波形例４１では、電気角３０度～電気角６０度が第２オン固定期間Ｔ２ｖである。波形例４１では、電気角１２０度～電気角１５０度が第２オン固定期間Ｔ２ｗである。 In waveform example 41, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 41, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In waveform example 41, the second fixed ON period T2v is between 30 electrical degrees and 60 electrical degrees. In waveform example 41, the second fixed ON period T2w is from 120 electrical degrees to 150 electrical degrees.
　波形例４１では、第１オン固定期間Ｔ１ｕと、第１オン固定期間Ｔ１ｖと、第１オン固定期間Ｔ１ｖとは同じである。詳しくは、波形例４１では、第１オン固定期間Ｔ１ｕ、第１オン固定期間Ｔ１ｕと、第１オン固定期間Ｔ１ｖと、第１オン固定期間Ｔ１ｖとは６０度である。 In waveform example 41, the first fixed ON period T1u, the first fixed ON period T1v, and the first fixed ON period T1v are the same. Specifically, in waveform example 41, the first fixed ON period T1u, the first fixed ON period T1u, the first fixed ON period T1v, and the first fixed ON period T1v are 60 degrees.
　波形例４１では、第２オン固定期間Ｔ２ｕが、第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗと異なる。詳しくは、波形例４１では、第２オン固定期間Ｔ２ｕが１２０度であるのに対し、第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗは３０度である。すなわち、波形例４１では、第２オン固定期間Ｔ２ｕが第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗよりも長い。したがって、図６１Ｂに示すように、Ｕ相の第２半導体スイッチング素子Ｕｎ（Ｌ（ロウサイド））のスイッチング損失がＶ相、Ｗ相に比べて小さくなっている。 In waveform example 41, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in waveform example 41, the second fixed ON period T2u is 120 degrees, while the second fixed ON period T2v and the second fixed ON period T2w are 30 degrees. That is, in waveform example 41, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 61B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
　以上、図６１Ａおよび図６１Ｂを参照して説明したように、波形例４１においても、波形例１と同様に、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。波形例４１では、Ｕ相の第１半導体スイッチング素子Ｕｐと、Ｕ相の第２半導体スイッチング素子Ｕｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 61A and 61B, in waveform example 41, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 41, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un.
　また、波形例４１では、図６１Ｂに示すように、Ｖ相の第１半導体スイッチング素子Ｖｐと、Ｖ相の第２半導体スイッチング素子Ｖｎと、Ｗ相の第１半導体スイッチング素子Ｗｐと、Ｗ相の第２半導体スイッチング素子Ｗｎとの発熱についても同時に抑えることができる。 In waveform example 41, as shown in FIG. 61B, the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
　図６２Ａおよび図６２Ｂを参照して、波形例４２について説明する。図６２Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図６２Ｂは、スイッチング損失を示す図である。 A waveform example 42 will be described with reference to FIGS. 62A and 62B. FIG. 62A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 62B is a diagram showing switching losses.
　図６２Ａに示すように、波形例４２は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例４２は、電気角７５度～電気角１０５度、電気角１５０度～電気角２７０度および電気角３３０度～電気角３６０度において、いずれか１相の出力が１に固定される波形である。また、波形例４２は、電気角０度～電気角７５度、電気角１０５度～電気角１５０度および電気角２７０度～電気角３３０度において、いずれか１相の出力が０に固定される波形である。波形例４２では、電気角７５度～電気角１０５度、電気角１５０度～電気角２７０度および電気角３３０度～電気角３６０度において、ハイサイドオン適用期間Ｔ３である。また、波形例４２では、電気角０度～電気角７５度、電気角１０５度～電気角１５０度および電気角２７０度～電気角３３０度において、ロウサイドオン適用期間Ｔ４である。 As shown in FIG. 62A , in waveform example 42, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, in waveform example 42, the output of any one phase is fixed to 1 at an electrical angle of 75 degrees to 105 degrees, from 150 degrees to 270 degrees, and from 330 degrees to 360 degrees. waveform. In waveform example 42, the output of any one phase is fixed to 0 at an electrical angle of 0 to 75 electrical degrees, 105 to 150 electrical degrees, and 270 to 330 electrical degrees. waveform. In waveform example 42, the high-side-on application period T3 is at an electrical angle of 75 degrees to 105 degrees, an electrical angle of 150 degrees to 270 degrees, and an electrical angle of 330 degrees to 360 degrees. Further, in waveform example 42, the low side-on application period T4 occurs at an electrical angle of 0 to 75 electrical degrees, 105 to 150 electrical degrees, and 270 to 330 electrical degrees.
　波形例４２では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｕと、第１オン固定期間Ｔ１ｖと、第１オン固定期間Ｔ１ｗとを含む。波形例４２では、電気角７５度～電気角１０５度が第１オン固定期間Ｔ１ｕである。波形例４２では、電気角１５０度～電気角２７０度が第１オン固定期間Ｔ１ｖである。波形例４２では、電気角３３０度～電気角３６０度が第１オン固定期間Ｔ１ｗである。 In waveform example 42, the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w. In waveform example 42, the first fixed ON period T1u is from 75 electrical degrees to 105 electrical degrees. In waveform example 42, the first fixed ON period T1v is from 150 electrical degrees to 270 electrical degrees. In waveform example 42, the first fixed ON period T1w is from 330 electrical degrees to 360 electrical degrees.
　波形例４２では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖと、第２オン固定期間Ｔ２ｗとを含む。波形例４２では、電気角２７０度～電気角３３０度が第２オン固定期間Ｔ２ｕである。波形例４２では、電気角０度～電気角７５度が第２オン固定期間Ｔ２ｖである。波形例４２では、電気角１０５度～電気角１５０度が第２オン固定期間Ｔ２ｗである。 In waveform example 42, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 42, the second fixed ON period T2u is from 270 degrees to 330 degrees in electrical angle. In waveform example 42, the second fixed ON period T2v is from 0 electrical angle to 75 electrical degrees. In waveform example 42, the second fixed ON period T2w is from 105 electrical degrees to 150 electrical degrees.
　波形例４２では、３相のうちＶ相において、第１オン固定期間Ｔ１ｖが、第１オン固定期間Ｔ１ｕおよび第１オン固定期間Ｔ１ｗと異なる。詳しくは、波形例４２では、第１オン固定期間Ｔ１ｖが１２０度であるのに対し、第１オン固定期間Ｔ１ｕおよび第１オン固定期間Ｔ１ｗは３０度である。すなわち、波形例４２では、第１オン固定期間Ｔ１ｖが第１オン固定期間Ｔ１ｕおよび第１オン固定期間Ｔ１ｗよりも長い。したがって、図６２Ｂに示すように、Ｖ相の第１半導体スイッチング素子Ｕｐ（Ｈ（ハイサイド））のスイッチング損失がＵ相およびＷ相に比べて小さくなっている。 In waveform example 42, in the V phase among the three phases, the first fixed ON period T1v differs from the first fixed ON period T1u and the first fixed ON period T1w. Specifically, in waveform example 42, the first fixed ON period T1v is 120 degrees, while the first fixed ON period T1u and the first fixed ON period T1w are 30 degrees. That is, in waveform example 42, the first fixed ON period T1v is longer than the first fixed ON period T1u and the first fixed ON period T1w. Therefore, as shown in FIG. 62B, the switching loss of the V-phase first semiconductor switching element Up (H (high side)) is smaller than those of the U-phase and W-phase.
　波形例４２では、第２オン固定期間Ｔ２ｖが、第２オン固定期間Ｔ２ｕおよび第２オン固定期間Ｔ２ｗと異なる。詳しくは、波形例４２では、第２オン固定期間Ｔ２ｖが７５度であるのに対し、第２オン固定期間Ｔ２ｕは６０度であり、第２オン固定期間Ｔ２ｗは４５度である。すなわち、波形例４２では、第２オン固定期間Ｔ２ｖが第２オン固定期間Ｔ２ｕおよび第２オン固定期間Ｔ２ｗよりも長い。したがって、図６２Ｂに示すように、Ｖ相の第２半導体スイッチング素子Ｖｎ（Ｌ（ロウサイド））のスイッチング損失がＵ相、Ｗ相に比べて小さくなっている。 In waveform example 42, the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in waveform example 42, the second fixed ON period T2v is 75 degrees, the second fixed ON period T2u is 60 degrees, and the second fixed ON period T2w is 45 degrees. That is, in waveform example 42, the second fixed ON period T2v is longer than the second fixed ON period T2u and the second fixed ON period T2w. Therefore, as shown in FIG. 62B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
　以上、図６２Ａおよび図６２Ｂを参照して説明したように、波形例４２においても、波形例１と同様に、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。波形例４２では、Ｖ相の第１半導体スイッチング素子Ｖｐと、Ｖ相の第２半導体スイッチング素子Ｖｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 62A and 62B , in waveform example 42, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 42, the heat generation of the V-phase first semiconductor switching element Vp and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
　また、波形例４２では、図６２Ｂに示すように、Ｕ相の第１半導体スイッチング素子Ｕｐと、Ｕ相の第２半導体スイッチング素子Ｕｎと、Ｗ相の第１半導体スイッチング素子Ｗｐと、Ｗ相の第２半導体スイッチング素子Ｗｎとの発熱についても同時に抑えることができる。 In waveform example 42, as shown in FIG. 62B, the U-phase first semiconductor switching element Up, the U-phase second semiconductor switching element Un, the W-phase first semiconductor switching element Wp, and the W-phase semiconductor switching element Wp Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
　図６３Ａおよび図６３Ｂを参照して、波形例４３について説明する。図６３Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図６３Ｂは、スイッチング損失を示す図である。 A waveform example 43 will be described with reference to FIGS. 63A and 63B. FIG. 63A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 63B is a diagram showing switching losses.
　図６３Ａに示すように、波形例４３は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例４３は、電気角０度～電気角３０度、電気角７５度～電気角１０５度、電気角１５０度～電気角２４０度および電気角３３０度～電気角３６０度において、いずれか１相の出力が１に固定される波形である。また、波形例４３は、電気角３０度～電気角７５度、電気角１０５度～電気角１５０度および電気角２４０度～電気角３３０度において、いずれか１相の出力が０に固定される波形である。波形例４３では、電気角０度～電気角３０度、電気角７５度～電気角１０５度、電気角１５０度～電気角２４０度および電気角３３０度～電気角３６０度において、ハイサイドオン適用期間Ｔ３である。また、波形例４３では、電気角３０度～電気角７５度、電気角１０５度～電気角１５０度および電気角２４０度～電気角３３０度において、ロウサイドオン適用期間Ｔ４である。 As shown in FIG. 63A, in waveform example 43, the output voltage of any one phase is fixed to 1 in a certain electrical angle section, and the output voltage of any one phase is fixed to 1 in another electrical angle section, depending on the electrical angle. is fixed to 0. Specifically, the waveform example 43 is any of the electrical angles of 0 to 30 electrical degrees, 75 to 105 electrical degrees, 150 to 240 electrical degrees, and 330 to 360 electrical degrees. or is a waveform in which the output of one phase is fixed at 1. In waveform example 43, the output of any one phase is fixed to 0 at an electrical angle of 30 degrees to 75 degrees, from 105 degrees to 150 degrees, and from 240 degrees to 330 degrees. waveform. In waveform example 43, high side ON is applied at an electrical angle of 0 to 30 electrical degrees, from 75 to 105 electrical degrees, from 150 to 240 electrical degrees, and from 330 to 360 electrical degrees. It is period T3. Further, in waveform example 43, the low side-on application period T4 occurs at an electrical angle of 30 to 75 electrical degrees, 105 to 150 electrical degrees, and 240 to 330 electrical degrees.
　波形例４３では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｕと、第１オン固定期間Ｔ１ｖと、第１オン固定期間Ｔ１ｗとを含む。波形例４３では、電気角７５度～電気角１０５度が第１オン固定期間Ｔ１ｕである。波形例４３では、電気角１５０度～電気角２４０度が第１オン固定期間Ｔ１ｖである。波形例４３では、電気角０度～電気角３０度および電気角３３０度～電気角３６０度が第１オン固定期間Ｔ１ｗである。 In waveform example 43, the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w. In waveform example 43, the first fixed ON period T1u is from 75 electrical degrees to 105 electrical degrees. In waveform example 43, the first fixed ON period T1v is from 150 electrical degrees to 240 electrical degrees. In waveform example 43, the first fixed ON period T1w is from an electrical angle of 0 degrees to an electrical angle of 30 degrees and from an electrical angle of 330 degrees to an electrical angle of 360 degrees.
　波形例４３では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖと、第２オン固定期間Ｔ２ｗとを含む。波形例４３では、電気角２４０度～電気角３３０度が第２オン固定期間Ｔ２ｕである。波形例４３では、電気角３０度～電気角７５度が第２オン固定期間Ｔ２ｖである。波形例４３では、電気角１０５度～電気角１５０度が第２オン固定期間Ｔ２ｗである。 In waveform example 43, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 43, the second fixed ON period T2u is from 240 degrees to 330 degrees in electrical angle. In waveform example 43, the second fixed ON period T2v is from 30 electrical degrees to 75 electrical degrees. In waveform example 43, the second fixed ON period T2w is from 105 electrical degrees to 150 electrical degrees.
　波形例４３では、３相のうちＶ相において、第１オン固定期間Ｔ１ｖが、第１オン固定期間Ｔ１ｕおよび第１オン固定期間Ｔ１ｗと異なる。詳しくは、波形例４３では、第１オン固定期間Ｔ１ｖが９０度であるのに対し、第１オン固定期間Ｔ１ｕは３０度であり、第１オン固定期間Ｔ１ｗは６０度である。すなわち、波形例４３では、第１オン固定期間Ｔ１ｖが第１オン固定期間Ｔ１ｕおよび第１オン固定期間Ｔ１ｗよりも長い。したがって、図６３Ｂに示すように、Ｖ相の第１半導体スイッチング素子Ｖｐ（Ｈ（ハイサイド））のスイッチング損失がＵ相およびＷ相に比べて小さくなっている。 In waveform example 43, in the V phase among the three phases, the first fixed ON period T1v differs from the first fixed ON period T1u and the first fixed ON period T1w. Specifically, in waveform example 43, the first fixed ON period T1v is 90 degrees, the first fixed ON period T1u is 30 degrees, and the first fixed ON period T1w is 60 degrees. That is, in waveform example 43, the first fixed ON period T1v is longer than the first fixed ON period T1u and the first fixed ON period T1w. Therefore, as shown in FIG. 63B, the switching loss of the V-phase first semiconductor switching element Vp (H (high side)) is smaller than those of the U-phase and W-phase.
　波形例４３では、第２オン固定期間Ｔ２ｕが、第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗと異なる。詳しくは、波形例４３では、第２オン固定期間Ｔ２ｕが９０度であるのに対し、第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗは４５度である。すなわち、波形例４３では、第２オン固定期間Ｔ２ｕが第２オン固定期間Ｔ２ｖおよび第２オン固定期間Ｔ２ｗよりも長い。したがって、図６３Ｂに示すように、Ｕ相の第２半導体スイッチング素子Ｕｎ（Ｌ（ロウサイド））のスイッチング損失がＶ相、Ｗ相に比べて小さくなっている。 In waveform example 43, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in waveform example 43, the second fixed ON period T2u is 90 degrees, while the second fixed ON period T2v and the second fixed ON period T2w are 45 degrees. That is, in waveform example 43, the second fixed on period T2u is longer than the second fixed on period T2v and the second fixed on period T2w. Therefore, as shown in FIG. 63B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
　以上、図６３Ａおよび図６３Ｂを参照して説明したように、波形例４３においても、波形例１と同様に、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。波形例４３では、Ｖ相の第１半導体スイッチング素子Ｖｐと、Ｕ相の第２半導体スイッチング素子Ｕｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 63A and 63B , in waveform example 43, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In the waveform example 43, the heat generation of the V-phase first semiconductor switching element Vp and the U-phase second semiconductor switching element Un can be suppressed at the same time.
　また、波形例４３では、図６３Ｂに示すように、Ｕ相の第１半導体スイッチング素子Ｕｐと、Ｖ相の第２半導体スイッチング素子Ｖｎと、Ｗ相の第１半導体スイッチング素子Ｗｐと、Ｗ相の第２半導体スイッチング素子Ｗｎとの発熱についても同時に抑えることができる。 In waveform example 43, as shown in FIG. 63B, the U-phase first semiconductor switching element Up, the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
　図６４Ａおよび図６４Ｂを参照して、波形例４４について説明する。図６４Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図６４Ｂは、スイッチング損失を示す図である。 A waveform example 44 will be described with reference to FIGS. 64A and 64B. FIG. 64A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 64B is a diagram showing switching losses.
　図６４Ａに示すように、波形例４４は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例４４は、電気角０度～電気角３０度、電気角１５０度～電気角２７０度および電気角３３０度～電気角３６０度において、いずれか１相の出力が１に固定される波形である。また、波形例４４は、電気角３０度～電気角１５０度、および電気角２７０度～電気角３３０度において、いずれか１相の出力が０に固定される波形である。波形例４４では、電気角０度～電気角３０度、電気角１５０度～電気角２７０度および電気角３３０度～電気角３６０度において、ハイサイドオン適用期間Ｔ３である。また、波形例４４では、電気角３０度～電気角１５０度、および電気角２７０度～電気角３３０度において、ロウサイドオン適用期間Ｔ４である。 As shown in FIG. 64A, in the waveform example 44, the output voltage of any one phase is fixed to 1 in a certain electrical angle section according to the electrical angle, and the output voltage of any one phase is fixed to 1 in another electrical angle section. is fixed to 0. Specifically, in waveform example 44, the output of any one phase is fixed to 1 at an electrical angle of 0 to 30 degrees, from 150 to 270 electrical degrees, and from 330 to 360 electrical degrees. waveform. Waveform example 44 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 30 degrees to 150 degrees and at an electrical angle of 270 degrees to 330 degrees. In waveform example 44, the high-side-on application period T3 occurs at an electrical angle of 0 to 30 electrical degrees, 150 to 270 electrical degrees, and 330 to 360 electrical degrees. Further, in waveform example 44, the low side-on application period T4 occurs at an electrical angle of 30 degrees to 150 degrees and at an electrical angle of 270 degrees to 330 degrees.
　波形例４４では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｖと、第１オン固定期間Ｔ１ｗとを含む。波形例４４では、電気角１５０度～電気角２７０度が第１オン固定期間Ｔ１ｖである。波形例４４では、電気角０度～電気角３０度および電気角３３０度～電気角３６０度が第１オン固定期間Ｔ１ｗである。 In waveform example 44, the first fixed ON period T1 includes a first fixed ON period T1v and a first fixed ON period T1w. In waveform example 44, the first fixed ON period T1v is from 150 electrical degrees to 270 electrical degrees. In waveform example 44, the first fixed ON period T1w is from 0 electrical angle to 30 electrical degrees and from 330 electrical degrees to 360 electrical degrees.
　波形例４４では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖと、第２オン固定期間Ｔ２ｗとを含む。波形例４４では、電気角２７０度～電気角３３０度が第２オン固定期間Ｔ２ｕである。波形例４４では、電気角３０度～電気角９０度が第２オン固定期間Ｔ２ｖである。波形例４４では、電気角９０度～電気角１５０度が第２オン固定期間Ｔ２ｗである。 In waveform example 44, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 44, the second fixed ON period T2u is from 270 degrees to 330 degrees in electrical angle. In waveform example 44, the second ON fixed period T2v is from 30 electrical degrees to 90 electrical degrees. In waveform example 44, the second fixed ON period T2w is from 90 electrical degrees to 150 electrical degrees.
　波形例４４では、３相のうちＵ相において、第１オン固定期間Ｔ１ｖが、第１オン固定期間Ｔ１ｕおよび第１オン固定期間Ｔ１ｗと異なる。詳しくは、波形例４４では、第１オン固定期間Ｔ１ｖが１２０度であるのに対し、第１オン固定期間Ｔ１ｕは無く、第１オン固定期間Ｔ１ｗは６０度である。すなわち、波形例４４では、第１オン固定期間Ｔ１ｖが第１オン固定期間Ｔ１ｕおよび第１オン固定期間Ｔ１ｗよりも長い。したがって、図６４Ｂに示すように、Ｖ相の第１半導体スイッチング素子Ｖｐ（Ｈ（ハイサイド））のスイッチング損失がＵ相およびＷ相に比べて小さくなっている。 In waveform example 44, the first fixed ON period T1v differs from the first fixed ON period T1u and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 44, the first fixed ON period T1v is 120 degrees, whereas the first fixed ON period T1u is absent and the first fixed ON period T1w is 60 degrees. That is, in waveform example 44, the first fixed ON period T1v is longer than the first fixed ON period T1u and the first fixed ON period T1w. Therefore, as shown in FIG. 64B, the switching loss of the V-phase first semiconductor switching element Vp (H (high side)) is smaller than those of the U-phase and W-phase.
　波形例４４では、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖと、第２オン固定期間Ｔ２ｗとは同じである。詳しくは、波形例４４では、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖと、第２オン固定期間Ｔ２ｗとは６０度である。 In waveform example 44, the second fixed ON period T2u, the second fixed ON period T2v, and the second fixed ON period T2w are the same. Specifically, in waveform example 44, the second fixed ON period T2u, the second fixed ON period T2v, and the second fixed ON period T2w are 60 degrees.
　以上、図６４Ａおよび図６４Ｂを参照して説明したように、波形例４４においても、波形例１と同様に、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。波形例４４では、Ｖ相の第１半導体スイッチング素子Ｖｐと、Ｕ相の第２半導体スイッチング素子Ｕｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 64A and 64B, in waveform example 44, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 44, it is possible to simultaneously suppress the heat generation of the V-phase first semiconductor switching element Vp and the U-phase second semiconductor switching element Un.
　また、波形例４４では、図６４Ｂに示すように、Ｖ相の第２半導体スイッチング素子Ｖｎと、Ｗ相の第１半導体スイッチング素子Ｗｐと、Ｗ相の第２半導体スイッチング素子Ｗｎとの発熱についても同時に抑えることができる。 In waveform example 44, as shown in FIG. 64B, the heat generated by the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
　図６５Ａおよび図６５Ｂを参照して、波形例４５について説明する。図６５Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図６５Ｂは、スイッチング損失を示す図である。 A waveform example 45 will be described with reference to FIGS. 65A and 65B. FIG. 65A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 65B is a diagram showing switching losses.
　図６５Ａに示すように、波形例４５は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例４５は、電気角０度～電気角３０度、電気角１５０度～電気角２４０度および電気角３００度～電気角３６０度において、いずれか１相の出力が１に固定される波形である。また、波形例４５は、電気角３０度～電気角１５０度、電気角２４０度～電気角３００度において、いずれか１相の出力が０に固定される波形である。波形例４５では、電気角０度～電気角３０度、電気角１５０度～電気角２４０度および電気角３００度～電気角３６０度において、ハイサイドオン適用期間Ｔ３である。また、波形例４５では、電気角３０度～電気角１５０度、電気角２４０度～電気角３００度において、ロウサイドオン適用期間Ｔ４である。 As shown in FIG. 65A , in waveform example 45, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, in waveform example 45, the output of any one phase is fixed to 1 at an electrical angle of 0 to 30 degrees, from 150 to 240 electrical degrees, and from 300 to 360 electrical degrees. waveform. Waveform example 45 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 30 degrees to 150 degrees and at an electrical angle of 240 degrees to 300 degrees. In waveform example 45, the high-side-on application period T3 occurs at an electrical angle of 0 to 30 electrical degrees, 150 to 240 electrical degrees, and 300 to 360 electrical degrees. Further, in waveform example 45, the low-side-on application period T4 occurs at an electrical angle of 30 degrees to 150 electrical degrees and at an electrical angle of 240 degrees to 300 electrical degrees.
　波形例４５では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｖと、第１オン固定期間Ｔ１ｗとを含む。波形例４５では、電気角１５０度～電気角２４０度が第１オン固定期間Ｔ１ｖである。波形例４５では、電気角０度～電気角３０度および電気角３００度～電気角３６０度が第１オン固定期間Ｔ１ｗである。 In waveform example 45, the first fixed ON period T1 includes a first fixed ON period T1v and a first fixed ON period T1w. In waveform example 45, the first fixed ON period T1v is from 150 electrical degrees to 240 electrical degrees. In waveform example 45, the first fixed ON period T1w is from an electrical angle of 0 degrees to an electrical angle of 30 degrees and from an electrical angle of 300 degrees to an electrical angle of 360 degrees.
　波形例４５では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖと、第２オン固定期間Ｔ２ｗとを含む。波形例４５では、電気角２４０度～電気角３００度が第２オン固定期間Ｔ２ｕである。波形例４５では、電気角３０度～電気角９０度が第２オン固定期間Ｔ２ｖである。波形例４５では、電気角９０度～電気角１５０度が第２オン固定期間Ｔ２ｗである。 In waveform example 45, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 45, the second fixed ON period T2u is from 240 electrical degrees to 300 electrical degrees. In waveform example 45, the second fixed ON period T2v is from 30 electrical degrees to 90 electrical degrees. In waveform example 45, the second fixed ON period T2w is from 90 electrical degrees to 150 electrical degrees.
　波形例４５では、３相のうちＶ相において、第１オン固定期間Ｔ１ｖが、第１オン固定期間Ｔ１ｕおよび第１オン固定期間Ｔ１ｗと異なる。詳しくは、波形例４５では、第１オン固定期間Ｔ１ｖが９０度であるのに対し、第１オン固定期間Ｔ１ｕは無い。すなわち、波形例４５では、第１オン固定期間Ｔ１ｖが第１オン固定期間Ｔ１ｕよりも長い。なお、第１オン固定期間Ｔ１ｗは、第１オン固定期間Ｔ１ｖと同じである。したがって、図６５Ｂに示すように、Ｖ相の第１半導体スイッチング素子Ｕｐ（Ｈ（ハイサイド））のスイッチング損失がＷ相に比べて小さくなっている。 In waveform example 45, in the V phase among the three phases, the first fixed ON period T1v differs from the first fixed ON period T1u and the first fixed ON period T1w. Specifically, in waveform example 45, the first fixed ON period T1v is 90 degrees, but there is no first fixed ON period T1u. That is, in waveform example 45, the first fixed ON period T1v is longer than the first fixed ON period T1u. The first fixed ON period T1w is the same as the first fixed ON period T1v. Therefore, as shown in FIG. 65B, the switching loss of the V-phase first semiconductor switching element Up (H (high side)) is smaller than that of the W-phase.
　波形例４５では、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖと、第２オン固定期間Ｔ２ｗとは同じである。詳しくは、波形例４５では、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖと、第２オン固定期間Ｔ２ｗとは６０度である。 In waveform example 45, the second fixed ON period T2u, the second fixed ON period T2v, and the second fixed ON period T2w are the same. Specifically, in waveform example 45, the second fixed ON period T2u, the second fixed ON period T2v, and the second fixed ON period T2w are 60 degrees.
　以上、図６５Ａおよび図６５Ｂを参照して説明したように、波形例４５においても、波形例１と同様に、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。波形例４５では、Ｖ相の第１半導体スイッチング素子Ｖｐと、Ｕ相の第２半導体スイッチング素子Ｕｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 65A and 65B , in waveform example 45, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In the waveform example 45, the heat generation of the V-phase first semiconductor switching element Vp and the U-phase second semiconductor switching element Un can be suppressed at the same time.
　また、波形例４５では、図６５Ｂに示すように、Ｖ相の第２半導体スイッチング素子Ｖｎと、Ｗ相の第１半導体スイッチング素子Ｗｐと、Ｗ相の第２半導体スイッチング素子Ｗｎとの発熱についても同時に抑えることができる。 In waveform example 45, as shown in FIG. 65B, the heat generated by the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
　図６６Ａおよび図６６Ｂを参照して、波形例４６について説明する。図６６Ａは、出力電圧Ｖｕ、出力電圧Ｖｖおよび出力電圧Ｖｗを示す図である。図６６Ｂは、スイッチング損失を示す図である。 A waveform example 46 will be described with reference to FIGS. 66A and 66B. FIG. 66A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 66B is a diagram showing switching losses.
　図６６Ａに示すように、波形例４６は、電気角に応じて、ある電気角区間ではいずれか１相の出力電圧が１に固定され、別のある電気角区間ではいずれか１相の出力電圧が０に固定される波形となっている。詳しくは、波形例４６は、電気角９０度～電気角２７０度において、いずれか１相の出力が１に固定される波形である。また、波形例４６は、電気角０度～電気角９０度および電気角２７０度～電気角３６０度において、いずれか１相の出力が０に固定される波形である。波形例４６では、電気角９０度～電気角２７０度において、ハイサイドオン適用期間Ｔ３である。また、波形例４６では、電気角０度～電気角９０度および電気角２７０度～電気角３６０度において、ロウサイドオン適用期間Ｔ４である。 As shown in FIG. 66A, in the waveform example 46, the output voltage of any one phase is fixed to 1 in a certain electrical angle section according to the electrical angle, and the output voltage of any one phase is fixed to 1 in another electrical angle section. is fixed to 0. Specifically, waveform example 46 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 90 degrees to 270 electrical degrees. Waveform example 46 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 to 90 degrees and at an electrical angle of 270 to 360 degrees. In waveform example 46, the high-side-on application period T3 is at an electrical angle of 90 degrees to 270 electrical degrees. Further, in the waveform example 46, the low side-on application period T4 occurs at an electrical angle of 0 to 90 electrical degrees and at an electrical angle of 270 to 360 electrical degrees.
　波形例４６では、第１オン固定期間Ｔ１は、第１オン固定期間Ｔ１ｕと、第１オン固定期間Ｔ１ｖとを含む。波形例４６では、電気角９０度～電気角１５０度が第１オン固定期間Ｔ１ｕである。波形例４６では、電気角１５０度～電気角２７０度が第１オン固定期間Ｔ１ｖである。 In waveform example 46, the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v. In the waveform example 46, the first fixed ON period T1u is from 90 electrical degrees to 150 electrical degrees. In waveform example 46, the first fixed ON period T1v is from 150 electrical degrees to 270 electrical degrees.
　波形例４６では、第２オン固定期間Ｔ２は、第２オン固定期間Ｔ２ｕと、第２オン固定期間Ｔ２ｖとを含む。波形例４６では、電気角２７０度～電気角３３０度が第２オン固定期間Ｔ２ｕである。波形例４６では、電気角０度～電気角９０度および電気角３３０度～電気角３６０度が第２オン固定期間Ｔ２ｖである。 In the waveform example 46, the second fixed ON period T2 includes a second fixed ON period T2u and a second fixed ON period T2v. In waveform example 46, the second fixed ON period T2u is from 270 electrical degrees to 330 electrical degrees. In waveform example 46, the second fixed ON period T2v is from 0 to 90 electrical degrees and from 330 to 360 electrical degrees.
　波形例４６では、３相のうちＶ相において、第１オン固定期間Ｔ１ｖが、第１オン固定期間Ｔ１ｕおよび第１オン固定期間Ｔ１ｗと異なる。詳しくは、波形例４６では、第１オン固定期間Ｔ１ｖが１２０度であるのに対し、第１オン固定期間Ｔ１ｕは６０度であり、第１オン固定期間Ｔ１ｗは無い。すなわち、波形例４６では、第１オン固定期間Ｔ１ｖが第１オン固定期間Ｔ１ｕおよび第１オン固定期間Ｔ１ｗよりも長い。したがって、図６６Ｂに示すように、Ｕ相の第１半導体スイッチング素子Ｖｐ（Ｈ（ハイサイド））のスイッチング損失がＵ相およびＷ相に比べて小さくなっている。 In waveform example 46, the first fixed ON period T1v differs from the first fixed ON period T1u and the first fixed ON period T1w in the V phase among the three phases. Specifically, in waveform example 46, the first fixed ON period T1v is 120 degrees, the first fixed ON period T1u is 60 degrees, and there is no first fixed ON period T1w. That is, in the waveform example 46, the first fixed ON period T1v is longer than the first fixed ON period T1u and the first fixed ON period T1w. Therefore, as shown in FIG. 66B, the switching loss of the U-phase first semiconductor switching element Vp (H (high side)) is smaller than those of the U-phase and W-phase.
　波形例４６では、第２オン固定期間Ｔ２ｖが、第２オン固定期間Ｔ２ｕおよび第２オン固定期間Ｔ２ｗと異なる。詳しくは、波形例４６では、第２オン固定期間Ｔ２ｖが１２０度であるのに対し、第２オン固定期間Ｔ２ｕは６０度であり、第２オン固定期間Ｔ２ｗは無い。すなわち、波形例４６では、第２オン固定期間Ｔ２ｖが第２オン固定期間Ｔ２ｕおよび第２オン固定期間Ｔ２ｗよりも長い。したがって、図６６Ｂに示すように、Ｖ相の第２半導体スイッチング素子Ｖｎ（Ｌ（ロウサイド））のスイッチング損失がＵ相、Ｗ相に比べて小さくなっている。 In waveform example 46, the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in waveform example 46, the second fixed ON period T2v is 120 degrees, the second fixed ON period T2u is 60 degrees, and there is no second fixed ON period T2w. That is, in waveform example 46, the second fixed ON period T2v is longer than the second fixed ON period T2u and the second fixed ON period T2w. Therefore, as shown in FIG. 66B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
　以上、図６６Ａおよび図６６Ｂを参照して説明したように、波形例４６においても、波形例１と同様に、ある相の第１半導体スイッチング素子と、ある相の第２半導体スイッチング素子との発熱を同時に抑えることで、電力変換器（インバータ）の昇温を抑制し信頼性を高めることができる。波形例４６では、Ｖ相の第１半導体スイッチング素子Ｖｐと、Ｖ相の第２半導体スイッチング素子Ｖｎとの発熱を同時に抑えることができる。 As described above with reference to FIGS. 66A and 66B , in waveform example 46, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In the waveform example 46, the heat generation of the V-phase first semiconductor switching element Vp and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
　また、波形例４６では、図６６Ｂに示すように、Ｕ相の第１半導体スイッチング素子Ｕｐと、Ｕ相の第２半導体スイッチング素子Ｕｎとの発熱についても同時に抑えることができる。 In addition, in the waveform example 46, as shown in FIG. 66B, the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un can be suppressed at the same time.
　以上、図面（図１～図６６Ｂ）を参照しながら本発明の実施形態を説明した。但し、本発明は、上記の実施形態に限られるものではなく、その要旨を逸脱しない範囲で種々の態様において実施することが可能である。図面は、理解しやすくするために、それぞれの構成要素を主体に模式的に示しており、図示された各構成要素の厚み、長さ、個数等は、図面作成の都合上から実際とは異なる。また、上記の実施形態で示す各構成要素の材質や形状、寸法等は一例であって、特に限定されるものではなく、本発明の効果から実質的に逸脱しない範囲で種々の変更が可能である。 The embodiments of the present invention have been described above with reference to the drawings (FIGS. 1 to 66B). However, the present invention is not limited to the above-described embodiments, and can be implemented in various aspects without departing from the gist of the present invention. In order to facilitate understanding, the drawings schematically show each component mainly, and the thickness, length, number, etc. of each component illustrated are different from the actual ones due to the convenience of drawing. . In addition, the material, shape, dimensions, etc. of each component shown in the above embodiment are examples and are not particularly limited, and various changes are possible within a range that does not substantially deviate from the effects of the present invention. be.
　図１～図６６Ｂを参照して説明したモータ駆動回路１００（電力変換器）は、３相の交流出力を出力していたが本発明はこれに限定されない。例えば、モータ駆動回路１００は、５相以上の交流出力を出力してもよい。例えば、モータ駆動回路１００は、５相の交流出力を出力することによって、５相のモータＭを駆動してもよい。 The motor drive circuit 100 (power converter) described with reference to FIGS. 1 to 66B outputs a three-phase AC output, but the present invention is not limited to this. For example, the motor drive circuit 100 may output AC outputs of five or more phases. For example, the motor drive circuit 100 may drive the 5-phase motor M by outputting a 5-phase AC output.
　本発明は、電力変換器およびモータモジュールに好適に利用できる。 The present invention can be suitably used for power converters and motor modules.
１００　　　　モータ駆動回路（電力変換器）
１０２、１０２ｕ、１０２ｖ、１０２ｗ　出力端子
１１２、１１２ｕ、１１２ｖ、１１２ｗ　直列体
１１４、１１４ｕ、１１４ｖ、１１４ｗ　接続点
２００　　　　モータモジュール
Ｍ　　　　　　モータ
Ｎ　　　　　　第２電源端子
Ｐ　　　　　　第１電源端子
Ｔ１、Ｔ１ｕ、Ｔ１ｖ、Ｔ１ｗ　第１オン固定期間
Ｔ２、Ｔ２ｕ、Ｔ２ｖ、Ｔ２ｗ　第２オン固定期間
Ｕｐ、Ｖｐ、Ｗｐ　第１半導体スイッチング素子
Ｕｎ、Ｖｎ、Ｗｎ　第２半導体スイッチング素子
Ｖ１　　　　　第１の電圧
Ｖ２　　　　　第２の電圧
Ｖｕ、Ｖｖ、Ｖｗ　出力電圧 100 Motor drive circuit (power converter)
102, 102u, 102v, 102w Output terminals 112, 112u, 112v, 112w Series bodies 114, 114u, 114v, 114w Connection point 200 Motor module M Motor N Second power terminal P First power terminals T1, T1u, T1v, T1w One fixed ON period T2, T2u, T2v, T2w Second fixed ON period Up, Vp, Wp First semiconductor switching element Un, Vn, Wn Second semiconductor switching element V1 First voltage V2 Second voltage Vu, Vv, Vw output voltage

Claims (14)

  1. 　直流電力をｎ相の交流電力に変換する電力変換器であって、
     ｎ相の出力電圧とｎ相の出力電流とを出力するｎ個の出力端子と、
     第１の電圧が印加される第１電源端子と、
     前記第１の電圧よりも低い第２の電圧が印加される第２電源端子と、
     ２つの半導体スイッチング素子が直列に接続されているｎ個の直列体とを備え、
     ｎは、交流出力の相数であって、３以上の奇数であり、
     前記ｎ個の直列体は、互いに並列に接続されており、
     前記ｎ個の直列体の各々は、一端が前記第１電源端子に接続されており、他端が前記第２電源端子に接続されており、
     前記ｎ個の直列体の各々は、
     前記第１電源端子に接続される第１半導体スイッチング素子と、
     前記第２電源端子に接続される第２半導体スイッチング素子とを有し、
     前記第１半導体スイッチング素子と前記第２半導体スイッチング素子とは接続点において接続されており、
     前記ｎ個の直列体の各々における前記接続点が、前記ｎ個の出力端子に接続されており、
     前記第１半導体スイッチング素子は、前記交流出力の周波数よりも高い周波数でオンとオフとが切り替えられ、
     前記第２半導体スイッチング素子は、前記交流出力の周波数よりも高い周波数でオンとオフとが切り替えられ、
     ｎ相の交流出力の１周期の間に、前記交流出力のうち少なくとも１相が、前記第１半導体スイッチング素子がオンに固定される第１オン固定期間と、前記第２半導体スイッチング素子がオンに固定される第２オン固定期間との少なくとも一方を有する保護動作モードを有し、
     前記保護動作モードにおいて、ｎ相のうち少なくとも１相において、前記第１オン固定期間が、他のいずれか１相の前記第１オン固定期間と異なるか、または前記第２オン固定期間が、他のいずれか１相の前記第２オン固定期間と異なる、電力変換器。     A power converter that converts DC power into n-phase AC power,
    n output terminals for outputting n-phase output voltages and n-phase output currents;
    a first power supply terminal to which a first voltage is applied;
    a second power supply terminal to which a second voltage lower than the first voltage is applied;
    and n series bodies in which two semiconductor switching elements are connected in series,
    n is the number of phases of the AC output and is an odd number of 3 or more,
    The n series bodies are connected in parallel with each other,
    Each of the n series bodies has one end connected to the first power terminal and the other end connected to the second power terminal,
    Each of the n serial bodies is
    a first semiconductor switching element connected to the first power supply terminal;
    a second semiconductor switching element connected to the second power supply terminal;
    the first semiconductor switching element and the second semiconductor switching element are connected at a connection point,
    the connection point in each of the n series bodies is connected to the n output terminals;
    The first semiconductor switching element is switched on and off at a frequency higher than the frequency of the AC output,
    The second semiconductor switching element is switched on and off at a frequency higher than the frequency of the AC output,
    During one cycle of the n-phase AC output, at least one phase of the AC output has a first fixed ON period during which the first semiconductor switching element is fixed ON and the second semiconductor switching element is ON. a protected operation mode having at least one of a fixed second ON fixed period;
    In the protection operation mode, in at least one of the n phases, the first fixed ON period is different from the first fixed ON period of any one of the other phases, or the second fixed ON period is different from the first fixed ON period of any other phase. A power converter that is different from the second fixed ON period of any one phase of .
  2. 　ＰＷＭデューティ波形が異なる複数の動作モードを有するとともに、電力変換中に前記複数の動作モードの切り替えを行う機能を有し、
     前記複数の動作モードのうち少なくとも１つは、前記保護動作モードである、請求項１に記載の電力変換器。     Having a plurality of operation modes with different PWM duty waveforms, and having a function of switching between the plurality of operation modes during power conversion,
    2. The power converter of claim 1, wherein at least one of said plurality of operating modes is said protected operating mode.
  3. 　前記保護動作モードは、
     前記交流出力の１周期の間に、各相が占める前記第１オン固定期間および前記第２オン固定期間のうち少なくとも一方の比率が異なる複数の保護動作パターンを有する、請求項２に記載の電力変換器。     The protection operation mode is
    3. The power according to claim 2, having a plurality of protection operation patterns in which the ratio of at least one of the first fixed ON period and the second fixed ON period occupied by each phase differs during one cycle of the AC output. converter.
  4. 　複数の前記保護動作モードおよび前記複数の保護動作パターンの切り替えは、前記第１半導体スイッチング素子または前記第２半導体スイッチング素子の少なくとも一方の温度情報に基づいて行う、請求項３に記載の電力変換器。 4. The power converter according to claim 3, wherein said plurality of protection operation modes and said plurality of protection operation patterns are switched based on temperature information of at least one of said first semiconductor switching element and said second semiconductor switching element. .
  5. 　前記保護動作モードは、少なくとも４種類の保護動作パターンを有する、請求項３または請求項４に記載の電力変換器。 The power converter according to claim 3 or 4, wherein the protection operation mode has at least four types of protection operation patterns.
  6. 　前記交流出力の１周期は複数の期間に分割され、前記複数の期間はそれぞれ、いずれかの相の前記第１オン固定期間またはいずれかの相の前記第２オン固定期間である、請求項１から請求項５のいずれか１項に記載の電力変換器。 2. One cycle of the AC output is divided into a plurality of periods, and each of the plurality of periods is the first fixed ON period of any phase or the second fixed ON period of any phase. 6. A power converter according to any one of claims 1 to 5.
  7. 　いずれか１相の前記第１オン固定期間が他の相の前記第１オン固定期間よりも長く、且つ、いずれか１相の前記第２オン固定期間が他の相の前記第２オン固定期間よりも長い、請求項１から請求項６のいずれか１項に記載の電力変換器。 The first fixed ON period of any one phase is longer than the first fixed ON period of the other phase, and the second fixed ON period of any one phase is the second fixed ON period of the other phase 7. A power converter as claimed in any one of claims 1 to 6 which is longer than .
  8. 　他の相の前記第１オン固定期間よりも前記第１オン固定期間が長い相の前記第１オン固定期間および他の相の前記第２オン固定期間よりも前記第２オン固定期間が長い相の前記第２オン固定期間がともに、π／ｎよりも長く、２π／ｎ以下である、請求項７に記載の電力変換器。 The first fixed ON period of the phase whose first fixed ON period is longer than the first fixed ON period of the other phase and the phase whose second fixed ON period is longer than the second fixed ON period of the other phase 8 . The power converter according to claim 7 , wherein both said second fixed ON periods of are longer than π/n and equal to or less than 2π/n.
  9. 　他の相の前記第１オン固定期間よりも前記第１オン固定期間が長い相の前記第１オン固定期間および他の相の前記第２オン固定期間よりも前記第２オン固定期間が長い相の前記第２オン固定期間がともに、２π／ｎであり、他の相の前記第１オン固定期間よりも前記第１オン固定期間が長い相の前記第１オン固定期間と他の相の前記第２オン固定期間よりも前記第２オン固定期間が長い相の前記第２オン固定期間とが互いに連続しない、請求項８に記載の電力変換器。 The first fixed ON period of the phase whose first fixed ON period is longer than the first fixed ON period of the other phase and the phase whose second fixed ON period is longer than the second fixed ON period of the other phase are both 2π/n, and the first fixed ON period of the phase whose first fixed ON period is longer than the first fixed ON period of the other phase and the said first fixed ON period of the other phase 9. The power converter according to claim 8, wherein said second fixed ON period of a phase having said second fixed ON period longer than said second fixed ON period is not continuous with each other.
  10. 　ｎ相のうち２相において、一方の相の前記第１オン固定期間と他方の相の前記第２オン固定期間とが互いに連続しており、前記一方の相の第１オン固定期間と前記他方の相の前記第２オン固定期間との合計が３π／ｎである、請求項１から請求項８のいずれか１項に記載の電力変換器。 In two of the n phases, the first fixed ON period of one phase and the second fixed ON period of the other phase are continuous, and the first fixed ON period of one phase and the other fixed ON period are continuous. 9. The power converter according to any one of claims 1 to 8, wherein the sum of the phases of , with the second on-fixed period is 3?/n.
  11. 　前記一方の相の前記第１オン固定期間および前記他方の相の前記第２オン固定期間とはそれぞれ３π／（２ｎ）である、請求項１０に記載の電力変換器。 11. The power converter according to claim 10, wherein said first fixed ON period of said one phase and said second fixed ON period of said other phase are each 3π/(2n).
  12. 　直流電力をｎ相の交流電力に変換する電力変換器であって、
     前記保護動作モードは、
     １つの相の前記第１半導体スイッチング素子と前記第２半導体スイッチング素子とを保護する第１選択保護動作モードを含み、
     前記第１選択保護動作モードは、１つの相以外の相の前記第１半導体スイッチング素子と前記第２半導体スイッチング素子のうち、ｋ個（ｋは２ｎ－３以下の自然数）の前記第１半導体スイッチング素子または前記第２半導体スイッチング素子を保護する、複数のｋ個保護動作モードを含み、温度情報に基づいて、前記ｋ個保護動作モードの選択を行う、請求項３から請求項９のいずれか１項に記載の電力変換器。     A power converter that converts DC power into n-phase AC power,
    The protection operation mode is
    including a first selective protection operation mode that protects the first semiconductor switching element and the second semiconductor switching element of one phase;
    In the first selective protection operation mode, k (k is a natural number of 2n−3 or less) first semiconductor switching elements among the first semiconductor switching elements and the second semiconductor switching elements of phases other than one phase. 10. Any one of claims 3 to 9, comprising a plurality of k protection operation modes for protecting the element or the second semiconductor switching element, wherein the k protection operation modes are selected based on temperature information. A power converter as described above.
  13. 　直流電力をｎ相の交流電力に変換する電力変換器であって、
     前記保護動作モードは、
     １つの相の前記第１半導体スイッチング素子と、他の相の前記第２半導体スイッチング素子とを保護する第２選択保護動作モードを含み、前記１つの相の前記第１オン固定期間と前記他の相の前記第２オン固定期間とが連続しており、
     前記第２選択保護動作モードは、前記１つの相の前記第１半導体スイッチング素子および前記他の相の前記第２半導体スイッチング素子以外の前記第１半導体スイッチング素子および前記第２半導体スイッチング素子のうち、ｋ個（ｋは２ｎ－３以下の自然数）の前記第１半導体スイッチング素子または前記第２半導体スイッチング素子を保護する、複数のｋ個保護動作モードを含み、温度情報に基づいて、前記ｋ個保護動作モードの選択を行う、請求項３から請求項８および請求項１０から請求項１１のいずれか１項に記載の電力変換器。     A power converter that converts DC power into n-phase AC power,
    The protection operation mode is
    a second selective protection operation mode for protecting the first semiconductor switching element of one phase and the second semiconductor switching element of another phase, wherein the first fixed ON period of the one phase and the other the second on-fixed period of the phase is continuous;
    In the second selective protection operation mode, of the first semiconductor switching element and the second semiconductor switching element other than the first semiconductor switching element of the one phase and the second semiconductor switching element of the other phase, including a plurality of k protection operation modes for protecting the k first semiconductor switching elements or the second semiconductor switching elements (k is a natural number of 2n−3 or less), and the k protection is based on temperature information; 12. A power converter as claimed in any one of claims 3 to 8 and 10 to 11 to provide operation mode selection.
  14. 　請求項１から請求項１３のいずれか１項に記載の電力変換器と、
     前記電力変換器の出力が入力されるモータとを備える、モータモジュール。     A power converter according to any one of claims 1 to 13;
    A motor module to which the output of the power converter is input.
PCT/JP2021/022217 2021-03-31 2021-06-10 Power converter and motor module WO2022208909A1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014220936A (en) * 2013-05-09 2014-11-20 三菱電機株式会社 Motor drive and exhaust fan
WO2017086310A1 (en) * 2015-11-16 2017-05-26 アイシン・エィ・ダブリュ株式会社 Electric power conversion device
JP2019103315A (en) * 2017-12-06 2019-06-24 トヨタ自動車株式会社 Driving unit

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014220936A (en) * 2013-05-09 2014-11-20 三菱電機株式会社 Motor drive and exhaust fan
WO2017086310A1 (en) * 2015-11-16 2017-05-26 アイシン・エィ・ダブリュ株式会社 Electric power conversion device
JP2019103315A (en) * 2017-12-06 2019-06-24 トヨタ自動車株式会社 Driving unit

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