WO2022208909A1 - Power converter and motor module - Google Patents
Power converter and motor module Download PDFInfo
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- WO2022208909A1 WO2022208909A1 PCT/JP2021/022217 JP2021022217W WO2022208909A1 WO 2022208909 A1 WO2022208909 A1 WO 2022208909A1 JP 2021022217 W JP2021022217 W JP 2021022217W WO 2022208909 A1 WO2022208909 A1 WO 2022208909A1
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- 239000004065 semiconductor Substances 0.000 claims abstract description 805
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- 238000010586 diagram Methods 0.000 description 231
- 230000020169 heat generation Effects 0.000 description 92
- 238000000034 method Methods 0.000 description 76
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 30
- FFBHFFJDDLITSX-UHFFFAOYSA-N benzyl N-[2-hydroxy-4-(3-oxomorpholin-4-yl)phenyl]carbamate Chemical compound OC1=C(NC(=O)OCC2=CC=CC=C2)C=CC(=C1)N1CCOCC1=O FFBHFFJDDLITSX-UHFFFAOYSA-N 0.000 description 6
- 230000007423 decrease Effects 0.000 description 6
- 239000000498 cooling water Substances 0.000 description 5
- 239000003990 capacitor Substances 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 230000005669 field effect Effects 0.000 description 2
- 230000017525 heat dissipation Effects 0.000 description 2
- 230000001629 suppression Effects 0.000 description 2
- 238000004364 calculation method Methods 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
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- 238000001816 cooling Methods 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
Definitions
- the present invention relates to power converters and motor modules.
- a motor control device that drives a three-phase motor is known (for example, Patent Document 1).
- the temperature rise of the switching element is suppressed by fixing each phase voltage of the three-phase voltage to 2 ⁇ /3 or ⁇ /3.
- the present invention has been made in view of the above problems, and its object is to simultaneously suppress the heat generation of the first semiconductor switching element of a certain phase and the heat generation of the second semiconductor switching element of a certain phase, thereby suppressing the temperature rise of the power converter.
- An object of the present invention is to provide a power converter and a motor module capable of suppressing and improving reliability.
- An exemplary power converter of the present invention converts DC power into n-phase AC power.
- the power converter includes n output terminals, a first power terminal, a second power terminal, and n series bodies.
- the n output terminals output n-phase output voltages and n-phase output currents.
- a first voltage is applied to the first power supply terminal.
- a second voltage lower than the first voltage is applied to the second power supply terminal.
- the n series bodies are formed by connecting two semiconductor switching elements in series.
- n is the number of AC output phases and is an odd number of 3 or more.
- the n series bodies are connected in parallel with each other. One end of each of the n series bodies is connected to the first power supply terminal.
- Each of the n series bodies has the other end connected to the second power supply terminal.
- Each of the n series bodies has a first semiconductor switching element and a second semiconductor switching element.
- the first semiconductor switching element is connected to the first power terminal.
- the second semiconductor switching element is connected to the second power terminal.
- the first semiconductor switching element and the second semiconductor switching element are connected at a connection point.
- the connection points in each of the n series bodies are connected to the n output terminals.
- the first semiconductor switching element is switched on and off at a frequency higher than the frequency of the AC output.
- the second semiconductor switching element is switched on and off at a frequency higher than the frequency of the AC output.
- at least one phase of the AC output has a first fixed ON period during which the first semiconductor switching element is fixed ON and the second semiconductor switching element is ON.
- It has a protection mode of operation having at least one of a fixed second ON fixed period.
- the first fixed ON period is different from the first fixed ON period of any one of the other phases, or the second fixed ON period is different from the first fixed ON period of any other phase. is different from the second on-fixed period of any one phase.
- An exemplary motor module of the present invention includes the power converter described above and a motor. The output of the power converter is input to the motor.
- the exemplary present invention by simultaneously suppressing the heat generation of the first semiconductor switching element of a certain phase and the heat generation of the second semiconductor switching element of a certain phase, it is possible to suppress the temperature rise of the power converter and improve the reliability. .
- FIG. 1 is a block diagram of a motor module according to an embodiment of the invention.
- FIG. 2 is a circuit diagram showing an inverter section.
- FIG. 3A is a diagram showing the output voltage.
- FIG. 3B is a diagram showing switching losses.
- FIG. 4 is a table showing the relationship between waveform examples and switching loss.
- FIG. 5A is a diagram showing the output voltage.
- FIG. 5B is a diagram showing switching losses.
- FIG. 6A is a diagram showing the output voltage.
- FIG. 6B is a diagram showing switching losses.
- FIG. 7A is a diagram showing the output voltage.
- FIG. 7B is a diagram showing switching losses.
- FIG. 8A is a diagram showing the output voltage.
- FIG. 8B is a diagram showing switching losses.
- FIG. 9A is a diagram showing the output voltage.
- FIG. 9B is a diagram showing switching losses.
- FIG. 10A is a diagram showing the output voltage.
- FIG. 10B is a diagram showing switching losses.
- FIG. 11A is a diagram showing output voltages.
- FIG. 11B is a diagram showing switching loss.
- FIG. 12A is a diagram showing the output voltage.
- FIG. 12B is a diagram showing switching losses.
- FIG. 13A is a diagram showing the output voltage.
- FIG. 13B is a diagram showing switching losses.
- FIG. 14A is a diagram showing the output voltage.
- FIG. 14B is a diagram showing switching losses.
- FIG. 15A is a diagram showing output voltages.
- FIG. 15B is a diagram showing switching losses.
- FIG. 16 is a diagram showing switching loss.
- FIG. 17 is a diagram for explaining switching of the UH_UL protection waveform.
- FIG. 18 is a diagram for explaining switching of the UH_UL protection waveform.
- FIG. 19 is a diagram showing switching loss.
- FIG. 20 is a diagram for explaining switching of the UH_UL protection waveform.
- FIG. 21 is a flow chart showing a protection waveform switching method.
- FIG. 22 is a flow chart showing a protection waveform switching method.
- FIG. 23 is a diagram showing a method of switching guard waveforms.
- FIG. 24 is a diagram showing a method of switching guard waveforms.
- FIG. 25 is a table showing the relationship between waveform examples and switching loss.
- FIG. 26A is a diagram showing the output voltage.
- FIG. 26B is a diagram showing switching loss.
- FIG. 27A is a diagram showing the output voltage.
- FIG. 27B is a diagram showing switching losses.
- FIG. 28A is a diagram showing the output voltage.
- FIG. 28B is a diagram showing switching losses.
- FIG. 29A is a diagram showing the output voltage.
- FIG. 29B is a diagram showing switching losses.
- FIG. 30A is a diagram showing the output voltage.
- FIG. 30B is a diagram showing switching losses.
- FIG. 31A is a diagram showing the output voltage.
- FIG. 31B is a diagram showing switching losses.
- FIG. 32A is a diagram showing the output voltage.
- FIG. 32B is a diagram showing switching losses.
- FIG. 33A is a diagram showing the output voltage.
- FIG. 33B is a diagram showing switching losses.
- FIG. 34A is a diagram showing the output voltage.
- FIG. 34A is a diagram showing the output voltage.
- FIG. 34A is a diagram showing the output voltage.
- FIG. 34A is
- FIG. 34B is a diagram showing switching losses.
- FIG. 35A is a diagram showing the output voltage.
- FIG. 35B is a diagram showing switching losses.
- FIG. 36A is a diagram showing the output voltage.
- FIG. 36B is a diagram showing switching losses.
- FIG. 37A is a diagram showing the output voltage.
- FIG. 37B is a diagram showing switching losses.
- FIG. 38A is a diagram showing the output voltage.
- FIG. 38B is a diagram showing switching losses.
- FIG. 39A is a diagram showing the output voltage.
- FIG. 39B is a diagram showing switching losses.
- FIG. 40A is a diagram showing the output voltage.
- FIG. 40B is a diagram showing switching losses.
- FIG. 41A is a diagram showing the output voltage.
- FIG. 41B is a diagram showing switching losses.
- FIG. 41A is a diagram showing the output voltage.
- FIG. 41B is a diagram showing switching losses.
- FIG. 41A is a diagram
- FIG. 42A is a diagram showing the output voltage.
- FIG. 42B is a diagram showing switching losses.
- FIG. 43 is a diagram showing switching loss.
- FIG. 44 is a diagram for explaining switching of the UH_VL protection waveform.
- FIG. 45 is a diagram for explaining switching of the UH_VL protection waveform.
- FIG. 46 is a diagram for explaining switching of the UH_VL protection waveform.
- FIG. 47 is a flow chart showing a protection waveform switching method.
- FIG. 48 is a diagram showing a method of switching guard waveforms.
- FIG. 49 is a diagram showing a method of switching guard waveforms.
- FIG. 50A is a diagram showing the output voltage.
- FIG. 50B is a diagram showing switching losses.
- FIG. 51A is a diagram showing output voltages.
- FIG. 51A is a diagram showing output voltages.
- FIG. 51B is a diagram showing switching loss.
- FIG. 52A is a diagram showing the output voltage.
- FIG. 52B is a diagram showing switching losses.
- FIG. 53A is a diagram showing the output voltage.
- FIG. 53B is a diagram showing switching losses.
- FIG. 54A is a diagram showing the output voltage.
- FIG. 54B is a diagram showing switching losses.
- FIG. 55A is a diagram showing the output voltage.
- FIG. 55B is a diagram showing switching losses.
- FIG. 56A is a diagram showing the output voltage.
- FIG. 56B is a diagram showing switching losses.
- FIG. 57A is a diagram showing the output voltage.
- FIG. 57B is a diagram showing switching losses.
- FIG. 58A is a diagram showing the output voltage.
- FIG. 58B is a diagram showing switching losses.
- FIG. 59A is a diagram showing the output voltage.
- FIG. 59B is a diagram showing switching losses.
- FIG. 60A is a diagram showing the output voltage.
- FIG. 60B is a diagram showing switching losses.
- FIG. 61A is a diagram showing the output voltage.
- FIG. 61B is a diagram showing switching losses.
- FIG. 62A is a diagram showing the output voltage.
- FIG. 62B is a diagram showing switching losses.
- FIG. 63A is a diagram showing the output voltage.
- FIG. 63B is a diagram showing switching losses.
- FIG. 64A is a diagram showing the output voltage.
- FIG. 64B is a diagram showing switching losses.
- FIG. 65A is a diagram showing the output voltage.
- FIG. 65B is a diagram showing switching losses.
- FIG. 66A is a diagram showing the output voltage.
- FIG. 66B is a diagram showing switching losses.
- FIG. 1 is a block diagram of a motor module 200 according to an embodiment of the invention.
- FIG. 2 is a circuit diagram showing the inverter section 110. As shown in FIG.
- the motor module 200 includes a motor drive circuit 100 and a three-phase motor M.
- a three-phase motor M is driven by a motor drive circuit 100 .
- the three-phase motor M is, for example, a brushless DC motor.
- a three-phase motor M has a U-phase, a V-phase and a W-phase.
- the output of the motor drive circuit 100 is input to the three-phase motor M.
- the motor drive circuit 100 corresponds to an example of a "power converter".
- the motor drive circuit 100 controls driving of the three-phase motor M.
- the motor drive circuit 100 includes an inverter section 110 and a signal generation section 120 .
- the motor drive circuit 100 converts DC power into n-phase AC power.
- n is the number of AC output phases and is an integer of 3 or more.
- the motor drive circuit 100 converts DC power into three-phase AC power.
- the motor drive circuit 100 has n output terminals 102 .
- the motor drive circuit 100 has three output terminals 102 .
- the three output terminals 102 include an output terminal 102u, an output terminal 102v, and an output terminal 102w.
- the n output terminals 102 output n-phase output voltages and n-phase output currents.
- the three output terminals 102 output three-phase output voltages and three-phase output currents to the three-phase motor M.
- the output terminal 102u outputs the U-phase output voltage Vu and the U-phase output current Iu to the three-phase motor M.
- Output terminal 102v outputs V-phase output voltage Vv and V-phase output current Iv to three-phase motor M.
- FIG. The output terminal 102w outputs the W-phase output voltage Vw and the W-phase output current Iw to the three-phase motor M.
- the motor drive circuit 100 includes a first power terminal P, a second power terminal N, a capacitor C, n series bodies 112, and six temperature sensors 20.
- the motor drive circuit 100 includes a first power terminal P, a second power terminal N, a capacitor C, three series bodies 112 and six temperature sensors 20 .
- the motor drive circuit 100 includes an inverter section 110.
- the inverter section 110 includes a first power terminal P, a second power terminal N, a capacitor C, and three series bodies. 112 and six temperature sensors 20 .
- Inverter section 110 further includes a DC voltage source B.
- the DC voltage source B may be provided outside the inverter section 110 .
- a first voltage V1 is applied to the first power supply terminal P.
- a first power supply terminal P is connected to a DC voltage source B;
- a second voltage V2 is applied to the second power supply terminal N.
- a second power supply terminal N is connected to a DC voltage source B. As shown in FIG. The second voltage V2 is lower than the first voltage V1.
- the capacitor C is connected between the first power terminal P and the second power terminal N.
- the semiconductor switching element is, for example, an IGBT (insulated gate bipolar transistor). Note that the semiconductor switching element may be another transistor such as a field effect transistor.
- the three series bodies 112 include a series body 112u, a series body 112v, and a series body 112w. The three series bodies 112 are connected in parallel with each other. Each of the three series bodies 112 is connected to the first power terminal P at one end. Each of the three series bodies 112 is connected to the second power terminal N at the other end.
- a rectifying element D is connected in parallel to each of these semiconductor switching elements, with the first power supply terminal P side (upper side of the paper) as a cathode and the second power supply terminal N side (lower side of the paper) as an anode. If a field effect transistor is used as the semiconductor switching element, a parasitic diode may be used as this rectifying element.
- Each of the three series bodies 112 has a first semiconductor switching element and a second semiconductor switching element.
- the series body 112u has a first semiconductor switching element Up and a second semiconductor switching element Un.
- Series body 112v has a first semiconductor switching element Vp and a second semiconductor switching element Vn.
- the series body 112w has a first semiconductor switching element Wp and a second semiconductor switching element Wn.
- the first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp are connected to the first power supply terminal P.
- the first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp are semiconductor switching elements on the high voltage side.
- the second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn are connected to the second power supply terminal N.
- the second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn are semiconductor switching elements on the low voltage side.
- the first semiconductor switching element and the second semiconductor switching element are connected at the connection point 114 .
- the first semiconductor switching element Up and the second semiconductor switching element Un are connected at a connection point 114u.
- the first semiconductor switching element Vp and the second semiconductor switching element Vn are connected at a connection point 114v.
- the first semiconductor switching element Wp and the second semiconductor switching element Wn are connected at a connection point 114w.
- connection point 114 in each of the three series bodies 112 is connected to the three output terminals 102 .
- a connection point 114u in the series body 112u is connected to the output terminal 102u.
- a connection point 114v in the series body 112v is connected to the output terminal 102v.
- a connection point 114w in the series body 112w is connected to the output terminal 102w.
- a PWM signal is input to the first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp.
- a PWM signal is output from the signal generator 120 .
- the PWM signal input to the first semiconductor switching element Up may be referred to as "UpPWM signal”.
- the PWM signal input to the first semiconductor switching element Vp may be referred to as "Vp PWM signal”.
- a PWM signal input to the first semiconductor switching element Wp may be referred to as a "Wp PWM signal”.
- the first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp are switched on and off at a frequency higher than the frequency of the AC output.
- the first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp are turned on when the UpPWM signal, the VpPWM signal, and the WpPWM signal are at HIGH level, respectively.
- the first semiconductor switching element Up, the first semiconductor switching element Vp and the first semiconductor switching element Wp are turned off when the UpPWM signal, the VpPWM signal and the WpPWM signal are at LOW level, respectively.
- a PWM signal is input to the second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn.
- a PWM signal is output from the signal generator 120 .
- the PWM signal input to the second semiconductor switching element Un may be referred to as "UnPWM signal”.
- the PWM signal input to the second semiconductor switching element Vn may be referred to as "Vn PWM signal”.
- a PWM signal input to the second semiconductor switching element Wn may be referred to as a "Wn PWM signal”.
- the second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn are switched on and off at a frequency higher than the frequency of the AC output.
- the second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn are turned on when the UnPWM signal, the VnPWM signal, and the WnPWM signal are at HIGH level, respectively.
- the second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn are turned off when the UnPWM signal, the VnPWM signal, and the WnPWM signal are at LOW level, respectively.
- the signal generation section 120 has a carrier generation section 122, a voltage command value generation section 124, and a comparison section 126.
- the signal generator 120 is a hardware circuit configured by a processor such as a CPU (Central Processing Unit) and an ASIC (Application Specific Integrated Circuit).
- the processor of signal generation unit 120 functions as carrier generation unit 122, voltage command value generation unit 124, and comparison unit 126 by executing computer programs stored in the storage device.
- the signal generation section 120 controls the inverter section 110 . Specifically, the signal generation unit 120 controls the inverter unit 110 by generating a PWM signal and outputting the PWM signal. More specifically, signal generator 120 generates a PWM signal to be input to each of three serial bodies 112 .
- the carrier generator 122 generates a carrier signal.
- a carrier signal is, for example, a triangular wave. Note that the carrier signal may be a sawtooth wave.
- the voltage command value generation unit 124 generates a voltage command value.
- a voltage command value corresponds to a voltage value output from the motor drive circuit 100 . That is, voltage command value generation unit 124 generates voltage values corresponding to output voltage Vu, output voltage Vv, and output voltage Vw as voltage command values.
- the comparator 126 generates a PWM signal by comparing the carrier signal and the voltage command value.
- the six temperature sensors 20 include a temperature sensor 21u, a temperature sensor 21v, a temperature sensor 21w, a temperature sensor 22u, a temperature sensor 22v, and a temperature sensor 22w.
- Six temperature sensors 20 are arranged in the vicinity of the semiconductor switching elements. Six temperature sensors 20 detect the temperature of the semiconductor switching elements. Specifically, the temperature sensor 21u is arranged near the first semiconductor switching element Up. The temperature sensor 21u detects the temperature of the first semiconductor switching element Up. The temperature sensor 21v is arranged near the first semiconductor switching element Vp. The temperature sensor 21v detects the temperature of the first semiconductor switching element Vp. The temperature sensor 21w is arranged near the first semiconductor switching element Wp. The temperature sensor 21w detects the temperature of the first semiconductor switching element Wp.
- the temperature sensor 22u is arranged near the second semiconductor switching element Un.
- the temperature sensor 22u detects the temperature of the second semiconductor switching element Un.
- the temperature sensor 22v is arranged near the second semiconductor switching element Vn.
- Temperature sensor 22v detects the temperature of second semiconductor switching element Vn.
- the temperature sensor 22w is arranged near the second semiconductor switching element Wn.
- the temperature sensor 22w detects the temperature of the second semiconductor switching element Wn.
- FIG. 3A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 3B is a diagram showing switching losses. The switching loss of each element is shown as a relative value when the switching loss per switching element is 1 in the case of three-phase modulation in which all three phases are switched.
- FIG. 3A shows waveform example 1 of the output voltage Vu, the output voltage Vv, and the output voltage Vw according to the embodiment of the present invention.
- the output voltage Vu is indicated by a solid line
- the output voltage Vv is indicated by a dashed line
- the output voltage Vw is indicated by a dashed line.
- the vertical axis of FIG. 3A represents the voltage value normalized by the input voltage V1-V2, and the output voltage of each phase takes a value in the range of 0-1.
- Output voltage 0 is the state in which the output voltage substantially matches V2
- output voltage 1 is the state in which the output voltage substantially matches V1.
- This value also represents the duty value, which is the ratio of the ON time of the first semiconductor switching element of each phase to the PWM cycle.
- the value obtained by subtracting the value on the vertical axis from 1 is the ratio of the ON time of the second semiconductor switching element to the PWM cycle.
- complementary switching is performed after providing an appropriate dead time to prevent both from being turned on at the same time.
- the horizontal axis of FIG. 3A represents the electrical rotation angle of the motor in degrees.
- a waveform example 1 of the output voltage Vu, the output voltage Vv, and the output voltage Vw according to the embodiment of the present invention will be described with reference to FIG. 3A.
- waveform example 1 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 30 degrees to 150 degrees. Also, the waveform is such that the output of any one phase is fixed to 0 at an electrical angle of 0 to 30 electrical degrees and at an electrical angle of 150 to 360 electrical degrees.
- the period during which the output of any one phase is fixed to 1 may be referred to as a high-side-on application period T3.
- the period during which the output of any one phase is fixed to 0 may be referred to as a low-side-on application period T4.
- the high-side-on application period is T3 at an electrical angle of 30 degrees to 150 electrical degrees.
- the low side-on application period T4 occurs at an electrical angle of 0 to 30 electrical degrees and at an electrical angle of 150 to 360 electrical degrees.
- the difference between the two phases of the output voltage Vu, the output voltage Vv, and the output voltage Vw is a sine wave. Therefore, a sine wave can be output as the voltage between the output terminals.
- a sine wave can be output as the voltage between the output terminals.
- At least one phase of the AC output has a first fixed ON period T1 and a second fixed ON period T2.
- the first fixed on period T1 is a period in which the first semiconductor switching element is fixed on.
- the second fixed on period T2 is a period during which the second semiconductor switching element is fixed on.
- the first fixed ON period T1 includes the first fixed ON period T1u.
- the first fixed on period T1u is a period in which the first semiconductor switching element Up is fixed on.
- the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees.
- the first fixed ON period T1 only one of the n phases of the first semiconductor switching element is fixed on, and in all of the other n phases, at least one of the first semiconductor switching element and the second semiconductor switching element is fixed. indicates the switching period.
- waveform example 1 in the first fixed on period T1u, only the U-phase first semiconductor switching element Up of the three phases is fixed on, and the V-phase first semiconductor switching element Vp or the second semiconductor switching element Vp of the three phases is fixed. At least one of the elements Vn and at least one of the W-phase first semiconductor switching element Wp or the second semiconductor switching element Wn switches.
- the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
- the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
- the second fixed ON period T2v is from 0 electrical angle to 30 electrical degrees and from 330 electrical degrees to 360 electrical degrees.
- the second fixed ON period T2w is from 150 electrical degrees to 210 electrical degrees.
- the second fixed on period T2 only one of the n phases of the second semiconductor switching element is fixed on, and at least one of the first semiconductor switching element and the second semiconductor switching element is set in all the other phases of the n phases. indicates the switching period.
- waveform example 1 in the second fixed on period T2u, only the U-phase second semiconductor switching element Un among the three phases is fixed on, and the V-phase first semiconductor switching element Vp or the second semiconductor switching element Vp among the three phases is fixed. At least one of the elements Vn and at least one of the W-phase first semiconductor switching element Wp or the second semiconductor switching element Wn switches.
- One cycle of the AC output is divided into a plurality of periods, and each of the plurality of periods is the first fixed ON period of one of the phases or the second fixed ON period of one of the phases.
- the second fixed ON period T2v is between an electrical angle of 0 degree and an electrical angle of 30 degrees.
- the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees.
- the second fixed ON period T2w is from 150 electrical degrees to 210 electrical degrees.
- the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
- the second fixed ON period T2v is from 330 electrical degrees to 360 electrical degrees. Therefore, since the switching of one phase is always stopped, temperature rise can be effectively suppressed, and the reliability of the inverter is enhanced.
- the motor drive circuit 100 has a protection operation mode.
- the protection operation mode has at least one of the first fixed ON period T1 and the second fixed ON period T2.
- the first fixed ON period T1 is different from the first fixed ON period T1 of any one of the other phases, or the second fixed ON period T2 is different from the first fixed ON period T1 of any other phase. is different from the second on-fixed period T2 of any one phase. This also includes the case where any other phase does not have the first fixed ON period T1 and the second fixed ON period T2.
- the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 1, the first fixed ON period T1u is 120 degrees, but there is no first fixed ON period T1v and no first fixed ON period T1w. That is, in Waveform Example 1, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 3B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
- the second fixed ON period T2u differs from the second fixed ON period T2v and the second fixed ON period T2w in the U phase among the three phases.
- the second fixed ON period T2u is 120 degrees, while the second fixed ON period T2v and the second fixed ON period T2w are 60 degrees. That is, in Waveform Example 1, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 3B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
- the first fixed ON period T1 is set to the first ON period of the other phases. It differs from the fixed period T1. Therefore, heat generation of the first semiconductor switching element of the phase having the first fixed ON period longer than the first fixed ON period T1 of the other phase can be suppressed.
- the second fixed ON period T2 is different from the second fixed ON periods T2 of the other phases. Therefore, heat generation of the second semiconductor switching element of the phase having the second fixed ON period longer than the second fixed ON period T2 of the other phase can be suppressed.
- the first fixed ON period T1 is different from the first fixed ON periods T1 of other phases
- the second fixed ON period T2 is different from that of the other phase. It is different from the second on-fixed period T2 of the phase. Therefore, by simultaneously suppressing the heat generation of the first semiconductor switching element of a certain phase and the heat generation of the second semiconductor switching element of a certain phase, temperature rise of the power converter (inverter) can be suppressed and reliability can be improved.
- the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase may have heat-generating components in their vicinity, or may be arranged in positions with poor heat dissipation efficiency.
- the switching heat generation of these two elements can be suppressed using the method of Waveform Example 1 to prevent the temperature of these two elements from rising excessively and improve the reliability of the power converter (inverter). can be enhanced.
- waveform example 1 the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un can be suppressed at the same time.
- the V-phase second semiconductor switching element Vn and the W Heat generation with the second semiconductor switching element Wn of the phase can also be suppressed at the same time. Therefore, when the temperature of the U phase is most likely to rise and the temperature of the second semiconductor switching elements of the other phases is likely to rise next, overheating of these elements is prevented to improve reliability.
- the first fixed ON period of any one phase is longer than the first fixed ON period of the other phase
- the second fixed ON period of any one phase is longer than the second fixed ON period of the other phase. long. Therefore, when the temperature of a specific phase becomes a problem due to a problem in the cooling water passage or the like, the heat generation of that phase can be suppressed, thereby increasing the reliability of the inverter.
- a stall occurs and current continuously flows through the first semiconductor switching element of a certain phase and the second semiconductor switching element of another phase and the temperature rises, this operation is performed when exiting the stall and starting operation. By doing so, it is possible to suppress the heat generation of the semiconductor switching elements whose temperature has risen under the stall condition, and to quickly lower the temperature, thereby increasing the reliability of the inverter.
- FIG. 4 is a table showing the relationship between waveform examples and switching loss.
- UH represents the switching loss of the U-phase first semiconductor switching element Up.
- UL represents the switching loss of the U-phase second semiconductor switching element Un.
- VH represents the switching loss of the V-phase first semiconductor switching element Vp.
- VL represents the switching loss of the V-phase second semiconductor switching element Vn.
- WH represents the switching loss of the W-phase first semiconductor switching element Wp.
- WL represents the switching loss of the W-phase second semiconductor switching element Wn.
- waveform examples 1 to 12 are waveform examples capable of protecting the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un.
- a waveform capable of protecting a first semiconductor switching element (eg Up) of a certain phase (eg U phase) and a second semiconductor switching element (eg Un) of the same phase may be referred to as a UH_UL protection waveform. .
- FIG. 5A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 5B is a diagram showing switching losses.
- waveform example 2 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 0 degree to 180 degrees.
- waveform example 2 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 180 degrees to 360 degrees.
- the high-side-on application period T3 is from 0 electrical angle to 180 electrical degrees.
- the low-side-on application period T4 occurs at an electrical angle of 180 degrees to 360 degrees.
- the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w.
- the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees.
- the first fixed ON period T1v is between 150 electrical degrees and 180 electrical degrees.
- the first ON fixed period T1w is from an electrical angle of 0 degree to an electrical angle of 30 degrees.
- the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
- the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
- the second fixed ON period T2v is from 330 electrical degrees to 360 electrical degrees.
- the second fixed ON period T2w is between 180 electrical degrees and 210 electrical degrees.
- the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 2, the first fixed ON period T1u is 120 degrees, while the first fixed ON period T1v and the first fixed ON period T1w are 30 degrees. That is, in Waveform Example 2, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 5B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
- the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w.
- the second fixed ON period T2u is 120 degrees, while the second fixed ON period T2v and the second fixed ON period T2w are 30 degrees. That is, in Waveform Example 2, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 5B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
- waveform example 2 as well as in waveform example 1, the heat generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved.
- the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un can be suppressed at the same time.
- waveform example 2 as shown in FIG. 5B, the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
- Waveform example 2 can be substituted with waveform example 9 (FIG. 12) described later, which has a higher effect of suppressing heat generation.
- FIG. 6A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 6B is a diagram showing switching losses.
- waveform example 3 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 0 to 210 electrical degrees and at an electrical angle of 330 to 360 electrical degrees.
- waveform example 3 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 210 degrees to 330 degrees.
- the high-side-on application period T3 occurs at an electrical angle of 0 to 210 electrical degrees and at an electrical angle of 330 to 360 electrical degrees.
- the low-side-on application period is T4 at an electrical angle of 210 degrees to 330 electrical degrees.
- the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w.
- the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees.
- the first fixed ON period T1v is between an electrical angle of 150 degrees and an electrical angle of 210 degrees.
- the first fixed ON period T1w is from an electrical angle of 0 degrees to an electrical angle of 30 degrees and from an electrical angle of 330 degrees to an electrical angle of 360 degrees.
- the second fixed ON period T2 includes the second fixed ON period T2u.
- the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
- the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 3, the first fixed ON period T1u is 120 degrees, while the first fixed ON period T1v and the first fixed ON period T1w are 60 degrees. That is, in Waveform Example 3, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 6B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
- the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in Waveform Example 3, the second fixed ON period T2u is 120 degrees, whereas the second fixed ON period T2v and the second fixed ON period T2w are absent. That is, in Waveform Example 3, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 6B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
- Waveform Example 3 As described above with reference to FIGS. 6A and 6B , in Waveform Example 3, as in Waveform Example 1, the heat generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 3, the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un can be suppressed at the same time.
- Waveform Example 3 As shown in FIG. 6B, the heat generation of the V-phase first semiconductor switching element Vp and the W-phase first semiconductor switching element Wp can be suppressed at the same time.
- FIG. 7A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 7B is a diagram showing switching losses.
- waveform example 4 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 30 degrees to 180 degrees.
- waveform example 4 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 to 30 degrees and at an electrical angle of 180 to 360 degrees.
- the high-side-on application period T3 is at an electrical angle of 30 degrees to 180 degrees.
- the low-side-on application period T4 occurs at an electrical angle of 0 to 30 electrical degrees and at an electrical angle of 180 to 360 electrical degrees.
- the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v.
- the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees.
- the first fixed ON period T1v is between 150 electrical degrees and 180 electrical degrees.
- the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
- the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
- the second fixed ON period T2v is from an electrical angle of 0 degree to an electrical angle of 30 degrees and from an electrical angle of 330 degrees to an electrical angle of 360 degrees.
- the second fixed ON period T2w is between 180 electrical degrees and 210 electrical degrees.
- the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 4, the first fixed ON period T1u is 120 degrees, the first fixed ON period T1v is 30 degrees, and there is no first fixed ON period T1w. That is, in Waveform Example 4, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 7B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
- the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w.
- the second fixed ON period T2u is 120 degrees
- the second fixed ON period T2v is 60 degrees
- the second fixed ON period T2w is 30 degrees. That is, in Waveform Example 4, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 7B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
- Waveform Example 4 As described above with reference to FIGS. 7A and 7B, in Waveform Example 4, as in Waveform Example 1, the heat generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 4, the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un can be suppressed at the same time.
- waveform example 4 as shown in FIG. 7B, the heat generated by the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
- Waveform example 4 can be substituted with waveform example 6 (FIG. 9) described later, which has a higher effect of suppressing heat generation.
- FIG. 8A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 8B is a diagram showing switching losses.
- waveform example 5 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 30 degrees to 210 degrees.
- waveform example 5 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 to 30 electrical degrees and at an electrical angle of 210 to 360 electrical degrees.
- the high-side-on application period T3 is at an electrical angle of 30 degrees to 210 degrees.
- the low-side-on application period T4 occurs at an electrical angle of 0 to 30 electrical degrees and at an electrical angle of 210 to 360 electrical degrees.
- the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v.
- the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees.
- the first fixed ON period T1v is between an electrical angle of 150 degrees and an electrical angle of 210 degrees.
- the second fixed ON period T2 includes a second fixed ON period T2u and a second fixed ON period T2v.
- the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
- the second fixed ON period T2v is from 0 electrical angle to 30 electrical degrees and from 330 electrical degrees to 360 electrical degrees.
- the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 5, the first fixed ON period T1u is 120 degrees, the first fixed ON period T1v is 60 degrees, and there is no first fixed ON period T1w. That is, in Waveform Example 5, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 8B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
- the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w.
- the second fixed ON period T2u is 120 degrees
- the second fixed ON period T2v is 60 degrees
- Waveform Example 5 As described above with reference to FIGS. 8A and 8B, in Waveform Example 5 as well as in Waveform Example 1, the heat generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved.
- the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un can be suppressed at the same time.
- FIG. 9A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 9B is a diagram showing switching losses.
- waveform example 6 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 30 degrees to 150 degrees and at an electrical angle of 180 degrees to 210 degrees.
- the output of any one phase is fixed to 0 at an electrical angle of 0 to 30 electrical degrees, 150 to 180 electrical degrees, and 210 to 360 electrical degrees.
- the high-side-on application period T3 occurs at an electrical angle of 30 degrees to 150 degrees and at an electrical angle of 180 degrees to 210 degrees.
- the low side-on application period T4 occurs at an electrical angle of 0 to 30 electrical degrees, 150 to 180 electrical degrees, and 210 to 360 electrical degrees.
- the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v.
- the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees.
- the first fixed ON period T1v is between an electrical angle of 180 degrees and an electrical angle of 210 degrees.
- the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
- the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
- the second fixed ON period T2v is between an electrical angle of 330 degrees and an electrical angle of 360 degrees and between an electrical angle of 0 degrees and an electrical angle of 30 degrees.
- the second fixed ON period T2w is between 150 electrical degrees and 180 electrical degrees.
- the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 6, the first fixed ON period T1u is 120 degrees, the first fixed ON period T1v is 30 degrees, and there is no first fixed ON period T1w. That is, in Waveform Example 6, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 9B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
- the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w.
- the second fixed ON period T2u is 120 degrees
- the second fixed ON period T2v is 60 degrees
- the second fixed ON period T2w is 30 degrees. That is, in Waveform Example 6, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 9B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
- Waveform Example 6 As described above with reference to FIGS. 9A and 9B, in Waveform Example 6, as in Waveform Example 1, the heat generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 6, the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un can be suppressed at the same time.
- FIG. 10A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 10B is a diagram showing switching losses.
- waveform example 7 is a waveform in which the output of any one phase is fixed to 1 in the electrical angle of 0 to 150 electrical degrees and in the electrical angle of 180 to 210 electrical degrees.
- waveform example 7 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 150 degrees to 180 degrees and at an electrical angle of 210 degrees to 360 degrees.
- the high-side-on application period T3 occurs at an electrical angle of 0 to 150 electrical degrees and at an electrical angle of 180 to 210 electrical degrees.
- the low side-on application period T4 occurs at an electrical angle of 150 degrees to 180 degrees and at an electrical angle of 210 degrees to 360 degrees.
- the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w.
- the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees.
- the first fixed ON period T1v is between an electrical angle of 180 degrees and an electrical angle of 210 degrees.
- the first ON fixed period T1w is from 0 electrical angle to 30 electrical degrees.
- the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
- the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
- the second fixed ON period T2v is between 330 electrical degrees and 360 electrical degrees.
- the second fixed ON period T2w is between 150 electrical degrees and 180 electrical degrees.
- the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 7, the first fixed ON period T1u is 120 degrees, while the first fixed ON period T1v and the first fixed ON period T1w are 30 degrees. That is, in Waveform Example 7, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 10B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
- the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w.
- the second fixed ON period T2u is 120 degrees, while the second fixed ON period T2v and the second fixed ON period T2w are 30 degrees. That is, in Waveform Example 7, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 10B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
- Waveform Example 7 As described above with reference to FIGS. 10A and 10B , in Waveform Example 7, as in Waveform Example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 7, the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un can be suppressed at the same time.
- waveform example 7 as shown in FIG. 10B, the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
- Waveform example 7 can be substituted with waveform example 9 (FIG. 12), which will be described later and has a higher effect of suppressing heat generation.
- FIG. 11A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 11B is a diagram showing switching loss.
- Waveform Example 8 the output voltage of any one phase is fixed to 1 in a certain electrical angle section according to the electrical angle, and the output voltage of any one phase is fixed to 1 in another electrical angle section. is fixed to 0. Specifically, in waveform example 8, the output of any one phase is fixed to 1 at an electrical angle of 0 to 150 degrees, from 180 to 210 electrical degrees, and from 330 to 360 electrical degrees. waveform. Waveform example 8 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 150 degrees to 180 degrees and at an electrical angle of 210 degrees to 330 degrees.
- the high side-on application period T3 is at the electrical angle of 0 to 150 electrical degrees, the electrical angle of 180 to 210 electrical degrees, and the electrical angle of 330 to 360 electrical degrees. Further, in Waveform Example 8, the low side-on application period T4 occurs at an electrical angle of 150 degrees to 180 degrees and at an electrical angle of 210 degrees to 330 degrees.
- the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w.
- the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees.
- the first fixed ON period T1v is between an electrical angle of 180 degrees and an electrical angle of 210 degrees.
- the first fixed ON period T1w is from an electrical angle of 0 degrees to an electrical angle of 30 degrees and from an electrical angle of 330 degrees to an electrical angle of 360 degrees.
- the second fixed ON period T2 includes a second fixed ON period T2u and a second fixed ON period T2w.
- the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
- the second fixed ON period T2w is between 150 electrical degrees and 180 electrical degrees.
- the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 8, the first fixed ON period T1u is 120 degrees, the first fixed ON period T1v is 30 degrees, and the first fixed ON period T1w is 60 degrees. That is, in Waveform Example 8, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 11B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
- the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w.
- the second fixed ON period T2u is 120 degrees
- the second fixed ON period T2v is absent and the second fixed ON period T2w is 30 degrees. That is, in Waveform Example 8, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 11B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
- Waveform Example 8 As described above with reference to FIGS. 11A and 11B, in Waveform Example 8, as in Waveform Example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 8, the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un can be suppressed at the same time.
- waveform example 8 as shown in FIG. 11B, the heat generated by the V-phase first semiconductor switching element Vp, the W-phase first semiconductor switching element Wp, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
- FIG. 12A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 12B is a diagram showing switching losses.
- waveform example 9 the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, in waveform example 9, the output of any one phase is fixed to 1 at an electrical angle of 30 degrees to 150 degrees, from 180 degrees to 210 degrees, and from 330 degrees to 360 degrees. waveform. Further, waveform example 9 corresponds to an electrical angle of 0 degree to an electrical angle of 30 degrees, an electrical angle of 150 degrees to an electrical angle of 180 degrees, and an electrical angle of 210 degrees to an electrical angle of 330 degrees.
- the electrical angle of 180 degrees to 210 degrees, and the electrical angle of 330 degrees to 360 degrees are the high side-on application period T3. Further, in waveform example 9, the low side-on application period T4 occurs at an electrical angle of 0 to 30 electrical degrees, 150 to 180 electrical degrees, and 210 to 330 electrical degrees.
- the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w.
- the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees.
- the first fixed ON period T1v is between an electrical angle of 180 degrees and an electrical angle of 210 degrees.
- the first fixed ON period T1w is from 330 electrical degrees to 360 electrical degrees.
- the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
- the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
- the second fixed ON period T2v is from an electrical angle of 0 degrees to an electrical angle of 30 degrees.
- the second fixed ON period T2w is between 150 electrical degrees and 180 electrical degrees.
- the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 9, the first fixed ON period T1u is 120 degrees, while the first fixed ON period T1v and the first fixed ON period T1w are 30 degrees. That is, in Waveform Example 9, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 12B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
- the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w.
- the second fixed ON period T2u is 120 degrees, while the second fixed ON period T2v and the second fixed ON period T2w are 30 degrees. That is, in Waveform Example 9, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 12B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
- Waveform Example 9 As described above with reference to FIGS. 12A and 12B, in Waveform Example 9, as in Waveform Example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In the waveform example 9, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un.
- the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
- FIG. 13A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 13B is a diagram showing switching losses.
- waveform example 10 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 0 to 150 electrical degrees and at an electrical angle of 330 to 360 electrical degrees.
- waveform example 10 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 150 degrees to 330 degrees.
- the high-side-on application period T3 occurs at an electrical angle of 0 to 150 electrical degrees and at an electrical angle of 330 to 360 electrical degrees.
- the low-side-on application period T4 occurs at an electrical angle of 150 degrees to 330 electrical degrees.
- the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1w.
- the first ON fixed period T1u is from 30 electrical degrees to 150 electrical degrees.
- the first fixed ON period T1w is from an electrical angle of 0 degrees to an electrical angle of 30 degrees and from an electrical angle of 330 degrees to an electrical angle of 360 degrees.
- the second fixed ON period T2 includes a second fixed ON period T2u and a second fixed ON period T2w.
- the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
- the second fixed ON period T2w is between 150 electrical degrees and 210 electrical degrees.
- the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 10, the first fixed ON period T1u is 120 degrees, whereas the first fixed ON period T1v is absent and the first fixed ON period T1w is 60 degrees. That is, in waveform example 10, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 13B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
- the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w.
- the second fixed ON period T2u is 120 degrees, while the second fixed ON period T2v is absent and the second fixed ON period T2w is 60 degrees. That is, in waveform example 10, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 13B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
- waveform example 10 As described above with reference to FIGS. 13A and 13B, in waveform example 10 as well as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved.
- waveform example 10 it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un.
- waveform example 10 as shown in FIG. 13B, the heat generation of the W-phase first semiconductor switching element Wp and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
- FIG. 14A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 14B is a diagram showing switching losses.
- waveform example 11 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 30 to 210 electrical degrees and at an electrical angle of 330 to 360 electrical degrees.
- waveform example 11 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 to 30 degrees and at an electrical angle of 210 to 330 degrees.
- the high side-on application period T3 occurs at an electrical angle of 30 to 210 electrical degrees and at an electrical angle of 330 to 360 electrical degrees.
- the low side-on application period T4 occurs at an electrical angle of 0 to 30 electrical degrees and at an electrical angle of 210 to 330 electrical degrees.
- the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w.
- the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees.
- the first fixed ON period T1v is between 150 electrical degrees and 210 electrical degrees.
- the first fixed ON period T1w is from 330 electrical degrees to 360 electrical degrees.
- the second fixed ON period T2 includes a second fixed ON period T2u and a second fixed ON period T2v.
- the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
- the second fixed ON period T2v is from 0 electrical angle to 30 electrical degrees.
- the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 11, the first fixed ON period T1u is 120 degrees, the first fixed ON period T1v is 60 degrees, and the first fixed ON period T1w is 30 degrees. That is, in waveform example 11, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 14B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
- the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w.
- the second fixed ON period T2u is 120 degrees
- the second fixed ON period T2v is 30 degrees
- waveform example 11 As described above with reference to FIGS. 14A and 14B, in waveform example 11, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 11, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un.
- waveform example 11 as shown in FIG. 14B, the heat generated by the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, and the W-phase first semiconductor switching element Wp can be suppressed at the same time.
- FIG. 15A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 15B is a diagram showing switching losses.
- waveform example 12 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 30 degrees to 150 degrees and at an electrical angle of 330 degrees to 360 degrees.
- waveform example 12 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 to 30 electrical degrees and at an electrical angle of 150 to 330 electrical degrees.
- the high side-on application period T3 occurs at an electrical angle of 30 degrees to 150 degrees and at an electrical angle of 330 degrees to 360 degrees.
- the low side-on application period T4 occurs at an electrical angle of 0 to 30 electrical degrees and at an electrical angle of 150 to 330 electrical degrees.
- the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1w.
- the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees.
- the first fixed ON period T1w is from 330 electrical degrees to 360 electrical degrees.
- the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
- the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
- the second fixed ON period T2v is from 0 electrical angle to 30 electrical degrees.
- the second fixed ON period T2w is from 150 electrical degrees to 210 electrical degrees.
- the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 12, the first fixed ON period T1u is 120 degrees, whereas the first fixed ON period T1v is absent and the first fixed ON period T1w is 30 degrees. That is, in waveform example 12, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 15B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
- the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w.
- the second fixed ON period T2u is 120 degrees
- the second fixed ON period T2v is 30 degrees
- the second fixed ON period T2w is 60 degrees. That is, in waveform example 12, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 15B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
- waveform example 12 As described above with reference to FIGS. 15A and 15B , in waveform example 12, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 12, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un.
- waveform example 12 as shown in FIG. 15B, the heat generated by the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
- FIG. 16 is a diagram showing switching loss.
- the switching loss is 0.13. That is, in the U-phase, if the high-side first fixed ON period T1u is 120 degrees and the low-side second fixed ON period T2u is 120 degrees, the switching loss is 0.13.
- the switching loss is 0.22. That is, in the U-phase, if the high-side first fixed ON period T1u is 120 degrees and the low-side second fixed ON period T2u is 100 degrees, the switching loss is 0.22.
- the switching loss is 0.35. That is, in the U-phase, if the high-side first fixed ON period T1u is 80 degrees and the low-side second fixed ON period T2u is 100 degrees, the switching loss is 0.22.
- the switching loss is 0.35. That is, in the U-phase, if the high-side first fixed ON period T1u is 80 degrees and the low-side second fixed ON period T2u is 80 degrees, the switching loss is 0.35.
- the switching loss is 0.50. That is, in the U-phase, if the high-side first fixed ON period T1u is 60 degrees and the low-side second fixed ON period T2u is 60 degrees, the switching loss is 0.50.
- both the first fixed ON period T1u and the second fixed ON period T2u are longer than ⁇ /3 (60 degrees) and 2 ⁇ /3 (120 degrees) or less. Preferably. More preferably, it is longer than 4 ⁇ /9 (80 degrees) and 2 ⁇ /3 (120 degrees) or less.
- FIG. 17 is a diagram for explaining switching of the UH_UL protection waveform.
- the waveforms of the output voltage and the switching loss are, from the left, (c) waveform example 3 (FIGS. 6A and 6B), (i) waveform example 9 (FIGS. 12A and 12B), (a) waveform example 1 (FIGS. 3A and 3B).
- Waveform example 3 shown in the left diagram is a waveform example in which the first fixed ON period T1v and the first fixed ON period T1w are extended. In other words, this is a waveform example that emphasizes suppression of heat generation on the high side.
- Waveform example 3 shown in the middle diagram is a waveform example in which the first fixed ON period T1v, the first fixed ON period T1w, the second fixed ON period T2v, and the second fixed ON period T2w are equalized. That is, it is a waveform example in which the first fixed ON period T1u and the period other than the first fixed ON period T1u are made uniform.
- Waveform example 1 shown in the right figure is a waveform example in which the second fixed ON period T2v and the second fixed ON period T2w are extended. In other words, this is an example of a waveform that emphasizes suppression of heat generation on the low side.
- the first fixed ON period T1v and the first fixed ON period T1w become longer as the diagram shifts to the left. Therefore, the switching losses of the V-phase first semiconductor switching element Vp (high side) and the W-phase first semiconductor switching element Wp (high side) decrease as the diagram shifts to the left.
- the second fixed ON period T2v and the second fixed ON period T2w become longer as it shifts to the right figure. Therefore, the switching loss of the V-phase second semiconductor switching element Vn (low side) and the W-phase second semiconductor switching element Wn (low side) decreases as the diagram shifts to the left.
- FIG. 16 is a diagram for explaining switching of the UH_UL protection waveform.
- the waveform of the output voltage and the switching loss are, from left to right, (e) waveform example 5 (FIGS. 8A and 8B), (i) waveform example 9 (FIGS. 12A and 12B), (j) waveform example 10 (FIGS. 13A and 13B).
- Waveform example 5 shown in the left diagram is a waveform example in which the first fixed ON period T1v and the second fixed ON period T2v are extended. In other words, this is an example of a waveform that emphasizes the V phase.
- Waveform example 9 shown in the middle diagram is a waveform example in which the first fixed ON period T1v, the first fixed ON period T1w, the second fixed ON period T2v, and the second fixed ON period T2w are equalized. That is, it is a waveform example in which the first fixed ON period T1u and the period other than the first fixed ON period T1u are made uniform.
- Waveform example 10 shown in the right figure is a waveform example in which the first fixed ON period T1w and the second fixed ON period T2w are extended. That is, it is an example of a waveform in which the W phase is emphasized.
- the first fixed ON period T1v and the second fixed ON period T2v become longer as the diagram shifts to the left. Therefore, the switching losses of the V-phase first semiconductor switching element Vp (high side) and the V-phase second semiconductor switching element Vn (low side) decrease as the diagram shifts to the left.
- the first fixed ON period T1w and the second fixed ON period T2w become longer as the figure shifts to the right. Therefore, the switching loss of the W-phase first semiconductor switching element Wp (high side) and the W-phase second semiconductor switching element Wn (low side) decreases as the drawing shifts to the right side.
- FIG. 19 is a diagram showing switching loss.
- FIG. 20 is a diagram for explaining switching of the UH_UL protection waveform.
- the waveform diagram shown in FIG. 20 corresponds to (i) waveform example 9 (FIG. 12A).
- Waveform example 1 corresponds to a waveform in which the second fixed ON period T2v and the second fixed ON period T2w are extended with respect to (i) waveform example 9. Therefore, the switching losses of the V-phase second semiconductor switching element Vn (VL) and the W-phase second semiconductor switching element Wn (WL) are reduced.
- Waveform example 3 corresponds to a waveform in which the first fixed ON period T1v and the first fixed ON period T1w are extended with respect to (i) waveform example 9. Therefore, the switching losses of the V-phase first semiconductor switching element Vp (VH) and the W-phase first semiconductor switching element Wp (WH) are reduced.
- Waveform example 5 corresponds to a waveform in which the first fixed ON period T1v and the second fixed ON period T2v are extended with respect to (i) waveform example 9. Therefore, the switching losses of the V-phase first semiconductor switching element Vp (VH) and the V-phase second semiconductor switching element Vn (VL) are reduced.
- Waveform example 10 corresponds to a waveform in which the first fixed ON period T1w and the second fixed ON period T2w are extended with respect to (i) waveform example 9. Therefore, the switching losses of the W-phase first semiconductor switching element Wp (WH) and the W-phase second semiconductor switching element Wn (WL) are reduced.
- Waveform example 6 corresponds to a waveform obtained by extending the second on-fixed period T2v from (i) waveform example 9. Therefore, the switching loss of the V-phase second semiconductor switching element Vn(VL) is reduced.
- Waveform example 8 corresponds to a waveform obtained by extending the first fixed ON period T1w with respect to (i) waveform example 9. Therefore, the switching loss of the W-phase first semiconductor switching element Wp(WH) is reduced.
- Waveform example 11 corresponds to a waveform obtained by extending the first fixed ON period T1v with respect to (i) waveform example 9. Therefore, the switching loss of the V-phase first semiconductor switching element Vp (VH) is reduced.
- Waveform example 12 corresponds to a waveform obtained by extending the second on-fixed period T2w from (i) waveform example 9. Therefore, the switching loss of the W-phase second semiconductor switching element Wn(WL) is reduced.
- FIG. 21 is a flow chart showing a protection waveform switching method.
- Step S102 The signal generator 120 acquires the temperature T_UH, temperature T_UL, temperature T_VH, temperature T_VL, temperature T_WH, and temperature T_WH of each arm (semiconductor switching element).
- a temperature T_UH indicates the temperature of the first semiconductor switching element Up.
- a temperature T_UL indicates the temperature of the second semiconductor switching element Un.
- a temperature T_VH indicates the temperature of the first semiconductor switching element Vp.
- a temperature T_VL indicates the temperature of the second semiconductor switching element Vn.
- a temperature T_WH indicates the temperature of the first semiconductor switching element Wp.
- a temperature T_WL indicates the temperature of the second semiconductor switching element Wn.
- the signal generation unit 120 sets the acquired temperature T_UH, temperature T_UL, temperature T_VH, temperature T_VL, temperature T_WH, and temperature T_WH to T_1, T_2, T_3, T_4, T_5, and T_6 in descending order of temperature. The process proceeds to step S104.
- Step S104 The signal generator 120 determines whether or not the highest temperature upper arm (first semiconductor switching element) and the highest temperature lower arm (second semiconductor switching element) are in phase. When the signal generator 120 determines that the highest temperature upper arm (first semiconductor switching element) and the highest temperature lower arm (second semiconductor switching element) are not in phase (step S104: No), the process proceeds to step S108. proceed to When the signal generator 120 determines that the highest temperature upper arm (first semiconductor switching element) and the highest temperature lower arm (second semiconductor switching element) are in phase (step S104: Yes), the process proceeds to step Proceed to S106.
- Step S106 The signal generator 120 modulates in a pattern that suppresses temperature rise in the upper and lower stages of the X phase.
- the X phase is, for example, U phase, V phase or W phase. Processing ends. Detailed processing of step S106 will be described later with reference to FIGS.
- Step S108 The signal generator 120 modulates in a pattern that suppresses temperature rise in the X-phase upper stage and the Y-phase lower stage.
- Y-phase is, for example, U-phase, V-phase or W-phase. Processing ends. Detailed processing of step S108 will be described later with reference to FIGS.
- FIG. 22 is a flow chart showing a protection waveform switching method.
- 23 and 24 are diagrams showing a switching method of the protection waveform. 22 to 24 show the switching method of the protection waveform when the U phase is used as an example of the X phase.
- Step S202 The signal generator 120 determines whether the temperatures T_3 to T_6 are equal to or lower than the threshold T_Thr1. When the signal generator 120 determines that the temperatures T_3 to T_6 are not equal to or lower than the threshold value T_Thr1 (step S202: No), the process proceeds to step S206. When the signal generator 120 determines that the temperatures T_3 to T_6 are equal to or lower than the threshold T_Thr1 (step S202: Yes), the process proceeds to step S204.
- Step S204 The signal generator 120 modulates with four protection patterns. Specifically, the signal generator 120 performs modulation with (i) waveform example 9; Processing ends.
- Step S206 The signal generator 120 determines whether the temperatures T_5 to T_6 are equal to or lower than the threshold T_Thr2. When the signal generator 120 determines that the temperatures T_5 to T_6 are not equal to or lower than the threshold value T_Thr2 (step S206: No), the process proceeds to step S210. When the signal generator 120 determines that the temperatures T_5 to T_6 are equal to or lower than the threshold T_Thr2 (step S206: Yes), the process proceeds to step S208.
- Step S208 The signal generator 120 modulates between the three protection patterns and the four protection patterns. Modulation in between the 3 guard pattern and the 4 guard pattern will be described later with reference to FIG. Processing ends.
- Step S210 The signal generator 120 determines whether the temperatures T_3 to T_5 are equal to or lower than the threshold T_Thr3. When the signal generator 120 determines that the temperatures T_3 to T_5 are not equal to or lower than the threshold value T_Thr3 (step S210: No), the process proceeds to step S214. When the signal generator 120 determines that the temperatures T_3 to T_5 are equal to or lower than the threshold T_Thr3 (step S210: Yes), the process proceeds to step S212.
- Step S212 The signal generator 120 modulates with three protection patterns. Specifically, the signal generation unit 120 selects the arms (or (Semiconductor switching elements) are modulated with a pattern that can protect them. Processing ends.
- Step S214 The signal generator 120 determines whether the temperatures T_4 to T_5 are equal to or lower than the threshold T_Thr4. When the signal generator 120 determines that the temperatures T_4 to T_5 are not equal to or lower than the threshold value T_Thr4 (step S214: No), the process proceeds to step S218. When the signal generator 120 determines that the temperatures T_4 to T_5 are equal to or lower than the threshold value T_Thr4 (step S214: Yes), the process proceeds to step S216.
- Step S216 The signal generator 120 modulates between the two protection patterns and the three protection patterns. Modulation in between the 2 guard pattern and the 3 guard pattern will be described later with reference to FIG. Processing ends.
- Step S218 The signal generator 120 modulates with two protection patterns. Specifically, the signal generator 120 generates (a) waveform example 1, (c) waveform example 3, (e) waveform example 5, (f) waveform example 6, (i) waveform example 9, and (j) waveform example 10. Of these, modulation is performed with a pattern that can protect arms (semiconductor switching elements) whose temperatures are T_3 and T_4. Processing ends.
- step S208 shown in FIG. 22 will be described with reference to FIG. That is, a description will be given of the processing in the case of performing modulation between the three protection patterns and the four protection patterns.
- the signal generation unit 120 determines the positions of the three arms (semiconductor switching elements) with the highest temperature, excluding UH (first semiconductor switching element Up) and UL (second semiconductor switching element Un).
- upper three arms semiconductor switching elements with higher temperatures excluding UH (first semiconductor switching element Up) and UL (second semiconductor switching element Un)
- the order of the temperatures of the top three arms does not matter.
- the order of the temperatures of the upper three arms may be VH (first semiconductor switching element Vp), VL (second semiconductor switching element Vn), and WH (first semiconductor switching element Wp), or VH (first semiconductor switching element Wp).
- the order of semiconductor switching element Vp), WH (first semiconductor switching element Wp) and VL (second semiconductor switching element Vn) is also acceptable.
- the order of the temperatures of the top three arms is similarly irrelevant.
- signal generation unit 120 determines that the upper three arms are VH (first semiconductor switching element Vp), VL (second semiconductor switching element Vn), and WL (second semiconductor switching element Wn), signal generation unit 120 modulates with (f) waveform example 6;
- step S216 shown in FIG. 22 will be described with reference to FIG. In other words, a description will be given of processing in the case of performing modulation between the two protection patterns and the three protection patterns.
- the signal generation unit 120 determines the positions of the upper two arms (semiconductor switching elements) with the highest temperature, excluding UH (first semiconductor switching element Up) and UL (second semiconductor switching element Un).
- UH first semiconductor switching element Up
- UL second semiconductor switching element Un
- the order of the temperatures of the upper two arms does not matter.
- the order of the temperatures of the upper two arms may be VL (second semiconductor switching element Vn) and WL (second semiconductor switching element Wn), or WL (second semiconductor switching element Wn) and VL (second semiconductor switching element Wn).
- the order of the semiconductor switching elements Vn) may also be used.
- the order of the temperatures of the top three arms is similarly irrelevant.
- the signal generation unit 120 determines the position of the arm (semiconductor switching element) with the third highest temperature, excluding UH (first semiconductor switching element Up) and UL (second semiconductor switching element Un).
- UH first semiconductor switching element Up
- UL second semiconductor switching element Un
- a signal When the positions of the upper two arms are VL (second semiconductor switching element Vn) and WL (second semiconductor switching element Vn), and the arm with the third highest temperature is WH (first semiconductor switching element Wp), a signal
- the generation unit 120 determines that (a) in the waveform example 1, the pattern in which 330 degrees to 330+30 ⁇ (T_Thr4 ⁇ (T_4 ⁇ T_5))/T_Thr4 degrees is applied to the first fixed ON period, the signal generation unit 120 modulate. Processing ends.
- a signal If the generating unit 120 determines, (e) in the waveform example 5, the pattern in which 330 degrees to 330+30 ⁇ (T_Thr4 ⁇ (T_4 ⁇ T_5))/T_Thr4 degrees is applied to the first fixed ON period, and the signal generating unit 120 modulate.
- a signal If the generating unit 120 determines, (e) in the waveform example 5, the pattern in which 150 degrees to 150+30 ⁇ (T_Thr4 ⁇ (T_4 ⁇ T_5))/T_Thr4 degrees is applied to the second fixed ON period, and the signal generating unit 120 modulate.
- a signal If the generating unit 120 determines, (i) in waveform example 9, the signal generating unit 120 modulates with a pattern in which 180 degrees to 180+30 ⁇ (T_Thr4 ⁇ (T_4 ⁇ T_5))/T_Thr4 degrees is applied to the second ON fixed period. I do.
- a signal When the positions of the upper two arms are VL (second semiconductor switching element Vn) and WH (first semiconductor switching element Wp), and the arm with the third highest temperature is VH (first semiconductor switching element Vp), a signal
- the generating unit 120 determines, (i) in the waveform example 9, the pattern in which 150 degrees to 150+30 ⁇ (T_Thr4 ⁇ (T_4 ⁇ T_5))/T_Thr4 degrees is applied to the first fixed ON period, and the signal generating unit 120 modulate.
- the generation unit 120 determines, (j) in waveform example 10, the signal generation unit 120 modulates with a pattern in which 0 degrees to 0+30 ⁇ (T_Thr4 ⁇ (T_4 ⁇ T_5))/T_Thr4 degrees is applied to the second ON fixed period. I do.
- the protection operation mode includes the first selective protection operation mode that protects the first semiconductor switching element and the second semiconductor switching element of one phase.
- k is a natural number of 2n ⁇ 3 or less
- first semiconductor switching elements or second semiconductor switching elements It includes a plurality of k protection modes of operation to protect the switching elements. Selection of k protection operation modes is performed based on the temperature information.
- FIG. 25 is a table showing the relationship between waveform examples and switching loss.
- UH represents the switching loss of the U-phase first semiconductor switching element Up.
- UL represents the switching loss of the U-phase second semiconductor switching element Un.
- VH represents the switching loss of the V-phase first semiconductor switching element Vp.
- VL represents the switching loss of the V-phase second semiconductor switching element Vn.
- WH represents the switching loss of the W-phase first semiconductor switching element Wp.
- WL represents the switching loss of the W-phase second semiconductor switching element Wn.
- UH is 0.32 and VL is 0.32.
- VH is 0.32
- VL is 0.32.
- the waveform examples 13 to 29 are waveform examples capable of protecting the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn.
- a waveform capable of protecting a first semiconductor switching element (eg Up) of a certain phase (eg U phase) and a second semiconductor switching element (eg Vn) of another phase (eg V phase) is referred to as a UH_VL protection waveform.
- This waveform example corresponds to the case where the former first fixed ON period and the latter second fixed ON period are continuous.
- FIG. 26A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 26B is a diagram showing switching losses.
- waveform example 13 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 150 degrees.
- waveform example 13 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 degrees and at an electrical angle of 150 to 360 degrees.
- the high-side-on application period T3 is at an electrical angle of 60 degrees to 150 degrees.
- the low side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees and at an electrical angle of 150 to 360 electrical degrees.
- the first fixed ON period T1 includes the first fixed ON period T1u.
- the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees.
- the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
- the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
- the second fixed ON period T2v is from an electrical angle of 0 degrees to an electrical angle of 60 degrees and from an electrical angle of 330 degrees to an electrical angle of 360 degrees.
- the second fixed ON period T2w is from 150 electrical degrees to 210 electrical degrees.
- the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 13, the first fixed ON period T1u is 120 degrees, but there is no first fixed ON period T1v and no first fixed ON period T1w. That is, in waveform example 13, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 26B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
- the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w.
- the second fixed ON period T2v is 90 degrees
- the second fixed ON period T2u is 120 degrees
- the second fixed ON period T2w is 60 degrees. That is, in waveform example 13, the second fixed ON period T2v is longer than the second fixed ON period T2w. Therefore, as shown in FIG. 26B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than that of the W-phase.
- waveform example 13 As described above with reference to FIGS. 26A and 26B , in waveform example 13, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 13, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn.
- FIG. 27A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 27B is a diagram showing switching losses.
- waveform example 14 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 180 degrees.
- waveform example 14 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 degrees to 60 degrees and at an electrical angle of 180 degrees to 360 degrees.
- the high-side-on application period T3 is at an electrical angle of 60 degrees to 180 degrees.
- the low side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees and at an electrical angle of 180 to 360 electrical degrees.
- the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v.
- the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees.
- the first fixed ON period T1v is between 150 electrical degrees and 180 electrical degrees.
- the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
- the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
- the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees.
- the second fixed ON period T2w is from 180 electrical degrees to 210 electrical degrees.
- the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 14, the first fixed ON period T1u is 90 degrees, the first fixed ON period T1v is 30 degrees, and there is no first fixed ON period T1w. That is, in Waveform Example 14, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 27B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
- the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w.
- the second fixed ON period T2v is 90 degrees
- the second fixed ON period T2u is 120 degrees
- the second fixed ON period T2w is 30 degrees. That is, in waveform example 14, the second fixed ON period T2v is longer than the second fixed ON period T2w. Therefore, as shown in FIG. 27B, the switching loss of the V-phase second semiconductor switching element Un (L (low side)) is smaller than that of the W-phase.
- waveform example 14 As described above with reference to FIGS. 27A and 27B, in waveform example 14, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved.
- the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
- FIG. 28A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 28B is a diagram showing switching losses.
- waveform example 15 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 210 degrees.
- waveform example 15 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 degrees and at an electrical angle of 210 to 360 degrees.
- the high-side-on application period T3 is at an electrical angle of 60 degrees to 210 electrical degrees.
- the low side-on application period is T4 at an electrical angle of 0 to 60 electrical degrees and at an electrical angle of 210 to 360 electrical degrees.
- the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v.
- the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees.
- the first fixed ON period T1v is between 150 electrical degrees and 210 electrical degrees.
- the second fixed ON period T2 includes a second fixed ON period T2u and a second fixed ON period T2v.
- the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
- the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees.
- the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 15, the first fixed ON period T1u is 90 degrees, the first fixed ON period T1v is 60 degrees, and there is no first fixed ON period T1w. That is, in waveform example 15, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 28B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
- the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w.
- the second fixed ON period T2v is 90 degrees
- the second fixed ON period T2u is 120 degrees
- waveform example 15 As described above with reference to FIGS. 28A and 28B , in waveform example 15, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 15, the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
- FIG. 29A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 29B is a diagram showing switching losses.
- waveform example 16 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 240 degrees.
- waveform example 16 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 degree to 60 electrical degrees and at an electrical angle of 240 degrees to 360 electrical degrees.
- the high-side-on application period T3 is at an electrical angle of 60 degrees to 240 electrical degrees.
- the low side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees and at an electrical angle of 240 to 360 electrical degrees.
- the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v.
- the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees.
- the first fixed ON period T1v is from 150 electrical degrees to 240 electrical degrees.
- the second fixed ON period T2 includes a second fixed ON period T2u and a second fixed ON period T2v.
- the second fixed ON period T2u is from 240 electrical degrees to 330 electrical degrees.
- the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees.
- the first fixed ON period T1u differs from the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 16, the first fixed ON period T1u is 90 degrees, but there is no first fixed ON period T1w. That is, in waveform example 16, the first fixed ON period T1u is longer than the first fixed ON period T1w. In waveform example 16, the first fixed ON period T1u and the first fixed ON period T1v are equal. Therefore, as shown in FIG. 29B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than that of the W-phase.
- the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in waveform example 16, the second fixed ON period T2v is 90 degrees, but there is no second fixed ON period T2w. That is, in waveform example 16, the second fixed ON period T2v is longer than the second fixed ON period T2w. In waveform example 16, the second fixed ON period T2u is equal to the second fixed ON period T2v. Therefore, as shown in FIG. 29B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than that of the W-phase.
- waveform example 16 As described above with reference to FIGS. 29A and 29B , in waveform example 16, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 16, the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
- FIG. 30A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 30B is a diagram showing switching losses.
- waveform example 17 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 270 degrees.
- waveform example 17 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 degree to 60 electrical degrees and at an electrical angle of 270 degrees to 360 electrical degrees.
- the high-side-on application period T3 is at an electrical angle of 60 degrees to 270 electrical degrees.
- the low-side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees and at an electrical angle of 270 to 360 electrical degrees.
- the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v.
- the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees.
- the first fixed ON period T1v is from 150 electrical degrees to 270 electrical degrees.
- the second fixed ON period T2 includes a second fixed ON period T2u and a second fixed ON period T2v.
- the second fixed ON period T2u is from 270 electrical degrees to 330 electrical degrees.
- the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees.
- the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 17, the first fixed ON period T1u is 90 degrees, the first fixed ON period T1v is 120 degrees, and there is no first fixed ON period T1w. That is, in waveform example 17, the first fixed ON period T1u is longer than the first fixed ON period T1w. Therefore, as shown in FIG. 30B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than that of the W-phase.
- the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w.
- the second fixed ON period T2v is 90 degrees
- the second fixed ON period T2u is 60 degrees
- waveform example 17 As described above with reference to FIGS. 30A and 30B , in waveform example 17, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 17, the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
- FIG. 31A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 31B is a diagram showing switching losses.
- waveform example 18 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 300 degrees.
- waveform example 18 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 electrical degrees and at an electrical angle of 300 to 360 electrical degrees.
- the high-side-on application period T3 is at an electrical angle of 60 degrees to 300 electrical degrees.
- the low side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees and at an electrical angle of 300 to 360 electrical degrees.
- the first fixed ON period T1 includes the first fixed ON period T1u.
- the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees.
- the first fixed ON period T1v is from 150 electrical degrees to 270 electrical degrees.
- the first fixed ON period T1w is from 270 electrical degrees to 300 electrical degrees.
- the second fixed ON period T2 includes a second fixed ON period T2u and a second fixed ON period T2v.
- the second fixed ON period T2u is between 300 electrical degrees and 330 electrical degrees.
- the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees.
- the first fixed ON period T1u is different from the first fixed ON period T1v and the first fixed ON period T1w.
- the first fixed ON period T1u is 90 degrees
- the first fixed ON period T1v is 120 degrees
- the first fixed ON period T1w is 30 degrees. That is, in waveform example 18, the first fixed ON period T1u is longer than the first fixed ON period T1w. Therefore, as shown in FIG. 31B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than that of the W-phase.
- the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w.
- the second fixed ON period T2v is 90 degrees
- the second fixed ON period T2u is 30 degrees
- waveform example 18 As described above with reference to FIGS. 31A and 31B, in waveform example 18, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 18, the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
- waveform example 18 as shown in FIG. 31B, the heat generated by the U-phase second semiconductor switching element Un, the V-phase first semiconductor switching element Vp, and the W-phase first semiconductor switching element Wp can be suppressed at the same time.
- FIG. 32A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 32B is a diagram showing switching losses.
- waveform example 19 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 330 degrees.
- waveform example 19 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 electrical degrees and at an electrical angle of 330 to 360 electrical degrees.
- the high-side-on application period T3 is at an electrical angle of 60 degrees to 330 electrical degrees.
- the low side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees and at an electrical angle of 330 to 360 electrical degrees.
- the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w.
- the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees.
- the first fixed ON period T1v is from 150 electrical degrees to 270 electrical degrees.
- the first fixed ON period T1w is from 270 electrical degrees to 330 electrical degrees.
- the second fixed ON period T2 includes the second fixed ON period T2v.
- the second fixed ON period T2v is from 0 electrical angle to 60 electrical degrees and from 330 electrical degrees to 360 electrical degrees.
- the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 19, the first fixed ON period T1u is 90 degrees, the first fixed ON period T1v is 120 degrees, and the first fixed ON period T1w is 60 degrees. That is, in waveform example 19, the first fixed ON period T1u is longer than the first fixed ON period T1w. Therefore, as shown in FIG. 32B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than that of the W-phase.
- the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in Waveform Example 19, the second fixed ON period T2v is 90 degrees, whereas the second fixed ON period T2u and the second fixed ON period T2w are absent. That is, in Waveform Example 19, the second fixed ON period T2v is longer than the second fixed ON period T2u and the second fixed ON period T2w. Therefore, as shown in FIG. 32B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
- waveform example 19 As described above with reference to FIGS. 32A and 32B , in waveform example 19, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 19, the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
- FIG. 33A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 33B is a diagram showing switching losses.
- waveform example 20 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 300 degrees to 330 degrees.
- the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 electrical degrees, 150 to 300 electrical degrees, and 330 to 360 electrical degrees.
- the high side-on application period T3 occurs at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 300 degrees to 330 degrees.
- the low side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees, 150 to 300 electrical degrees, and 330 to 360 electrical degrees.
- the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1w.
- the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees.
- the first fixed ON period T1w is between 300 electrical degrees and 330 electrical degrees.
- the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
- the second fixed ON period T2u is from 210 electrical degrees to 300 electrical degrees.
- the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees.
- the second fixed ON period T2w is from 150 electrical degrees to 210 electrical degrees.
- the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 20, the first fixed ON period T1u is 90 degrees, but the first fixed ON period T1v is absent and the first fixed ON period T1w is 30 degrees. That is, in waveform example 20, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 33B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
- the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w.
- the second fixed ON period T2v is 90 degrees
- the second fixed ON period T2u is 90 degrees
- the second fixed ON period T2w is 60 degrees. That is, in waveform example 20, the second fixed ON period T2v is longer than the second fixed ON period T2w. Therefore, as shown in FIG. 33B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than that of the W-phase.
- waveform example 20 As described above with reference to FIGS. 33A and 33B, in waveform example 20 as well as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved.
- waveform example 20 it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn.
- FIG. 34A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 34B is a diagram showing switching losses.
- waveform example 21 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 270 degrees to 330 degrees.
- the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 electrical degrees, 150 to 270 electrical degrees, and 330 to 360 electrical degrees.
- the high side-on application period T3 occurs at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 270 degrees to 330 degrees.
- the low side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees, 150 to 270 electrical degrees, and 330 to 360 electrical degrees.
- the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1w.
- the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees.
- the first fixed ON period T1w is from 270 electrical degrees to 330 electrical degrees.
- the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
- the second fixed ON period T2u is from 210 electrical degrees to 270 electrical degrees.
- the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees.
- the second fixed ON period T2w is between 150 electrical degrees and 210 electrical degrees.
- the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 21, the first fixed ON period T1u is 90 degrees, but the first fixed ON period T1v is absent and the first fixed ON period T1w is 60 degrees. That is, in waveform example 21, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 34B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
- the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w.
- the second fixed ON period T2v is 90 degrees
- the second fixed ON period T2u is 60 degrees
- the second fixed ON period T2w is 60 degrees. That is, in waveform example 21, the second fixed ON period T2v is longer than the second fixed ON period T2u and the second fixed ON period T2w. Therefore, as shown in FIG. 34B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
- waveform example 21 As described above with reference to FIGS. 34A and 34B , in waveform example 21, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 21, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn.
- FIG. 35A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 35B is a diagram showing switching losses.
- waveform example 22 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 240 degrees to 330 degrees.
- the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 electrical degrees, 150 to 240 electrical degrees, and 330 to 360 electrical degrees. waveform.
- the high side-on application period T3 occurs at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 240 degrees to 330 degrees.
- the low-side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees, 150 to 240 electrical degrees, and 330 to 360 electrical degrees.
- the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w.
- the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees.
- the first fixed ON period T1v is between 240 electrical degrees and 270 electrical degrees.
- the first fixed ON period T1w is from 270 electrical degrees to 330 electrical degrees.
- the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
- the second fixed ON period T2u is from 210 electrical degrees to 240 electrical degrees.
- the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees.
- the second fixed ON period T2w is between 150 electrical degrees and 210 electrical degrees.
- the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 22, the first fixed ON period T1u is 90 degrees, the first fixed ON period T1v is 30 degrees, and the first fixed ON period T1w is 60 degrees. That is, in waveform example 22, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 35B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
- the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w.
- the second fixed ON period T2v is 90 degrees
- the second fixed ON period T2u is 30 degrees
- the second fixed ON period T2w is 60 degrees. That is, in waveform example 22, the second fixed ON period T2v is longer than the second fixed ON period T2u and the second fixed ON period T2w. Therefore, as shown in FIG. 35B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
- waveform example 22 As described above with reference to FIGS. 35A and 35B , in waveform example 22, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 22, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn.
- the U-phase second semiconductor switching element Un As shown in FIG. 35B, the V-phase first semiconductor switching element Vp, the W-phase first semiconductor switching element Wp, and the W-phase semiconductor switching element Wp Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
- FIG. 36A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 36B is a diagram showing switching losses.
- waveform example 23 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 210 degrees to 330 degrees.
- the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 electrical degrees, 150 to 210 electrical degrees, and 330 to 360 electrical degrees. waveform.
- the high side-on application period T3 occurs at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 210 degrees to 330 degrees.
- the low side-on application period T4 is at the electrical angle of 0 to 60 electrical degrees, the electrical angle of 150 to 210 electrical degrees, and the electrical angle of 330 to 360 electrical degrees.
- the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w.
- the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees.
- the first fixed ON period T1v is between 210 electrical degrees and 270 electrical degrees.
- the first fixed ON period T1u is from 270 electrical degrees to 330 electrical degrees.
- the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
- the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees.
- the second fixed ON period T2w is from 150 electrical degrees to 210 electrical degrees.
- the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 23, the first fixed ON period T1u is 90 degrees, while the first fixed ON period T1v and the first fixed ON period T1w are 60 degrees. That is, in waveform example 23, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 36B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
- the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in waveform example 23, the second fixed ON period T2v is 90 degrees, whereas the second fixed ON period T2u is absent and the second fixed ON period T2w is 60 degrees. That is, in waveform example 23, the second fixed ON period T2v is longer than the second fixed ON period T2w. Therefore, as shown in FIG. 36B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
- waveform example 23 As described above with reference to FIGS. 36A and 36B, in waveform example 23, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 23, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn.
- waveform example 23 as shown in FIG. 36B, the heat generated by the V-phase first semiconductor switching element Vp, the W-phase first semiconductor switching element Wp, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
- FIG. 37A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 37B is a diagram showing switching losses.
- waveform example 24 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 180 degrees to 330 degrees.
- the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 electrical degrees, 150 to 180 electrical degrees, and 330 to 360 electrical degrees.
- the high-side-on application period T3 is at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 180 degrees to 330 degrees.
- the low side-on application period T4 is at an electrical angle of 0 to 60 electrical degrees, 150 to 180 electrical degrees, and 330 to 360 electrical degrees.
- the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w.
- the first ON fixed period T1u is from 60 electrical degrees to 150 electrical degrees.
- the first fixed ON period T1v is from 180 degrees to 270 degrees in electrical angle.
- the first fixed ON period T1w is from 270 electrical degrees to 330 electrical degrees.
- the second fixed ON period T2 includes a second fixed ON period T2v and a second fixed ON period T2w.
- the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees.
- the second fixed ON period T2w is between 150 electrical degrees and 180 electrical degrees.
- the first fixed ON period T1u differs from the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 24, the first fixed ON period T1u is 90 degrees, while the first fixed ON period T1w is 60 degrees. That is, in waveform example 24, the first fixed ON period T1u is longer than the first fixed ON period T1w. Note that the first fixed ON period T1u and the first fixed ON period T1v are the same. Therefore, as shown in FIG. 37B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than that of the W-phase.
- the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in waveform example 24, the second fixed ON period T2v is 90 degrees, while the second fixed ON period T2w is 30 degrees. That is, in waveform example 24, the second fixed ON period T2v is longer than the second fixed ON period T2w. Therefore, as shown in FIG. 37B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than that of the W-phase.
- waveform example 24 As described above with reference to FIGS. 37A and 37B, in waveform example 24, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved.
- the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
- waveform example 24 as shown in FIG. 37B, the heat generated by the V-phase first semiconductor switching element Vp, the W-phase first semiconductor switching element Wp, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
- FIG. 38A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 38B is a diagram showing switching losses.
- waveform example 25 the output voltage of any one phase is fixed to 1 in a certain electrical angle section, and the output voltage of any one phase is fixed to 1 in another electrical angle section, depending on the electrical angle. is fixed to 0. Specifically, in waveform example 25, the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 150 degrees, from 210 degrees to 240 degrees, and from 270 degrees to 330 degrees. waveform. In addition, waveform example 25 is any of the electrical angle of 0 to 60 electrical degrees, 150 to 210 electrical degrees, 240 to 270 electrical degrees, and 330 to 360 electrical degrees. It is a waveform in which the output of one phase is fixed to 0. In waveform example 25, the high-side-on application period T3 occurs at an electrical angle of 60 to 150 electrical degrees, 210 to 240 electrical degrees, and 270 to 330 electrical degrees. In addition, in waveform example 25, the low side This is the ON application period T4.
- the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w.
- the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees.
- the first fixed ON period T1v is between 210 electrical degrees and 240 electrical degrees.
- the first fixed ON period T1w is from 270 electrical degrees to 330 electrical degrees.
- the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
- the second fixed ON period T2u is from 240 electrical degrees to 270 electrical degrees.
- the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees.
- the second fixed ON period T2w is from 150 electrical degrees to 210 electrical degrees.
- the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 25, the first fixed ON period T1u is 90 degrees, the first fixed ON period T1v is 30 degrees, and the first fixed ON period T1w is 60 degrees. That is, in waveform example 25, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 38B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
- the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w.
- the second fixed ON period T2v is 90 degrees
- the second fixed ON period T2u is 30 degrees
- the second fixed ON period T2w is 60 degrees. That is, in waveform example 25, the second fixed ON period T2v is longer than the second fixed ON period T2u and the second fixed ON period T2w. Therefore, as shown in FIG. 38B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
- waveform example 25 As described above with reference to FIGS. 38A and 38B , in waveform example 25, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In the waveform example 25, the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
- the U-phase second semiconductor switching element Un the V-phase first semiconductor switching element Vp, the W-phase first semiconductor switching element Wp, and the W-phase semiconductor switching element Wp Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
- FIG. 39A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 39B is a diagram showing switching losses.
- waveform example 26 the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, in waveform example 26, the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 150 degrees, from 195 degrees to 240 degrees, and from 285 degrees to 330 degrees. waveform. In addition, waveform example 26 is any of the electrical angles of 0 to 60 electrical degrees, 150 to 195 electrical degrees, 240 to 285 electrical degrees, and 330 to 360 electrical degrees. It is a waveform in which the output of one phase is fixed to 0. In waveform example 26, the high-side-on application period T3 is at an electrical angle of 60 to 150 electrical degrees, 195 to 240 electrical degrees, and 285 to 330 electrical degrees. Further, in waveform example 26, the low side This is the ON application period T4.
- the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w.
- the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees.
- the first fixed ON period T1v is between an electrical angle of 195 degrees and an electrical angle of 240 degrees.
- the first fixed ON period T1w is between an electrical angle of 285 degrees and an electrical angle of 330 degrees.
- the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
- the second fixed ON period T2u is from 240 electrical degrees to 285 electrical degrees.
- the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees.
- the second fixed ON period T2w is from 150 electrical degrees to 195 electrical degrees.
- the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 26, the first fixed ON period T1u is 90 degrees, while the first fixed ON period T1v and the first fixed ON period T1w are 45 degrees. That is, in waveform example 26, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 39B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
- the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w.
- the second fixed ON period T2v is 90 degrees, while the second fixed ON period T2u and the second fixed ON period T2w are 45 degrees. That is, in waveform example 26, the second fixed ON period T2v is longer than the second fixed ON period T2u and the second fixed ON period T2w. Therefore, as shown in FIG. 39B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
- waveform example 26 As described above with reference to FIGS. 39A and 39B, in waveform example 26, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved.
- the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
- the U-phase second semiconductor switching element Un the V-phase first semiconductor switching element Vp, the W-phase first semiconductor switching element Wp, and the W-phase Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
- FIG. 40A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 40B is a diagram showing switching losses.
- waveform example 27 the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, in waveform example 27, the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 150 degrees, from 180 degrees to 240 degrees, and from 300 degrees to 330 degrees. waveform. Further, waveform example 27 is any of the electrical angle of 0 to 60 electrical degrees, the electrical angle of 150 to 180 electrical degrees, the electrical angle of 240 to 300 electrical degrees, and the electrical angle of 330 to 360 electrical degrees. It is a waveform in which the output of one phase is fixed to 0. In waveform example 27, the high-side-on application period T3 occurs at an electrical angle of 60 to 150 electrical degrees, 180 to 240 electrical degrees, and 300 to 330 electrical degrees. Further, in waveform example 27, the low side This is the ON application period T4.
- the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w.
- the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees.
- the first fixed ON period T1v is from 180 electrical degrees to 240 electrical degrees.
- the first fixed ON period T1w is between 300 electrical degrees and 330 electrical degrees.
- the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
- the second fixed ON period T2u is from 240 electrical degrees to 300 electrical degrees.
- the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees.
- the second fixed ON period T2w is between 150 electrical degrees and 180 electrical degrees.
- the first fixed ON period T1u is different from the first fixed ON period T1v and the first fixed ON period T1w.
- the first fixed ON period T1u is 90 degrees
- the first fixed ON period T1v is 60 degrees
- the first fixed ON period T1w is 30 degrees. That is, in waveform example 27, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 40B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
- the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w.
- the second fixed ON period T2v is 90 degrees
- the second fixed ON period T2u is 60 degrees
- the second fixed ON period T2w is 30 degrees. That is, in waveform example 27, the second fixed ON period T2v is longer than the second fixed ON period T2u and the second fixed ON period T2w. Therefore, as shown in FIG. 40B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
- waveform example 27 As described above with reference to FIGS. 40A and 40B, in waveform example 27, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 27, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn.
- the U-phase second semiconductor switching element Un the V-phase first semiconductor switching element Vp, the W-phase first semiconductor switching element Wp, and the W-phase Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
- FIG. 41A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 41B is a diagram showing switching losses.
- waveform example 28 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 210 degrees to 270 degrees.
- the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 electrical degrees, 150 to 210 electrical degrees, and 270 to 360 electrical degrees.
- the high side-on application period T3 occurs at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 210 degrees to 270 degrees.
- the low side-on application period T4 is at an electrical angle of 0 to 60 electrical degrees, 150 to 210 electrical degrees, and 270 to 360 electrical degrees.
- the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v.
- the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees.
- the first fixed ON period T1v is between 210 electrical degrees and 270 electrical degrees.
- the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
- the second fixed ON period T2u is from 270 electrical degrees to 330 electrical degrees.
- the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees.
- the second fixed ON period T2w is from 150 electrical degrees to 210 electrical degrees.
- the first fixed ON period T1u is different from the first fixed ON period T1v and the first fixed ON period T1w.
- the first fixed ON period T1u is 90 degrees
- the first fixed ON period T1v is 60 degrees
- the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w.
- the second fixed ON period T2v is 90 degrees, while the second fixed ON period T2u and the second fixed ON period T2w are 60 degrees. That is, in waveform example 28, the second fixed ON period T2v is longer than the second fixed ON period T2u and the second fixed ON period T2w. Therefore, as shown in FIG. 41B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
- waveform example 28 As described above with reference to FIGS. 41A and 41B , in waveform example 28, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved.
- the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
- waveform example 28 as shown in FIG. 41B, the heat generated by the U-phase second semiconductor switching element Un, the V-phase first semiconductor switching element Vp, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
- FIG. 42A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 42B is a diagram showing switching losses.
- waveform example 29 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 210 degrees and at an electrical angle of 270 degrees to 330 degrees.
- the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 electrical degrees, 210 to 270 electrical degrees, and 330 to 360 electrical degrees.
- the high-side-on application period T3 occurs at an electrical angle of 60 degrees to 210 degrees and at an electrical angle of 270 degrees to 330 degrees.
- the low side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees, 210 to 270 electrical degrees, and 330 to 360 electrical degrees.
- the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w.
- the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees.
- the first fixed ON period T1v is between 150 electrical degrees and 210 electrical degrees.
- the first fixed ON period T1w is from 270 electrical degrees to 330 electrical degrees.
- the second fixed ON period T2 includes a second fixed ON period T2u and a second fixed ON period T2v.
- the second fixed ON period T2u is from 210 electrical degrees to 270 electrical degrees.
- the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees.
- the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 29, the first fixed ON period T1u is 90 degrees, while the first fixed ON period T1v and the first fixed ON period T1w are 60 degrees. That is, in waveform example 29, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 42B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
- the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w.
- the second fixed ON period T2v is 90 degrees
- the second fixed ON period T2u is 60 degrees
- waveform example 29 As described above with reference to FIGS. 42A and 42B , in waveform example 29, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved.
- the waveform example 29 it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn.
- the first fixed ON period is longer than the first fixed ON period of the other phases.
- the first fixed ON period of the phase having a longer ON period and the second fixed ON period of the phase having a longer second fixed ON period than the second fixed ON period of the other phase are both longer than ⁇ /n and 2 ⁇ /n or less be.
- it is 1.5 ⁇ /n to 2 ⁇ /n.
- heat generation can be effectively suppressed.
- the lower limit may be slightly deviated from ⁇ /n.
- the upper limit may deviate slightly from 2 ⁇ /n.
- the second fixed ON period of the phase with the longer ON fixed period is both 2 ⁇ /n.
- the first fixed ON period of the phase whose first fixed ON period is longer than the first fixed ON period of the other phase and the second fixed ON period of the phase whose second fixed ON period is longer than the second fixed ON period of the other phase ON fixed period is not continuous with each other.
- the first fixed ON period of one phase and the second fixed ON period of the other phase are mutually different. Contiguous.
- the U-phase first fixed ON period T1u and the V-phase second fixed ON period T2v are continuous with each other.
- the sum of the first fixed ON period of one phase and the second fixed ON period of the other phase is 3 ⁇ /n.
- the first fixed ON period T1u of the U phase is 90 degrees
- the second fixed ON period T2v of the V phase is 90 degrees.
- the sum with the on-fixed period T2v is 180 degrees (3 ⁇ /n). Note that the total may deviate slightly from 3 ⁇ /n.
- the first fixed ON period of one phase and the second fixed ON period of the other phase are each 3 ⁇ /(2n).
- the U-phase first fixed ON period T1u and the V-phase second fixed ON period T2v are 90 degrees (3 ⁇ /(2n)). Therefore, in waveform examples 13 to 29, when a current continuously flows through the first semiconductor switching element of a phase in which a stall occurs and the second semiconductor switching element of another phase and the temperature rises, the stall escapes. By performing this operation when starting the operation, heat generation of the semiconductor switching element whose temperature has risen under the stall can be suppressed, and the temperature can be quickly lowered, so that the reliability of the inverter is improved.
- FIG. 43 is a diagram showing switching loss.
- the second fixed ON period is applied at an electrical angle of 0 to 60 electrical degrees and from 330 to 360 electrical degrees
- the first fixed period is applied at an electrical angle of 60 to 150 electrical degrees.
- the ON fixed period is applied, the switching loss of the first semiconductor switching element Up (UH) is 0.32.
- the switching loss of the second semiconductor switching element Vn(VL) is 0.32.
- the fixed period on the high side is 90 degrees.
- the switching loss of the first semiconductor switching element Up(UH) is 0.39.
- the switching loss of the second semiconductor switching element Vn(VL) is 0.25.
- the fixed period on the high side is 80 degrees.
- the second fixed ON period When the second fixed ON period is applied at an electrical angle of 0 to 80 electrical degrees and from 330 to 360 electrical degrees, and the first fixed ON period is applied at an electrical angle of 80 to 150 electrical degrees.
- the switching loss of the first semiconductor switching element Up (UH) is 0.47.
- the switching loss of the second semiconductor switching element Vn(VL) is 0.18.
- the fixed period on the high side is 70 degrees.
- the switching loss of the first semiconductor switching element Up (UH) is 0.56.
- the switching loss of the second semiconductor switching element Vn(VL) is 0.13.
- the fixed period on the high side is 60 degrees.
- both the first fixed ON period T1u and the second fixed ON period T2u are longer than ⁇ /3 (60 degrees) and 2 ⁇ /3 (120 degrees) or less. Preferably. More preferably, it is longer than 7 ⁇ /18 (70 degrees) and 2 ⁇ /3 (120 degrees) or less.
- FIG. 44 is a diagram for explaining switching of the UH_VL protection waveform.
- the waveform of the output voltage and the switching loss are, from the left, (n) waveform example 26 (FIGS. 39A and 39B), (o) waveform example 27 (FIGS. 40A and 40B), (d) waveform example 16 (FIGS. 29A and 29B).
- Waveform example 26 shown in the left diagram is a waveform example in which the first fixed ON period T1v, the first fixed ON period T1w, the second fixed ON period T2u, and the second fixed ON period T2w are made equal.
- this is an example of waveforms in which periods other than the first fixed ON period T1u and the second fixed ON period T2v are made uniform.
- Waveform example 27 shown in the middle diagram is a waveform example in which the first fixed ON period T1v and the second fixed ON period T2u are extended. In other words, this is an example of waveforms in which the U-phase and V-phase are emphasized.
- Waveform example 16 shown in the right figure is a waveform example in which the first fixed ON period T1v and the second fixed ON period T2u are further extended from (o) Waveform example 27. In other words, this is an example of waveforms in which the U-phase and V-phase are emphasized.
- the first fixed ON period T1v and the second fixed ON period T2u become longer as the diagram shifts to the right. Therefore, the switching loss of the V-phase first semiconductor switching element Vp (high side) and the U-phase second semiconductor switching element Un (low side) decreases as the diagram shifts to the right.
- FIG. 45 is a diagram for explaining switching of the UH_VL protection waveform.
- the output voltage waveform and switching loss correspond to (n) waveform example 26 (FIGS. 39A and 39B) and (m) waveform example 25 (FIGS. 38A and 38B) in order from the left.
- Waveform example 26 shown in the left diagram is a waveform example in which the first fixed ON period T1v, the first fixed ON period T1w, the second fixed ON period T2u, and the second fixed ON period T2w are made equal.
- this is an example of waveforms in which periods other than the first fixed ON period T1u and the second fixed ON period T2v are made uniform.
- Waveform example 25 shown in the right figure is a waveform example in which the first fixed ON period T1w and the second fixed ON period T2w are extended. That is, it is an example of a waveform in which the W phase is emphasized.
- the first fixed ON period T1w and the second fixed ON period T2w become longer as the diagram shifts to the right. Therefore, the switching loss of the W-phase first semiconductor switching element Wp (high side) and the W-phase second semiconductor switching element Wn (low side) decreases as the drawing shifts to the right side.
- FIG. 46 is a diagram for explaining switching of the UH_VL protection waveform.
- the waveform of the output voltage and the switching loss are, from the left, (g) waveform example 19 (FIGS. 32A and 32B), (n) waveform example 26 (FIGS. 39A and 39B), (a) waveform example 13 (FIGS. 26A and 26B).
- Waveform example 26 shown in the middle diagram is a waveform example in which the first fixed ON period T1v, the first fixed ON period T1w, the second fixed ON period T2v, and the second fixed ON period T2w are equalized. That is, it is a waveform example in which the first fixed ON period T1u and the period other than the first fixed ON period T1u are made uniform.
- FIG. 47 is a flow chart showing a protection waveform switching method.
- 48 and 49 are diagrams showing a method of switching guard waveforms. 47 to 49 show the switching method of the protection waveform when the U phase is used as an example of the X phase and the V phase is used as an example of the Y phase.
- Step S502 The signal generator 120 determines whether the temperatures T_3 to T_6 are equal to or lower than the threshold T_Thr5. When the signal generator 120 determines that the temperatures T_3 to T_6 are not equal to or lower than the threshold value T_Thr5 (step S502: No), the process proceeds to step S506. When the signal generator 120 determines that the temperatures T_3 to T_6 are equal to or lower than the threshold value T_Thr5 (step S502: Yes), the process proceeds to step S504.
- Step S504 The signal generator 120 modulates with four protection patterns. Specifically, the signal generator 120 performs modulation with (i) waveform example 21 . Processing ends.
- Step S506 The signal generator 120 determines whether the temperatures T_5 to T_6 are equal to or lower than the threshold T_Thr6. When the signal generator 120 determines that the temperatures T_5 to T_6 are not equal to or lower than the threshold value T_Thr6 (step S506: No), the process proceeds to step S510. When the signal generator 120 determines that the temperatures T_5 to T_6 are equal to or lower than the threshold T_Thr6 (step S506: Yes), the process proceeds to step S508.
- Step S508 The signal generator 120 modulates between the three protection patterns and the four protection patterns. Modulation in between the 3 guard pattern and the 4 guard pattern is described below with reference to FIG. Processing ends.
- Step S510 The signal generator 120 determines whether the temperatures T_3 to T_5 are equal to or lower than the threshold T_Thr7. When the signal generator 120 determines that the temperatures T_3 to T_5 are not equal to or lower than the threshold value T_Thr7 (step S510: No), the process proceeds to step S514. When the signal generator 120 determines that the temperatures T_3 to T_5 are equal to or lower than the threshold T_Thr7 (step S510: Yes), the process proceeds to step S512.
- Step S512 The signal generator 120 modulates with three protection patterns. Specifically, the signal generation unit 120 selects the arms (i) waveform example 21, (k) waveform example 23, (p) waveform example 28, and (q) waveform example 29 whose temperatures are T_3, T_4, and T_5. (Semiconductor switching elements) are modulated with a pattern that can protect them. Processing ends.
- Step S514 The signal generator 120 determines whether the temperatures T_4 to T_5 are equal to or lower than the threshold T_Thr8. When the signal generator 120 determines that the temperatures T_4 to T_5 are not equal to or lower than the threshold T_Thr8 (step S514: No), the process proceeds to step S518. When the signal generator 120 determines that the temperatures T_4 to T_5 are equal to or lower than the threshold T_Thr8 (step S514: Yes), the process proceeds to step S516.
- Step S516 The signal generator 120 modulates between the two protection patterns and the three protection patterns. Modulation in between two guard patterns and three guard patterns is described below with reference to FIG. Processing ends.
- Step S518 The signal generator 120 modulates with two protection patterns. Specifically, the signal generator 120 generates (a) waveform example 13, (c) waveform example 15, (e) waveform example 17, (g) waveform example 19, (i) waveform example 21, and (p) waveform example 28. Of these, modulation is performed with a pattern that can protect arms (semiconductor switching elements) whose temperatures are T_3 and T_4. Processing ends.
- step S508 shown in FIG. 47 will be described with reference to FIG. That is, a description will be given of the processing in the case of performing modulation between the three protection patterns and the four protection patterns.
- the signal generation unit 120 determines the positions of the three arms (semiconductor switching elements) with the highest temperature, excluding UH (first semiconductor switching element Up) and VL (second semiconductor switching element Vn).
- UH first semiconductor switching element Up
- VL second semiconductor switching element Vn
- upper three arms semiconductor switching elements with higher temperatures excluding UH (first semiconductor switching element Up) and UL (second semiconductor switching element Un)
- the order of the temperatures of the top three arms does not matter.
- the order of the temperatures of the upper three arms may be UL (second semiconductor switching element Un), WH (first semiconductor switching element Wp), and WL (second semiconductor switching element Wn), or UL (second semiconductor switching element Wn).
- the order of semiconductor switching element Un), WL (second semiconductor switching element Wn), and WH (first semiconductor switching element Wp) is also acceptable.
- the order of the temperatures of the top three arms is similarly irrelevant.
- signal generation unit 120 determines that the three arms with the highest temperature are UL (second semiconductor switching element Un), VH (first semiconductor switching element Vp), and WL (second semiconductor switching element Wn), (p )
- 195 degrees to 195 + 15 x (T_Thr6 - (T_5 - T_6))/T_Thr6 degrees is the first ON fixed period
- 240 degrees to 240 + 45 x (T_Thr6 - (T_5 - T_6))/T_Thr6 is the second ON period.
- the signal generation unit 120 performs modulation with a pattern in which 285 degrees to 285+45 ⁇ (T_Thr6-(T_5-T_6))/T_Thr6 degrees is applied to the first ON fixed period.
- signal generation unit 120 determines that the three arms with the highest temperature are UL (second semiconductor switching element Un), VH (first semiconductor switching element Vp), and WH (first semiconductor switching element Wp), (q )
- 150 degrees to 150 + 45 x (T_Thr6 - (T_5 - T_6)) / T_Thr6 is the second ON fixed period
- 210 degrees to 210 + 30 x (T_Thr6 - (T_5 - T_6)) / T_Thr6 is the first ON
- the signal generation unit 120 performs modulation with a pattern in which 270 degrees to 270+15 ⁇ (T_Thr6-(T_5-T_6))/T_Thr6 degrees is applied to the second ON fixed period.
- step S516 shown in FIG. 47 will be described with reference to FIG. In other words, a description will be given of processing in the case of performing modulation between the two protection patterns and the three protection patterns.
- process 1 when the positions of the two arms with the highest temperature and the priority of both are UL>WL and the arm with temperature T_5 is VH, process 1 is performed.
- the signal generator 120 performs modulation with a pattern obtained by applying 210 degrees to 210+60 ⁇ (T_Thr8-(T_4-T_5))/T_Thr8 degrees in (a) waveform example 13 to the first ON fixed period.
- process 1 When the position of the two arms with the highest temperature and the priority of both are UL>WL and the arm with the temperature of T_5 is WH, process 1 is performed.
- the signal generator 120 performs modulation with a pattern obtained by applying 270 degrees to 270+60 ⁇ (T_Thr8-(T_4-T_5))/T_Thr8 degrees in (a) waveform example 13 to the first ON fixed period.
- process 1 When the position of the two arms with the highest temperature and the priority of both are UL ⁇ WL and the arm with temperature T_5 is VH, process 1 is performed.
- the signal generator 120 performs modulation with a pattern obtained by applying 210 degrees to 210+60 ⁇ (T_Thr8-(T_4-T_5))/T_Thr8 degrees in (a) waveform example 13 to the first ON fixed period.
- process 2 If the position of the two arms with the highest temperature and the priority of both are UL ⁇ WL and the arm with temperature T_5 is WH, process 2 is performed.
- the signal generator 120 performs modulation with a pattern obtained by applying 270 degrees to 270+60 ⁇ (T_Thr8 ⁇ (T_4 ⁇ T_5))/T_Thr8 degrees in (a) waveform example 13 to the first ON fixed period.
- process 3 is performed.
- (a) in waveform example 13 150 degrees to 150 + 60 x (T_Thr8 - (T_4 - T_5)) / T_Thr8 degrees, 270 degrees to 270 + 60 x (T_Thr8 - (T_4 - T_5)) / T_Thr8 degrees are the first
- the signal generating section 120 performs modulation with the pattern applied to the ON-fixed period.
- process 2 When the position of the two arms with the highest temperature and the priority of both are UL>WH and the arm with the temperature of T_5 is VL, process 2 is performed.
- the signal generator 120 performs modulation with a pattern obtained by applying 270 degrees to 270+60 ⁇ (T_Thr8 ⁇ (T_4 ⁇ T_5))/T_Thr8 degrees in (a) waveform example 13 to the first ON fixed period.
- process 4 When the position of the two arms with the highest temperature and the priority of both are UL>VH and the arm with temperature T_5 is WH, process 4 is performed.
- the signal generator 120 modulates with a pattern obtained by applying 270 degrees to 270+60 ⁇ (T_Thr8-(T_4-T_5))/T_Thr8 degrees in (c) waveform example 15 to the first ON fixed period.
- process 5 is performed.
- (c) in waveform example 15 150 degrees to 150+60 ⁇ (T_Thr8 ⁇ (T_4 ⁇ T_5))/T_Thr8 degrees is the second ON fixed period, 210 degrees to 210+60 ⁇ (T_Thr8 ⁇ (T_4 ⁇ T_5))
- the signal generator 120 performs modulation with a pattern in which /T_Thr8 is applied to the first fixed ON period.
- process 6 is performed.
- process 6 (e) in waveform example 17, 210 degrees to 210+60 ⁇ (T_Thr8 ⁇ (T_4 ⁇ T_5))/T_Thr8 degrees is the second ON fixed period, 270 degrees to 270+60 ⁇ (T_Thr8 ⁇ (T_4 ⁇ T_5))
- the signal generator 120 performs modulation with a pattern in which /T_Thr8 is applied to the first fixed ON period.
- process 7 When the position of the two arms with the highest temperature and the priority of both are UL ⁇ VH, and the arm with the temperature T_5 is WL, process 7 is performed.
- the signal generator 120 modulates with a pattern obtained by applying 150 degrees to 150+60 ⁇ (T_Thr8-(T_4-T_5))/T_Thr8 degrees in (e) waveform example 17 to the second ON fixed period.
- process 7 When the position of the two arms with the highest temperature and the priority of both are VH>WL, and the arm with the temperature of T_5 is WL, process 7 is performed.
- the signal generator 120 modulates with a pattern obtained by applying 150 degrees to 150+60 ⁇ (T_Thr8-(T_4-T_5))/T_Thr8 degrees in (e) waveform example 17 to the second ON fixed period.
- process 8 If the position of the two arms with the highest temperature and the priority of both are VH>WL, and if the arm whose temperature is T_5 is WH, then process 8 is performed.
- process 8 (e) in waveform example 17, 150 degrees to 150+60 ⁇ (T_Thr8 ⁇ (T_4 ⁇ T_5))/T_Thr8 degrees is the second ON fixed period, 270 degrees to 270+60 ⁇ (T_Thr8 ⁇ (T_4 ⁇ T_5))
- the signal generator 120 performs modulation with a pattern in which /T_Thr8 is applied to the first fixed ON period.
- process 9 is performed.
- the signal generator 120 modulates with a pattern obtained by applying 210 degrees to 210+60 ⁇ (T_Thr8-(T_4-T_5))/T_Thr8 degrees in (g) waveform example 19 to the second ON fixed period.
- process 10 When the position of the two arms with the highest temperature and the priority of both are VH>WH and the arm with the temperature of T_5 is WL, process 10 is performed.
- the signal generator 120 modulates with a pattern obtained by applying 150 degrees to 150+60 ⁇ (T_Thr8 ⁇ (T_4 ⁇ T_5))/T_Thr8 degrees in (g) waveform example 19 to the second ON fixed period.
- process 9 If the position of the two arms with the highest temperature and the priority of both are VH ⁇ WH, and if the arm whose temperature is T_5 is UL, process 9 is performed.
- the signal generator 120 modulates with a pattern obtained by applying 210 degrees to 210+60 ⁇ (T_Thr8-(T_4-T_5))/T_Thr8 degrees in (g) waveform example 19 to the second ON fixed period.
- process 10 When the position of the two arms with the highest temperature and the priority of both are VH ⁇ WH, and the arm with the temperature of T_5 is WL, process 10 is performed.
- the signal generator 120 modulates with a pattern obtained by applying 150 degrees to 150+60 ⁇ (T_Thr8 ⁇ (T_4 ⁇ T_5))/T_Thr8 degrees in (g) waveform example 19 to the second ON fixed period.
- process 11 is performed.
- the signal generator 120 performs modulation with a pattern in which 150 degrees to 150+60 ⁇ (T_Thr8-(T_4-T_5))/T_Thr8 degrees is applied to the first ON fixed period.
- process 12 is performed.
- the signal generator 120 (i) modulates the waveform example 21 .
- process 12 If the position of the two arms with the highest temperature and the priority of both are WH>WL, and if the arm whose temperature is T_5 is UL, process 12 is performed. In process 12 , the signal generator 120 (i) modulates the waveform example 21 .
- process 13 is performed.
- the signal generator 120 performs modulation with a pattern in which 210 degrees to 210+60 ⁇ (T_Thr8-(T_4-T_5))/T_Thr8 degrees is applied to the first ON fixed period.
- process 12 If the position of the two arms with the highest temperature and the priority of both are WH ⁇ WL, and if the arm whose temperature is T_5 is UL, process 12 is performed. In process 12 , the signal generator 120 (i) modulates the waveform example 21 .
- process 14 is performed.
- the signal generator 120 performs modulation with (p) waveform example 28 .
- process 15 If the position of the two arms with the highest temperature and the priority of both are VH ⁇ WL, and if the arm whose temperature is T_5 is WH, process 15 is performed.
- the signal generator 120 performs modulation with a pattern obtained by applying 270 degrees to 270+60 ⁇ (T_Thr8 ⁇ (T_4 ⁇ T_5))/T_Thr8 degrees in (p) waveform example 28 to the first ON fixed period.
- the protection operation mode is the second selective protection operation that protects the first semiconductor switching element of one phase and the second semiconductor switching element of another phase. Including mode.
- the first fixed ON period of one phase and the second fixed ON period of another phase are continuous.
- k (k is 2n ⁇ A natural number of 3 or less) includes a plurality of k protection operation modes for protecting the first semiconductor switching elements or the second semiconductor switching elements, and the k protection operation modes are selected based on the temperature information. Therefore, when a current continuously flows through the first semiconductor switch of a certain phase and the second semiconductor switch of another phase due to a stall and the temperature rises, this operation must be performed when the stall is released and the operation is started.
- the motor drive circuit 100 has a plurality of operation modes with different PWM duty waveforms, and has a function of switching between the plurality of operation modes during power conversion. have. At least one of the plurality of operating modes is a protected operating mode.
- the protection operation mode has a plurality of protection operation patterns in which the ratio of at least one of the first fixed ON period and the second fixed ON period occupied by each phase differs during one cycle of the AC output. Therefore, various protection modes can be supported. For example, in addition to the normal mode (one type), it is possible to centrally protect each phase (multiple types).
- a plurality of protection operation modes and a plurality of protection operation patterns are switched based on temperature information of at least one of the first semiconductor switching element and the second semiconductor switching element.
- the temperature information is, for example, temperatures acquired by the six temperature sensors 20 of each semiconductor switching element.
- the temperature sensor 20 may be arranged in the vicinity of some of the semiconductor switching elements, and the temperature of the semiconductor switching elements where the temperature sensor 20 is not arranged may be estimated by calculation.
- the environmental temperature may be monitored and the temperature may be estimated using the values of a current sensor and a voltage sensor (not shown) installed in the motor drive circuit 100 .
- the ambient temperature is, for example, the ambient temperature, the temperature of the substrate, and the temperature of the cooling water. Cooling water is a liquid for cooling motor drive circuit 100 .
- Switching between a plurality of protection operation modes and a plurality of protection operation patterns is performed based on temperature information of at least one of the first semiconductor switching element and the second semiconductor switching element, whereby the semiconductor switching element with a high temperature is selectively switched. It is possible to suppress heat generation, promote heat dissipation, and improve the reliability of the power converter.
- the protection operation mode has at least four types of protection operation patterns. Therefore, various protection modes can be supported. For example, in addition to the normal mode (one type), it is possible to centrally protect each phase (multiple types).
- FIG. 50A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 50B is a diagram showing switching losses.
- waveform example 30 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 90 degrees to 210 electrical degrees.
- waveform example 30 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 to 90 degrees and at an electrical angle of 210 to 360 degrees.
- the high-side-on application period T3 is at an electrical angle of 90 degrees to 210 electrical degrees.
- the low side-on application period T4 occurs at an electrical angle of 0 to 90 electrical degrees and at an electrical angle of 210 to 360 electrical degrees.
- the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v.
- the first fixed ON period T1u is from 90 electrical degrees to 150 electrical degrees.
- the first fixed ON period T1v is between an electrical angle of 150 degrees and an electrical angle of 210 degrees.
- the second fixed ON period T2 includes a second fixed ON period T2u and a second fixed ON period T2v.
- the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
- the second fixed ON period T2v is from 0 to 90 electrical degrees and from 330 to 360 electrical degrees.
- the first fixed ON period T1u differs from the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 30, the first fixed ON period T1u is 60 degrees, but there is no first fixed ON period T1w. That is, in waveform example 30, the first fixed ON period T1u is longer than the first fixed ON period T1w. The first fixed ON period T1v is the same as the first fixed ON period T1u. Therefore, as shown in FIG. 50B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than that of the W-phase.
- the second fixed ON period T2u is different from the second fixed ON period T2u and the second fixed ON period T2w.
- the second fixed ON period T2u is 120 degrees, but there is no second fixed ON period T2w. That is, in waveform example 30, the second fixed ON period T2u is longer than the second fixed ON period T2w.
- the second fixed ON period T2v is the same as the second fixed ON period T2u. Therefore, as shown in FIG. 50B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than that of the W-phase.
- waveform example 30 As described above with reference to FIGS. 50A and 50B , in waveform example 30, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 30, the heat generation of the U-phase second semiconductor switching element Un and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
- the heat generation of the U-phase first semiconductor switching element Up and the V-phase first semiconductor switching element Vp can be suppressed at the same time.
- FIG. 51A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 51B is a diagram showing switching loss.
- the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0.
- the waveform example 31 is a waveform in which the output of any one phase is fixed to 1 in the electrical angle of 45 degrees to 135 electrical degrees and in the electrical angle of 180 degrees to 210 electrical degrees.
- the output of any one phase is fixed to 0 at an electrical angle of 0 to 45 electrical degrees, 135 to 180 electrical degrees, and 210 to 360 electrical degrees.
- the high-side-on application period T3 occurs at an electrical angle of 45 degrees to 135 degrees and at an electrical angle of 180 degrees to 210 degrees.
- the low side-on application period T4 occurs at an electrical angle of 0 to 45 electrical degrees, 135 to 180 electrical degrees, and 210 to 360 electrical degrees.
- the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v.
- the first fixed ON period T1u is from an electrical angle of 45 degrees to an electrical angle of 135 degrees.
- the first fixed ON period T1v is from 180 degrees to 210 degrees in electrical angle.
- the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
- the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
- the second fixed ON period T2v is from an electrical angle of 0 degrees to an electrical angle of 45 degrees and from an electrical angle of 330 degrees to an electrical angle of 360 degrees.
- the second fixed ON period T2w is from 135 electrical degrees to 180 electrical degrees.
- the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 31, the first fixed ON period T1u is 90 degrees, while the first fixed ON period T1v and the first fixed ON period T1w are 30 degrees. That is, in waveform example 31, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 51B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
- the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w.
- the second fixed ON period T2u is 120 degrees
- the second fixed ON period T2v is 75 degrees
- the second fixed ON period T2w is 45 degrees. That is, in waveform example 31, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 51B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
- Waveform Example 31 As described above with reference to FIGS. 51A and 51B , in Waveform Example 31, as in Waveform Example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 31, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un.
- waveform example 31 as shown in FIG. 51B, the heat generated by the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
- FIG. 52A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 52B is a diagram showing switching losses.
- waveform example 32 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 120 degrees and at an electrical angle of 150 degrees to 210 degrees.
- the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 electrical degrees, 120 to 150 electrical degrees, and 210 to 360 electrical degrees.
- the high-side-on application period T3 occurs at an electrical angle of 60 degrees to 120 degrees and at an electrical angle of 150 degrees to 210 degrees.
- the low side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees, 120 to 150 electrical degrees, and 210 to 360 electrical degrees.
- the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v.
- the first fixed ON period T1u is from 60 electrical degrees to 120 electrical degrees.
- the first fixed ON period T1v is between 150 electrical degrees and 210 electrical degrees.
- the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
- the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
- the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees.
- the second fixed ON period T2w is between 120 electrical degrees and 150 electrical degrees.
- the first fixed ON period T1u differs from the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 32, the first fixed ON period T1u is 60 degrees, but there is no first fixed ON period T1w. That is, in waveform example 32, the first fixed ON period T1u is longer than the first fixed ON period T1w. The first fixed ON period T1v is the same as the first fixed ON period T1u. Therefore, as shown in FIG. 52B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than that of the W-phase.
- the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w.
- the second fixed ON period T2u is 120 degrees
- the second fixed ON period T2v is 90 degrees
- the second fixed ON period T2w is 30 degrees. That is, in waveform example 32, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 52B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
- waveform example 32 As described above with reference to FIGS. 52A and 52B , in waveform example 32, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 32, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un.
- waveform example 32 as shown in FIG. 52B, the heat generated by the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
- FIG. 53A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 53B is a diagram showing switching losses.
- the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0.
- the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 120 degrees, from 180 degrees to 210 degrees, and from 330 degrees to 360 degrees.
- the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 electrical degrees, 120 to 180 electrical degrees, and 210 to 330 electrical degrees. waveform.
- the high side-on application period T3 is at an electrical angle of 60 to 120 electrical degrees, 180 to 210 electrical degrees, and 330 to 360 electrical degrees. Further, in waveform example 33, the low side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees, 120 to 180 electrical degrees, and 210 to 330 electrical degrees.
- the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w.
- the first fixed ON period T1u is from 60 electrical degrees to 120 electrical degrees.
- the first fixed ON period T1v is from 180 degrees to 210 degrees in electrical angle.
- the first fixed ON period T1w is from 330 electrical degrees to 360 electrical degrees.
- the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
- the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
- the second fixed ON period T2v is from 0 electrical angle to 60 electrical degrees.
- the second fixed ON period T2w is from 120 electrical degrees to 180 electrical degrees.
- the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w.
- the first fixed ON period T1u is 60 degrees, while the first fixed ON period T1v and the first fixed ON period T1w are 30 degrees. That is, in waveform example 33, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 53B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
- the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w.
- the second fixed ON period T2u is 120 degrees, while the second fixed ON period T2v and the second fixed ON period T2w are 60 degrees. That is, in waveform example 33, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 53B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
- waveform example 33 As described above with reference to FIGS. 53A and 53B , in waveform example 33, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 33, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un.
- the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
- FIG. 54A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 54B is a diagram showing switching losses.
- waveform example 34 the output voltage of any one phase is fixed to 1 in a certain electrical angle section, and the output voltage of any one phase is fixed to 1 in another electrical angle section, depending on the electrical angle. is fixed to 0. More specifically, waveform example 34 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 75 degrees to 105 degrees and at an electrical angle of 150 degrees to 240 degrees. In waveform example 34, the output of any one phase is fixed to 0 at an electrical angle of 0 to 75 electrical degrees, 105 to 150 electrical degrees, and 240 to 360 electrical degrees. waveform.
- the high-side-on application period T3 occurs at an electrical angle of 75 degrees to 105 degrees and at an electrical angle of 150 degrees to 240 degrees.
- the low side-on application period T4 occurs at an electrical angle of 105 degrees to 150 degrees and at an electrical angle of 240 degrees to 360 degrees.
- the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v.
- the first fixed ON period T1u is from 75 electrical degrees to 105 electrical degrees.
- the first fixed ON period T1v is from 150 electrical degrees to 240 electrical degrees.
- the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
- the second fixed ON period T2u is from 240 electrical degrees to 330 electrical degrees.
- the second fixed ON period T2v is from an electrical angle of 0 degrees to an electrical angle of 75 degrees and from an electrical angle of 330 degrees to an electrical angle of 360 degrees.
- the second fixed ON period T2w is from 105 electrical degrees to 150 electrical degrees.
- the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases.
- the first fixed ON period T1v is 90 degrees
- the first fixed ON period T1u is 30 degrees
- the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w.
- the second fixed ON period T2v is 105 degrees
- the second fixed ON period T2u is 90 degrees
- the second fixed ON period T2w is 45 degrees. That is, in waveform example 34, the second fixed ON period T2v is longer than the second fixed ON period T2u and the second fixed ON period T2w. Therefore, as shown in FIG. 54B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
- waveform example 34 As described above with reference to FIGS. 54A and 54B , in waveform example 34, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 34, the heat generation of the V-phase first semiconductor switching element Vp and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
- waveform example 34 as shown in FIG. 54B, the heat generated by the U-phase first semiconductor switching element Up, the U-phase second semiconductor switching element Un, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
- FIG. 55A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 55B is a diagram showing switching losses.
- the output voltage of any one phase is fixed to 1 in a certain electrical angle section, and the output voltage of any one phase is fixed to 1 in another electrical angle section, depending on the electrical angle. is fixed to 0.
- the output of any one phase is fixed to 1 at an electrical angle of 75 degrees to 105 degrees, from 150 degrees to 210 degrees, and from 330 degrees to 360 degrees.
- the output of any one phase is fixed to 0 at an electrical angle of 0 to 75 electrical degrees, 105 to 150 electrical degrees, and 210 to 330 electrical degrees. waveform.
- the high-side-on application period T3 is at an electrical angle of 75 degrees to 105 degrees, an electrical angle of 150 degrees to 210 degrees, and an electrical angle of 330 degrees to 360 degrees.
- the low side-on application period T4 occurs at an electrical angle of 0 to 75 electrical degrees, 105 to 150 electrical degrees, and 210 to 330 electrical degrees.
- the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w.
- the first fixed ON period T1u is from 75 electrical degrees to 105 electrical degrees.
- the first fixed ON period T1v is from 150 electrical degrees to 210 electrical degrees.
- the first fixed ON period T1w is from 330 electrical degrees to 360 electrical degrees.
- the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
- the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
- the second fixed ON period T2v is from 0 electrical angle to 75 electrical degrees.
- the second fixed ON period T2w is from 105 electrical degrees to 150 electrical degrees.
- the first fixed ON period T1v differs from the first fixed ON period T1u and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 35, the first fixed ON period T1v is 60 degrees, while the first fixed ON period T1u and the first fixed ON period T1w are 30 degrees. That is, in waveform example 35, the first fixed ON period T1v is longer than the first fixed ON period T1u and the first fixed ON period T1w. Therefore, as shown in FIG. 55B, the switching loss of the V-phase first semiconductor switching element Vp (H (high side)) is smaller than those of the U-phase and W-phase.
- the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w.
- the second fixed ON period T2u is 120 degrees
- the second fixed ON period T2v is 75 degrees
- the second fixed ON period T2w is 45 degrees. That is, in waveform example 35, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 55B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
- waveform example 35 As described above with reference to FIGS. 55A and 55B , in waveform example 35 as well as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved.
- the heat generation of the V-phase first semiconductor switching element Vp and the U-phase second semiconductor switching element Un can be suppressed at the same time.
- FIG. 56A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 56B is a diagram showing switching losses.
- waveform example 36 the output voltage of any one phase is fixed to 1 in a certain electrical angle section, and the output voltage of any one phase is fixed to 1 in another electrical angle section, depending on the electrical angle. is fixed to 0. More specifically, waveform example 36 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 150 degrees to 240 degrees and at an electrical angle of 330 degrees to 360 degrees. Waveform example 36 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 degree to 150 electrical degrees and at an electrical angle of 240 degrees to 330 electrical degrees.
- the high side-on application period T3 occurs at an electrical angle of 150 degrees to 240 degrees and at an electrical angle of 330 degrees to 360 degrees. Further, in waveform example 36, the low side-on application period T4 occurs at an electrical angle of 0 to 150 electrical degrees and at an electrical angle of 240 to 330 electrical degrees.
- the first fixed ON period T1 includes a first fixed ON period T1v and a first fixed ON period T1w.
- the first fixed ON period T1v is from 150 electrical degrees to 240 electrical degrees.
- the first fixed ON period T1w is between 330 electrical degrees and 360 electrical degrees.
- the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
- the second fixed ON period T2u is from 240 electrical degrees to 330 electrical degrees.
- the second fixed ON period T2v is from 0 electrical angle to 90 electrical degrees.
- the second fixed ON period T2w is from 90 electrical degrees to 150 electrical degrees.
- the first fixed ON period T1v differs from the first fixed ON period T1u and the first fixed ON period T1w.
- the first fixed ON period T1v is 90 degrees
- the first fixed ON period T1u is absent
- the first fixed ON period T1w is 30 degrees. That is, in waveform example 36, the first fixed ON period T1v is longer than the first fixed ON period T1u and the first fixed ON period T1w. Therefore, as shown in FIG. 56B, the switching loss of the V-phase first semiconductor switching element Vp (H (high side)) is smaller than those of the U-phase and W-phase.
- the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w.
- the second fixed ON period T2u is 90 degrees, while the second fixed ON period T2w is 60 degrees. That is, in waveform example 36, the second fixed ON period T2u is longer than the second fixed ON period T2w.
- the second fixed ON period T2v is the same as the second fixed ON period T2u. Therefore, as shown in FIG. 56B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than that of the W-phase.
- waveform example 36 As described above with reference to FIGS. 56A and 56B , in waveform example 36, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 36, it is possible to simultaneously suppress the heat generation of the V-phase first semiconductor switching element Vp and the U-phase second semiconductor switching element Un.
- waveform example 36 as shown in FIG. 56B, the heat generated by the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
- FIG. 57A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 57B is a diagram showing switching losses.
- waveform example 37 As shown in FIG. 57A, in waveform example 37, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0.
- waveform example 37 is a waveform in which the output of any one phase is fixed to 1 in the electrical angle of 0 to 30 electrical degrees, the electrical angle of 150 to 210 electrical degrees, and the electrical angle of 330 to 360 electrical degrees. is.
- Waveform example 37 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 30 degrees to 150 degrees and at an electrical angle of 210 degrees to 330 degrees.
- the high-side-on application period T3 occurs at an electrical angle of 0 to 30 electrical degrees, from 150 to 210 electrical degrees, and from 330 to 360 electrical degrees.
- the low-side-on application period T4 occurs at an electrical angle of 30 degrees to 150 degrees and at an electrical angle of 210 degrees to 330 degrees.
- the first fixed ON period T1 includes a first fixed ON period T1v and a first fixed ON period T1w.
- the first fixed ON period T1v is from 150 electrical degrees to 210 electrical degrees.
- the first fixed ON period T1w is from an electrical angle of 0 degree to an electrical angle of 30 degrees and from an electrical angle of 330 degrees to an electrical angle of 360 degrees.
- the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
- the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
- the second fixed ON period T2v is from 30 electrical degrees to 90 electrical degrees.
- the second fixed ON period T2w is from 90 electrical degrees to 150 electrical degrees.
- the first fixed ON period T1v differs from the first fixed ON period T1u in the U phase among the three phases. Specifically, in waveform example 37, the first fixed ON period T1v is 60 degrees, but there is no first fixed ON period T1u. That is, in waveform example 37, the first fixed ON period T1v is longer than the first fixed ON period T1u.
- the first fixed ON period T1w is the same as the first fixed ON period T1v. Therefore, as shown in FIG. 57B, the switching loss of the V-phase first semiconductor switching element Up (H (high side)) is smaller than that of the U-phase.
- the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w.
- the second fixed ON period T2u is 120 degrees, while the second fixed ON period T2v and the second fixed ON period T2w are 60 degrees. That is, in waveform example 37, the second fixed on period T2u is longer than the second fixed on period T2v and the second fixed on period T2w. Therefore, as shown in FIG. 57B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
- waveform example 37 As described above with reference to FIGS. 57A and 57B , in waveform example 37, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 37, it is possible to simultaneously suppress the heat generation of the V-phase first semiconductor switching element Vp and the U-phase second semiconductor switching element Un.
- waveform example 37 as shown in FIG. 57B, the heat generated by the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
- FIG. 58A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 58B is a diagram showing switching losses.
- waveform example 38 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 45 degrees to 135 degrees and at an electrical angle of 150 degrees to 240 degrees.
- waveform example 38 the output of any one phase is fixed to 0 at an electrical angle of 0 to 45 electrical degrees, 135 to 150 electrical degrees, and 240 to 360 electrical degrees. waveform.
- the high-side-on application period T3 occurs at an electrical angle of 45 degrees to 135 degrees and at an electrical angle of 150 degrees to 240 degrees. Further, in waveform example 38, the low side-on application period T4 occurs at an electrical angle of 0 to 45 electrical degrees, 135 to 150 electrical degrees, and 240 to 360 electrical degrees.
- the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v.
- the first fixed ON period T1u is from 45 electrical degrees to 135 electrical degrees.
- the first fixed ON period T1v is from 150 electrical degrees to 240 electrical degrees.
- the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
- the second fixed ON period T2u is from 240 electrical degrees to 330 electrical degrees.
- the second fixed ON period T2v is from an electrical angle of 0 degree to an electrical angle of 45 degrees and from an electrical angle of 330 degrees to an electrical angle of 360 degrees.
- the second fixed ON period T2w is from 135 electrical degrees to 150 electrical degrees.
- the first fixed ON period T1u differs from the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 38, the first fixed ON period T1u is 90 degrees, but there is no first fixed ON period T1w. That is, in waveform example 38, the first fixed ON period T1u is longer than the first fixed ON period T1w. The first fixed ON period T1v is the same as the first fixed ON period T1u. Therefore, as shown in FIG. 58B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than that of the W-phase.
- the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w.
- the second fixed ON period T2u is 90 degrees
- the second fixed ON period T2v is 75 degrees
- the second fixed ON period T2w is 15 degrees. That is, in waveform example 38, the second fixed on period T2u is longer than the second fixed on period T2v and the second fixed on period T2w. Therefore, as shown in FIG. 58B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
- waveform example 38 As described above with reference to FIGS. 58A and 58B , in waveform example 38, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 38, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un.
- waveform example 38 as shown in FIG. 58B, the heat generated by the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
- FIG. 59A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 59B is a diagram showing switching losses.
- the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0.
- the output of any one phase is fixed to 1 at an electrical angle of 45 degrees to 135 degrees, from 150 degrees to 210 degrees and from 330 degrees to 360 degrees.
- the output of any one phase is fixed to 0 at an electrical angle of 0 to 45 electrical degrees, 135 to 150 electrical degrees, and 210 to 330 electrical degrees. waveform.
- the high-side-on application period T3 is at an electrical angle of 45 degrees to 135 degrees, at an electrical angle of 150 degrees to 210 degrees, and at an electrical angle of 330 degrees to 360 degrees.
- the low side-on application period T4 occurs at an electrical angle of 0 to 45 electrical degrees, 135 to 150 electrical degrees, and 210 to 330 electrical degrees.
- the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w.
- the first fixed ON period T1u is from 45 electrical degrees to 135 electrical degrees.
- the first fixed ON period T1v is from 150 electrical degrees to 210 electrical degrees.
- the first fixed ON period T1w is from 330 electrical degrees to 360 electrical degrees.
- the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
- the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
- the second fixed ON period T2v is from 0 electrical angle to 45 electrical degrees.
- the second fixed ON period T2w is from 135 electrical degrees to 150 electrical degrees.
- the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases.
- the first fixed ON period T1u is 90 degrees
- the first fixed ON period T1v is 60 degrees
- the first fixed ON period T1w is 30 degrees. That is, in waveform example 39, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 59B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
- the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w.
- the second fixed ON period T2u is 120 degrees
- the second fixed ON period T2v is 45 degrees
- the second fixed ON period T2w is 15 degrees. That is, in Waveform Example 39, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 59B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
- waveform example 39 As described above with reference to FIGS. 59A and 59B , in waveform example 39, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 39, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un.
- the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
- FIG. 60A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 60B is a diagram showing switching losses.
- the output voltage of any one phase is fixed to 1 in a certain electrical angle section according to the electrical angle, and the output voltage of any one phase is fixed to 1 in another electrical angle section. is fixed to 0.
- the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 120 degrees, from 150 degrees to 240 degrees, and from 330 degrees to 360 degrees.
- the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 degrees, 120 to 150 electrical degrees, and 240 to 330 electrical degrees. waveform.
- the high-side-on application period T3 is at an electrical angle of 60 to 120 electrical degrees, 150 to 240 electrical degrees, and 330 to 360 electrical degrees.
- the low side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees, 120 to 150 electrical degrees, and 240 to 330 electrical degrees.
- the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w.
- the first fixed ON period T1u is from 60 electrical degrees to 120 electrical degrees.
- the first fixed ON period T1v is from 150 electrical degrees to 240 electrical degrees.
- the first fixed ON period T1w is from 330 electrical degrees to 360 electrical degrees.
- the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
- the second fixed ON period T2u is from 240 electrical degrees to 330 electrical degrees.
- the second fixed ON period T2v is from 0 electrical angle to 60 electrical degrees.
- the second fixed ON period T2w is between 120 electrical degrees and 150 electrical degrees.
- the first fixed ON period T1v in the V phase among the three phases, is different from the first fixed ON period T1u and the first fixed ON period T1w.
- the first fixed ON period T1v is 90 degrees
- the first fixed ON period T1u is 60 degrees
- the first fixed ON period T1w is 30 degrees. That is, in waveform example 40, the first fixed ON period T1v is longer than the first fixed ON period T1u and the first fixed ON period T1w. Therefore, as shown in FIG. 60B, the switching loss of the U-phase first semiconductor switching element Vp (H (high side)) is smaller than those of the U-phase and W-phase.
- the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w.
- the second fixed ON period T2u is 90 degrees
- the second fixed ON period T2v is 60 degrees
- the second fixed ON period T2w is 30 degrees. That is, in waveform example 40, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 60B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
- waveform example 40 As described above with reference to FIGS. 60A and 60B , in waveform example 40 as well as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved.
- the heat generation of the V-phase first semiconductor switching element Vp and the U-phase second semiconductor switching element Un can be suppressed at the same time.
- the U-phase first semiconductor switching element Up the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
- FIG. 61A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 61B is a diagram showing switching losses.
- waveform example 41 the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0.
- the waveform example 41 is any of the electrical angles of 0 to 30 electrical degrees, 60 to 120 electrical degrees, 150 to 210 electrical degrees, and 330 to 360 electrical degrees. or is a waveform in which the output of one phase is fixed at 1.
- the output of any one phase is fixed to 0 at an electrical angle of 30 degrees to 60 degrees, from 120 degrees to 150 degrees and from 210 degrees to 330 degrees. waveform.
- high side ON is applied at an electrical angle of 0 to 30 electrical degrees, from 60 to 120 electrical degrees, from 150 to 210 electrical degrees, and from 330 to 360 electrical degrees. It is period T3. Further, in waveform example 41, the low side-on application period T4 is at an electrical angle of 30 to 60 electrical degrees, 120 to 150 electrical degrees, and 210 to 330 electrical degrees.
- the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w.
- the first fixed ON period T1u is from 60 electrical degrees to 120 electrical degrees.
- the first fixed ON period T1v is from 150 electrical degrees to 210 electrical degrees.
- the first fixed ON period T1w is from an electrical angle of 0 degrees to an electrical angle of 30 degrees and from an electrical angle of 330 degrees to an electrical angle of 360 degrees.
- the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
- the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
- the second fixed ON period T2v is between 30 electrical degrees and 60 electrical degrees.
- the second fixed ON period T2w is from 120 electrical degrees to 150 electrical degrees.
- the first fixed ON period T1u, the first fixed ON period T1v, and the first fixed ON period T1v are the same. Specifically, in waveform example 41, the first fixed ON period T1u, the first fixed ON period T1u, the first fixed ON period T1v, and the first fixed ON period T1v are 60 degrees.
- the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w.
- the second fixed ON period T2u is 120 degrees, while the second fixed ON period T2v and the second fixed ON period T2w are 30 degrees. That is, in waveform example 41, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 61B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
- waveform example 41 As described above with reference to FIGS. 61A and 61B, in waveform example 41, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 41, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un.
- the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
- FIG. 62A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 62B is a diagram showing switching losses.
- the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0.
- the output of any one phase is fixed to 1 at an electrical angle of 75 degrees to 105 degrees, from 150 degrees to 270 degrees, and from 330 degrees to 360 degrees.
- the output of any one phase is fixed to 0 at an electrical angle of 0 to 75 electrical degrees, 105 to 150 electrical degrees, and 270 to 330 electrical degrees. waveform.
- the high-side-on application period T3 is at an electrical angle of 75 degrees to 105 degrees, an electrical angle of 150 degrees to 270 degrees, and an electrical angle of 330 degrees to 360 degrees.
- the low side-on application period T4 occurs at an electrical angle of 0 to 75 electrical degrees, 105 to 150 electrical degrees, and 270 to 330 electrical degrees.
- the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w.
- the first fixed ON period T1u is from 75 electrical degrees to 105 electrical degrees.
- the first fixed ON period T1v is from 150 electrical degrees to 270 electrical degrees.
- the first fixed ON period T1w is from 330 electrical degrees to 360 electrical degrees.
- the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
- the second fixed ON period T2u is from 270 degrees to 330 degrees in electrical angle.
- the second fixed ON period T2v is from 0 electrical angle to 75 electrical degrees.
- the second fixed ON period T2w is from 105 electrical degrees to 150 electrical degrees.
- the first fixed ON period T1v differs from the first fixed ON period T1u and the first fixed ON period T1w.
- the first fixed ON period T1v is 120 degrees, while the first fixed ON period T1u and the first fixed ON period T1w are 30 degrees. That is, in waveform example 42, the first fixed ON period T1v is longer than the first fixed ON period T1u and the first fixed ON period T1w. Therefore, as shown in FIG. 62B, the switching loss of the V-phase first semiconductor switching element Up (H (high side)) is smaller than those of the U-phase and W-phase.
- the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w.
- the second fixed ON period T2v is 75 degrees
- the second fixed ON period T2u is 60 degrees
- the second fixed ON period T2w is 45 degrees. That is, in waveform example 42, the second fixed ON period T2v is longer than the second fixed ON period T2u and the second fixed ON period T2w. Therefore, as shown in FIG. 62B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
- waveform example 42 As described above with reference to FIGS. 62A and 62B , in waveform example 42, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 42, the heat generation of the V-phase first semiconductor switching element Vp and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
- waveform example 42 as shown in FIG. 62B, the U-phase first semiconductor switching element Up, the U-phase second semiconductor switching element Un, the W-phase first semiconductor switching element Wp, and the W-phase semiconductor switching element Wp Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
- FIG. 63A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 63B is a diagram showing switching losses.
- waveform example 43 the output voltage of any one phase is fixed to 1 in a certain electrical angle section, and the output voltage of any one phase is fixed to 1 in another electrical angle section, depending on the electrical angle. is fixed to 0.
- the waveform example 43 is any of the electrical angles of 0 to 30 electrical degrees, 75 to 105 electrical degrees, 150 to 240 electrical degrees, and 330 to 360 electrical degrees. or is a waveform in which the output of one phase is fixed at 1.
- the output of any one phase is fixed to 0 at an electrical angle of 30 degrees to 75 degrees, from 105 degrees to 150 degrees, and from 240 degrees to 330 degrees. waveform.
- high side ON is applied at an electrical angle of 0 to 30 electrical degrees, from 75 to 105 electrical degrees, from 150 to 240 electrical degrees, and from 330 to 360 electrical degrees. It is period T3. Further, in waveform example 43, the low side-on application period T4 occurs at an electrical angle of 30 to 75 electrical degrees, 105 to 150 electrical degrees, and 240 to 330 electrical degrees.
- the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w.
- the first fixed ON period T1u is from 75 electrical degrees to 105 electrical degrees.
- the first fixed ON period T1v is from 150 electrical degrees to 240 electrical degrees.
- the first fixed ON period T1w is from an electrical angle of 0 degrees to an electrical angle of 30 degrees and from an electrical angle of 330 degrees to an electrical angle of 360 degrees.
- the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
- the second fixed ON period T2u is from 240 degrees to 330 degrees in electrical angle.
- the second fixed ON period T2v is from 30 electrical degrees to 75 electrical degrees.
- the second fixed ON period T2w is from 105 electrical degrees to 150 electrical degrees.
- the first fixed ON period T1v differs from the first fixed ON period T1u and the first fixed ON period T1w.
- the first fixed ON period T1v is 90 degrees
- the first fixed ON period T1u is 30 degrees
- the first fixed ON period T1w is 60 degrees. That is, in waveform example 43, the first fixed ON period T1v is longer than the first fixed ON period T1u and the first fixed ON period T1w. Therefore, as shown in FIG. 63B, the switching loss of the V-phase first semiconductor switching element Vp (H (high side)) is smaller than those of the U-phase and W-phase.
- the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w.
- the second fixed ON period T2u is 90 degrees, while the second fixed ON period T2v and the second fixed ON period T2w are 45 degrees. That is, in waveform example 43, the second fixed on period T2u is longer than the second fixed on period T2v and the second fixed on period T2w. Therefore, as shown in FIG. 63B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
- waveform example 43 As described above with reference to FIGS. 63A and 63B , in waveform example 43, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In the waveform example 43, the heat generation of the V-phase first semiconductor switching element Vp and the U-phase second semiconductor switching element Un can be suppressed at the same time.
- waveform example 43 as shown in FIG. 63B, the U-phase first semiconductor switching element Up, the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
- FIG. 64A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 64B is a diagram showing switching losses.
- the output voltage of any one phase is fixed to 1 in a certain electrical angle section according to the electrical angle, and the output voltage of any one phase is fixed to 1 in another electrical angle section. is fixed to 0.
- the output of any one phase is fixed to 1 at an electrical angle of 0 to 30 degrees, from 150 to 270 electrical degrees, and from 330 to 360 electrical degrees.
- Waveform example 44 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 30 degrees to 150 degrees and at an electrical angle of 270 degrees to 330 degrees.
- the high-side-on application period T3 occurs at an electrical angle of 0 to 30 electrical degrees, 150 to 270 electrical degrees, and 330 to 360 electrical degrees. Further, in waveform example 44, the low side-on application period T4 occurs at an electrical angle of 30 degrees to 150 degrees and at an electrical angle of 270 degrees to 330 degrees.
- the first fixed ON period T1 includes a first fixed ON period T1v and a first fixed ON period T1w.
- the first fixed ON period T1v is from 150 electrical degrees to 270 electrical degrees.
- the first fixed ON period T1w is from 0 electrical angle to 30 electrical degrees and from 330 electrical degrees to 360 electrical degrees.
- the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
- the second fixed ON period T2u is from 270 degrees to 330 degrees in electrical angle.
- the second ON fixed period T2v is from 30 electrical degrees to 90 electrical degrees.
- the second fixed ON period T2w is from 90 electrical degrees to 150 electrical degrees.
- the first fixed ON period T1v differs from the first fixed ON period T1u and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 44, the first fixed ON period T1v is 120 degrees, whereas the first fixed ON period T1u is absent and the first fixed ON period T1w is 60 degrees. That is, in waveform example 44, the first fixed ON period T1v is longer than the first fixed ON period T1u and the first fixed ON period T1w. Therefore, as shown in FIG. 64B, the switching loss of the V-phase first semiconductor switching element Vp (H (high side)) is smaller than those of the U-phase and W-phase.
- the second fixed ON period T2u, the second fixed ON period T2v, and the second fixed ON period T2w are the same. Specifically, in waveform example 44, the second fixed ON period T2u, the second fixed ON period T2v, and the second fixed ON period T2w are 60 degrees.
- waveform example 44 As described above with reference to FIGS. 64A and 64B, in waveform example 44, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 44, it is possible to simultaneously suppress the heat generation of the V-phase first semiconductor switching element Vp and the U-phase second semiconductor switching element Un.
- waveform example 44 as shown in FIG. 64B, the heat generated by the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
- FIG. 65A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 65B is a diagram showing switching losses.
- waveform example 45 the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, in waveform example 45, the output of any one phase is fixed to 1 at an electrical angle of 0 to 30 degrees, from 150 to 240 electrical degrees, and from 300 to 360 electrical degrees. waveform. Waveform example 45 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 30 degrees to 150 degrees and at an electrical angle of 240 degrees to 300 degrees.
- the high-side-on application period T3 occurs at an electrical angle of 0 to 30 electrical degrees, 150 to 240 electrical degrees, and 300 to 360 electrical degrees. Further, in waveform example 45, the low-side-on application period T4 occurs at an electrical angle of 30 degrees to 150 electrical degrees and at an electrical angle of 240 degrees to 300 electrical degrees.
- the first fixed ON period T1 includes a first fixed ON period T1v and a first fixed ON period T1w.
- the first fixed ON period T1v is from 150 electrical degrees to 240 electrical degrees.
- the first fixed ON period T1w is from an electrical angle of 0 degrees to an electrical angle of 30 degrees and from an electrical angle of 300 degrees to an electrical angle of 360 degrees.
- the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w.
- the second fixed ON period T2u is from 240 electrical degrees to 300 electrical degrees.
- the second fixed ON period T2v is from 30 electrical degrees to 90 electrical degrees.
- the second fixed ON period T2w is from 90 electrical degrees to 150 electrical degrees.
- the first fixed ON period T1v differs from the first fixed ON period T1u and the first fixed ON period T1w.
- the first fixed ON period T1v is 90 degrees, but there is no first fixed ON period T1u. That is, in waveform example 45, the first fixed ON period T1v is longer than the first fixed ON period T1u.
- the first fixed ON period T1w is the same as the first fixed ON period T1v. Therefore, as shown in FIG. 65B, the switching loss of the V-phase first semiconductor switching element Up (H (high side)) is smaller than that of the W-phase.
- the second fixed ON period T2u, the second fixed ON period T2v, and the second fixed ON period T2w are the same. Specifically, in waveform example 45, the second fixed ON period T2u, the second fixed ON period T2v, and the second fixed ON period T2w are 60 degrees.
- waveform example 45 As described above with reference to FIGS. 65A and 65B , in waveform example 45, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In the waveform example 45, the heat generation of the V-phase first semiconductor switching element Vp and the U-phase second semiconductor switching element Un can be suppressed at the same time.
- waveform example 45 as shown in FIG. 65B, the heat generated by the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
- FIG. 66A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw.
- FIG. 66B is a diagram showing switching losses.
- waveform example 46 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 90 degrees to 270 electrical degrees.
- waveform example 46 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 to 90 degrees and at an electrical angle of 270 to 360 degrees.
- the high-side-on application period T3 is at an electrical angle of 90 degrees to 270 electrical degrees.
- the low side-on application period T4 occurs at an electrical angle of 0 to 90 electrical degrees and at an electrical angle of 270 to 360 electrical degrees.
- the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v.
- the first fixed ON period T1u is from 90 electrical degrees to 150 electrical degrees.
- the first fixed ON period T1v is from 150 electrical degrees to 270 electrical degrees.
- the second fixed ON period T2 includes a second fixed ON period T2u and a second fixed ON period T2v.
- the second fixed ON period T2u is from 270 electrical degrees to 330 electrical degrees.
- the second fixed ON period T2v is from 0 to 90 electrical degrees and from 330 to 360 electrical degrees.
- the first fixed ON period T1v differs from the first fixed ON period T1u and the first fixed ON period T1w in the V phase among the three phases. Specifically, in waveform example 46, the first fixed ON period T1v is 120 degrees, the first fixed ON period T1u is 60 degrees, and there is no first fixed ON period T1w. That is, in the waveform example 46, the first fixed ON period T1v is longer than the first fixed ON period T1u and the first fixed ON period T1w. Therefore, as shown in FIG. 66B, the switching loss of the U-phase first semiconductor switching element Vp (H (high side)) is smaller than those of the U-phase and W-phase.
- the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w.
- the second fixed ON period T2v is 120 degrees
- the second fixed ON period T2u is 60 degrees
- waveform example 46 As described above with reference to FIGS. 66A and 66B , in waveform example 46, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In the waveform example 46, the heat generation of the V-phase first semiconductor switching element Vp and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
- FIGS. 1 to 66B The embodiments of the present invention have been described above with reference to the drawings (FIGS. 1 to 66B).
- the present invention is not limited to the above-described embodiments, and can be implemented in various aspects without departing from the gist of the present invention.
- the drawings schematically show each component mainly, and the thickness, length, number, etc. of each component illustrated are different from the actual ones due to the convenience of drawing. .
- the material, shape, dimensions, etc. of each component shown in the above embodiment are examples and are not particularly limited, and various changes are possible within a range that does not substantially deviate from the effects of the present invention. be.
- the motor drive circuit 100 (power converter) described with reference to FIGS. 1 to 66B outputs a three-phase AC output, but the present invention is not limited to this.
- the motor drive circuit 100 may output AC outputs of five or more phases.
- the motor drive circuit 100 may drive the 5-phase motor M by outputting a 5-phase AC output.
- the present invention can be suitably used for power converters and motor modules.
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Abstract
This power converter converts DC power into AC power of n phases. The power converter comprises: n-number of output terminals; a first power supply terminal; a second power supply terminal; and n-number of serial bodies. During one period of AC outputs of the n phases, at least one phase of the AC outputs has a protective operation mode having at least one of a first on-fixed period during which a first semiconductor switching element is set to ON in a fixed manner and a second on-fixed period during which a second semiconductor switching element set to ON in a fixed manner. In the protective operation mode, in at least one of the n phases, the first on-fixed period is different from that of one of the other phases, or the second on-fixed period is different from that of one of the other phases.
Description
本発明は、電力変換器およびモータモジュールに関する。
The present invention relates to power converters and motor modules.
3相のモータを駆動するモータ制御装置が知られている(例えば特許文献1)。特許文献1に記載のモータ制御装置では、3相電圧の各相電圧を2π/3またはπ/3に固定することによって、スイッチング素子の温度上昇を抑制している。
A motor control device that drives a three-phase motor is known (for example, Patent Document 1). In the motor control device described in Patent Document 1, the temperature rise of the switching element is suppressed by fixing each phase voltage of the three-phase voltage to 2π/3 or π/3.
しかしながら、特許文献1に記載のモータ制御装置では、ハイサイド側の、スイッチング素子を均等に温度上昇の抑制、または、ロウサイド側のスイッチング素子を均等に温度上昇の抑制、あるいは、全てのスイッチング素子を均等に温度上昇の抑制をすることしかできない。したがって、特定の相の特定の半導体スイッチング素子を保護することができない。
However, in the motor control device described in Patent Document 1, the temperature rise of switching elements on the high side is evenly suppressed, the temperature rise of switching elements on the low side is evenly suppressed, or all switching elements are suppressed. It is only possible to uniformly suppress the temperature rise. Therefore, it is not possible to protect specific semiconductor switching elements of specific phases.
本発明は上記課題に鑑みてなされたものであり、その目的はある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子の発熱を同時に抑えることで、電力変換器の昇温を抑制し信頼性を高めることができる電力変換器およびモータモジュールを提供することにある。
The present invention has been made in view of the above problems, and its object is to simultaneously suppress the heat generation of the first semiconductor switching element of a certain phase and the heat generation of the second semiconductor switching element of a certain phase, thereby suppressing the temperature rise of the power converter. An object of the present invention is to provide a power converter and a motor module capable of suppressing and improving reliability.
本発明の例示的な電力変換器は、直流電力をn相の交流電力に変換する。前記電力変換器は、n個の出力端子と、第1電源端子と、第2電源端子と、n個の直列体とを備える。前記n個の出力端子は、n相の出力電圧とn相の出力電流とを出力する。前記第1電源端子には、第1の電圧が印加される。前記第2電源端子には、前記第1の電圧よりも低い第2の電圧が印加される。前記n個の直列体は、2つの半導体スイッチング素子が直列に接続されている。nは、交流出力の相数であって、3以上の奇数である。前記n個の直列体は、互いに並列に接続されている。前記n個の直列体の各々は、一端が前記第1電源端子に接続されている。前記n個の直列体の各々は、他端が前記第2電源端子に接続されている。前記n個の直列体の各々は、第1半導体スイッチング素子と、第2半導体スイッチング素子とを有する。前記第1半導体スイッチング素子は、前記第1電源端子に接続される。前記第2半導体スイッチング素子は、前記第2電源端子に接続される。前記第1半導体スイッチング素子と前記第2半導体スイッチング素子とは接続点において接続されている。前記n個の直列体の各々における前記接続点が、前記n個の出力端子に接続されている。前記第1半導体スイッチング素子は、前記交流出力の周波数よりも高い周波数でオンとオフとが切り替えられる。前記第2半導体スイッチング素子は、前記交流出力の周波数よりも高い周波数でオンとオフとが切り替えられる。n相の交流出力の1周期の間に、前記交流出力のうち少なくとも1相が、前記第1半導体スイッチング素子がオンに固定される第1オン固定期間と、前記第2半導体スイッチング素子がオンに固定される第2オン固定期間との少なくとも一方を有する保護動作モードを有する。前記保護動作モードにおいて、n相のうち少なくとも1相において、前記第1オン固定期間が、他のいずれか1相の前記第1オン固定期間と異なるか、または前記第2オン固定期間が、他のいずれか1相の前記第2オン固定期間と異なる。
An exemplary power converter of the present invention converts DC power into n-phase AC power. The power converter includes n output terminals, a first power terminal, a second power terminal, and n series bodies. The n output terminals output n-phase output voltages and n-phase output currents. A first voltage is applied to the first power supply terminal. A second voltage lower than the first voltage is applied to the second power supply terminal. The n series bodies are formed by connecting two semiconductor switching elements in series. n is the number of AC output phases and is an odd number of 3 or more. The n series bodies are connected in parallel with each other. One end of each of the n series bodies is connected to the first power supply terminal. Each of the n series bodies has the other end connected to the second power supply terminal. Each of the n series bodies has a first semiconductor switching element and a second semiconductor switching element. The first semiconductor switching element is connected to the first power terminal. The second semiconductor switching element is connected to the second power terminal. The first semiconductor switching element and the second semiconductor switching element are connected at a connection point. The connection points in each of the n series bodies are connected to the n output terminals. The first semiconductor switching element is switched on and off at a frequency higher than the frequency of the AC output. The second semiconductor switching element is switched on and off at a frequency higher than the frequency of the AC output. During one cycle of the n-phase AC output, at least one phase of the AC output has a first fixed ON period during which the first semiconductor switching element is fixed ON and the second semiconductor switching element is ON. It has a protection mode of operation having at least one of a fixed second ON fixed period. In the protection operation mode, in at least one of the n phases, the first fixed ON period is different from the first fixed ON period of any one of the other phases, or the second fixed ON period is different from the first fixed ON period of any other phase. is different from the second on-fixed period of any one phase.
本発明の例示的なモータモジュールは、上記に記載の電力変換器と、モータとを備える。前記モータには、前記電力変換器の出力が入力される。
An exemplary motor module of the present invention includes the power converter described above and a motor. The output of the power converter is input to the motor.
例示的な本発明によればある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子の発熱を同時に抑えることで、電力変換器の昇温を抑制し信頼性を高めることができる。
According to the exemplary present invention, by simultaneously suppressing the heat generation of the first semiconductor switching element of a certain phase and the heat generation of the second semiconductor switching element of a certain phase, it is possible to suppress the temperature rise of the power converter and improve the reliability. .
以下、本発明の実施形態について、図面を参照しながら説明する。なお、図中、同一または相当部分については同一の参照符号を付して説明を繰り返さない。
Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.
図1および図2を参照して、本発明の実施形態に係るモータモジュール200について説明する。図1は、本発明の実施形態に係るモータモジュール200のブロック図である。図2は、インバータ部110を示す回路図である。
A motor module 200 according to an embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a block diagram of a motor module 200 according to an embodiment of the invention. FIG. 2 is a circuit diagram showing the inverter section 110. As shown in FIG.
図1に示すように、モータモジュール200は、モータ駆動回路100と、3相モータMとを備える。3相モータMは、モータ駆動回路100によって駆動される。3相モータMは、例えば、ブラシレスDCモータである。3相モータMは、U相、V相およびW相を有する。3相モータMには、モータ駆動回路100の出力が入力される。なお、モータ駆動回路100は、「電力変換器」の一例に相当する。
As shown in FIG. 1, the motor module 200 includes a motor drive circuit 100 and a three-phase motor M. A three-phase motor M is driven by a motor drive circuit 100 . The three-phase motor M is, for example, a brushless DC motor. A three-phase motor M has a U-phase, a V-phase and a W-phase. The output of the motor drive circuit 100 is input to the three-phase motor M. As shown in FIG. Note that the motor drive circuit 100 corresponds to an example of a "power converter".
モータ駆動回路100は、3相モータMの駆動を制御する。モータ駆動回路100は、インバータ部110と、信号生成部120とを備える。
The motor drive circuit 100 controls driving of the three-phase motor M. The motor drive circuit 100 includes an inverter section 110 and a signal generation section 120 .
モータ駆動回路100は、直流電力をn相の交流電力に変換する。nは、交流出力の相数であって、3以上の整数である。本実施形態では、モータ駆動回路100は、直流電力を3相の交流電力に変換する。モータ駆動回路100は、n個の出力端子102を備える。本実施形態では、モータ駆動回路100は、3つの出力端子102を備える。3つの出力端子102は、出力端子102uと、出力端子102vと、出力端子102wとを含む。n個の出力端子102は、n相の出力電圧とn相の出力電流とを出力する。本実施形態では、3つの出力端子102は、3相の出力電圧と3相の出力電流とを3相モータMへ出力する。詳しくは、出力端子102uは、U相の出力電圧Vuと、U相の出力電流Iuとを3相モータMへ出力する。出力端子102vは、V相の出力電圧Vvと、V相の出力電流Ivとを3相モータMへ出力する。出力端子102wは、W相の出力電圧Vwと、W相の出力電流Iwとを3相モータMへ出力する。
The motor drive circuit 100 converts DC power into n-phase AC power. n is the number of AC output phases and is an integer of 3 or more. In this embodiment, the motor drive circuit 100 converts DC power into three-phase AC power. The motor drive circuit 100 has n output terminals 102 . In this embodiment, the motor drive circuit 100 has three output terminals 102 . The three output terminals 102 include an output terminal 102u, an output terminal 102v, and an output terminal 102w. The n output terminals 102 output n-phase output voltages and n-phase output currents. In this embodiment, the three output terminals 102 output three-phase output voltages and three-phase output currents to the three-phase motor M. FIG. More specifically, the output terminal 102u outputs the U-phase output voltage Vu and the U-phase output current Iu to the three-phase motor M. Output terminal 102v outputs V-phase output voltage Vv and V-phase output current Iv to three-phase motor M. FIG. The output terminal 102w outputs the W-phase output voltage Vw and the W-phase output current Iw to the three-phase motor M.
図2に示すように、モータ駆動回路100は、第1電源端子Pと、第2電源端子Nと、コンデンサCと、n個の直列体112と、6つの温度センサ20とを備える。本実施形態では、モータ駆動回路100は、第1電源端子Pと、第2電源端子Nと、コンデンサCと、3つの直列体112と、6つの温度センサ20とを備える。より具体的には、本実施形態では、モータ駆動回路100は、インバータ部110を備え、インバータ部110は、第1電源端子Pと、第2電源端子Nと、コンデンサCと、3つの直列体112と、6つの温度センサ20とを備える。インバータ部110は、直流電圧源Bをさらに備える。なお、直流電圧源Bは、インバータ部110の外部にあってもよい。
As shown in FIG. 2, the motor drive circuit 100 includes a first power terminal P, a second power terminal N, a capacitor C, n series bodies 112, and six temperature sensors 20. In this embodiment, the motor drive circuit 100 includes a first power terminal P, a second power terminal N, a capacitor C, three series bodies 112 and six temperature sensors 20 . More specifically, in this embodiment, the motor drive circuit 100 includes an inverter section 110. The inverter section 110 includes a first power terminal P, a second power terminal N, a capacitor C, and three series bodies. 112 and six temperature sensors 20 . Inverter section 110 further includes a DC voltage source B. FIG. Note that the DC voltage source B may be provided outside the inverter section 110 .
第1電源端子Pには、第1の電圧V1が印加される。第1電源端子Pは、直流電圧源Bに接続されている。
A first voltage V1 is applied to the first power supply terminal P. A first power supply terminal P is connected to a DC voltage source B;
第2電源端子Nには、第2の電圧V2が印加される。第2電源端子Nは、直流電圧源Bに接続されている。第2の電圧V2は、第1の電圧V1よりも低い。
A second voltage V2 is applied to the second power supply terminal N. A second power supply terminal N is connected to a DC voltage source B. As shown in FIG. The second voltage V2 is lower than the first voltage V1.
コンデンサCは、第1電源端子Pと第2電源端子Nとの間に接続される。
The capacitor C is connected between the first power terminal P and the second power terminal N.
3つの直列体112には、2つの半導体スイッチング素子が直列に接続されている。半導体スイッチング素子は、例えば、IGBT(絶縁ゲートバイポーラトランジスタ)である。なお、半導体スイッチング素子は、電界効果トランジスタのような他のトランジスタであってもよい。3つの直列体112は、直列体112uと、直列体112vと、直列体112wとを含む。3つの直列体112は、互いに並列に接続されている。3つの直列体112の各々は、一端が第1電源端子Pに接続されている。3つの直列体112の各々は、他端が第2電源端子Nに接続されている。これらの半導体スイッチング素子にはそれぞれ、第1電源端子P側(紙面上側)をカソード、第2電源端子N側(紙面下側)をアノードとして、整流素子Dが並列に接続される。半導体スイッチング素子として電界効果トランジスタを用いる場合には、寄生ダイオードをこの整流素子として用いてもよい。
Two semiconductor switching elements are connected in series to the three series bodies 112 . The semiconductor switching element is, for example, an IGBT (insulated gate bipolar transistor). Note that the semiconductor switching element may be another transistor such as a field effect transistor. The three series bodies 112 include a series body 112u, a series body 112v, and a series body 112w. The three series bodies 112 are connected in parallel with each other. Each of the three series bodies 112 is connected to the first power terminal P at one end. Each of the three series bodies 112 is connected to the second power terminal N at the other end. A rectifying element D is connected in parallel to each of these semiconductor switching elements, with the first power supply terminal P side (upper side of the paper) as a cathode and the second power supply terminal N side (lower side of the paper) as an anode. If a field effect transistor is used as the semiconductor switching element, a parasitic diode may be used as this rectifying element.
3つの直列体112の各々は、第1半導体スイッチング素子と、第2半導体スイッチング素子とを有する。詳しくは、直列体112uは、第1半導体スイッチング素子Upと、第2半導体スイッチング素子Unとを有する。直列体112vは、第1半導体スイッチング素子Vpと、第2半導体スイッチング素子Vnとを有する。直列体112wは、第1半導体スイッチング素子Wpと、第2半導体スイッチング素子Wnとを有する。
Each of the three series bodies 112 has a first semiconductor switching element and a second semiconductor switching element. Specifically, the series body 112u has a first semiconductor switching element Up and a second semiconductor switching element Un. Series body 112v has a first semiconductor switching element Vp and a second semiconductor switching element Vn. The series body 112w has a first semiconductor switching element Wp and a second semiconductor switching element Wn.
第1半導体スイッチング素子Up、第1半導体スイッチング素子Vpおよび第1半導体スイッチング素子Wpは、第1電源端子Pに接続される。換言すると、第1半導体スイッチング素子Up、第1半導体スイッチング素子Vpおよび第1半導体スイッチング素子Wpは、高電圧側の半導体スイッチング素子である。
The first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp are connected to the first power supply terminal P. In other words, the first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp are semiconductor switching elements on the high voltage side.
第2半導体スイッチング素子Un、第2半導体スイッチング素子Vnおよび第2半導体スイッチング素子Wnは、第2電源端子Nに接続される。換言すると、第2半導体スイッチング素子Un、第2半導体スイッチング素子Vnおよび第2半導体スイッチング素子Wnは、低電圧側の半導体スイッチング素子である。
The second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn are connected to the second power supply terminal N. In other words, the second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn are semiconductor switching elements on the low voltage side.
第1半導体スイッチング素子と第2半導体スイッチング素子とは接続点114において接続されている。詳しくは、第1半導体スイッチング素子Upと、第2半導体スイッチング素子Unとは、接続点114uにおいて接続されている。第1半導体スイッチング素子Vpと、第2半導体スイッチング素子Vnとは、接続点114vにおいて接続されている。第1半導体スイッチング素子Wpと、第2半導体スイッチング素子Wnとは、接続点114wにおいて接続されている。
The first semiconductor switching element and the second semiconductor switching element are connected at the connection point 114 . Specifically, the first semiconductor switching element Up and the second semiconductor switching element Un are connected at a connection point 114u. The first semiconductor switching element Vp and the second semiconductor switching element Vn are connected at a connection point 114v. The first semiconductor switching element Wp and the second semiconductor switching element Wn are connected at a connection point 114w.
3つの直列体112の各々における接続点114が、3つの出力端子102に接続されている。詳しくは、直列体112uにおける接続点114uが、出力端子102uに接続されている。直列体112vにおける接続点114vが、出力端子102vに接続されている。直列体112wにおける接続点114wが、出力端子102wに接続されている。
A connection point 114 in each of the three series bodies 112 is connected to the three output terminals 102 . Specifically, a connection point 114u in the series body 112u is connected to the output terminal 102u. A connection point 114v in the series body 112v is connected to the output terminal 102v. A connection point 114w in the series body 112w is connected to the output terminal 102w.
第1半導体スイッチング素子Up、第1半導体スイッチング素子Vpおよび第1半導体スイッチング素子Wpには、PWM信号が入力される。PWM信号は、信号生成部120から出力される。以下、本明細書において、第1半導体スイッチング素子Upに入力されるPWM信号を「UpPWM信号」と記載することがある。また、第1半導体スイッチング素子Vpに入力されるPWM信号を「VpPWM信号」と記載することがある。第1半導体スイッチング素子Wpに入力されるPWM信号を「WpPWM信号」と記載することがある。第1半導体スイッチング素子Up、第1半導体スイッチング素子Vpおよび第1半導体スイッチング素子Wpは、交流出力の周波数よりも高い周波数でオンとオフとが切り替えられる。例えば、第1半導体スイッチング素子Up、第1半導体スイッチング素子Vpおよび第1半導体スイッチング素子Wpは、それぞれ、UpPWM信号、VpPWM信号およびWpPWM信号がHIGHレベルの場合に、オンとなる。一方、第1半導体スイッチング素子Up、第1半導体スイッチング素子Vpおよび第1半導体スイッチング素子Wpは、それぞれ、UpPWM信号、VpPWM信号およびWpPWM信号がLOWレベルの場合に、オフとなる。
A PWM signal is input to the first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp. A PWM signal is output from the signal generator 120 . Hereinafter, in this specification, the PWM signal input to the first semiconductor switching element Up may be referred to as "UpPWM signal". Also, the PWM signal input to the first semiconductor switching element Vp may be referred to as "Vp PWM signal". A PWM signal input to the first semiconductor switching element Wp may be referred to as a "Wp PWM signal". The first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp are switched on and off at a frequency higher than the frequency of the AC output. For example, the first semiconductor switching element Up, the first semiconductor switching element Vp, and the first semiconductor switching element Wp are turned on when the UpPWM signal, the VpPWM signal, and the WpPWM signal are at HIGH level, respectively. On the other hand, the first semiconductor switching element Up, the first semiconductor switching element Vp and the first semiconductor switching element Wp are turned off when the UpPWM signal, the VpPWM signal and the WpPWM signal are at LOW level, respectively.
第2半導体スイッチング素子Un、第2半導体スイッチング素子Vnおよび第2半導体スイッチング素子Wnには、PWM信号が入力される。PWM信号は、信号生成部120から出力される。以下、本明細書において、第2半導体スイッチング素子Unに入力されるPWM信号を「UnPWM信号」と記載することがある。また、第2半導体スイッチング素子Vnに入力されるPWM信号を「VnPWM信号」と記載することがある。第2半導体スイッチング素子Wnに入力されるPWM信号を「WnPWM信号」と記載することがある。第2半導体スイッチング素子Un、第2半導体スイッチング素子Vnおよび第2半導体スイッチング素子Wnは、交流出力の周波数よりも高い周波数でオンとオフとが切り替えられる。例えば、第2半導体スイッチング素子Un、第2半導体スイッチング素子Vnおよび第2半導体スイッチング素子Wnは、それぞれ、UnPWM信号、VnPWM信号およびWnPWM信号がHIGHレベルの場合に、オンとなる。一方、第2半導体スイッチング素子Un、第2半導体スイッチング素子Vnおよび第2半導体スイッチング素子Wnは、それぞれ、UnPWM信号、VnPWM信号およびWnPWM信号がLOWレベルの場合に、オフとなる。
A PWM signal is input to the second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn. A PWM signal is output from the signal generator 120 . Hereinafter, in this specification, the PWM signal input to the second semiconductor switching element Un may be referred to as "UnPWM signal". Also, the PWM signal input to the second semiconductor switching element Vn may be referred to as "Vn PWM signal". A PWM signal input to the second semiconductor switching element Wn may be referred to as a "Wn PWM signal". The second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn are switched on and off at a frequency higher than the frequency of the AC output. For example, the second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn are turned on when the UnPWM signal, the VnPWM signal, and the WnPWM signal are at HIGH level, respectively. On the other hand, the second semiconductor switching element Un, the second semiconductor switching element Vn, and the second semiconductor switching element Wn are turned off when the UnPWM signal, the VnPWM signal, and the WnPWM signal are at LOW level, respectively.
図1に示すように、信号生成部120は、キャリア生成部122と、電圧指令値生成部124と、比較部126とを有する。信号生成部120は、CPU(Central Processing Unit)のようなプロセッサー、およびASIC(Application Specific Integrated Circuit)等によって構成されるハードウェア回路である。そして、信号生成部120のプロセッサーは、記憶装置に記憶されたコンピュータープログラムを実行することによって、キャリア生成部122と、電圧指令値生成部124と、比較部126として機能する。
As shown in FIG. 1, the signal generation section 120 has a carrier generation section 122, a voltage command value generation section 124, and a comparison section 126. The signal generator 120 is a hardware circuit configured by a processor such as a CPU (Central Processing Unit) and an ASIC (Application Specific Integrated Circuit). The processor of signal generation unit 120 functions as carrier generation unit 122, voltage command value generation unit 124, and comparison unit 126 by executing computer programs stored in the storage device.
信号生成部120は、インバータ部110を制御する。具体的には、信号生成部120は、PWM信号を生成してPWM信号を出力することによって、インバータ部110を制御する。より具体的には、信号生成部120は、3つの直列体112のそれぞれに入力するPWM信号を生成する。
The signal generation section 120 controls the inverter section 110 . Specifically, the signal generation unit 120 controls the inverter unit 110 by generating a PWM signal and outputting the PWM signal. More specifically, signal generator 120 generates a PWM signal to be input to each of three serial bodies 112 .
キャリア生成部122は、キャリア信号を生成する。キャリア信号は、例えば、三角波である。なお、キャリア信号は、鋸波であってもよい。
The carrier generator 122 generates a carrier signal. A carrier signal is, for example, a triangular wave. Note that the carrier signal may be a sawtooth wave.
電圧指令値生成部124は、電圧指令値を生成する。電圧指令値は、モータ駆動回路100から出力する電圧値に相当する。すなわち、電圧指令値生成部124は、出力電圧Vu、出力電圧Vvおよび出力電圧Vwに応じた電圧値を電圧指令値として生成する。
The voltage command value generation unit 124 generates a voltage command value. A voltage command value corresponds to a voltage value output from the motor drive circuit 100 . That is, voltage command value generation unit 124 generates voltage values corresponding to output voltage Vu, output voltage Vv, and output voltage Vw as voltage command values.
比較部126は、キャリア信号と、電圧指令値とを比較することによってPWM信号を生成する。
The comparator 126 generates a PWM signal by comparing the carrier signal and the voltage command value.
6つの温度センサ20は、温度センサ21uと、温度センサ21vと、温度センサ21wと、温度センサ22uと、温度センサ22vと、温度センサ22wとを含む。6つの温度センサ20は、半導体スイッチング素子の近傍に配置される。6つの温度センサ20は、半導体スイッチング素子の温度を検出する。詳しくは、温度センサ21uは、第1半導体スイッチング素子Upの近傍に配置される。温度センサ21uは、第1半導体スイッチング素子Upの温度を検出する。温度センサ21vは、第1半導体スイッチング素子Vpの近傍に配置される。温度センサ21vは、第1半導体スイッチング素子Vpの温度を検出する。温度センサ21wは、第1半導体スイッチング素子Wpの近傍に配置される。温度センサ21wは、第1半導体スイッチング素子Wpの温度を検出する。温度センサ22uは、第2半導体スイッチング素子Unの近傍に配置される。温度センサ22uは、第2半導体スイッチング素子Unの温度を検出する。温度センサ22vは、第2半導体スイッチング素子Vnの近傍に配置される。温度センサ22vは、第2半導体スイッチング素子Vnの温度を検出する。温度センサ22wは、第2半導体スイッチング素子Wnの近傍に配置される。温度センサ22wは、第2半導体スイッチング素子Wnの温度を検出する。
The six temperature sensors 20 include a temperature sensor 21u, a temperature sensor 21v, a temperature sensor 21w, a temperature sensor 22u, a temperature sensor 22v, and a temperature sensor 22w. Six temperature sensors 20 are arranged in the vicinity of the semiconductor switching elements. Six temperature sensors 20 detect the temperature of the semiconductor switching elements. Specifically, the temperature sensor 21u is arranged near the first semiconductor switching element Up. The temperature sensor 21u detects the temperature of the first semiconductor switching element Up. The temperature sensor 21v is arranged near the first semiconductor switching element Vp. The temperature sensor 21v detects the temperature of the first semiconductor switching element Vp. The temperature sensor 21w is arranged near the first semiconductor switching element Wp. The temperature sensor 21w detects the temperature of the first semiconductor switching element Wp. The temperature sensor 22u is arranged near the second semiconductor switching element Un. The temperature sensor 22u detects the temperature of the second semiconductor switching element Un. The temperature sensor 22v is arranged near the second semiconductor switching element Vn. Temperature sensor 22v detects the temperature of second semiconductor switching element Vn. The temperature sensor 22w is arranged near the second semiconductor switching element Wn. The temperature sensor 22w detects the temperature of the second semiconductor switching element Wn.
次に、図3Aおよび図3Bを参照して、出力電圧について説明する。図3Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図3Bは、スイッチング損失を示す図である。3相すべてをスイッチングする3相変調の場合のスイッチング素子1つあたりのスイッチング損失を1とした場合の相対値として、各素子のスイッチング損失を表している。図3Aは、本発明の実施形態に係る出力電圧Vu、出力電圧Vvおよび出力電圧Vwの波形例1を示す。
Next, the output voltage will be described with reference to FIGS. 3A and 3B. FIG. 3A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 3B is a diagram showing switching losses. The switching loss of each element is shown as a relative value when the switching loss per switching element is 1 in the case of three-phase modulation in which all three phases are switched. FIG. 3A shows waveform example 1 of the output voltage Vu, the output voltage Vv, and the output voltage Vw according to the embodiment of the present invention.
図3Aにおいて、出力電圧Vuを実線で示しており、出力電圧Vvを破線で示しており、出力電圧Vwを一点鎖線で示している。図3Aの縦軸は入力電圧V1-V2で規格化した電圧値を表しており、各相の出力電圧は0~1の範囲の値をとる。出力電圧0とは、出力電圧がV2に実質的に一致する状態であり、出力電圧1とは、出力電圧がV1に実質的に一致する状態である。またこの値は、PWM周期に対する各相の第1半導体スイッチング素子のオン時間の比率であるデューティ値も表している。第2半導体スイッチング素子をスイッチングする場合は、1から縦軸の値を引いたものが、PWM周期に対する第2半導体スイッチング素子のオン時間の比率となる。第1半導体スイッチング素子と第2半導体スイッチング素子との両方をスイッチングする場合は、両者が同時にオンすることを防ぐために適当なデッドタイムを設けた上で、相補的にスイッチングを行う。図3Aの横軸は、モータの電気回転角を表しており、単位は度である。
In FIG. 3A, the output voltage Vu is indicated by a solid line, the output voltage Vv is indicated by a dashed line, and the output voltage Vw is indicated by a dashed line. The vertical axis of FIG. 3A represents the voltage value normalized by the input voltage V1-V2, and the output voltage of each phase takes a value in the range of 0-1. Output voltage 0 is the state in which the output voltage substantially matches V2, and output voltage 1 is the state in which the output voltage substantially matches V1. This value also represents the duty value, which is the ratio of the ON time of the first semiconductor switching element of each phase to the PWM cycle. When switching the second semiconductor switching element, the value obtained by subtracting the value on the vertical axis from 1 is the ratio of the ON time of the second semiconductor switching element to the PWM cycle. When both the first semiconductor switching element and the second semiconductor switching element are switched, complementary switching is performed after providing an appropriate dead time to prevent both from being turned on at the same time. The horizontal axis of FIG. 3A represents the electrical rotation angle of the motor in degrees.
図3Aを参照して、本発明の実施形態に係る出力電圧Vu、出力電圧Vvおよび出力電圧Vwの波形例1について説明する。
A waveform example 1 of the output voltage Vu, the output voltage Vv, and the output voltage Vw according to the embodiment of the present invention will be described with reference to FIG. 3A.
図3Aに示すように、波形例1は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例1は、電気角30度~電気角150度において、いずれか1相の出力が1に固定される波形である。また、電気角0度~電気角30度および電気角150度~電気角360度において、いずれか1相の出力が0に固定される波形である。本明細書において、いずれか1相の出力が1に固定される期間を、ハイサイドオン適用期間T3と記載することがある。また、本明細書において、いずれか1相の出力が0に固定される期間を、ロウサイドオン適用期間T4と記載することがある。波形例1では、電気角30度~電気角150度において、ハイサイドオン適用期間T3である。また、波形例1では、電気角0度~電気角30度および電気角150度~電気角360度において、ロウサイドオン適用期間T4である。出力電圧Vu、出力電圧Vvおよび出力電圧Vwの2相の差分が正弦波となっていることが好ましい。したがって、出力端子間電圧としては正弦波を出力することができる。その結果、例えばモータを駆動する場合にはノイズおよびトルクムラの少ない動作が可能となる。例えば、2π/nずつの位相差を有する正弦波から共通のオフセット波形を差し引くことで、各相の出力電圧波形が得られ、この各相の出力電圧波形を電圧指令値とすることができる。
As shown in FIG. 3A, in waveform example 1, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval according to the electrical angle, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, waveform example 1 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 30 degrees to 150 degrees. Also, the waveform is such that the output of any one phase is fixed to 0 at an electrical angle of 0 to 30 electrical degrees and at an electrical angle of 150 to 360 electrical degrees. In this specification, the period during which the output of any one phase is fixed to 1 may be referred to as a high-side-on application period T3. Also, in this specification, the period during which the output of any one phase is fixed to 0 may be referred to as a low-side-on application period T4. In waveform example 1, the high-side-on application period is T3 at an electrical angle of 30 degrees to 150 electrical degrees. Further, in waveform example 1, the low side-on application period T4 occurs at an electrical angle of 0 to 30 electrical degrees and at an electrical angle of 150 to 360 electrical degrees. It is preferable that the difference between the two phases of the output voltage Vu, the output voltage Vv, and the output voltage Vw is a sine wave. Therefore, a sine wave can be output as the voltage between the output terminals. As a result, for example, when driving a motor, it is possible to operate with little noise and torque unevenness. For example, by subtracting a common offset waveform from sine waves having a phase difference of 2π/n each, an output voltage waveform for each phase can be obtained, and this output voltage waveform for each phase can be used as a voltage command value.
図3Aに示すように、n相の交流出力の1周期の間に、交流出力のうち少なくとも1相が、第1オン固定期間T1と、第2オン固定期間T2とを有する。第1オン固定期間T1は、第1半導体スイッチング素子がオンに固定される期間である。第2オン固定期間T2は、第2半導体スイッチング素子がオンに固定される期間である。
As shown in FIG. 3A, during one cycle of the n-phase AC output, at least one phase of the AC output has a first fixed ON period T1 and a second fixed ON period T2. The first fixed on period T1 is a period in which the first semiconductor switching element is fixed on. The second fixed on period T2 is a period during which the second semiconductor switching element is fixed on.
波形例1では、第1オン固定期間T1は、第1オン固定期間T1uを含む。第1オン固定期間T1uは、第1半導体スイッチング素子Upがオンに固定される期間である。波形例1では、電気角30度~電気角150度が第1オン固定期間T1uである。
In Waveform Example 1, the first fixed ON period T1 includes the first fixed ON period T1u. The first fixed on period T1u is a period in which the first semiconductor switching element Up is fixed on. In Waveform Example 1, the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees.
第1オン固定期間T1は、n相のうち1相のみの第1半導体スイッチング素子がオン固定となり、n相のうち他の相全てにおいて、第1半導体スイッチング素子または第2半導体スイッチング素子の少なくとも一方がスイッチングする期間を示す。波形例1では、第1オン固定期間T1uにおいて、3相のうちU相の第1半導体スイッチング素子Upのみがオン固定となり、3相のうちV相の第1半導体スイッチング素子Vpまたは第2半導体スイッチング素子Vnの少なくとも一方、およびW相の第1半導体スイッチング素子Wpまたは第2半導体スイッチング素子Wnの少なくとも一方がスイッチングする。
In the first fixed ON period T1, only one of the n phases of the first semiconductor switching element is fixed on, and in all of the other n phases, at least one of the first semiconductor switching element and the second semiconductor switching element is fixed. indicates the switching period. In waveform example 1, in the first fixed on period T1u, only the U-phase first semiconductor switching element Up of the three phases is fixed on, and the V-phase first semiconductor switching element Vp or the second semiconductor switching element Vp of the three phases is fixed. At least one of the elements Vn and at least one of the W-phase first semiconductor switching element Wp or the second semiconductor switching element Wn switches.
波形例1では、第2オン固定期間T2は、第2オン固定期間T2uと、第2オン固定期間T2vと、第2オン固定期間T2wとを含む。波形例1では、電気角210度~電気角330度が第2オン固定期間T2uである。波形例1では、電気角0度~電気角30度および電気角330度~電気角360度が第2オン固定期間T2vである。波形例1では、電気角150度~電気角210度が第2オン固定期間T2wである。
In Waveform Example 1, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In Waveform Example 1, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In waveform example 1, the second fixed ON period T2v is from 0 electrical angle to 30 electrical degrees and from 330 electrical degrees to 360 electrical degrees. In Waveform Example 1, the second fixed ON period T2w is from 150 electrical degrees to 210 electrical degrees.
第2オン固定期間T2は、n相のうち1相のみの第2半導体スイッチング素子がオン固定となり、n相のうち他の相全てにおいて、第1半導体スイッチング素子または第2半導体スイッチング素子の少なくとも一方がスイッチングする期間を示す。波形例1では、第2オン固定期間T2uにおいて、3相のうちU相の第2半導体スイッチング素子Unのみがオン固定となり、3相のうちV相の第1半導体スイッチング素子Vpまたは第2半導体スイッチング素子Vnの少なくとも一方、およびW相の第1半導体スイッチング素子Wpまたは第2半導体スイッチング素子Wnの少なくとも一方がスイッチングする。波形例1では、第2オン固定期間T2vにおいて、3相のうちV相の第2半導体スイッチング素子Vnのみがオン固定となり、3相のうちU相の第1半導体スイッチング素子Upまたは第2半導体スイッチング素子Unの少なくとも一方、およびW相の第1半導体スイッチング素子Wpまたは第2半導体スイッチング素子Wnの少なくとも一方がスイッチングする。波形例1では、第2オン固定期間T2wにおいて、3相のうちW相の第2半導体スイッチング素子Wnのみがオン固定となり、3相のうちU相の第1半導体スイッチング素子Upまたは第2半導体スイッチング素子Unの少なくとも一方、およびV相の第1半導体スイッチング素子Vpまたは第2半導体スイッチング素子Vnの少なくとも一方がスイッチングする。
In the second fixed on period T2, only one of the n phases of the second semiconductor switching element is fixed on, and at least one of the first semiconductor switching element and the second semiconductor switching element is set in all the other phases of the n phases. indicates the switching period. In waveform example 1, in the second fixed on period T2u, only the U-phase second semiconductor switching element Un among the three phases is fixed on, and the V-phase first semiconductor switching element Vp or the second semiconductor switching element Vp among the three phases is fixed. At least one of the elements Vn and at least one of the W-phase first semiconductor switching element Wp or the second semiconductor switching element Wn switches. In the waveform example 1, only the V-phase second semiconductor switching element Vn of the three phases is fixed on during the second fixed ON period T2v, and the U-phase first semiconductor switching element Up or the second semiconductor switching element Vn of the three phases is fixed. At least one of the elements Un and at least one of the W-phase first semiconductor switching element Wp or second semiconductor switching element Wn switches. In waveform example 1, only the W-phase second semiconductor switching element Wn among the three phases is fixed to the ON state during the second fixed ON period T2w, and the U-phase first semiconductor switching element Up or the second semiconductor switching element Wn among the three phases is turned ON. At least one of the elements Un and at least one of the V-phase first semiconductor switching element Vp or second semiconductor switching element Vn switches.
交流出力の1周期は複数の期間に分割され、複数の期間はそれぞれ、いずれかの相の第1オン固定期間またはいずれかの相の第2オン固定期間である。詳しくは、波形例1では、電気角0度~電気角30度が第2オン固定期間T2vである。波形例1では、電気角30度~電気角150度が第1オン固定期間T1uである。波形例1では、電気角150度~電気角210度が第2オン固定期間T2wである。波形例1では、電気角210度~電気角330度が第2オン固定期間T2uである。波形例1では、電気角330度~電気角360度が第2オン固定期間T2vである。したがって、常に一相のスイッチングを停止するので、効果的な昇温抑制が可能となり、インバータの信頼性が高まる。
One cycle of the AC output is divided into a plurality of periods, and each of the plurality of periods is the first fixed ON period of one of the phases or the second fixed ON period of one of the phases. Specifically, in Waveform Example 1, the second fixed ON period T2v is between an electrical angle of 0 degree and an electrical angle of 30 degrees. In Waveform Example 1, the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees. In Waveform Example 1, the second fixed ON period T2w is from 150 electrical degrees to 210 electrical degrees. In Waveform Example 1, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In Waveform Example 1, the second fixed ON period T2v is from 330 electrical degrees to 360 electrical degrees. Therefore, since the switching of one phase is always stopped, temperature rise can be effectively suppressed, and the reliability of the inverter is enhanced.
モータ駆動回路100は、保護動作モードを有する。保護動作モードは、第1オン固定期間T1と第2オン固定期間T2との少なくとも一方を有する。保護動作モードにおいて、n相のうち少なくとも1相において、第1オン固定期間T1が、他のいずれか1相の第1オン固定期間T1と異なるか、または、第2オン固定期間T2が、他のいずれか1相の第2オン固定期間T2と異なる。他のいずれか1相が第1オン固定期間T1および第2オン固定期間T2を有さない場合もこれに含まれる。
The motor drive circuit 100 has a protection operation mode. The protection operation mode has at least one of the first fixed ON period T1 and the second fixed ON period T2. In the protection operation mode, in at least one of the n phases, the first fixed ON period T1 is different from the first fixed ON period T1 of any one of the other phases, or the second fixed ON period T2 is different from the first fixed ON period T1 of any other phase. is different from the second on-fixed period T2 of any one phase. This also includes the case where any other phase does not have the first fixed ON period T1 and the second fixed ON period T2.
波形例1では、3相のうちU相において、第1オン固定期間T1uが、第1オン固定期間T1vおよび第1オン固定期間T1wと異なる。詳しくは、波形例1では、第1オン固定期間T1uが120度であるのに対し、第1オン固定期間T1vおよび第1オン固定期間T1wは無い。すなわち、波形例1では、第1オン固定期間T1uが第1オン固定期間T1vおよび第1オン固定期間T1wよりも長い。したがって、図3Bに示すように、U相の第1半導体スイッチング素子Up(H(ハイサイド))のスイッチング損失がV相およびW相に比べて小さくなっている。
In waveform example 1, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 1, the first fixed ON period T1u is 120 degrees, but there is no first fixed ON period T1v and no first fixed ON period T1w. That is, in Waveform Example 1, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 3B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
波形例1では、3相のうちU相において、第2オン固定期間T2uが、第2オン固定期間T2vおよび第2オン固定期間T2wと異なる。詳しくは、波形例1では、第2オン固定期間T2uが120度であるのに対し、第2オン固定期間T2vおよび第2オン固定期間T2wは60度である。すなわち、波形例1では、第2オン固定期間T2uが第2オン固定期間T2vおよび第2オン固定期間T2wよりも長い。したがって、図3Bに示すように、U相の第2半導体スイッチング素子Un(L(ロウサイド))のスイッチング損失がV相およびW相に比べて小さくなっている。
In waveform example 1, the second fixed ON period T2u differs from the second fixed ON period T2v and the second fixed ON period T2w in the U phase among the three phases. Specifically, in Waveform Example 1, the second fixed ON period T2u is 120 degrees, while the second fixed ON period T2v and the second fixed ON period T2w are 60 degrees. That is, in Waveform Example 1, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 3B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
以上、図1~図3Bを参照して説明したように、波形例1では、保護動作モードにおいて、n相のうち少なくとも1相において、第1オン固定期間T1が、他の相の第1オン固定期間T1と異なる。したがって、他の相の第1オン固定期間T1よりも長い第1オン固定期間を有する相の第1半導体スイッチング素子の発熱を抑制することができる。また、n相のうち少なくとも1相において、第2オン固定期間T2が、他の相の第2オン固定期間T2と異なる。したがって、他の相の第2オン固定期間T2よりも長い第2オン固定期間を有する相の第2半導体スイッチング素子の発熱を抑制することができる。また特に、波形例1では、少なくとも1相において、第1オン固定期間T1が、他の相の第1オン固定期間T1と異なり、かつ少なくとも1相において、第2オン固定期間T2が、他の相の第2オン固定期間T2と異なる。したがって、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。例えば、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子とが、近傍に発熱部品が存在する、あるいは放熱効率の悪い位置に配置されている、等の原因により、スイッチング動作により温度上昇が起こりやすい場合、波形例1の手法によってこれら2つの素子のスイッチング発熱を抑制することで、これら2素子が過度に温度上昇することを防ぎ、電力変換器(インバータ)の信頼性を高めることができる。波形例1では、U相の第1半導体スイッチング素子Upと、U相の第2半導体スイッチング素子Unとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 1 to 3B, in the waveform example 1, in the protection operation mode, in at least one of the n phases, the first fixed ON period T1 is set to the first ON period of the other phases. It differs from the fixed period T1. Therefore, heat generation of the first semiconductor switching element of the phase having the first fixed ON period longer than the first fixed ON period T1 of the other phase can be suppressed. Moreover, in at least one of the n phases, the second fixed ON period T2 is different from the second fixed ON periods T2 of the other phases. Therefore, heat generation of the second semiconductor switching element of the phase having the second fixed ON period longer than the second fixed ON period T2 of the other phase can be suppressed. In particular, in Waveform Example 1, in at least one phase, the first fixed ON period T1 is different from the first fixed ON periods T1 of other phases, and in at least one phase, the second fixed ON period T2 is different from that of the other phase. It is different from the second on-fixed period T2 of the phase. Therefore, by simultaneously suppressing the heat generation of the first semiconductor switching element of a certain phase and the heat generation of the second semiconductor switching element of a certain phase, temperature rise of the power converter (inverter) can be suppressed and reliability can be improved. For example, the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase may have heat-generating components in their vicinity, or may be arranged in positions with poor heat dissipation efficiency. If the temperature rise is likely to occur due to the power converter (inverter), the switching heat generation of these two elements can be suppressed using the method of Waveform Example 1 to prevent the temperature of these two elements from rising excessively and improve the reliability of the power converter (inverter). can be enhanced. In waveform example 1, the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un can be suppressed at the same time.
また、波形例1では、図3Bに示すように、V相の第2オン固定期間T2vおよびW相の第2オン固定期間T2wを設けることにより、V相の第2半導体スイッチング素子Vnと、W相の第2半導体スイッチング素子Wnとの発熱についても同時に抑えることができる。このため、U相が最も温度上昇しやすく、続いて他の相の第2半導体スイッチング素子が温度上昇しやすい環境にある場合、これらの素子の過熱を防止し信頼性を高める。
Further, in the waveform example 1, as shown in FIG. 3B, by providing the V-phase second fixed ON period T2v and the W-phase second fixed ON period T2w, the V-phase second semiconductor switching element Vn and the W Heat generation with the second semiconductor switching element Wn of the phase can also be suppressed at the same time. Therefore, when the temperature of the U phase is most likely to rise and the temperature of the second semiconductor switching elements of the other phases is likely to rise next, overheating of these elements is prevented to improve reliability.
また、いずれか1相の第1オン固定期間が他の相の第1オン固定期間よりも長く、且つ、いずれか1相の第2オン固定期間が他の相の第2オン固定期間よりも長い。したがって、冷却水路の問題などで特定の相の温度が問題となる場合、その相の発熱を抑制できるので、インバータの信頼性が高まる。あるいは、ストールが発生してある相の第1半導体スイッチング素子と別の相の第2半導体スイッチング素子に連続的に電流が流れ温度上昇した場合、ストールを脱して動作を開始する際にこの動作を行うことで、ストール下で温度上昇した半導体スイッチング素子の発熱を抑え、速やかに温度を下げることができるので、インバータの信頼性が高まる。
Further, the first fixed ON period of any one phase is longer than the first fixed ON period of the other phase, and the second fixed ON period of any one phase is longer than the second fixed ON period of the other phase. long. Therefore, when the temperature of a specific phase becomes a problem due to a problem in the cooling water passage or the like, the heat generation of that phase can be suppressed, thereby increasing the reliability of the inverter. Alternatively, when a stall occurs and current continuously flows through the first semiconductor switching element of a certain phase and the second semiconductor switching element of another phase and the temperature rises, this operation is performed when exiting the stall and starting operation. By doing so, it is possible to suppress the heat generation of the semiconductor switching elements whose temperature has risen under the stall condition, and to quickly lower the temperature, thereby increasing the reliability of the inverter.
図4~図15Bを参照して、本発明の実施形態に係る波形例についてさらに説明する。図4は、波形例とスイッチング損失との関係を示す表である。図4において、UHは、U相の第1半導体スイッチング素子Upのスイッチング損失を示す。ULは、U相の第2半導体スイッチング素子Unのスイッチング損失を示す。VHは、V相の第1半導体スイッチング素子Vpのスイッチング損失を示す。VLは、V相の第2半導体スイッチング素子Vnのスイッチング損失を示す。WHは、W相の第1半導体スイッチング素子Wpのスイッチング損失を示す。WLは、W相の第2半導体スイッチング素子Wnのスイッチング損失を示す。
Examples of waveforms according to embodiments of the present invention will be further described with reference to FIGS. 4 to 15B. FIG. 4 is a table showing the relationship between waveform examples and switching loss. In FIG. 4, UH represents the switching loss of the U-phase first semiconductor switching element Up. UL represents the switching loss of the U-phase second semiconductor switching element Un. VH represents the switching loss of the V-phase first semiconductor switching element Vp. VL represents the switching loss of the V-phase second semiconductor switching element Vn. WH represents the switching loss of the W-phase first semiconductor switching element Wp. WL represents the switching loss of the W-phase second semiconductor switching element Wn.
図4に示すように、波形例1~波形例12では、UHが0.13であり、ULが0.13である、すなわち、波形例1~波形例12では、U相の第1半導体スイッチング素子UpおよびU相の第2半導体スイッチング素子Unのスイッチング損失が少ない波形例である。つまり、波形例1~波形例12は、U相の第1半導体スイッチング素子UpおよびU相の第2半導体スイッチング素子Unを保護できる波形例である。本明細書において、ある相(例えばU相)の第1半導体スイッチング素子(例えばUp)および同一相の第2半導体スイッチング素子(例えばUn)を保護できる波形を、UH_UL保護波形と記載することがある。
As shown in FIG. 4, in waveform examples 1 to 12, UH is 0.13 and UL is 0.13. This is a waveform example in which the switching loss of the element Up and the U-phase second semiconductor switching element Un is small. That is, waveform examples 1 to 12 are waveform examples capable of protecting the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un. In this specification, a waveform capable of protecting a first semiconductor switching element (eg Up) of a certain phase (eg U phase) and a second semiconductor switching element (eg Un) of the same phase may be referred to as a UH_UL protection waveform. .
図5Aおよび図5Bを参照して、波形例2について説明する。図5Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図5Bは、スイッチング損失を示す図である。
Waveform example 2 will be described with reference to FIGS. 5A and 5B. FIG. 5A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 5B is a diagram showing switching losses.
図5Aに示すように、波形例2は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例2は、電気角0度~電気角180度において、いずれか1相の出力が1に固定される波形である。また、波形例2は、電気角180度~電気角360度において、いずれか1相の出力が0に固定される波形である。波形例2では、電気角0度~電気角180度において、ハイサイドオン適用期間T3である。また、波形例2では、電気角180度~電気角360度において、ロウサイドオン適用期間T4である。
As shown in FIG. 5A, in waveform example 2, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. More specifically, waveform example 2 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 0 degree to 180 degrees. Waveform example 2 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 180 degrees to 360 degrees. In waveform example 2, the high-side-on application period T3 is from 0 electrical angle to 180 electrical degrees. In waveform example 2, the low-side-on application period T4 occurs at an electrical angle of 180 degrees to 360 degrees.
波形例2では、第1オン固定期間T1は、第1オン固定期間T1uと、第1オン固定期間T1vと、第1オン固定期間T1wとを含む。波形例2では、電気角30度~電気角150度が第1オン固定期間T1uである。波形例2では、電気角150度~電気角180度が第1オン固定期間T1vである。波形例2では、電気角0度~電気角30度が第1オン固定期間T1wである。
In Waveform Example 2, the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w. In Waveform Example 2, the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees. In Waveform Example 2, the first fixed ON period T1v is between 150 electrical degrees and 180 electrical degrees. In Waveform Example 2, the first ON fixed period T1w is from an electrical angle of 0 degree to an electrical angle of 30 degrees.
波形例2では、第2オン固定期間T2は、第2オン固定期間T2uと、第2オン固定期間T2vと、第2オン固定期間T2wとを含む。波形例2では、電気角210度~電気角330度が第2オン固定期間T2uである。波形例2では、電気角330度~電気角360度が第2オン固定期間T2vである。波形例2では、電気角180度~電気角210度が第2オン固定期間T2wである。
In Waveform Example 2, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 2, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In Waveform Example 2, the second fixed ON period T2v is from 330 electrical degrees to 360 electrical degrees. In Waveform Example 2, the second fixed ON period T2w is between 180 electrical degrees and 210 electrical degrees.
波形例2では、3相のうちU相において、第1オン固定期間T1uが、第1オン固定期間T1vおよび第1オン固定期間T1wと異なる。詳しくは、波形例2では、第1オン固定期間T1uが120度であるのに対し、第1オン固定期間T1vおよび第1オン固定期間T1wは30度である。すなわち、波形例2では、第1オン固定期間T1uが第1オン固定期間T1vおよび第1オン固定期間T1wよりも長い。したがって、図5Bに示すように、U相の第1半導体スイッチング素子Up(H(ハイサイド))のスイッチング損失がV相およびW相に比べて小さくなっている。
In waveform example 2, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 2, the first fixed ON period T1u is 120 degrees, while the first fixed ON period T1v and the first fixed ON period T1w are 30 degrees. That is, in Waveform Example 2, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 5B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
波形例2では、第2オン固定期間T2uが、第2オン固定期間T2vおよび第2オン固定期間T2wと異なる。詳しくは、波形例2では、第2オン固定期間T2uが120度であるのに対し、第2オン固定期間T2vおよび第2オン固定期間T2wは30度である。すなわち、波形例2では、第2オン固定期間T2uが第2オン固定期間T2vおよび第2オン固定期間T2wよりも長い。したがって、図5Bに示すように、U相の第2半導体スイッチング素子Un(L(ロウサイド))のスイッチング損失がV相およびW相に比べて小さくなっている。
In waveform example 2, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in Waveform Example 2, the second fixed ON period T2u is 120 degrees, while the second fixed ON period T2v and the second fixed ON period T2w are 30 degrees. That is, in Waveform Example 2, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 5B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
以上、図5Aおよび図5Bを参照して説明したように、波形例2においても、波形例1と同様に、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。波形例2では、U相の第1半導体スイッチング素子Upと、U相の第2半導体スイッチング素子Unとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 5A and 5B, in waveform example 2 as well as in waveform example 1, the heat generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In the waveform example 2, the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un can be suppressed at the same time.
また、波形例2では、図5Bに示すように、V相の第1半導体スイッチング素子Vpと、V相の第2半導体スイッチング素子Vnと、W相の第1半導体スイッチング素子Wpと、W相の第2半導体スイッチング素子Wnとの発熱についても同時に抑えることができる。なお、波形例2は、発熱の抑制効果のより高い後述する波形例9(図12)で代用が可能である。
In waveform example 2, as shown in FIG. 5B, the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time. Waveform example 2 can be substituted with waveform example 9 (FIG. 12) described later, which has a higher effect of suppressing heat generation.
図6Aおよび図6Bを参照して、波形例3について説明する。図6Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図6Bは、スイッチング損失を示す図である。
Waveform example 3 will be described with reference to FIGS. 6A and 6B. FIG. 6A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 6B is a diagram showing switching losses.
図6Aに示すように、波形例3は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例3は、電気角0度~電気角210度および電気角330度~電気角360度において、いずれか1相の出力が1に固定される波形である。また、波形例3は、電気角210度~電気角330度において、いずれか1相の出力が0に固定される波形である。波形例3では、電気角0度~電気角210度および電気角330度~電気角360度において、ハイサイドオン適用期間T3である。また、波形例3では、電気角210度~電気角330度において、ロウサイドオン適用期間T4である。
As shown in FIG. 6A, in waveform example 3, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. More specifically, waveform example 3 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 0 to 210 electrical degrees and at an electrical angle of 330 to 360 electrical degrees. Waveform example 3 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 210 degrees to 330 degrees. In waveform example 3, the high-side-on application period T3 occurs at an electrical angle of 0 to 210 electrical degrees and at an electrical angle of 330 to 360 electrical degrees. Further, in waveform example 3, the low-side-on application period is T4 at an electrical angle of 210 degrees to 330 electrical degrees.
波形例3では、第1オン固定期間T1は、第1オン固定期間T1uと、第1オン固定期間T1vと、第1オン固定期間T1wとを含む。波形例3では、電気角30度~電気角150度が第1オン固定期間T1uである。波形例3では、電気角150度~電気角210度が第1オン固定期間T1vである。波形例3では、電気角0度~電気角30度および電気角330度~電気角360度が第1オン固定期間T1wである。
In Waveform Example 3, the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w. In Waveform Example 3, the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees. In Waveform Example 3, the first fixed ON period T1v is between an electrical angle of 150 degrees and an electrical angle of 210 degrees. In waveform example 3, the first fixed ON period T1w is from an electrical angle of 0 degrees to an electrical angle of 30 degrees and from an electrical angle of 330 degrees to an electrical angle of 360 degrees.
波形例3では、第2オン固定期間T2は、第2オン固定期間T2uを含む。波形例3では、電気角210度~電気角330度が第2オン固定期間T2uである。
In Waveform Example 3, the second fixed ON period T2 includes the second fixed ON period T2u. In Waveform Example 3, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees.
波形例3では、3相のうちU相において、第1オン固定期間T1uが、第1オン固定期間T1vおよび第1オン固定期間T1wと異なる。詳しくは、波形例3では、第1オン固定期間T1uが120度であるのに対し、第1オン固定期間T1vおよび第1オン固定期間T1wは60度である。すなわち、波形例3では、第1オン固定期間T1uが第1オン固定期間T1vおよび第1オン固定期間T1wよりも長い。したがって、図6Bに示すように、U相の第1半導体スイッチング素子Up(H(ハイサイド))のスイッチング損失がV相およびW相に比べて小さくなっている。
In waveform example 3, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 3, the first fixed ON period T1u is 120 degrees, while the first fixed ON period T1v and the first fixed ON period T1w are 60 degrees. That is, in Waveform Example 3, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 6B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
波形例3では、第2オン固定期間T2uが、第2オン固定期間T2vおよび第2オン固定期間T2wと異なる。詳しくは、波形例3では、第2オン固定期間T2uが120度であるのに対し、第2オン固定期間T2vおよび第2オン固定期間T2wは無い。すなわち、波形例3では、第2オン固定期間T2uが第2オン固定期間T2vおよび第2オン固定期間T2wよりも長い。したがって、図6Bに示すように、U相の第2半導体スイッチング素子Un(L(ロウサイド))のスイッチング損失がV相およびW相に比べて小さくなっている。
In Waveform Example 3, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in Waveform Example 3, the second fixed ON period T2u is 120 degrees, whereas the second fixed ON period T2v and the second fixed ON period T2w are absent. That is, in Waveform Example 3, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 6B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
以上、図6Aおよび図6Bを参照して説明したように、波形例3においても、波形例1と同様に、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。波形例3では、U相の第1半導体スイッチング素子Upと、U相の第2半導体スイッチング素子Unとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 6A and 6B , in Waveform Example 3, as in Waveform Example 1, the heat generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 3, the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un can be suppressed at the same time.
また、波形例3では、図6Bに示すように、V相の第1半導体スイッチング素子Vpと、W相の第1半導体スイッチング素子Wpとの発熱についても同時に抑えることができる。
Further, in Waveform Example 3, as shown in FIG. 6B, the heat generation of the V-phase first semiconductor switching element Vp and the W-phase first semiconductor switching element Wp can be suppressed at the same time.
図7Aおよび図7Bを参照して、波形例4について説明する。図7Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図7Bは、スイッチング損失を示す図である。
Waveform example 4 will be described with reference to FIGS. 7A and 7B. FIG. 7A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 7B is a diagram showing switching losses.
図7Aに示すように、波形例4は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例4は、電気角30度~電気角180度において、いずれか1相の出力が1に固定される波形である。また、波形例4は、電気角0度~電気角30度および電気角180度~電気角360度において、ずれか1相の出力が0に固定される波形である。波形例4では、電気角30度~電気角180度において、ハイサイドオン適用期間T3である。また、波形例4では、電気角0度~電気角30度および電気角180度~電気角360度において、ロウサイドオン適用期間T4である。
As shown in FIG. 7A, in waveform example 4, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, waveform example 4 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 30 degrees to 180 degrees. Waveform example 4 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 to 30 degrees and at an electrical angle of 180 to 360 degrees. In Waveform Example 4, the high-side-on application period T3 is at an electrical angle of 30 degrees to 180 degrees. Further, in Waveform Example 4, the low-side-on application period T4 occurs at an electrical angle of 0 to 30 electrical degrees and at an electrical angle of 180 to 360 electrical degrees.
波形例4では、第1オン固定期間T1は、第1オン固定期間T1uと、第1オン固定期間T1vとを含む。波形例4では、電気角30度~電気角150度が第1オン固定期間T1uである。波形例4では、電気角150度~電気角180度が第1オン固定期間T1vである。
In Waveform Example 4, the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v. In Waveform Example 4, the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees. In Waveform Example 4, the first fixed ON period T1v is between 150 electrical degrees and 180 electrical degrees.
波形例4では、第2オン固定期間T2は、第2オン固定期間T2uと、第2オン固定期間T2vと、第2オン固定期間T2wとを含む。波形例4では、電気角210度~電気角330度が第2オン固定期間T2uである。波形例4では、電気角0度~電気角30度および電気角330度~電気角360度が第2オン固定期間T2vである。波形例4では、電気角180度~電気角210度が第2オン固定期間T2wである。
In Waveform Example 4, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In Waveform Example 4, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In Waveform Example 4, the second fixed ON period T2v is from an electrical angle of 0 degree to an electrical angle of 30 degrees and from an electrical angle of 330 degrees to an electrical angle of 360 degrees. In Waveform Example 4, the second fixed ON period T2w is between 180 electrical degrees and 210 electrical degrees.
波形例4では、3相のうちU相において、第1オン固定期間T1uが、第1オン固定期間T1vおよび第1オン固定期間T1wと異なる。詳しくは、波形例4では、第1オン固定期間T1uが120度であるのに対し、第1オン固定期間T1vが30度であり、第1オン固定期間T1wは無い。すなわち、波形例4では、第1オン固定期間T1uが第1オン固定期間T1vおよび第1オン固定期間T1wよりも長い。したがって、図7Bに示すように、U相の第1半導体スイッチング素子Up(H(ハイサイド))のスイッチング損失がV相およびW相に比べて小さくなっている。
In waveform example 4, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 4, the first fixed ON period T1u is 120 degrees, the first fixed ON period T1v is 30 degrees, and there is no first fixed ON period T1w. That is, in Waveform Example 4, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 7B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
波形例4では、第2オン固定期間T2uが、第2オン固定期間T2vおよび第2オン固定期間T2wと異なる。詳しくは、波形例4では、第2オン固定期間T2uが120度であるのに対し、第2オン固定期間T2vは60度であり、第2オン固定期間T2wは30度である。すなわち、波形例4では、第2オン固定期間T2uが第2オン固定期間T2vおよび第2オン固定期間T2wよりも長い。したがって、図7Bに示すように、U相の第2半導体スイッチング素子Un(L(ロウサイド))のスイッチング損失がV相およびW相に比べて小さくなっている。
In waveform example 4, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in Waveform Example 4, the second fixed ON period T2u is 120 degrees, the second fixed ON period T2v is 60 degrees, and the second fixed ON period T2w is 30 degrees. That is, in Waveform Example 4, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 7B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
以上、図7Aおよび図7Bを参照して説明したように、波形例4においても、波形例1と同様に、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。波形例4では、U相の第1半導体スイッチング素子Upと、U相の第2半導体スイッチング素子Unとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 7A and 7B, in Waveform Example 4, as in Waveform Example 1, the heat generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 4, the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un can be suppressed at the same time.
また、波形例4では、図7Bに示すように、V相の第1半導体スイッチング素子Vpと、V相の第2半導体スイッチング素子Vnと、W相の第2半導体スイッチング素子Wnとの発熱についても同時に抑えることができる。なお、波形例4は、発熱の抑制効果のより高い後述する波形例6(図9)で代用が可能である。
In waveform example 4, as shown in FIG. 7B, the heat generated by the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, and the W-phase second semiconductor switching element Wn can be suppressed at the same time. Waveform example 4 can be substituted with waveform example 6 (FIG. 9) described later, which has a higher effect of suppressing heat generation.
図8Aおよび図8Bを参照して、波形例5について説明する。図8Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図8Bは、スイッチング損失を示す図である。
Waveform example 5 will be described with reference to FIGS. 8A and 8B. FIG. 8A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 8B is a diagram showing switching losses.
図8Aに示すように、波形例5は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例5は、電気角30度~電気角210度において、いずれか1相の出力が1に固定される波形である。また、波形例5は、電気角0度~電気角30度および電気角210度~電気角360度において、いずれか1相の出力が0に固定される波形である。波形例5では、電気角30度~電気角210度において、ハイサイドオン適用期間T3である。また、波形例5では、電気角0度~電気角30度および電気角210度~電気角360度において、ロウサイドオン適用期間T4である。
As shown in FIG. 8A, in waveform example 5, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, waveform example 5 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 30 degrees to 210 degrees. Waveform example 5 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 to 30 electrical degrees and at an electrical angle of 210 to 360 electrical degrees. In waveform example 5, the high-side-on application period T3 is at an electrical angle of 30 degrees to 210 degrees. Further, in Waveform Example 5, the low-side-on application period T4 occurs at an electrical angle of 0 to 30 electrical degrees and at an electrical angle of 210 to 360 electrical degrees.
波形例5では、第1オン固定期間T1は、第1オン固定期間T1uと、第1オン固定期間T1vとを含む。波形例5では、電気角30度~電気角150度が第1オン固定期間T1uである。波形例5では、電気角150度~電気角210度が第1オン固定期間T1vである。
In waveform example 5, the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v. In Waveform Example 5, the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees. In Waveform Example 5, the first fixed ON period T1v is between an electrical angle of 150 degrees and an electrical angle of 210 degrees.
波形例5では、第2オン固定期間T2は、第2オン固定期間T2uと、第2オン固定期間T2vとを含む。波形例5では、電気角210度~電気角330度が第2オン固定期間T2uである。波形例5では、電気角0度~電気角30度および電気角330度~電気角360度が第2オン固定期間T2vである。
In waveform example 5, the second fixed ON period T2 includes a second fixed ON period T2u and a second fixed ON period T2v. In waveform example 5, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In Waveform Example 5, the second fixed ON period T2v is from 0 electrical angle to 30 electrical degrees and from 330 electrical degrees to 360 electrical degrees.
波形例5では、3相のうちU相において、第1オン固定期間T1uが、第1オン固定期間T1vおよび第1オン固定期間T1wと異なる。詳しくは、波形例5では、第1オン固定期間T1uが120度であるのに対し、第1オン固定期間T1vは60度であり、第1オン固定期間T1wは無い。すなわち、波形例5では、第1オン固定期間T1uが第1オン固定期間T1vおよび第1オン固定期間T1wよりも長い。したがって、図8Bに示すように、U相の第1半導体スイッチング素子Up(H(ハイサイド))のスイッチング損失がV相およびW相に比べて小さくなっている。
In waveform example 5, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 5, the first fixed ON period T1u is 120 degrees, the first fixed ON period T1v is 60 degrees, and there is no first fixed ON period T1w. That is, in Waveform Example 5, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 8B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
波形例5では、第2オン固定期間T2uが、第2オン固定期間T2vおよび第2オン固定期間T2wと異なる。詳しくは、波形例5では、第2オン固定期間T2uが120度であるのに対し、第2オン固定期間T2vは60度であり、第2オン固定期間T2wは無い。すなわち、波形例5では、第2オン固定期間T2uが第2オン固定期間T2vおよび第2オン固定期間T2wよりも長い。したがって、図8Bに示すように、U相の第2半導体スイッチング素子Un(L(ロウサイド))のスイッチング損失がV相およびW相に比べて小さくなっている。
In waveform example 5, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in Waveform Example 5, the second fixed ON period T2u is 120 degrees, the second fixed ON period T2v is 60 degrees, and there is no second fixed ON period T2w. That is, in Waveform Example 5, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 8B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
以上、図8Aおよび図8Bを参照して説明したように、波形例5においても、波形例1と同様に、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。波形例5では、U相の第1半導体スイッチング素子Upと、U相の第2半導体スイッチング素子Unとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 8A and 8B, in Waveform Example 5 as well as in Waveform Example 1, the heat generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 5, the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un can be suppressed at the same time.
また、波形例5では、図8Bに示すように、V相の第1半導体スイッチング素子Vpと、V相の第2半導体スイッチング素子Vnとの発熱についても同時に抑えることができる。
Further, in Waveform Example 5, as shown in FIG. 8B, the heat generation of the V-phase first semiconductor switching element Vp and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
図9Aおよび図9Bを参照して、波形例6について説明する。図9Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図9Bは、スイッチング損失を示す図である。
Waveform example 6 will be described with reference to FIGS. 9A and 9B. FIG. 9A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 9B is a diagram showing switching losses.
図9Aに示すように、波形例6は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例6は、電気角30度~電気角150度および電気角180度~電気角210度において、いずれか1相の出力が1に固定される波形である。また、波形例6は、電気角0度~電気角30度、電気角150度~電気角180度および電気角210度~電気角360度において、いずれか1相の出力が0に固定される波形である。波形例6では、電気角30度~電気角150度および電気角180度~電気角210度において、ハイサイドオン適用期間T3である。また、波形例6では、電気角0度~電気角30度、電気角150度~電気角180度および電気角210度~電気角360度において、ロウサイドオン適用期間T4である。
As shown in FIG. 9A, in waveform example 6, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, waveform example 6 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 30 degrees to 150 degrees and at an electrical angle of 180 degrees to 210 degrees. In waveform example 6, the output of any one phase is fixed to 0 at an electrical angle of 0 to 30 electrical degrees, 150 to 180 electrical degrees, and 210 to 360 electrical degrees. waveform. In Waveform Example 6, the high-side-on application period T3 occurs at an electrical angle of 30 degrees to 150 degrees and at an electrical angle of 180 degrees to 210 degrees. Further, in Waveform Example 6, the low side-on application period T4 occurs at an electrical angle of 0 to 30 electrical degrees, 150 to 180 electrical degrees, and 210 to 360 electrical degrees.
波形例6では、第1オン固定期間T1は、第1オン固定期間T1uと、第1オン固定期間T1vとを含む。波形例6では、電気角30度~電気角150度が第1オン固定期間T1uである。波形例6では、電気角180度~電気角210度が第1オン固定期間T1vである。
In Waveform Example 6, the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v. In Waveform Example 6, the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees. In Waveform Example 6, the first fixed ON period T1v is between an electrical angle of 180 degrees and an electrical angle of 210 degrees.
波形例6では、第2オン固定期間T2は、第2オン固定期間T2uと、第2オン固定期間T2vと、第2オン固定期間T2wとを含む。波形例6では、電気角210度~電気角330度が第2オン固定期間T2uである。波形例6では、電気角330度~電気角360度と電気角0度~電気角30度とが第2オン固定期間T2vである。波形例6では、電気角150度~電気角180度が第2オン固定期間T2wである。
In Waveform Example 6, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 6, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In Waveform Example 6, the second fixed ON period T2v is between an electrical angle of 330 degrees and an electrical angle of 360 degrees and between an electrical angle of 0 degrees and an electrical angle of 30 degrees. In Waveform Example 6, the second fixed ON period T2w is between 150 electrical degrees and 180 electrical degrees.
波形例6では、3相のうちU相において、第1オン固定期間T1uが、第1オン固定期間T1vおよび第1オン固定期間T1wと異なる。詳しくは、波形例6では、第1オン固定期間T1uが120度であるのに対し、第1オン固定期間T1vが30度であり、第1オン固定期間T1wは無い。すなわち、波形例6では、第1オン固定期間T1uが第1オン固定期間T1vおよび第1オン固定期間T1wよりも長い。したがって、図9Bに示すように、U相の第1半導体スイッチング素子Up(H(ハイサイド))のスイッチング損失がV相およびW相に比べて小さくなっている。
In waveform example 6, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 6, the first fixed ON period T1u is 120 degrees, the first fixed ON period T1v is 30 degrees, and there is no first fixed ON period T1w. That is, in Waveform Example 6, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 9B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
波形例6では、第2オン固定期間T2uが、第2オン固定期間T2vおよび第2オン固定期間T2wと異なる。詳しくは、波形例6では、第2オン固定期間T2uが120度であるのに対し、第2オン固定期間T2vが60度であり、第2オン固定期間T2wは30度である。すなわち、波形例6では、第2オン固定期間T2uが第2オン固定期間T2vおよび第2オン固定期間T2wよりも長い。したがって、図9Bに示すように、U相の第2半導体スイッチング素子Un(L(ロウサイド))のスイッチング損失がV相およびW相に比べて小さくなっている。
In waveform example 6, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in Waveform Example 6, the second fixed ON period T2u is 120 degrees, the second fixed ON period T2v is 60 degrees, and the second fixed ON period T2w is 30 degrees. That is, in Waveform Example 6, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 9B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
以上、図9Aおよび図9Bを参照して説明したように、波形例6においても、波形例1と同様に、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。波形例6では、U相の第1半導体スイッチング素子Upと、U相の第2半導体スイッチング素子Unとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 9A and 9B, in Waveform Example 6, as in Waveform Example 1, the heat generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 6, the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un can be suppressed at the same time.
また、波形例6では、図9Bに示すように、V相の第1半導体スイッチング素子Vpと、V相の第2半導体スイッチング素子Vnと、W相の第2半導体スイッチング素子Wnとの発熱についても同時に抑えることができる。
In waveform example 6, as shown in FIG. 9B, the heat generated by the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
図10Aおよび図10Bを参照して、波形例7について説明する。図10Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図10Bは、スイッチング損失を示す図である。
Waveform example 7 will be described with reference to FIGS. 10A and 10B. FIG. 10A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 10B is a diagram showing switching losses.
図10Aに示すように、波形例7は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例7は、電気角0度~電気角150度および電気角180度~電気角210度において、いずれか1相の出力が1に固定される波形である。また、波形例7は、電気角150度~電気角180度および電気角210度~電気角360度において、いずれか1相の出力が0に固定される波形である。波形例7では、電気角0度~電気角150度および電気角180度~電気角210度において、ハイサイドオン適用期間T3である。また、波形例7では、電気角150度~電気角180度および電気角210度~電気角360度において、ロウサイドオン適用期間T4である。
As shown in FIG. 10A, in waveform example 7, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval according to the electrical angle, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, waveform example 7 is a waveform in which the output of any one phase is fixed to 1 in the electrical angle of 0 to 150 electrical degrees and in the electrical angle of 180 to 210 electrical degrees. Waveform example 7 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 150 degrees to 180 degrees and at an electrical angle of 210 degrees to 360 degrees. In Waveform Example 7, the high-side-on application period T3 occurs at an electrical angle of 0 to 150 electrical degrees and at an electrical angle of 180 to 210 electrical degrees. Further, in Waveform Example 7, the low side-on application period T4 occurs at an electrical angle of 150 degrees to 180 degrees and at an electrical angle of 210 degrees to 360 degrees.
波形例7では、第1オン固定期間T1は、第1オン固定期間T1uと、第1オン固定期間T1vと、第1オン固定期間T1wとを含む。波形例7では、電気角30度~電気角150度が第1オン固定期間T1uである。波形例7では、電気角180度~電気角210度が第1オン固定期間T1vである。波形例7では、電気角0度~電気角30度が第1オン固定期間T1wである。
In Waveform Example 7, the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w. In Waveform Example 7, the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees. In Waveform Example 7, the first fixed ON period T1v is between an electrical angle of 180 degrees and an electrical angle of 210 degrees. In Waveform Example 7, the first ON fixed period T1w is from 0 electrical angle to 30 electrical degrees.
波形例7では、第2オン固定期間T2は、第2オン固定期間T2uと、第2オン固定期間T2vと、第2オン固定期間T2wとを含む。波形例7では、電気角210度~電気角330度が第2オン固定期間T2uである。波形例7では、電気角330度~電気角360度が第2オン固定期間T2vである。波形例7では、電気角150度~電気角180度が第2オン固定期間T2wである。
In Waveform Example 7, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In Waveform Example 7, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In Waveform Example 7, the second fixed ON period T2v is between 330 electrical degrees and 360 electrical degrees. In Waveform Example 7, the second fixed ON period T2w is between 150 electrical degrees and 180 electrical degrees.
波形例7では、3相のうちU相において、第1オン固定期間T1uが、第1オン固定期間T1vおよび第1オン固定期間T1wと異なる。詳しくは、波形例7では、第1オン固定期間T1uが120度であるのに対し、第1オン固定期間T1vおよび第1オン固定期間T1wは30度である。すなわち、波形例7では、第1オン固定期間T1uが第1オン固定期間T1vおよび第1オン固定期間T1wよりも長い。したがって、図10Bに示すように、U相の第1半導体スイッチング素子Up(H(ハイサイド))のスイッチング損失がV相およびW相に比べて小さくなっている。
In waveform example 7, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 7, the first fixed ON period T1u is 120 degrees, while the first fixed ON period T1v and the first fixed ON period T1w are 30 degrees. That is, in Waveform Example 7, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 10B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
波形例7では、第2オン固定期間T2uが、第2オン固定期間T2vおよび第2オン固定期間T2wと異なる。詳しくは、波形例7では、第2オン固定期間T2uが120度であるのに対し、第2オン固定期間T2vおよび第2オン固定期間T2wは30度である。すなわち、波形例7では、第2オン固定期間T2uが第2オン固定期間T2vおよび第2オン固定期間T2wよりも長い。したがって、図10Bに示すように、U相の第2半導体スイッチング素子Un(L(ロウサイド))のスイッチング損失がV相およびW相に比べて小さくなっている。
In Waveform Example 7, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in Waveform Example 7, the second fixed ON period T2u is 120 degrees, while the second fixed ON period T2v and the second fixed ON period T2w are 30 degrees. That is, in Waveform Example 7, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 10B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
以上、図10Aおよび図10Bを参照して説明したように、波形例7においても、波形例1と同様に、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。波形例7では、U相の第1半導体スイッチング素子Upと、U相の第2半導体スイッチング素子Unとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 10A and 10B , in Waveform Example 7, as in Waveform Example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 7, the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un can be suppressed at the same time.
また、波形例7では、図10Bに示すように、V相の第1半導体スイッチング素子Vpと、V相の第2半導体スイッチング素子Vnと、W相の第1半導体スイッチング素子Wpと、W相の第2半導体スイッチング素子Wnとの発熱についても同時に抑えることができる。なお、波形例7は、発熱の抑制効果のより高い後述する波形例9(図12)で代用が可能である。
In waveform example 7, as shown in FIG. 10B, the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time. Waveform example 7 can be substituted with waveform example 9 (FIG. 12), which will be described later and has a higher effect of suppressing heat generation.
図11Aおよび図11Bを参照して、波形例8について説明する。図11Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図11Bは、スイッチング損失を示す図である。
Waveform example 8 will be described with reference to FIGS. 11A and 11B. FIG. 11A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 11B is a diagram showing switching loss.
図11Aに示すように、波形例8は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例8は、電気角0度~電気角150度、電気角180度~電気角210度および電気角330度~電気角360度において、いずれか1相の出力が1に固定される波形である。また、波形例8は、電気角150度~電気角180度および電気角210度~電気角330度において、いずれか1相の出力が0に固定される波形である。波形例8では、電気角0度~電気角150度、電気角180度~電気角210度および電気角330度~電気角360度において、ハイサイドオン適用期間T3である。また、波形例8では、電気角150度~電気角180度および電気角210度~電気角330度において、ロウサイドオン適用期間T4である。
As shown in FIG. 11A, in Waveform Example 8, the output voltage of any one phase is fixed to 1 in a certain electrical angle section according to the electrical angle, and the output voltage of any one phase is fixed to 1 in another electrical angle section. is fixed to 0. Specifically, in waveform example 8, the output of any one phase is fixed to 1 at an electrical angle of 0 to 150 degrees, from 180 to 210 electrical degrees, and from 330 to 360 electrical degrees. waveform. Waveform example 8 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 150 degrees to 180 degrees and at an electrical angle of 210 degrees to 330 degrees. In Waveform Example 8, the high side-on application period T3 is at the electrical angle of 0 to 150 electrical degrees, the electrical angle of 180 to 210 electrical degrees, and the electrical angle of 330 to 360 electrical degrees. Further, in Waveform Example 8, the low side-on application period T4 occurs at an electrical angle of 150 degrees to 180 degrees and at an electrical angle of 210 degrees to 330 degrees.
波形例8では、第1オン固定期間T1は、第1オン固定期間T1uと、第1オン固定期間T1vと、第1オン固定期間T1wとを含む。波形例8では、電気角30度~電気角150度が第1オン固定期間T1uである。波形例8では、電気角180度~電気角210度が第1オン固定期間T1vである。波形例8では、電気角0度~電気角30度および電気角330度~電気角360度が第1オン固定期間T1wである。
In Waveform Example 8, the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w. In Waveform Example 8, the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees. In Waveform Example 8, the first fixed ON period T1v is between an electrical angle of 180 degrees and an electrical angle of 210 degrees. In Waveform Example 8, the first fixed ON period T1w is from an electrical angle of 0 degrees to an electrical angle of 30 degrees and from an electrical angle of 330 degrees to an electrical angle of 360 degrees.
波形例8では、第2オン固定期間T2は、第2オン固定期間T2uと、第2オン固定期間T2wとを含む。波形例8では、電気角210度~電気角330度が第2オン固定期間T2uである。波形例8では、電気角150度~電気角180度が第2オン固定期間T2wである。
In Waveform Example 8, the second fixed ON period T2 includes a second fixed ON period T2u and a second fixed ON period T2w. In Waveform Example 8, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In Waveform Example 8, the second fixed ON period T2w is between 150 electrical degrees and 180 electrical degrees.
波形例8では、3相のうちU相において、第1オン固定期間T1uが、第1オン固定期間T1vおよび第1オン固定期間T1wと異なる。詳しくは、波形例8では、第1オン固定期間T1uが120度であるのに対し、第1オン固定期間T1vは30度であり、第1オン固定期間T1wは60度である。すなわち、波形例8では、第1オン固定期間T1uが第1オン固定期間T1vおよび第1オン固定期間T1wよりも長い。したがって、図11Bに示すように、U相の第1半導体スイッチング素子Up(H(ハイサイド))のスイッチング損失がV相およびW相に比べて小さくなっている。
In waveform example 8, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 8, the first fixed ON period T1u is 120 degrees, the first fixed ON period T1v is 30 degrees, and the first fixed ON period T1w is 60 degrees. That is, in Waveform Example 8, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 11B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
波形例8では、第2オン固定期間T2uが、第2オン固定期間T2vおよび第2オン固定期間T2wと異なる。詳しくは、波形例8では、第2オン固定期間T2uが120度であるのに対し、第2オン固定期間T2vは無く、第2オン固定期間T2wは30度である。すなわち、波形例8では、第2オン固定期間T2uが第2オン固定期間T2vおよび第2オン固定期間T2wよりも長い。したがって、図11Bに示すように、U相の第2半導体スイッチング素子Un(L(ロウサイド))のスイッチング損失がV相およびW相に比べて小さくなっている。
In Waveform Example 8, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in Waveform Example 8, the second fixed ON period T2u is 120 degrees, whereas the second fixed ON period T2v is absent and the second fixed ON period T2w is 30 degrees. That is, in Waveform Example 8, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 11B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
以上、図11Aおよび図11Bを参照して説明したように、波形例8においても、波形例1と同様に、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。波形例8では、U相の第1半導体スイッチング素子Upと、U相の第2半導体スイッチング素子Unとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 11A and 11B, in Waveform Example 8, as in Waveform Example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 8, the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un can be suppressed at the same time.
また、波形例8では、図11Bに示すように、V相の第1半導体スイッチング素子Vpと、W相の第1半導体スイッチング素子Wpと、W相の第2半導体スイッチング素子Wnとの発熱についても同時に抑えることができる。
In waveform example 8, as shown in FIG. 11B, the heat generated by the V-phase first semiconductor switching element Vp, the W-phase first semiconductor switching element Wp, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
図12Aおよび図12Bを参照して、波形例9について説明する。図12Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図12Bは、スイッチング損失を示す図である。
Waveform example 9 will be described with reference to FIGS. 12A and 12B. FIG. 12A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 12B is a diagram showing switching losses.
図12Aに示すように、波形例9は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例9は、電気角30度~電気角150度、電気角180度~電気角210度および電気角330度~電気角360度において、いずれか1相の出力が1に固定される波形である。また、波形例9は、電気角0度~電気角30度、電気角150度~電気角180度および電気角210度~電気角330度において、波形例9では、電気角30度~電気角150度、電気角180度~電気角210度および電気角330度~電気角360度において、ハイサイドオン適用期間T3である。また、波形例9では、電気角0度~電気角30度、電気角150度~電気角180度および電気角210度~電気角330度において、ロウサイドオン適用期間T4である。
As shown in FIG. 12A, in waveform example 9, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, in waveform example 9, the output of any one phase is fixed to 1 at an electrical angle of 30 degrees to 150 degrees, from 180 degrees to 210 degrees, and from 330 degrees to 360 degrees. waveform. Further, waveform example 9 corresponds to an electrical angle of 0 degree to an electrical angle of 30 degrees, an electrical angle of 150 degrees to an electrical angle of 180 degrees, and an electrical angle of 210 degrees to an electrical angle of 330 degrees. 150 degrees, the electrical angle of 180 degrees to 210 degrees, and the electrical angle of 330 degrees to 360 degrees are the high side-on application period T3. Further, in waveform example 9, the low side-on application period T4 occurs at an electrical angle of 0 to 30 electrical degrees, 150 to 180 electrical degrees, and 210 to 330 electrical degrees.
波形例9では、第1オン固定期間T1は、第1オン固定期間T1uと、第1オン固定期間T1vと、第1オン固定期間T1wとを含む。波形例9では、電気角30度~電気角150度が第1オン固定期間T1uである。波形例9では、電気角180度~電気角210度が第1オン固定期間T1vである。波形例9では、電気角330度~電気角360度が第1オン固定期間T1wである。
In Waveform Example 9, the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w. In waveform example 9, the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees. In Waveform Example 9, the first fixed ON period T1v is between an electrical angle of 180 degrees and an electrical angle of 210 degrees. In Waveform Example 9, the first fixed ON period T1w is from 330 electrical degrees to 360 electrical degrees.
波形例9では、第2オン固定期間T2は、第2オン固定期間T2uと、第2オン固定期間T2vと、第2オン固定期間T2wとを含む。波形例9では、電気角210度~電気角330度が第2オン固定期間T2uである。波形例9では、電気角0度~電気角30度が第2オン固定期間T2vである。波形例9では、電気角150度~電気角180度が第2オン固定期間T2wである。
In Waveform Example 9, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 9, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In Waveform Example 9, the second fixed ON period T2v is from an electrical angle of 0 degrees to an electrical angle of 30 degrees. In Waveform Example 9, the second fixed ON period T2w is between 150 electrical degrees and 180 electrical degrees.
波形例9では、3相のうちU相において、第1オン固定期間T1uが、第1オン固定期間T1vおよび第1オン固定期間T1wと異なる。詳しくは、波形例9では、第1オン固定期間T1uが120度であるのに対し、第1オン固定期間T1vおよび第1オン固定期間T1wは30度である。すなわち、波形例9では、第1オン固定期間T1uが第1オン固定期間T1vおよび第1オン固定期間T1wよりも長い。したがって、図12Bに示すように、U相の第1半導体スイッチング素子Up(H(ハイサイド))のスイッチング損失がV相およびW相に比べて小さくなっている。
In waveform example 9, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 9, the first fixed ON period T1u is 120 degrees, while the first fixed ON period T1v and the first fixed ON period T1w are 30 degrees. That is, in Waveform Example 9, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 12B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
波形例9では、第2オン固定期間T2uが、第2オン固定期間T2vおよび第2オン固定期間T2wと異なる。詳しくは、波形例9では、第2オン固定期間T2uが120度であるのに対し、第2オン固定期間T2vおよび第2オン固定期間T2wは30度である。すなわち、波形例9では、第2オン固定期間T2uが第2オン固定期間T2vおよび第2オン固定期間T2wよりも長い。したがって、図12Bに示すように、U相の第2半導体スイッチング素子Un(L(ロウサイド))のスイッチング損失がV相およびW相に比べて小さくなっている。
In waveform example 9, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in Waveform Example 9, the second fixed ON period T2u is 120 degrees, while the second fixed ON period T2v and the second fixed ON period T2w are 30 degrees. That is, in Waveform Example 9, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 12B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
以上、図12Aおよび図12Bを参照して説明したように、波形例9においても、波形例1と同様に、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。波形例9では、U相の第1半導体スイッチング素子Upと、U相の第2半導体スイッチング素子Unとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 12A and 12B, in Waveform Example 9, as in Waveform Example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In the waveform example 9, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un.
また、波形例9では、図12Bに示すように、V相の第1半導体スイッチング素子Vpと、V相の第2半導体スイッチング素子Vnと、W相の第1半導体スイッチング素子Wpと、W相の第2半導体スイッチング素子Wnとの発熱についても同時に抑えることができる。
In waveform example 9, as shown in FIG. 12B, the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
図13Aおよび図13Bを参照して、波形例10について説明する。図13Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図13Bは、スイッチング損失を示す図である。
A waveform example 10 will be described with reference to FIGS. 13A and 13B. FIG. 13A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 13B is a diagram showing switching losses.
図13Aに示すように、波形例10は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例10は、電気角0度~電気角150度および電気角330度~電気角360度において、いずれか1相の出力が1に固定される波形である。また、波形例10は、電気角150度~電気角330度において、いずれか1相の出力が0に固定される波形である。波形例10では、電気角0度~電気角150度および電気角330度~電気角360度において、ハイサイドオン適用期間T3である。また、波形例10では、電気角150度~電気角330度において、ロウサイドオン適用期間T4である。
As shown in FIG. 13A, in waveform example 10, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. More specifically, waveform example 10 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 0 to 150 electrical degrees and at an electrical angle of 330 to 360 electrical degrees. Waveform example 10 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 150 degrees to 330 degrees. In waveform example 10, the high-side-on application period T3 occurs at an electrical angle of 0 to 150 electrical degrees and at an electrical angle of 330 to 360 electrical degrees. Further, in waveform example 10, the low-side-on application period T4 occurs at an electrical angle of 150 degrees to 330 electrical degrees.
波形例10では、第1オン固定期間T1は、第1オン固定期間T1uと、第1オン固定期間T1wとを含む。波形例10では、電気角30度~電気角150度が第1オン固定期間T1uである。波形例10では、電気角0度~電気角30度および電気角330度~電気角360度が第1オン固定期間T1wである。
In waveform example 10, the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1w. In waveform example 10, the first ON fixed period T1u is from 30 electrical degrees to 150 electrical degrees. In waveform example 10, the first fixed ON period T1w is from an electrical angle of 0 degrees to an electrical angle of 30 degrees and from an electrical angle of 330 degrees to an electrical angle of 360 degrees.
波形例10では、第2オン固定期間T2は、第2オン固定期間T2uと、第2オン固定期間T2wとを含む。波形例10では、電気角210度~電気角330度が第2オン固定期間T2uである。波形例10では、電気角150度~電気角210度が第2オン固定期間T2wである。
In waveform example 10, the second fixed ON period T2 includes a second fixed ON period T2u and a second fixed ON period T2w. In waveform example 10, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In waveform example 10, the second fixed ON period T2w is between 150 electrical degrees and 210 electrical degrees.
波形例10では、3相のうちU相において、第1オン固定期間T1uが、第1オン固定期間T1vおよび第1オン固定期間T1wと異なる。詳しくは、波形例10では、第1オン固定期間T1uが120度であるのに対し、第1オン固定期間T1vは無く、第1オン固定期間T1wは60度である。すなわち、波形例10では、第1オン固定期間T1uが第1オン固定期間T1vおよび第1オン固定期間T1wよりも長い。したがって、図13Bに示すように、U相の第1半導体スイッチング素子Up(H(ハイサイド))のスイッチング損失がV相およびW相に比べて小さくなっている。
In waveform example 10, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 10, the first fixed ON period T1u is 120 degrees, whereas the first fixed ON period T1v is absent and the first fixed ON period T1w is 60 degrees. That is, in waveform example 10, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 13B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
波形例10では、第2オン固定期間T2uが、第2オン固定期間T2vおよび第2オン固定期間T2wと異なる。詳しくは、波形例10では、第2オン固定期間T2uが120度であるのに対し、第2オン固定期間T2vは無く、および第2オン固定期間T2wは60度である。すなわち、波形例10では、第2オン固定期間T2uが第2オン固定期間T2vおよび第2オン固定期間T2wよりも長い。したがって、図13Bに示すように、U相の第2半導体スイッチング素子Un(L(ロウサイド))のスイッチング損失がV相およびW相に比べて小さくなっている。
In waveform example 10, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in Waveform Example 10, the second fixed ON period T2u is 120 degrees, while the second fixed ON period T2v is absent and the second fixed ON period T2w is 60 degrees. That is, in waveform example 10, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 13B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
以上、図13Aおよび図13Bを参照して説明したように、波形例10においても、波形例1と同様に、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。波形例10では、U相の第1半導体スイッチング素子Upと、U相の第2半導体スイッチング素子Unとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 13A and 13B, in waveform example 10 as well as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 10, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un.
また、波形例10では、図13Bに示すように、W相の第1半導体スイッチング素子Wpと、W相の第2半導体スイッチング素子Wnとの発熱についても同時に抑えることができる。
Further, in waveform example 10, as shown in FIG. 13B, the heat generation of the W-phase first semiconductor switching element Wp and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
図14Aおよび図14Bを参照して、波形例11について説明する。図14Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図14Bは、スイッチング損失を示す図である。
A waveform example 11 will be described with reference to FIGS. 14A and 14B. FIG. 14A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 14B is a diagram showing switching losses.
図14Aに示すように、波形例11は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例11は、電気角30度~電気角210度および電気角330度~電気角360度において、いずれか1相の出力が1に固定される波形である。また、波形例11は、電気角0度~電気角30度および電気角210度~電気角330度において、いずれか1相の出力が0に固定される波形である。波形例11では、電気角30度~電気角210度および電気角330度~電気角360度において、ハイサイドオン適用期間T3である。また、波形例11では、電気角0度~電気角30度および電気角210度~電気角330度において、ロウサイドオン適用期間T4である。
As shown in FIG. 14A, in waveform example 11, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. More specifically, waveform example 11 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 30 to 210 electrical degrees and at an electrical angle of 330 to 360 electrical degrees. Waveform example 11 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 to 30 degrees and at an electrical angle of 210 to 330 degrees. In waveform example 11, the high side-on application period T3 occurs at an electrical angle of 30 to 210 electrical degrees and at an electrical angle of 330 to 360 electrical degrees. Further, in waveform example 11, the low side-on application period T4 occurs at an electrical angle of 0 to 30 electrical degrees and at an electrical angle of 210 to 330 electrical degrees.
波形例11では、第1オン固定期間T1は、第1オン固定期間T1uと、第1オン固定期間T1vと、第1オン固定期間T1wとを含む。波形例11では、電気角30度~電気角150度が第1オン固定期間T1uである。波形例11では、電気角150度~電気角210度が第1オン固定期間T1vである。波形例11では、電気角330度~電気角360度が第1オン固定期間T1wである。
In waveform example 11, the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w. In waveform example 11, the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees. In waveform example 11, the first fixed ON period T1v is between 150 electrical degrees and 210 electrical degrees. In waveform example 11, the first fixed ON period T1w is from 330 electrical degrees to 360 electrical degrees.
波形例11では、第2オン固定期間T2は、第2オン固定期間T2uと、第2オン固定期間T2vとを含む。波形例11では、電気角210度~電気角330度が第2オン固定期間T2uである。波形例11では、電気角0度~電気角30度が第2オン固定期間T2vである。
In waveform example 11, the second fixed ON period T2 includes a second fixed ON period T2u and a second fixed ON period T2v. In waveform example 11, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In waveform example 11, the second fixed ON period T2v is from 0 electrical angle to 30 electrical degrees.
波形例11では、3相のうちU相において、第1オン固定期間T1uが、第1オン固定期間T1vおよび第1オン固定期間T1wと異なる。詳しくは、波形例11では、第1オン固定期間T1uが120度であるのに対し、第1オン固定期間T1vは60度であり、第1オン固定期間T1wは30度である。すなわち、波形例11では、第1オン固定期間T1uが第1オン固定期間T1vおよび第1オン固定期間T1wよりも長い。したがって、図14Bに示すように、U相の第1半導体スイッチング素子Up(H(ハイサイド))のスイッチング損失がV相およびW相に比べて小さくなっている。
In waveform example 11, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 11, the first fixed ON period T1u is 120 degrees, the first fixed ON period T1v is 60 degrees, and the first fixed ON period T1w is 30 degrees. That is, in waveform example 11, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 14B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
波形例11では、第2オン固定期間T2uが、第2オン固定期間T2vおよび第2オン固定期間T2wと異なる。詳しくは、波形例11では、第2オン固定期間T2uが120度であるのに対し、第2オン固定期間T2vは、30度であり、第2オン固定期間T2wは無い。すなわち、波形例11では、第2オン固定期間T2uが第2オン固定期間T2vおよび第2オン固定期間T2wよりも長い。したがって、図14Bに示すように、U相の第2半導体スイッチング素子Un(L(ロウサイド))のスイッチング損失がV相およびW相に比べて小さくなっている。
In waveform example 11, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in waveform example 11, the second fixed ON period T2u is 120 degrees, the second fixed ON period T2v is 30 degrees, and there is no second fixed ON period T2w. That is, in waveform example 11, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 14B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
以上、図14Aおよび図14Bを参照して説明したように、波形例11においても、波形例1と同様に、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。波形例11では、U相の第1半導体スイッチング素子Upと、U相の第2半導体スイッチング素子Unとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 14A and 14B, in waveform example 11, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 11, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un.
また、波形例11では、図14Bに示すように、V相の第1半導体スイッチング素子Vpと、V相の第2半導体スイッチング素子Vnと、W相の第1半導体スイッチング素子Wpとの発熱についても同時に抑えることができる。
In waveform example 11, as shown in FIG. 14B, the heat generated by the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, and the W-phase first semiconductor switching element Wp can be suppressed at the same time.
図15Aおよび図15Bを参照して、波形例12について説明する。図15Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図15Bは、スイッチング損失を示す図である。
Waveform example 12 will be described with reference to FIGS. 15A and 15B. FIG. 15A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 15B is a diagram showing switching losses.
図15Aに示すように、波形例12は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例12は、電気角30度~電気角150度および電気角330度~電気角360度において、いずれか1相の出力が1に固定される波形である。また、波形例12は、電気角0度~電気角30度および電気角150度~電気角330度において、いずれか1相の出力が0に固定される波形である。波形例12では、電気角30度~電気角150度および電気角330度~電気角360度において、ハイサイドオン適用期間T3である。また、波形例12では、電気角0度~電気角30度および電気角150度~電気角330度において、ロウサイドオン適用期間T4である。
As shown in FIG. 15A, in waveform example 12, the output voltage of any one phase is fixed to 1 in a certain electrical angle section, and the output voltage of any one phase is fixed to 1 in another electrical angle section. is fixed to 0. Specifically, waveform example 12 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 30 degrees to 150 degrees and at an electrical angle of 330 degrees to 360 degrees. Waveform example 12 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 to 30 electrical degrees and at an electrical angle of 150 to 330 electrical degrees. In waveform example 12, the high side-on application period T3 occurs at an electrical angle of 30 degrees to 150 degrees and at an electrical angle of 330 degrees to 360 degrees. Further, in waveform example 12, the low side-on application period T4 occurs at an electrical angle of 0 to 30 electrical degrees and at an electrical angle of 150 to 330 electrical degrees.
波形例12では、第1オン固定期間T1は、第1オン固定期間T1uと、第1オン固定期間T1wとを含む。波形例12では、電気角30度~電気角150度が第1オン固定期間T1uである。波形例12では、電気角330度~電気角360度が第1オン固定期間T1wである。
In waveform example 12, the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1w. In waveform example 12, the first fixed ON period T1u is from 30 electrical degrees to 150 electrical degrees. In waveform example 12, the first fixed ON period T1w is from 330 electrical degrees to 360 electrical degrees.
波形例12では、第2オン固定期間T2は、第2オン固定期間T2uと、第2オン固定期間T2vと、第2オン固定期間T2wとを含む。波形例12では、電気角210度~電気角330度が第2オン固定期間T2uである。波形例12では、電気角0度~電気角30度が第2オン固定期間T2vである。波形例12では、電気角150度~電気角210度が第2オン固定期間T2wである。
In Waveform Example 12, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 12, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In waveform example 12, the second fixed ON period T2v is from 0 electrical angle to 30 electrical degrees. In waveform example 12, the second fixed ON period T2w is from 150 electrical degrees to 210 electrical degrees.
波形例12では、3相のうちU相において、第1オン固定期間T1uが、第1オン固定期間T1vおよび第1オン固定期間T1wと異なる。詳しくは、波形例12では、第1オン固定期間T1uが120度であるのに対し、第1オン固定期間T1vは無く、第1オン固定期間T1wは30度である。すなわち、波形例12では、第1オン固定期間T1uが第1オン固定期間T1vおよび第1オン固定期間T1wよりも長い。したがって、図15Bに示すように、U相の第1半導体スイッチング素子Up(H(ハイサイド))のスイッチング損失がV相およびW相に比べて小さくなっている。
In waveform example 12, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 12, the first fixed ON period T1u is 120 degrees, whereas the first fixed ON period T1v is absent and the first fixed ON period T1w is 30 degrees. That is, in waveform example 12, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 15B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
波形例12では、第2オン固定期間T2uが、第2オン固定期間T2vおよび第2オン固定期間T2wと異なる。詳しくは、波形例12では、第2オン固定期間T2uが120度であるのに対し、第2オン固定期間T2vは30度であり、第2オン固定期間T2wは60度である。すなわち、波形例12では、第2オン固定期間T2uが第2オン固定期間T2vおよび第2オン固定期間T2wよりも長い。したがって、図15Bに示すように、U相の第2半導体スイッチング素子Un(L(ロウサイド))のスイッチング損失がV相およびW相に比べて小さくなっている。
In waveform example 12, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in waveform example 12, the second fixed ON period T2u is 120 degrees, the second fixed ON period T2v is 30 degrees, and the second fixed ON period T2w is 60 degrees. That is, in waveform example 12, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 15B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
以上、図15Aおよび図15Bを参照して説明したように、波形例12においても、波形例1と同様に、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。波形例12では、U相の第1半導体スイッチング素子Upと、U相の第2半導体スイッチング素子Unとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 15A and 15B , in waveform example 12, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 12, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un.
また、波形例12では、図15Bに示すように、V相の第2半導体スイッチング素子Vnと、W相の第1半導体スイッチング素子Wpと、W相の第2半導体スイッチング素子Wnとの発熱についても同時に抑えることができる。
In waveform example 12, as shown in FIG. 15B, the heat generated by the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
図16を参照して、U相の固定期間を変化させた場合のスイッチング損失について説明する。図16は、スイッチング損失を示す図である。
The switching loss when the fixed period of the U phase is changed will be described with reference to FIG. FIG. 16 is a diagram showing switching loss.
図16に示すように、U相において、ハイサイド側の第1オン固定期間T1uを電気角30度~電気角150度、ロウサイド側の第2オン固定期間T2uを電気角210度~電気角330度にした場合、スイッチング損失は0.13となる。つまり、U相において、ハイサイド側の第1オン固定期間T1uを120度、ロウサイド側の第2オン固定期間T2uを120度にした場合、スイッチング損失は0.13となる。
As shown in FIG. 16, in the U phase, the first fixed ON period T1u on the high side is 30 to 150 electrical degrees in electrical angle, and the second fixed ON period T2u on the low side is 210 to 330 electrical degrees in electrical angle. , the switching loss is 0.13. That is, in the U-phase, if the high-side first fixed ON period T1u is 120 degrees and the low-side second fixed ON period T2u is 120 degrees, the switching loss is 0.13.
U相において、ハイサイド側の第1オン固定期間T1uを電気角40度~電気角140度、ロウサイド側の第2オン固定期間T2uを電気角220度~電気角330度にした場合、スイッチング損失は0.22となる。つまり、U相において、ハイサイド側の第1オン固定期間T1uを120度、ロウサイド側の第2オン固定期間T2uを100度にした場合、スイッチング損失は0.22となる。
In the U phase, when the first fixed ON period T1u on the high side is set at an electrical angle of 40 degrees to 140 degrees and the second fixed ON period T2u on the low side is set at an electrical angle of 220 degrees to 330 degrees, the switching loss is is 0.22. That is, in the U-phase, if the high-side first fixed ON period T1u is 120 degrees and the low-side second fixed ON period T2u is 100 degrees, the switching loss is 0.22.
U相において、ハイサイド側の第1オン固定期間T1uを電気角50度~電気角130度、ロウサイド側の第2オン固定期間T2uを電気角230度~電気角310度にした場合、スイッチング損失は0.35となる。つまり、U相において、ハイサイド側の第1オン固定期間T1uを80度、ロウサイド側の第2オン固定期間T2uを100度にした場合、スイッチング損失は0.22となる。
In the U phase, when the first fixed ON period T1u on the high side is set at an electrical angle of 50 degrees to 130 degrees, and the second fixed ON period T2u on the low side is set at an electrical angle of 230 degrees to 310 degrees, the switching loss is is 0.35. That is, in the U-phase, if the high-side first fixed ON period T1u is 80 degrees and the low-side second fixed ON period T2u is 100 degrees, the switching loss is 0.22.
U相において、ハイサイド側の第1オン固定期間T1uを電気角50度~電気角130度、ロウサイド側の第2オン固定期間T2uを電気角230度~電気角310度にした場合、スイッチング損失は0.35となる。つまり、U相において、ハイサイド側の第1オン固定期間T1uを80度、ロウサイド側の第2オン固定期間T2uを80度にした場合、スイッチング損失は0.35となる。
In the U phase, when the first fixed ON period T1u on the high side is set at an electrical angle of 50 degrees to 130 degrees, and the second fixed ON period T2u on the low side is set at an electrical angle of 230 degrees to 310 degrees, the switching loss is is 0.35. That is, in the U-phase, if the high-side first fixed ON period T1u is 80 degrees and the low-side second fixed ON period T2u is 80 degrees, the switching loss is 0.35.
U相において、ハイサイド側の第1オン固定期間T1uを電気角60度~電気角120度、ロウサイド側の第2オン固定期間T2uを電気角240度~電気角300度にした場合、スイッチング損失は0.50となる。つまり、U相において、ハイサイド側の第1オン固定期間T1uを60度、ロウサイド側の第2オン固定期間T2uを60度にした場合、スイッチング損失は0.50となる。
In the U phase, when the first fixed ON period T1u on the high side is set at an electrical angle of 60 degrees to 120 degrees and the second fixed ON period T2u on the low side is set at an electrical angle of 240 degrees to 300 degrees, the switching loss is is 0.50. That is, in the U-phase, if the high-side first fixed ON period T1u is 60 degrees and the low-side second fixed ON period T2u is 60 degrees, the switching loss is 0.50.
以上、図16を参照して説明したように、第1オン固定期間T1uおよび第2オン固定期間T2uは、共に、π/3(60度)よりも長く、2π/3(120度)以下であることが好ましい。より好ましくは、4π/9(80度)よりも長く、2π/3(120度)以下であることが好ましい。
As described above with reference to FIG. 16, both the first fixed ON period T1u and the second fixed ON period T2u are longer than π/3 (60 degrees) and 2π/3 (120 degrees) or less. Preferably. More preferably, it is longer than 4π/9 (80 degrees) and 2π/3 (120 degrees) or less.
次に、図17を参照して、UH_UL保護波形の切り替えについてさらに説明する。図17は、UH_UL保護波形の切り替えを説明するための図である。
Next, switching of the UH_UL protection waveform will be further described with reference to FIG. FIG. 17 is a diagram for explaining switching of the UH_UL protection waveform.
図17において、出力電圧の波形およびスイッチング損失は、左から順に、(c)波形例3(図6Aおよび図6B)、(i)波形例9(図12Aおよび図12B)、(a)波形例1(図3Aおよび図3B)に相当する。
In FIG. 17, the waveforms of the output voltage and the switching loss are, from the left, (c) waveform example 3 (FIGS. 6A and 6B), (i) waveform example 9 (FIGS. 12A and 12B), (a) waveform example 1 (FIGS. 3A and 3B).
左の図に示す(c)波形例3は、第1オン固定期間T1vおよび第1オン固定期間T1wを延長した波形例である。つまり、ハイサイドの発熱抑制を重視した波形例である。
(c) Waveform example 3 shown in the left diagram is a waveform example in which the first fixed ON period T1v and the first fixed ON period T1w are extended. In other words, this is a waveform example that emphasizes suppression of heat generation on the high side.
中央の図に示す(i)波形例3は、第1オン固定期間T1v、第1オン固定期間T1w、第2オン固定期間T2vおよび第2オン固定期間T2wを均等にした波形例である。つまり、第1オン固定期間T1u、第1オン固定期間T1u以外を均等にした波形例である。
(i) Waveform example 3 shown in the middle diagram is a waveform example in which the first fixed ON period T1v, the first fixed ON period T1w, the second fixed ON period T2v, and the second fixed ON period T2w are equalized. That is, it is a waveform example in which the first fixed ON period T1u and the period other than the first fixed ON period T1u are made uniform.
右の図に示す(a)波形例1は、第2オン固定期間T2vおよび第2オン固定期間T2wを延長した波形例である。つまり、ロウサイドの発熱抑制を重視した波形例である。
(a) Waveform example 1 shown in the right figure is a waveform example in which the second fixed ON period T2v and the second fixed ON period T2w are extended. In other words, this is an example of a waveform that emphasizes suppression of heat generation on the low side.
左の図に移行するにつれて、第1オン固定期間T1vおよび第1オン固定期間T1wは長くなる。したがって、左の図に移行するにつれて、V相の第1半導体スイッチング素子Vp(ハイサイド)およびW相の第1半導体スイッチング素子Wp(ハイサイド)のスイッチング損失が減少する。
The first fixed ON period T1v and the first fixed ON period T1w become longer as the diagram shifts to the left. Therefore, the switching losses of the V-phase first semiconductor switching element Vp (high side) and the W-phase first semiconductor switching element Wp (high side) decrease as the diagram shifts to the left.
一方、右の図に移行するにつれて、第2オン固定期間T2vおよび第2オン固定期間T2wは長くなる。したがって、左の図に移行するにつれて、V相の第2半導体スイッチング素子Vn(ロウサイド)およびW相の第2半導体スイッチング素子Wn(ロウサイド)のスイッチング損失が減少する。
On the other hand, the second fixed ON period T2v and the second fixed ON period T2w become longer as it shifts to the right figure. Therefore, the switching loss of the V-phase second semiconductor switching element Vn (low side) and the W-phase second semiconductor switching element Wn (low side) decreases as the diagram shifts to the left.
次に、図16を参照して、UH_UL保護波形の切り替えについてさらに説明する。図16は、UH_UL保護波形の切り替えを説明するための図である。
Next, switching of the UH_UL protection waveform will be further described with reference to FIG. FIG. 16 is a diagram for explaining switching of the UH_UL protection waveform.
図16において、出力電圧の波形およびスイッチング損失は、左から順に、(e)波形例5(図8Aおよび図8B)、(i)波形例9(図12Aおよび図12B)、(j)波形例10(図13Aおよび図13B)に相当する。
In FIG. 16, the waveform of the output voltage and the switching loss are, from left to right, (e) waveform example 5 (FIGS. 8A and 8B), (i) waveform example 9 (FIGS. 12A and 12B), (j) waveform example 10 (FIGS. 13A and 13B).
左の図に示す(e)波形例5は、第1オン固定期間T1vおよび第2オン固定期間T2vを延長した波形例である。つまり、V相を重視した波形例である。
(e) Waveform example 5 shown in the left diagram is a waveform example in which the first fixed ON period T1v and the second fixed ON period T2v are extended. In other words, this is an example of a waveform that emphasizes the V phase.
中央の図に示す(i)波形例9は、第1オン固定期間T1v、第1オン固定期間T1w、第2オン固定期間T2vおよび第2オン固定期間T2wを均等にした波形例である。つまり、第1オン固定期間T1u、第1オン固定期間T1u以外を均等にした波形例である。
(i) Waveform example 9 shown in the middle diagram is a waveform example in which the first fixed ON period T1v, the first fixed ON period T1w, the second fixed ON period T2v, and the second fixed ON period T2w are equalized. That is, it is a waveform example in which the first fixed ON period T1u and the period other than the first fixed ON period T1u are made uniform.
右の図に示す(j)波形例10は、第1オン固定期間T1wおよび第2オン固定期間T2wを延長した波形例である。つまり、W相を重視した波形例である。
(j) Waveform example 10 shown in the right figure is a waveform example in which the first fixed ON period T1w and the second fixed ON period T2w are extended. That is, it is an example of a waveform in which the W phase is emphasized.
左の図に移行するにつれて、第1オン固定期間T1vおよび第2オン固定期間T2vは長くなる。したがって、左の図に移行するにつれて、V相の第1半導体スイッチング素子Vp(ハイサイド)およびV相の第2半導体スイッチング素子Vn(ロウサイド)のスイッチング損失が減少する。
The first fixed ON period T1v and the second fixed ON period T2v become longer as the diagram shifts to the left. Therefore, the switching losses of the V-phase first semiconductor switching element Vp (high side) and the V-phase second semiconductor switching element Vn (low side) decrease as the diagram shifts to the left.
一方、右の図に移行するにつれて、第1オン固定期間T1wおよび第2オン固定期間T2wは長くなる。したがって、右の図に移行するにつれて、W相の第1半導体スイッチング素子Wp(ハイサイド)およびW相の第2半導体スイッチング素子Wn(ロウサイド)のスイッチング損失が減少する。
On the other hand, the first fixed ON period T1w and the second fixed ON period T2w become longer as the figure shifts to the right. Therefore, the switching loss of the W-phase first semiconductor switching element Wp (high side) and the W-phase second semiconductor switching element Wn (low side) decreases as the drawing shifts to the right side.
次に、図19を参照して、UH_UL保護波形の切り替えについてさらに説明する。図19は、スイッチング損失を示す図である。
Next, switching of the UH_UL protection waveform will be further described with reference to FIG. FIG. 19 is a diagram showing switching loss.
図19に示すように、(f)波形例6(図9A)、(h)波形例8(図11A)、(k)波形例11(図14A)および(l)波形例12(図15A)では、第1半導体スイッチング素子Up(UH)のスイッチング損失および第2半導体スイッチング素子Un(UL)のスイッチング損失は、0.13である。
As shown in FIG. 19, (f) waveform example 6 (FIG. 9A), (h) waveform example 8 (FIG. 11A), (k) waveform example 11 (FIG. 14A) and (l) waveform example 12 (FIG. 15A) Then, the switching loss of the first semiconductor switching element Up (UH) and the switching loss of the second semiconductor switching element Un (UL) are 0.13.
(f)波形例6では、第1半導体スイッチング素子Up(UH)および第2半導体スイッチング素子Un(UL)に加えて、さらに第2半導体スイッチング素子Vn(VL)のスイッチング損失を0.57と減少させることができる。
(f) In waveform example 6, in addition to the first semiconductor switching element Up (UH) and the second semiconductor switching element Un (UL), the switching loss of the second semiconductor switching element Vn (VL) is reduced to 0.57. can be made
(h)波形例8では、第1半導体スイッチング素子Up(UH)および第2半導体スイッチング素子Un(UL)に加えて、さらに第1半導体スイッチング素子Wp(WH)のスイッチング損失を0.57と減少させることができる。
(h) In waveform example 8, in addition to the first semiconductor switching element Up (UH) and the second semiconductor switching element Un (UL), the switching loss of the first semiconductor switching element Wp (WH) is reduced to 0.57. can be made
(k)波形例11では、第1半導体スイッチング素子Up(UH)および第2半導体スイッチング素子Un(UL)に加えて、さらに第1半導体スイッチング素子Vp(VH)のスイッチング損失が0.57と減少させることができる。
(k) In waveform example 11, in addition to the first semiconductor switching element Up (UH) and the second semiconductor switching element Un (UL), the switching loss of the first semiconductor switching element Vp (VH) is reduced to 0.57. can be made
(l)波形例12では、第1半導体スイッチング素子Up(UH)および第2半導体スイッチング素子Un(UL)に加えて、さらに第2半導体スイッチング素子Wn(WL)のスイッチング損失が0.57と減少させることができる。
(l) In waveform example 12, in addition to the first semiconductor switching element Up (UH) and the second semiconductor switching element Un (UL), the switching loss of the second semiconductor switching element Wn (WL) is reduced to 0.57. can be made
図20を参照して、UH_UL保護波形の切り替えについてさらに説明する。図20は、UH_UL保護波形の切り替えを説明するための図である。
The switching of the UH_UL protection waveform will be further described with reference to FIG. FIG. 20 is a diagram for explaining switching of the UH_UL protection waveform.
図20に示す波形図は、(i)波形例9(図12A)に相当する。
The waveform diagram shown in FIG. 20 corresponds to (i) waveform example 9 (FIG. 12A).
(a)波形例1(図3A)は、(i)波形例9に対して、第2オン固定期間T2vおよび第2オン固定期間T2wを延長した波形に相当する。したがって、V相の第2半導体スイッチング素子Vn(VL)およびW相の第2半導体スイッチング素子Wn(WL)のスイッチング損失が減少する。
(a) Waveform example 1 (FIG. 3A) corresponds to a waveform in which the second fixed ON period T2v and the second fixed ON period T2w are extended with respect to (i) waveform example 9. Therefore, the switching losses of the V-phase second semiconductor switching element Vn (VL) and the W-phase second semiconductor switching element Wn (WL) are reduced.
(c)波形例3(図6A)は、(i)波形例9に対して、第1オン固定期間T1vおよび第1オン固定期間T1wを延長した波形に相当する。したがって、V相の第1半導体スイッチング素子Vp(VH)およびW相の第1半導体スイッチング素子Wp(WH)のスイッチング損失が減少する。
(c) Waveform example 3 (FIG. 6A) corresponds to a waveform in which the first fixed ON period T1v and the first fixed ON period T1w are extended with respect to (i) waveform example 9. Therefore, the switching losses of the V-phase first semiconductor switching element Vp (VH) and the W-phase first semiconductor switching element Wp (WH) are reduced.
(e)波形例5(図8A)は、(i)波形例9に対して、第1オン固定期間T1vおよび第2オン固定期間T2vを延長した波形に相当する。したがって、V相の第1半導体スイッチング素子Vp(VH)およびV相の第2半導体スイッチング素子Vn(VL)のスイッチング損失が減少する。
(e) Waveform example 5 (FIG. 8A) corresponds to a waveform in which the first fixed ON period T1v and the second fixed ON period T2v are extended with respect to (i) waveform example 9. Therefore, the switching losses of the V-phase first semiconductor switching element Vp (VH) and the V-phase second semiconductor switching element Vn (VL) are reduced.
(j)波形例10(図13A)は、(i)波形例9に対して、第1オン固定期間T1wおよび第2オン固定期間T2wを延長した波形に相当する。したがって、W相の第1半導体スイッチング素子Wp(WH)およびW相の第2半導体スイッチング素子Wn(WL)のスイッチング損失が減少する。
(j) Waveform example 10 (FIG. 13A) corresponds to a waveform in which the first fixed ON period T1w and the second fixed ON period T2w are extended with respect to (i) waveform example 9. Therefore, the switching losses of the W-phase first semiconductor switching element Wp (WH) and the W-phase second semiconductor switching element Wn (WL) are reduced.
(f)波形例6(図9A)は、(i)波形例9に対して、第2オン固定期間T2vを延長した波形に相当する。したがって、V相の第2半導体スイッチング素子Vn(VL)のスイッチング損失が減少する。
(f) Waveform example 6 (FIG. 9A) corresponds to a waveform obtained by extending the second on-fixed period T2v from (i) waveform example 9. Therefore, the switching loss of the V-phase second semiconductor switching element Vn(VL) is reduced.
(h)波形例8(図11A)は、(i)波形例9に対して、第1オン固定期間T1wを延長した波形に相当する。したがって、W相の第1半導体スイッチング素子Wp(WH)のスイッチング損失が減少する。
(h) Waveform example 8 (FIG. 11A) corresponds to a waveform obtained by extending the first fixed ON period T1w with respect to (i) waveform example 9. Therefore, the switching loss of the W-phase first semiconductor switching element Wp(WH) is reduced.
(k)波形例11(図14A)は、(i)波形例9に対して、第1オン固定期間T1vを延長した波形に相当する。したがって、V相の第1半導体スイッチング素子Vp(VH)のスイッチング損失が減少する。
(k) Waveform example 11 (FIG. 14A) corresponds to a waveform obtained by extending the first fixed ON period T1v with respect to (i) waveform example 9. Therefore, the switching loss of the V-phase first semiconductor switching element Vp (VH) is reduced.
(l)波形例12(図15A)は、(i)波形例9に対して、第2オン固定期間T2wを延長した波形に相当する。したがって、W相の第2半導体スイッチング素子Wn(WL)のスイッチング損失が減少する。
(l) Waveform example 12 (FIG. 15A) corresponds to a waveform obtained by extending the second on-fixed period T2w from (i) waveform example 9. Therefore, the switching loss of the W-phase second semiconductor switching element Wn(WL) is reduced.
図21を参照して保護波形の切替方法について説明する。図21は、保護波形の切替方法を示すフローチャートである。
A method of switching the protection waveform will be described with reference to FIG. FIG. 21 is a flow chart showing a protection waveform switching method.
ステップS102:、信号生成部120は、各アーム(半導体スイッチング素子)の温度T_UH、温度T_UL、温度T_VH、温度T_VL、温度T_WH、温度T_WHを取得する。温度T_UHは、第1半導体スイッチング素子Upの温度を示す。温度T_ULは、第2半導体スイッチング素子Unの温度を示す。温度T_VHは、第1半導体スイッチング素子Vpの温度を示す。温度T_VLは、第2半導体スイッチング素子Vnの温度を示す。温度T_WHは、第1半導体スイッチング素子Wpの温度を示す。温度T_WLは、第2半導体スイッチング素子Wnの温度を示す。
Step S102: The signal generator 120 acquires the temperature T_UH, temperature T_UL, temperature T_VH, temperature T_VL, temperature T_WH, and temperature T_WH of each arm (semiconductor switching element). A temperature T_UH indicates the temperature of the first semiconductor switching element Up. A temperature T_UL indicates the temperature of the second semiconductor switching element Un. A temperature T_VH indicates the temperature of the first semiconductor switching element Vp. A temperature T_VL indicates the temperature of the second semiconductor switching element Vn. A temperature T_WH indicates the temperature of the first semiconductor switching element Wp. A temperature T_WL indicates the temperature of the second semiconductor switching element Wn.
そして、信号生成部120は、取得した温度T_UH、温度T_UL、温度T_VH、温度T_VL、温度T_WH、温度T_WHを、温度が高い順にT_1、T_2、T_3、T_4、T_5およびT_6とする。処理は、ステップS104に進む。
Then, the signal generation unit 120 sets the acquired temperature T_UH, temperature T_UL, temperature T_VH, temperature T_VL, temperature T_WH, and temperature T_WH to T_1, T_2, T_3, T_4, T_5, and T_6 in descending order of temperature. The process proceeds to step S104.
ステップS104:信号生成部120は、最高温の上アーム(第1半導体スイッチング素子)と、最高温の下アーム(第2半導体スイッチング素子)は同相であるか否かを判定する。最高温の上アーム(第1半導体スイッチング素子)と、最高温の下アーム(第2半導体スイッチング素子)は同相でないと、信号生成部120が判定した場合(ステップS104:No)、処理はステップS108に進む。最高温の上アーム(第1半導体スイッチング素子)と、最高温の下アーム(第2半導体スイッチング素子)は同相であると、信号生成部120が判定した場合(ステップS104:Yes)、処理はステップS106に進む。
Step S104: The signal generator 120 determines whether or not the highest temperature upper arm (first semiconductor switching element) and the highest temperature lower arm (second semiconductor switching element) are in phase. When the signal generator 120 determines that the highest temperature upper arm (first semiconductor switching element) and the highest temperature lower arm (second semiconductor switching element) are not in phase (step S104: No), the process proceeds to step S108. proceed to When the signal generator 120 determines that the highest temperature upper arm (first semiconductor switching element) and the highest temperature lower arm (second semiconductor switching element) are in phase (step S104: Yes), the process proceeds to step Proceed to S106.
ステップS106:信号生成部120は、X相上下段の温度上昇を抑制するようなパターンで変調を行う。X相は、例えば、U相、V相またはW相である。処理は、終了する。ステップS106の詳細な処理については、図22~図24を参照して後述する。
Step S106: The signal generator 120 modulates in a pattern that suppresses temperature rise in the upper and lower stages of the X phase. The X phase is, for example, U phase, V phase or W phase. Processing ends. Detailed processing of step S106 will be described later with reference to FIGS.
ステップS108:信号生成部120は、X相上段とY相下段の温度上昇を抑制するようなパターンで変調を行う。Y相は、例えば、U相、V相またはW相である。処理は、終了する。ステップS108の詳細な処理については、図47~図49を参照して後述する。
Step S108: The signal generator 120 modulates in a pattern that suppresses temperature rise in the X-phase upper stage and the Y-phase lower stage. Y-phase is, for example, U-phase, V-phase or W-phase. Processing ends. Detailed processing of step S108 will be described later with reference to FIGS.
図22から図24を参照して図21に示したステップS106の詳細な処理について説明する。すなわち、X相上下段の温度上昇を抑制するようなパターンで変調する場合の処理について説明する。図22は、保護波形の切替方法を示すフローチャートである。図23および図24は、保護波形の切替方法を示す図である。なお、図22~図24は、X相の例としてU相を用いた場合の保護波形の切替方法を示している。
The detailed processing of step S106 shown in FIG. 21 will be described with reference to FIGS. 22 to 24. FIG. In other words, a description will be given of processing in the case of modulation in a pattern that suppresses temperature rise in the upper and lower stages of the X phase. FIG. 22 is a flow chart showing a protection waveform switching method. 23 and 24 are diagrams showing a switching method of the protection waveform. 22 to 24 show the switching method of the protection waveform when the U phase is used as an example of the X phase.
ステップS202:信号生成部120は、温度T_3~T_6が閾値T_Thr1以下であるか否かを判定する。温度T_3~T_6が閾値T_Thr1以下でないと、信号生成部120が判定した場合(ステップS202:No)、処理はステップS206に進む。温度T_3~T_6が閾値T_Thr1以下であると、信号生成部120が判定した場合(ステップS202:Yes)、処理はステップS204に進む。
Step S202: The signal generator 120 determines whether the temperatures T_3 to T_6 are equal to or lower than the threshold T_Thr1. When the signal generator 120 determines that the temperatures T_3 to T_6 are not equal to or lower than the threshold value T_Thr1 (step S202: No), the process proceeds to step S206. When the signal generator 120 determines that the temperatures T_3 to T_6 are equal to or lower than the threshold T_Thr1 (step S202: Yes), the process proceeds to step S204.
ステップS204:信号生成部120は、4つ保護パターンで変調を行う。詳しくは、信号生成部120は、(i)波形例9で変調を行う。処理は終了する。
Step S204: The signal generator 120 modulates with four protection patterns. Specifically, the signal generator 120 performs modulation with (i) waveform example 9; Processing ends.
ステップS206:信号生成部120は、温度T_5~T_6が閾値T_Thr2以下であるか否かを判定する。温度T_5~T_6が閾値T_Thr2以下でないと、信号生成部120が判定した場合(ステップS206:No)、処理はステップS210に進む。温度T_5~T_6が閾値T_Thr2以下であると、信号生成部120が判定した場合(ステップS206:Yes)、処理はステップS208に進む。
Step S206: The signal generator 120 determines whether the temperatures T_5 to T_6 are equal to or lower than the threshold T_Thr2. When the signal generator 120 determines that the temperatures T_5 to T_6 are not equal to or lower than the threshold value T_Thr2 (step S206: No), the process proceeds to step S210. When the signal generator 120 determines that the temperatures T_5 to T_6 are equal to or lower than the threshold T_Thr2 (step S206: Yes), the process proceeds to step S208.
ステップS208:信号生成部120は、3つ保護パターンと4つ保護パターンとの中間で変調を行う。3つ保護パターンと4つ保護パターンとの中間で変調については、図23を参照して後述する。処理は終了する。
Step S208: The signal generator 120 modulates between the three protection patterns and the four protection patterns. Modulation in between the 3 guard pattern and the 4 guard pattern will be described later with reference to FIG. Processing ends.
ステップS210:信号生成部120は、温度T_3~T_5が閾値T_Thr3以下であるか否かを判定する。温度T_3~T_5が閾値T_Thr3以下でないと、信号生成部120が判定した場合(ステップS210:No)、処理はステップS214に進む。温度T_3~T_5が閾値T_Thr3以下であると、信号生成部120が判定した場合(ステップS210:Yes)、処理はステップS212に進む。
Step S210: The signal generator 120 determines whether the temperatures T_3 to T_5 are equal to or lower than the threshold T_Thr3. When the signal generator 120 determines that the temperatures T_3 to T_5 are not equal to or lower than the threshold value T_Thr3 (step S210: No), the process proceeds to step S214. When the signal generator 120 determines that the temperatures T_3 to T_5 are equal to or lower than the threshold T_Thr3 (step S210: Yes), the process proceeds to step S212.
ステップS212:信号生成部120は、3つ保護パターンで変調を行う。詳しくは、信号生成部120は、(k)波形例11、(f)波形例6、(h)波形例8、(l)波形例12のうち、温度がT_3、T_4、T_5となるアーム(半導体スイッチング素子)を保護できるパターンで変調を行う。処理は終了する。
Step S212: The signal generator 120 modulates with three protection patterns. Specifically, the signal generation unit 120 selects the arms (or (Semiconductor switching elements) are modulated with a pattern that can protect them. Processing ends.
ステップS214:信号生成部120は、温度T_4~T_5が閾値T_Thr4以下であるか否かを判定する。温度T_4~T_5が閾値T_Thr4以下でないと、信号生成部120が判定した場合(ステップS214:No)、処理はステップS218に進む。温度T_4~T_5が閾値T_Thr4以下であると、信号生成部120が判定した場合(ステップS214:Yes)、処理はステップS216に進む。
Step S214: The signal generator 120 determines whether the temperatures T_4 to T_5 are equal to or lower than the threshold T_Thr4. When the signal generator 120 determines that the temperatures T_4 to T_5 are not equal to or lower than the threshold value T_Thr4 (step S214: No), the process proceeds to step S218. When the signal generator 120 determines that the temperatures T_4 to T_5 are equal to or lower than the threshold value T_Thr4 (step S214: Yes), the process proceeds to step S216.
ステップS216:信号生成部120は、2つ保護パターンと3つ保護パターンとの中間で変調を行う。2つ保護パターンと3つ保護パターンとの中間で変調については、図24を参照して後述する。処理は終了する。
Step S216: The signal generator 120 modulates between the two protection patterns and the three protection patterns. Modulation in between the 2 guard pattern and the 3 guard pattern will be described later with reference to FIG. Processing ends.
ステップS218:信号生成部120は、2つ保護パターンで変調を行う。詳しくは、信号生成部120は、(a)波形例1、(c)波形例3、(e)波形例5、(f)波形例6、(i)波形例9および(j)波形例10のうち、温度がT_3、T_4となるアーム(半導体スイッチング素子)を保護できるパターンで変調を行う。処理は終了する。
Step S218: The signal generator 120 modulates with two protection patterns. Specifically, the signal generator 120 generates (a) waveform example 1, (c) waveform example 3, (e) waveform example 5, (f) waveform example 6, (i) waveform example 9, and (j) waveform example 10. Of these, modulation is performed with a pattern that can protect arms (semiconductor switching elements) whose temperatures are T_3 and T_4. Processing ends.
次に、図23を参照して図22に示したステップS208の詳細な処理について説明する。すなわち、3つ保護パターンと4つ保護パターンとの中間で変調を行う場合の処理について説明する。
Next, the detailed processing of step S208 shown in FIG. 22 will be described with reference to FIG. That is, a description will be given of the processing in the case of performing modulation between the three protection patterns and the four protection patterns.
信号生成部120は、UH(第1半導体スイッチング素子Up)およびUL(第2半導体スイッチング素子Un)を除いて温度の高い上位3アーム(半導体スイッチング素子)の位置を判定する。以下、図23の説明において、「UH(第1半導体スイッチング素子Up)およびUL(第2半導体スイッチング素子Un)を除いて温度の高い上位3アーム(半導体スイッチング素子)」を、単に「上位3アーム」と記載することがある。なお、上位3アームの温度の順番は問わない。例えば、上位3アームの温度の順番が、VH(第1半導体スイッチング素子Vp)、VL(第2半導体スイッチング素子Vn)およびWH(第1半導体スイッチング素子Wp)の順でもよいし、VH(第1半導体スイッチング素子Vp)、WH(第1半導体スイッチング素子Wp)およびVL(第2半導体スイッチング素子Vn)の順でもよい。以下、同様の記載についても同様に上位3アームの温度の順番は問わない。
The signal generation unit 120 determines the positions of the three arms (semiconductor switching elements) with the highest temperature, excluding UH (first semiconductor switching element Up) and UL (second semiconductor switching element Un). Hereinafter, in the description of FIG. 23, "upper three arms (semiconductor switching elements) with higher temperatures excluding UH (first semiconductor switching element Up) and UL (second semiconductor switching element Un)" will simply be referred to as "upper three arms ” may be stated. Note that the order of the temperatures of the top three arms does not matter. For example, the order of the temperatures of the upper three arms may be VH (first semiconductor switching element Vp), VL (second semiconductor switching element Vn), and WH (first semiconductor switching element Wp), or VH (first semiconductor switching element Wp). The order of semiconductor switching element Vp), WH (first semiconductor switching element Wp) and VL (second semiconductor switching element Vn) is also acceptable. In the same description below, the order of the temperatures of the top three arms is similarly irrelevant.
信号生成部120が、上位3アームがVH(第1半導体スイッチング素子Vp)、VL(第2半導体スイッチング素子Vn)およびWH(第1半導体スイッチング素子Wp)であると判定した場合、(k)波形例11において、150度~150+30×(T_Thr2-(T_5-T_6))/T_Thr2度を第1オン固定期間、330度~330+30×(T_Thr2-(T_5-T_6))/T_Thr2度を第2オン固定期間に適用したパターンで、信号生成部120は変調を行う。
When signal generation unit 120 determines that the upper three arms are VH (first semiconductor switching element Vp), VL (second semiconductor switching element Vn), and WH (first semiconductor switching element Wp), (k) waveform In Example 11, 150 degrees to 150+30×(T_Thr2−(T_5−T_6))/T_Thr2 degrees is the first fixed ON period, and 330 degrees to 330+30×(T_Thr2−(T_5−T_6))/T_Thr2 degrees is the second fixed ON period. The signal generator 120 modulates with the pattern applied to the period.
信号生成部120が、上位3アームがVH(第1半導体スイッチング素子Vp)、VL(第2半導体スイッチング素子Vn)およびWL(第2半導体スイッチング素子Wn)であると判定した場合、信号生成部120は、(f)波形例6で変調を行う。
When signal generation unit 120 determines that the upper three arms are VH (first semiconductor switching element Vp), VL (second semiconductor switching element Vn), and WL (second semiconductor switching element Wn), signal generation unit 120 modulates with (f) waveform example 6;
信号生成部120が、上位3アームがVH(第1半導体スイッチング素子Vp)、VL(第2半導体スイッチング素子Vn)およびWH(第1半導体スイッチング素子Wp)であると判定した場合、(h)波形例8において、0度~0+30×(T_Thr2-(T_5-T_6))/T_Thr2度を第1オン固定期間、330度~330+30×(T_Thr2-(T_5-T_6))/T_Thr2を第2オン固定期間に適用したパターンで、信号生成部120は変調を行う。
When signal generation unit 120 determines that the upper three arms are VH (first semiconductor switching element Vp), VL (second semiconductor switching element Vn), and WH (first semiconductor switching element Wp), (h) waveform In Example 8, 0 degrees to 0+30×(T_Thr2−(T_5−T_6))/T_Thr2 degrees is the first fixed ON period, and 330 degrees to 330+30×(T_Thr2−(T_5−T_6))/T_Thr2 is the second fixed ON period. The signal generator 120 modulates with the pattern applied to .
信号生成部120が、上位3アームがVH(第1半導体スイッチング素子Vp)、VL(第2半導体スイッチング素子Vn)およびWL(第2半導体スイッチング素子Wn)であると判定した場合、(l)波形例12において、0度~0+30×(T_Thr2-(T_5-T_6))/T_Thr2度を第1オン固定期間、330度~330+30×(T_Thr2-(T_5-T_6))/T_Thr2度を第2オン固定期間に適用したパターンで、信号生成部120は変調を行う。
When signal generation unit 120 determines that the upper three arms are VH (first semiconductor switching element Vp), VL (second semiconductor switching element Vn), and WL (second semiconductor switching element Wn), (l) waveform In Example 12, 0 degrees to 0+30×(T_Thr2−(T_5−T_6))/T_Thr2 degrees is the first fixed ON period, and 330 degrees to 330+30×(T_Thr2−(T_5−T_6))/T_Thr2 degrees is the second fixed ON period. The signal generator 120 modulates with the pattern applied to the period.
次に、図24を参照して図22に示したステップS216の詳細な処理について説明する。すなわち、2つ保護パターンと3つ保護パターンとの中間で変調を行う場合の処理について説明する。
Next, the detailed processing of step S216 shown in FIG. 22 will be described with reference to FIG. In other words, a description will be given of processing in the case of performing modulation between the two protection patterns and the three protection patterns.
信号生成部120は、UH(第1半導体スイッチング素子Up)およびUL(第2半導体スイッチング素子Un)を除いて温度の高い上位2アーム(半導体スイッチング素子)の位置を判定する。以下、図24の説明において、「UH(第1半導体スイッチング素子Up)およびUL(第2半導体スイッチング素子Un)を除いて温度の高い上位2アーム(半導体スイッチング素子)」を、単に「上位2アーム」と記載することがある。なお、上位2アームの温度の順番は問わない。例えば、上位2アームの温度の順番が、VL(第2半導体スイッチング素子Vn)およびWL(第2半導体スイッチング素子Wn)の順でもよいし、WL(第2半導体スイッチング素子Wn)およびVL(第2半導体スイッチング素子Vn)の順でもよい。以下、同様の記載についても同様に上位3アームの温度の順番は問わない。
The signal generation unit 120 determines the positions of the upper two arms (semiconductor switching elements) with the highest temperature, excluding UH (first semiconductor switching element Up) and UL (second semiconductor switching element Un). Hereinafter, in the description of FIG. 24, "upper two arms (semiconductor switching elements) with higher temperatures excluding UH (first semiconductor switching element Up) and UL (second semiconductor switching element Un)" will simply be referred to as "upper two arms ” may be stated. Note that the order of the temperatures of the upper two arms does not matter. For example, the order of the temperatures of the upper two arms may be VL (second semiconductor switching element Vn) and WL (second semiconductor switching element Wn), or WL (second semiconductor switching element Wn) and VL (second semiconductor switching element Wn). The order of the semiconductor switching elements Vn) may also be used. In the same description below, the order of the temperatures of the top three arms is similarly irrelevant.
さらに、信号生成部120は、UH(第1半導体スイッチング素子Up)およびUL(第2半導体スイッチング素子Un)を除いて上位3番目に高温のアーム(半導体スイッチング素子)の位置を判定する。以下、図24の説明において、「UH(第1半導体スイッチング素子Up)およびUL(第2半導体スイッチング素子Un)を除いて上位3番目に高温のアーム(半導体スイッチング素子)」を、単に「上位3番目に高温のアーム」と記載することがある。
Furthermore, the signal generation unit 120 determines the position of the arm (semiconductor switching element) with the third highest temperature, excluding UH (first semiconductor switching element Up) and UL (second semiconductor switching element Un). Hereinafter, in the description of FIG. 24, "upper third hot arm (semiconductor switching element) excluding UH (first semiconductor switching element Up) and UL (second semiconductor switching element Un)" is simply referred to as "upper three It is sometimes described as "the arm with the highest temperature".
上位2アームの位置がVL(第2半導体スイッチング素子Vn)およびWL(第2半導体スイッチング素子Vn)、かつ、上位3番目に高温のアームがVH(第1半導体スイッチング素子Vp)であると、信号生成部120が判定した場合、(a)波形例1において、180度~180+30×(T_Thr4-(T_4-T_5))/T_Thr4度を第1オン固定期間に適用したパターンで、信号生成部120は変調を行う。処理は終了する。
When the positions of the upper two arms are VL (second semiconductor switching element Vn) and WL (second semiconductor switching element Vn), and the arm with the third highest temperature is VH (first semiconductor switching element Vp), a signal When the generation unit 120 determines that (a) in the waveform example 1, the pattern in which 180 degrees to 180+30×(T_Thr4−(T_4−T_5))/T_Thr4 degrees is applied to the first fixed ON period, the signal generation unit 120 modulate. Processing ends.
上位2アームの位置がVL(第2半導体スイッチング素子Vn)およびWL(第2半導体スイッチング素子Vn)、かつ、上位3番目に高温のアームがWH(第1半導体スイッチング素子Wp)であると、信号生成部120が判定した場合、(a)波形例1において、330度~330+30×(T_Thr4-(T_4-T_5))/T_Thr4度を第1オン固定期間に適用したパターンで、信号生成部120は変調を行う。処理は終了する。
When the positions of the upper two arms are VL (second semiconductor switching element Vn) and WL (second semiconductor switching element Vn), and the arm with the third highest temperature is WH (first semiconductor switching element Wp), a signal When the generation unit 120 determines that (a) in the waveform example 1, the pattern in which 330 degrees to 330+30×(T_Thr4−(T_4−T_5))/T_Thr4 degrees is applied to the first fixed ON period, the signal generation unit 120 modulate. Processing ends.
上位2アームの位置がVH(第1半導体スイッチング素子Vp)およびWH(第1半導体スイッチング素子Wp)、かつ、上位3番目に高温のアームがVL(第2半導体スイッチング素子Vn)であると、信号生成部120が判定した場合、(c)波形例3において、0度~0+30×(T_Thr4-(T_4-T_5))/T_Thr4度を第2オン固定期間に適用したパターンで、信号生成部120は変調を行う。
When the positions of the upper two arms are VH (first semiconductor switching element Vp) and WH (first semiconductor switching element Wp), and the arm with the third highest temperature is VL (second semiconductor switching element Vn), a signal When the generation unit 120 determines that (c) in the waveform example 3, the pattern in which 0 degrees to 0+30×(T_Thr4−(T_4−T_5))/T_Thr4 degrees is applied to the second fixed ON period, the signal generation unit 120 modulate.
上位2アームの位置がVH(第1半導体スイッチング素子Vp)およびWH(第1半導体スイッチング素子Wp)、かつ、上位3番目に高温のアームがWL(第2半導体スイッチング素子Wn)であると、信号生成部120が判定した場合、(c)波形例3において、150度~150+30×(T_Thr4-(T_4-T_5))/T_Thr4度を第2オン固定期間に適用したパターンで、信号生成部120は変調を行う。
When the positions of the upper two arms are VH (first semiconductor switching element Vp) and WH (first semiconductor switching element Wp), and the arm with the third highest temperature is WL (second semiconductor switching element Wn), a signal When the generating unit 120 determines that (c) in the waveform example 3, the pattern in which 150 degrees to 150+30×(T_Thr4−(T_4−T_5))/T_Thr4 degrees is applied to the second fixed ON period, the signal generating unit 120 modulate.
上位2アームの位置がVH(第1半導体スイッチング素子Vp)およびVL(第2半導体スイッチング素子Vn)、かつ、上位3番目に高温のアームがWH(第1半導体スイッチング素子Wp)であると、信号生成部120が判定した場合、(e)波形例5において、330度~330+30×(T_Thr4-(T_4-T_5))/T_Thr4度を第1オン固定期間に適用したパターンで、信号生成部120は変調を行う。
When the positions of the upper two arms are VH (first semiconductor switching element Vp) and VL (second semiconductor switching element Vn), and the arm with the third highest temperature is WH (first semiconductor switching element Wp), a signal If the generating unit 120 determines, (e) in the waveform example 5, the pattern in which 330 degrees to 330+30×(T_Thr4−(T_4−T_5))/T_Thr4 degrees is applied to the first fixed ON period, and the signal generating unit 120 modulate.
上位2アームの位置がVH(第1半導体スイッチング素子Vp)およびVL(第2半導体スイッチング素子Vn)、かつ、上位3番目に高温のアームがWL(第2半導体スイッチング素子Wn)であると、信号生成部120が判定した場合、(e)波形例5において、150度~150+30×(T_Thr4-(T_4-T_5))/T_Thr4度を第2オン固定期間に適用したパターンで、信号生成部120は変調を行う。
When the positions of the upper two arms are VH (first semiconductor switching element Vp) and VL (second semiconductor switching element Vn), and the arm with the third highest temperature is WL (second semiconductor switching element Wn), a signal If the generating unit 120 determines, (e) in the waveform example 5, the pattern in which 150 degrees to 150+30×(T_Thr4−(T_4−T_5))/T_Thr4 degrees is applied to the second fixed ON period, and the signal generating unit 120 modulate.
上位2アームの位置がVH(第1半導体スイッチング素子Vp)およびWL(第2半導体スイッチング素子Wn)、かつ、上位3番目に高温のアームがWH(第1半導体スイッチング素子Wp)であると、信号生成部120が判定した場合、(f)波形例6において、330度~330+60×(T_Thr4-(T_4-T_5))/T_Thr4度を第1オン固定期間に適用したパターンで、信号生成部120は変調を行う。但し、上限が360度をD度だけ超える場合、(f)波形例6において第1オン固定期間を適用する区間は、0度~D度及び330度~360度とする。
When the positions of the upper two arms are VH (first semiconductor switching element Vp) and WL (second semiconductor switching element Wn), and the arm with the third highest temperature is WH (first semiconductor switching element Wp), a signal When the generation unit 120 determines that (f) in the waveform example 6, the pattern in which 330 degrees to 330+60×(T_Thr4−(T_4−T_5))/T_Thr4 degrees is applied to the first fixed ON period, the signal generation unit 120 modulate. However, if the upper limit exceeds 360 degrees by D degrees, the sections to which the first fixed ON period is applied in (f) waveform example 6 are 0 degrees to D degrees and 330 degrees to 360 degrees.
上位2アームの位置がVH(第1半導体スイッチング素子Vp)およびWL(第2半導体スイッチング素子Wn)、かつ、上位3番目に高温のアームがVL(第2半導体スイッチング素子Vn)であると、信号生成部120が判定した場合、信号生成部120は、(f)波形例6で変調を行う。処理は終了する。
When the positions of the upper two arms are VH (first semiconductor switching element Vp) and WL (second semiconductor switching element Wn), and the arm with the third highest temperature is VL (second semiconductor switching element Vn), a signal If the generation unit 120 determines, the signal generation unit 120 modulates with (f) waveform example 6 . Processing ends.
上位2アームの位置がVL(第2半導体スイッチング素子Vn)およびWH(第1半導体スイッチング素子Wp)、かつ、上位3番目に高温のアームがWL(第2半導体スイッチング素子Wn)であると、信号生成部120判定した場合、(i)波形例9において、180度~180+30×(T_Thr4-(T_4-T_5))/T_Thr4度を第2オン固定期間に適用したパターンで、信号生成部120は変調を行う。
When the positions of the upper two arms are VL (second semiconductor switching element Vn) and WH (first semiconductor switching element Wp), and the arm with the third highest temperature is WL (second semiconductor switching element Wn), a signal If the generating unit 120 determines, (i) in waveform example 9, the signal generating unit 120 modulates with a pattern in which 180 degrees to 180+30×(T_Thr4−(T_4−T_5))/T_Thr4 degrees is applied to the second ON fixed period. I do.
上位2アームの位置がVL(第2半導体スイッチング素子Vn)およびWH(第1半導体スイッチング素子Wp)、かつ、上位3番目に高温のアームがVH(第1半導体スイッチング素子Vp)であると、信号生成部120が判定した場合、(i)波形例9において、150度~150+30×(T_Thr4-(T_4-T_5))/T_Thr4度を第1オン固定期間に適用したパターンで、信号生成部120は変調を行う。
When the positions of the upper two arms are VL (second semiconductor switching element Vn) and WH (first semiconductor switching element Wp), and the arm with the third highest temperature is VH (first semiconductor switching element Vp), a signal When the generating unit 120 determines, (i) in the waveform example 9, the pattern in which 150 degrees to 150+30×(T_Thr4−(T_4−T_5))/T_Thr4 degrees is applied to the first fixed ON period, and the signal generating unit 120 modulate.
上位2アームの位置がWH(第1半導体スイッチング素子Wp)およびWL(第2半導体スイッチング素子Wn)、かつ、上位3番目に高温のアームがVL(第2半導体スイッチング素子Vn)であると、信号生成部120判定した場合、(j)波形例10において、0度~0+30×(T_Thr4-(T_4-T_5))/T_Thr4度を第2オン固定期間に適用したパターンで、信号生成部120は変調を行う。
When the positions of the upper two arms are WH (first semiconductor switching element Wp) and WL (second semiconductor switching element Wn), and the arm with the third highest temperature is VL (second semiconductor switching element Vn), a signal If the generation unit 120 determines, (j) in waveform example 10, the signal generation unit 120 modulates with a pattern in which 0 degrees to 0+30×(T_Thr4−(T_4−T_5))/T_Thr4 degrees is applied to the second ON fixed period. I do.
上位2アームの位置がWH(第1半導体スイッチング素子Wp)およびWL(第2半導体スイッチング素子Wn)、かつ、上位3番目に高温のアームがVH(第1半導体スイッチング素子Vp)であると、信号生成部120が判定した場合、(j)波形例10において、180度~180+30×(T_Thr4-(T_4-T_5))/T_Thr4度を第1オン固定期間に適用したパターンで、信号生成部120は変調を行う。
When the positions of the upper two arms are WH (first semiconductor switching element Wp) and WL (second semiconductor switching element Wn), and the arm with the third highest temperature is VH (first semiconductor switching element Vp), a signal When the generation unit 120 determines that (j) in waveform example 10, the pattern in which 180 degrees to 180+30×(T_Thr4−(T_4−T_5))/T_Thr4 degrees is applied to the first fixed ON period, the signal generation unit 120 modulate.
以上、図21~図24を参照して説明したように、保護動作モードは、1つの相の第1半導体スイッチング素子と第2半導体スイッチング素子とを保護する第1選択保護動作モードを含む、第1選択保護動作モードは、1つの相以外の相の第1半導体スイッチング素子と第2半導体スイッチング素子のうち、k個(kは2n-3以下の自然数)の第1半導体スイッチング素子または第2半導体スイッチング素子を保護する、複数のk個保護動作モードを含む。温度情報に基づいて、k個保護動作モードの選択を行う。したがって、冷却水路の問題などで特定の相の温度が問題となる場合、特定の相の温度が問題となる場合、特定の1相の第1半導体スイッチング素子と第2半導体スイッチング素子との昇温を最大限に抑制しながら、他の半導体スイッチング素子も温度状況に応じて必要な半導体スイッチング素子の昇温を抑制することで、インバータの信頼性が高まる。
As described above with reference to FIGS. 21 to 24, the protection operation mode includes the first selective protection operation mode that protects the first semiconductor switching element and the second semiconductor switching element of one phase. In the one-selection protection operation mode, among the first semiconductor switching elements and the second semiconductor switching elements of phases other than one phase, k (k is a natural number of 2n−3 or less) first semiconductor switching elements or second semiconductor switching elements It includes a plurality of k protection modes of operation to protect the switching elements. Selection of k protection operation modes is performed based on the temperature information. Therefore, if the temperature of a specific phase becomes a problem due to a problem in the cooling water passage, etc., if the temperature of the specific phase becomes a problem, the temperature rise of the first semiconductor switching element and the second semiconductor switching element of a specific phase While suppressing to the maximum extent possible, other semiconductor switching elements also suppress the temperature rise of necessary semiconductor switching elements in accordance with the temperature conditions, thereby increasing the reliability of the inverter.
図25~図42Bを参照して、本発明の実施形態に係る波形例についてさらに説明する。図25は、波形例とスイッチング損失との関係を示す表である。図25において、UHは、U相の第1半導体スイッチング素子Upのスイッチング損失を示す。ULは、U相の第2半導体スイッチング素子Unのスイッチング損失を示す。VHは、V相の第1半導体スイッチング素子Vpのスイッチング損失を示す。VLは、V相の第2半導体スイッチング素子Vnのスイッチング損失を示す。WHは、W相の第1半導体スイッチング素子Wpのスイッチング損失を示す。WLは、W相の第2半導体スイッチング素子Wnのスイッチング損失を示す。
Waveform examples according to embodiments of the present invention will be further described with reference to FIGS. 25 to 42B. FIG. 25 is a table showing the relationship between waveform examples and switching loss. In FIG. 25, UH represents the switching loss of the U-phase first semiconductor switching element Up. UL represents the switching loss of the U-phase second semiconductor switching element Un. VH represents the switching loss of the V-phase first semiconductor switching element Vp. VL represents the switching loss of the V-phase second semiconductor switching element Vn. WH represents the switching loss of the W-phase first semiconductor switching element Wp. WL represents the switching loss of the W-phase second semiconductor switching element Wn.
図25に示すように、波形例13~波形例29では、UHが0.32であり、VLが0.32である、すなわち、波形例13~波形例29では、U相の第1半導体スイッチング素子UpおよびV相の第2半導体スイッチング素子Vnのスイッチング損失が少ない波形例である。つまり、波形例13~波形例29は、U相の第1半導体スイッチング素子UpおよびV相の第2半導体スイッチング素子Vnを保護できる波形例である。本明細書において、ある相(例えばU相)の第1半導体スイッチング素子(例えばUp)および他の相(例えばV相)の第2半導体スイッチング素子(例えばVn)を保護できる波形を、UH_VL保護波形と記載することがある。これの波形例は、前者の第1オン固定期間と後者の第2オン固定期間とが連続する場合に相当する。
As shown in FIG. 25, in waveform examples 13 to 29, UH is 0.32 and VL is 0.32. This is an example of a waveform in which the switching loss of the element Up and the V-phase second semiconductor switching element Vn is small. That is, the waveform examples 13 to 29 are waveform examples capable of protecting the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn. In this specification, a waveform capable of protecting a first semiconductor switching element (eg Up) of a certain phase (eg U phase) and a second semiconductor switching element (eg Vn) of another phase (eg V phase) is referred to as a UH_VL protection waveform. is sometimes described. This waveform example corresponds to the case where the former first fixed ON period and the latter second fixed ON period are continuous.
図26Aおよび図26Bを参照して、波形例13について説明する。図26Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図26Bは、スイッチング損失を示す図である。
Waveform example 13 will be described with reference to FIGS. 26A and 26B. FIG. 26A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 26B is a diagram showing switching losses.
図26Aに示すように、波形例13は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例13は、電気角60度~電気角150度において、いずれか1相の出力が1に固定される波形である。また、波形例13は、電気角0度~電気角60度および電気角150度~電気角360度において、いずれか1相の出力が0に固定される波形である。波形例13では、電気角60度~電気角150度において、ハイサイドオン適用期間T3である。また、波形例13では、電気角0度~電気角60度および電気角150度~電気角360度において、ロウサイドオン適用期間T4である。
As shown in FIG. 26A, in waveform example 13, the output voltage of any one phase is fixed to 1 in a certain electrical angle section, and the output voltage of any one phase is fixed to 1 in another electrical angle section. is fixed to 0. Specifically, waveform example 13 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 150 degrees. Waveform example 13 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 degrees and at an electrical angle of 150 to 360 degrees. In waveform example 13, the high-side-on application period T3 is at an electrical angle of 60 degrees to 150 degrees. Further, in waveform example 13, the low side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees and at an electrical angle of 150 to 360 electrical degrees.
波形例13では、第1オン固定期間T1は、第1オン固定期間T1uを含む。波形例13では、電気角60度~電気角150度が第1オン固定期間T1uである。
In waveform example 13, the first fixed ON period T1 includes the first fixed ON period T1u. In waveform example 13, the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees.
波形例13では、第2オン固定期間T2は、第2オン固定期間T2uと、第2オン固定期間T2vと、第2オン固定期間T2wとを含む。波形例13では、電気角210度~電気角330度が第2オン固定期間T2uである。波形例13では、電気角0度~電気角60度および電気角330度~電気角360度が第2オン固定期間T2vである。波形例13では、電気角150度~電気角210度が第2オン固定期間T2wである。
In Waveform Example 13, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 13, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In waveform example 13, the second fixed ON period T2v is from an electrical angle of 0 degrees to an electrical angle of 60 degrees and from an electrical angle of 330 degrees to an electrical angle of 360 degrees. In waveform example 13, the second fixed ON period T2w is from 150 electrical degrees to 210 electrical degrees.
波形例13では、3相のうちU相において、第1オン固定期間T1uが、第1オン固定期間T1vおよび第1オン固定期間T1wと異なる。詳しくは、波形例13では、第1オン固定期間T1uが120度であるのに対し、第1オン固定期間T1vおよび第1オン固定期間T1wは無い。すなわち、波形例13では、第1オン固定期間T1uが第1オン固定期間T1vおよび第1オン固定期間T1wよりも長い。したがって、図26Bに示すように、U相の第1半導体スイッチング素子Up(H(ハイサイド))のスイッチング損失がV相およびW相に比べて小さくなっている。
In waveform example 13, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 13, the first fixed ON period T1u is 120 degrees, but there is no first fixed ON period T1v and no first fixed ON period T1w. That is, in waveform example 13, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 26B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
波形例13では、第2オン固定期間T2vが、第2オン固定期間T2uおよび第2オン固定期間T2wと異なる。詳しくは、波形例13では、第2オン固定期間T2vが90度であるのに対し、第2オン固定期間T2uは120度であり、第2オン固定期間T2wは60度である。すなわち、波形例13では、第2オン固定期間T2vが第2オン固定期間T2wよりも長い。したがって、図26Bに示すように、V相の第2半導体スイッチング素子Vn(L(ロウサイド))のスイッチング損失がW相に比べて小さくなっている。
In waveform example 13, the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in waveform example 13, the second fixed ON period T2v is 90 degrees, the second fixed ON period T2u is 120 degrees, and the second fixed ON period T2w is 60 degrees. That is, in waveform example 13, the second fixed ON period T2v is longer than the second fixed ON period T2w. Therefore, as shown in FIG. 26B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than that of the W-phase.
以上、図26Aおよび図26Bを参照して説明したように、波形例13においても、波形例1と同様に、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。波形例13では、U相の第1半導体スイッチング素子Upと、V相の第2半導体スイッチング素子Vnとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 26A and 26B , in waveform example 13, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 13, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn.
また、波形例13では、図26Bに示すように、U相の第2半導体スイッチング素子Unと、W相の第2半導体スイッチング素子Wnとの発熱についても同時に抑えることができる。
Further, in waveform example 13, as shown in FIG. 26B, the heat generation of the U-phase second semiconductor switching element Un and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
図27Aおよび図27Bを参照して、波形例14について説明する。図27Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図27Bは、スイッチング損失を示す図である。
Waveform example 14 will be described with reference to FIGS. 27A and 27B. FIG. 27A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 27B is a diagram showing switching losses.
図27Aに示すように、波形例14は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例14は、電気角60度~電気角180度において、いずれか1相の出力が1に固定される波形である。また、波形例14は、電気角0度~電気角60度および電気角180度~電気角360度において、いずれか1相の出力が0に固定される波形である。波形例14では、電気角60度~電気角180度において、ハイサイドオン適用期間T3である。また、波形例14では、電気角0度~電気角60度および電気角180度~電気角360度において、ロウサイドオン適用期間T4である。
As shown in FIG. 27A, in waveform example 14, according to the electrical angle, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, waveform example 14 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 180 degrees. Waveform example 14 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 degrees to 60 degrees and at an electrical angle of 180 degrees to 360 degrees. In waveform example 14, the high-side-on application period T3 is at an electrical angle of 60 degrees to 180 degrees. Further, in Waveform Example 14, the low side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees and at an electrical angle of 180 to 360 electrical degrees.
波形例14では、第1オン固定期間T1は、第1オン固定期間T1uと、第1オン固定期間T1vとを含む。波形例14では、電気角60度~電気角150度が第1オン固定期間T1uである。波形例14では、電気角150度~電気角180度が第1オン固定期間T1vである。
In Waveform Example 14, the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v. In waveform example 14, the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees. In waveform example 14, the first fixed ON period T1v is between 150 electrical degrees and 180 electrical degrees.
波形例14では、第2オン固定期間T2は、第2オン固定期間T2uと、第2オン固定期間T2vと、第2オン固定期間T2wとを含む。波形例14では、電気角210度~電気角330度が第2オン固定期間T2uである。波形例14では、電気角0度~電気角60度および電気角330度~電気角360度が第2オン固定期間T2vである。波形例14では、電気角180度~電気角210度が第2オン固定期間T2wである。
In Waveform Example 14, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 14, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In waveform example 14, the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees. In Waveform Example 14, the second fixed ON period T2w is from 180 electrical degrees to 210 electrical degrees.
波形例14では、3相のうちU相において、第1オン固定期間T1uが、第1オン固定期間T1vおよび第1オン固定期間T1wと異なる。詳しくは、波形例14では、第1オン固定期間T1uが90度であるのに対し、第1オン固定期間T1vが30度であり、第1オン固定期間T1wは無い。すなわち、波形例14では、第1オン固定期間T1uが第1オン固定期間T1vおよび第1オン固定期間T1wよりも長い。したがって、図27Bに示すように、U相の第1半導体スイッチング素子Up(H(ハイサイド))のスイッチング損失がV相およびW相に比べて小さくなっている。
In waveform example 14, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 14, the first fixed ON period T1u is 90 degrees, the first fixed ON period T1v is 30 degrees, and there is no first fixed ON period T1w. That is, in Waveform Example 14, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 27B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
波形例14では、第2オン固定期間T2vが、第2オン固定期間T2uおよび第2オン固定期間T2wと異なる。詳しくは、波形例14では、第2オン固定期間T2vが90度であるのに対し、第2オン固定期間T2uは120度であり、第2オン固定期間T2wは30度である。すなわち、波形例14では、第2オン固定期間T2vが第2オン固定期間T2wよりも長い。したがって、図27Bに示すように、V相の第2半導体スイッチング素子Un(L(ロウサイド))のスイッチング損失がW相に比べて小さくなっている。
In waveform example 14, the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in Waveform Example 14, the second fixed ON period T2v is 90 degrees, the second fixed ON period T2u is 120 degrees, and the second fixed ON period T2w is 30 degrees. That is, in waveform example 14, the second fixed ON period T2v is longer than the second fixed ON period T2w. Therefore, as shown in FIG. 27B, the switching loss of the V-phase second semiconductor switching element Un (L (low side)) is smaller than that of the W-phase.
以上、図27Aおよび図27Bを参照して説明したように、波形例14においても、波形例1と同様に、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。波形例14では、U相の第1半導体スイッチング素子Upと、V相の第2半導体スイッチング素子Vnとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 27A and 27B, in waveform example 14, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 14, the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
また、波形例14では、図27Bに示すように、U相の第2半導体スイッチング素子Unと、V相の第1半導体スイッチング素子Vpと、W相の第2半導体スイッチング素子Wnとの発熱についても同時に抑えることができる。
In waveform example 14, as shown in FIG. 27B, the heat generated by the U-phase second semiconductor switching element Un, the V-phase first semiconductor switching element Vp, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
図28Aおよび図28Bを参照して、波形例15について説明する。図28Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図28Bは、スイッチング損失を示す図である。
Waveform example 15 will be described with reference to FIGS. 28A and 28B. FIG. 28A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 28B is a diagram showing switching losses.
図28Aに示すように、波形例15は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例15は、電気角60度~電気角210度において、いずれか1相の出力が1に固定される波形である。また、波形例15は、電気角0度~電気角60度および電気角210度~電気角360度において、いずれか1相の出力が0に固定される波形である。波形例15では、電気角60度~電気角210度において、ハイサイドオン適用期間T3である。また、波形例15では、電気角0度~電気角60度および電気角210度~電気角360度において、ロウサイドオン適用期間T4である。
As shown in FIG. 28A , in waveform example 15, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, waveform example 15 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 210 degrees. Waveform example 15 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 degrees and at an electrical angle of 210 to 360 degrees. In waveform example 15, the high-side-on application period T3 is at an electrical angle of 60 degrees to 210 electrical degrees. In waveform example 15, the low side-on application period is T4 at an electrical angle of 0 to 60 electrical degrees and at an electrical angle of 210 to 360 electrical degrees.
波形例15では、第1オン固定期間T1は、第1オン固定期間T1uと、第1オン固定期間T1vとを含む。波形例15では、電気角60度~電気角150度が第1オン固定期間T1uである。波形例15では、電気角150度~電気角210度が第1オン固定期間T1vである。
In Waveform Example 15, the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v. In waveform example 15, the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees. In waveform example 15, the first fixed ON period T1v is between 150 electrical degrees and 210 electrical degrees.
波形例15では、第2オン固定期間T2は、第2オン固定期間T2uと、第2オン固定期間T2vとを含む。波形例15では、電気角210度~電気角330度が第2オン固定期間T2uである。波形例15では、電気角0度~電気角60度および電気角330度~電気角360度が第2オン固定期間T2vである。
In Waveform Example 15, the second fixed ON period T2 includes a second fixed ON period T2u and a second fixed ON period T2v. In waveform example 15, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In waveform example 15, the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees.
波形例15では、3相のうちU相において、第1オン固定期間T1uが、第1オン固定期間T1vおよび第1オン固定期間T1wと異なる。詳しくは、波形例15では、第1オン固定期間T1uが90度であるのに対し、第1オン固定期間T1vは60度であり、第1オン固定期間T1wは無い。すなわち、波形例15では、第1オン固定期間T1uが第1オン固定期間T1vおよび第1オン固定期間T1wよりも長い。したがって、図28Bに示すように、U相の第1半導体スイッチング素子Up(H(ハイサイド))のスイッチング損失がV相およびW相に比べて小さくなっている。
In waveform example 15, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 15, the first fixed ON period T1u is 90 degrees, the first fixed ON period T1v is 60 degrees, and there is no first fixed ON period T1w. That is, in waveform example 15, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 28B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
波形例15では、第2オン固定期間T2vが、第2オン固定期間T2uおよび第2オン固定期間T2wと異なる。詳しくは、波形例15では、第2オン固定期間T2vが90度であるのに対し、第2オン固定期間T2uは120度であり、第2オン固定期間T2wは無い。すなわち、波形例15では、第2オン固定期間T2vが第2オン固定期間T2wよりも長い。したがって、図28Bに示すように、V相の第2半導体スイッチング素子Vn(L(ロウサイド))のスイッチング損失がW相に比べて小さくなっている。
In waveform example 15, the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in waveform example 15, the second fixed ON period T2v is 90 degrees, the second fixed ON period T2u is 120 degrees, and there is no second fixed ON period T2w. That is, in waveform example 15, the second fixed ON period T2v is longer than the second fixed ON period T2w. Therefore, as shown in FIG. 28B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than that of the W-phase.
以上、図28Aおよび図28Bを参照して説明したように、波形例15においても、波形例1と同様に、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。波形例15では、U相の第1半導体スイッチング素子Upと、V相の第2半導体スイッチング素子Vnとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 28A and 28B , in waveform example 15, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 15, the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
また、波形例15では、図28Bに示すように、U相の第2半導体スイッチング素子Unと、V相の第1半導体スイッチング素子Vpとの発熱についても同時に抑えることができる。
Further, in waveform example 15, as shown in FIG. 28B, the heat generation of the U-phase second semiconductor switching element Un and the V-phase first semiconductor switching element Vp can be suppressed at the same time.
図29Aおよび図29Bを参照して、波形例16について説明する。図29Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図29Bは、スイッチング損失を示す図である。
Waveform example 16 will be described with reference to FIGS. 29A and 29B. FIG. 29A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 29B is a diagram showing switching losses.
図29Aに示すように、波形例16は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例16は、電気角60度~電気角240度において、いずれか1相の出力が1に固定される波形である。また、波形例16は、電気角0度~電気角60度および電気角240度~電気角360度において、いずれか1相の出力が0に固定される波形である。波形例16では、電気角60度~電気角240度において、ハイサイドオン適用期間T3である。また、波形例16では、電気角0度~電気角60度および電気角240度~電気角360度において、ロウサイドオン適用期間T4である。
As shown in FIG. 29A, in waveform example 16, according to the electrical angle, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, waveform example 16 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 240 degrees. Waveform example 16 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 degree to 60 electrical degrees and at an electrical angle of 240 degrees to 360 electrical degrees. In waveform example 16, the high-side-on application period T3 is at an electrical angle of 60 degrees to 240 electrical degrees. Further, in waveform example 16, the low side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees and at an electrical angle of 240 to 360 electrical degrees.
波形例16では、第1オン固定期間T1は、第1オン固定期間T1uと、第1オン固定期間T1vとを含む。波形例16では、電気角60度~電気角150度が第1オン固定期間T1uである。波形例16では、電気角150度~電気角240度が第1オン固定期間T1vである。
In Waveform Example 16, the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v. In waveform example 16, the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees. In waveform example 16, the first fixed ON period T1v is from 150 electrical degrees to 240 electrical degrees.
波形例16では、第2オン固定期間T2は、第2オン固定期間T2uと、第2オン固定期間T2vとを含む。波形例16では、電気角240度~電気角330度が第2オン固定期間T2uである。波形例16では、電気角0度~電気角60度および電気角330度~電気角360度が第2オン固定期間T2vである。
In Waveform Example 16, the second fixed ON period T2 includes a second fixed ON period T2u and a second fixed ON period T2v. In waveform example 16, the second fixed ON period T2u is from 240 electrical degrees to 330 electrical degrees. In waveform example 16, the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees.
波形例16では、3相のうちU相において、第1オン固定期間T1uが、第1オン固定期間T1wと異なる。詳しくは、波形例16では、第1オン固定期間T1uが90度であるのに対し、第1オン固定期間T1wは無い。すなわち、波形例16では、第1オン固定期間T1uが第1オン固定期間T1wよりも長い。なお、波形例16では、第1オン固定期間T1uと、第1オン固定期間T1vとは等しい。したがって、図29Bに示すように、U相の第1半導体スイッチング素子Up(H(ハイサイド))のスイッチング損失がW相に比べて小さくなっている。
In waveform example 16, the first fixed ON period T1u differs from the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 16, the first fixed ON period T1u is 90 degrees, but there is no first fixed ON period T1w. That is, in waveform example 16, the first fixed ON period T1u is longer than the first fixed ON period T1w. In waveform example 16, the first fixed ON period T1u and the first fixed ON period T1v are equal. Therefore, as shown in FIG. 29B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than that of the W-phase.
波形例16では、第2オン固定期間T2vが、第2オン固定期間T2uおよび第2オン固定期間T2wと異なる。詳しくは、波形例16では、第2オン固定期間T2vが90度であるのに対し、第2オン固定期間T2wは無い。すなわち、波形例16では、第2オン固定期間T2vが第2オン固定期間T2wよりも長い。なお、波形例16では、第2オン固定期間T2uと、第2オン固定期間T2vとは等しい。したがって、図29Bに示すように、V相の第2半導体スイッチング素子Vn(L(ロウサイド))のスイッチング損失がW相に比べて小さくなっている。
In waveform example 16, the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in waveform example 16, the second fixed ON period T2v is 90 degrees, but there is no second fixed ON period T2w. That is, in waveform example 16, the second fixed ON period T2v is longer than the second fixed ON period T2w. In waveform example 16, the second fixed ON period T2u is equal to the second fixed ON period T2v. Therefore, as shown in FIG. 29B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than that of the W-phase.
以上、図29Aおよび図29Bを参照して説明したように、波形例16においても、波形例1と同様に、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。波形例16では、U相の第1半導体スイッチング素子Upと、V相の第2半導体スイッチング素子Vnとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 29A and 29B , in waveform example 16, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 16, the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
また、波形例16では、図29Bに示すように、U相の第2半導体スイッチング素子Unと、V相の第1半導体スイッチング素子Vpとの発熱についても同時に抑えることができる。
Further, in waveform example 16, as shown in FIG. 29B, the heat generation of the U-phase second semiconductor switching element Un and the V-phase first semiconductor switching element Vp can be suppressed at the same time.
図30Aおよび図30Bを参照して、波形例17について説明する。図30Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図30Bは、スイッチング損失を示す図である。
Waveform example 17 will be described with reference to FIGS. 30A and 30B. FIG. 30A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 30B is a diagram showing switching losses.
図30Aに示すように、波形例17は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例17は、電気角60度~電気角270度において、いずれか1相の出力が1に固定される波形である。また、波形例17は、電気角0度~電気角60度および電気角270度~電気角360度において、いずれか1相の出力が0に固定される波形である。波形例17では、電気角60度~電気角270度において、ハイサイドオン適用期間T3である。また、波形例17では、電気角0度~電気角60度および電気角270度~電気角360度において、ロウサイドオン適用期間T4である。
As shown in FIG. 30A, in waveform example 17, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, waveform example 17 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 270 degrees. Waveform example 17 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 degree to 60 electrical degrees and at an electrical angle of 270 degrees to 360 electrical degrees. In waveform example 17, the high-side-on application period T3 is at an electrical angle of 60 degrees to 270 electrical degrees. Further, in waveform example 17, the low-side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees and at an electrical angle of 270 to 360 electrical degrees.
波形例17では、第1オン固定期間T1は、第1オン固定期間T1uと、第1オン固定期間T1vとを含む。波形例17では、電気角60度~電気角150度が第1オン固定期間T1uである。波形例17では、電気角150度~電気角270度が第1オン固定期間T1vである。
In Waveform Example 17, the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v. In waveform example 17, the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees. In waveform example 17, the first fixed ON period T1v is from 150 electrical degrees to 270 electrical degrees.
波形例17では、第2オン固定期間T2は、第2オン固定期間T2uと、第2オン固定期間T2vとを含む。波形例17では、電気角270度~電気角330度が第2オン固定期間T2uである。波形例17では、電気角0度~電気角60度および電気角330度~電気角360度が第2オン固定期間T2vである。
In waveform example 17, the second fixed ON period T2 includes a second fixed ON period T2u and a second fixed ON period T2v. In waveform example 17, the second fixed ON period T2u is from 270 electrical degrees to 330 electrical degrees. In waveform example 17, the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees.
波形例17では、3相のうちU相において、第1オン固定期間T1uが、第1オン固定期間T1vおよび第1オン固定期間T1wと異なる。詳しくは、波形例17では、第1オン固定期間T1uが90度であるのに対し、第1オン固定期間T1vは120度であり、第1オン固定期間T1wは無い。すなわち、波形例17では、第1オン固定期間T1uが第1オン固定期間T1wよりも長い。したがって、図30Bに示すように、U相の第1半導体スイッチング素子Up(H(ハイサイド))のスイッチング損失がW相に比べて小さくなっている。
In waveform example 17, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in Waveform Example 17, the first fixed ON period T1u is 90 degrees, the first fixed ON period T1v is 120 degrees, and there is no first fixed ON period T1w. That is, in waveform example 17, the first fixed ON period T1u is longer than the first fixed ON period T1w. Therefore, as shown in FIG. 30B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than that of the W-phase.
波形例17では、第2オン固定期間T2vが、第2オン固定期間T2uおよび第2オン固定期間T2wと異なる。詳しくは、波形例17では、第2オン固定期間T2vが90度であるのに対し、第2オン固定期間T2uは60度であり、第2オン固定期間T2wは無い。すなわち、波形例17では、第2オン固定期間T2vが第2オン固定期間T2uおよび第2オン固定期間T2wよりも長い。したがって、図30Bに示すように、V相の第2半導体スイッチング素子Vn(L(ロウサイド))のスイッチング損失がU相およびW相に比べて小さくなっている。
In waveform example 17, the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in Waveform Example 17, the second fixed ON period T2v is 90 degrees, the second fixed ON period T2u is 60 degrees, and there is no second fixed ON period T2w. That is, in Waveform Example 17, the second fixed ON period T2v is longer than the second fixed ON period T2u and the second fixed ON period T2w. Therefore, as shown in FIG. 30B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
以上、図30Aおよび図30Bを参照して説明したように、波形例17においても、波形例1と同様に、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。波形例17では、U相の第1半導体スイッチング素子Upと、V相の第2半導体スイッチング素子Vnとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 30A and 30B , in waveform example 17, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 17, the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
また、波形例17では、図30Bに示すように、U相の第2半導体スイッチング素子Unと、V相の第1半導体スイッチング素子Vpとの発熱についても同時に抑えることができる。
Further, in waveform example 17, as shown in FIG. 30B, the heat generation of the U-phase second semiconductor switching element Un and the V-phase first semiconductor switching element Vp can be suppressed at the same time.
図31Aおよび図31Bを参照して、波形例18について説明する。図31Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図31Bは、スイッチング損失を示す図である。
Waveform example 18 will be described with reference to FIGS. 31A and 31B. FIG. 31A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 31B is a diagram showing switching losses.
図31Aに示すように、波形例18は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例18は、電気角60度~電気角300度において、いずれか1相の出力が1に固定される波形である。また、波形例18は、電気角0度~電気角60度および電気角300度~電気角360度において、いずれか1相の出力が0に固定される波形である。波形例18では、電気角60度~電気角300度において、ハイサイドオン適用期間T3である。また、波形例18では、電気角0度~電気角60度および電気角300度~電気角360度において、ロウサイドオン適用期間T4である。
As shown in FIG. 31A, in waveform example 18, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, waveform example 18 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 300 degrees. Waveform example 18 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 electrical degrees and at an electrical angle of 300 to 360 electrical degrees. In waveform example 18, the high-side-on application period T3 is at an electrical angle of 60 degrees to 300 electrical degrees. Further, in waveform example 18, the low side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees and at an electrical angle of 300 to 360 electrical degrees.
波形例18では、第1オン固定期間T1は、第1オン固定期間T1uを含む。波形例18では、電気角60度~電気角150度が第1オン固定期間T1uである。波形例18では、電気角150度~電気角270度が第1オン固定期間T1vである。波形例18では、電気角270度~電気角300度が第1オン固定期間T1wである。
In waveform example 18, the first fixed ON period T1 includes the first fixed ON period T1u. In waveform example 18, the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees. In waveform example 18, the first fixed ON period T1v is from 150 electrical degrees to 270 electrical degrees. In waveform example 18, the first fixed ON period T1w is from 270 electrical degrees to 300 electrical degrees.
波形例18では、第2オン固定期間T2は、第2オン固定期間T2uと、第2オン固定期間T2vとを含む。波形例18では、電気角300度~電気角330度が第2オン固定期間T2uである。波形例18では、電気角0度~電気角60度および電気角330度~電気角360度が第2オン固定期間T2vである。
In Waveform Example 18, the second fixed ON period T2 includes a second fixed ON period T2u and a second fixed ON period T2v. In waveform example 18, the second fixed ON period T2u is between 300 electrical degrees and 330 electrical degrees. In waveform example 18, the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees.
波形例18では、3相のうちU相において、第1オン固定期間T1uが、第1オン固定期間T1vおよび第1オン固定期間T1wと異なる。詳しくは、波形例18では、第1オン固定期間T1uが90度であるのに対し、第1オン固定期間T1vは、120度であり、第1オン固定期間T1wは30度である。すなわち、波形例18では、第1オン固定期間T1uが第1オン固定期間T1wよりも長い。したがって、図31Bに示すように、U相の第1半導体スイッチング素子Up(H(ハイサイド))のスイッチング損失がW相に比べて小さくなっている。
In waveform example 18, in the U phase among the three phases, the first fixed ON period T1u is different from the first fixed ON period T1v and the first fixed ON period T1w. Specifically, in waveform example 18, the first fixed ON period T1u is 90 degrees, the first fixed ON period T1v is 120 degrees, and the first fixed ON period T1w is 30 degrees. That is, in waveform example 18, the first fixed ON period T1u is longer than the first fixed ON period T1w. Therefore, as shown in FIG. 31B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than that of the W-phase.
波形例18では、第2オン固定期間T2vが、第2オン固定期間T2uおよび第2オン固定期間T2wと異なる。詳しくは、波形例18では、第2オン固定期間T2vが90度であるのに対し、第2オン固定期間T2uは30度であり、第2オン固定期間T2wは無い。すなわち、波形例18では、第2オン固定期間T2vが第2オン固定期間T2uおよび第2オン固定期間T2wよりも長い。したがって、図31Bに示すように、V相の第2半導体スイッチング素子Vn(L(ロウサイド))のスイッチング損失がU相およびW相に比べて小さくなっている。
In waveform example 18, the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in Waveform Example 18, the second fixed ON period T2v is 90 degrees, the second fixed ON period T2u is 30 degrees, and there is no second fixed ON period T2w. That is, in Waveform Example 18, the second fixed ON period T2v is longer than the second fixed ON period T2u and the second fixed ON period T2w. Therefore, as shown in FIG. 31B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
以上、図31Aおよび図31Bを参照して説明したように、波形例18においても、波形例1と同様に、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。波形例18では、U相の第1半導体スイッチング素子Upと、V相の第2半導体スイッチング素子Vnとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 31A and 31B, in waveform example 18, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 18, the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
また、波形例18では、図31Bに示すように、U相の第2半導体スイッチング素子Unと、V相の第1半導体スイッチング素子Vpと、W相の第1半導体スイッチング素子Wpとの発熱についても同時に抑えることができる。
In waveform example 18, as shown in FIG. 31B, the heat generated by the U-phase second semiconductor switching element Un, the V-phase first semiconductor switching element Vp, and the W-phase first semiconductor switching element Wp can be suppressed at the same time.
図32Aおよび図32Bを参照して、波形例19について説明する。図32Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図32Bは、スイッチング損失を示す図である。
Waveform example 19 will be described with reference to FIGS. 32A and 32B. FIG. 32A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 32B is a diagram showing switching losses.
図32Aに示すように、波形例19は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例19は、電気角60度~電気角330度において、いずれか1相の出力が1に固定される波形である。また、波形例19は、電気角0度~電気角60度および電気角330度~電気角360度において、いずれか1相の出力が0に固定される波形である。波形例19では、電気角60度~電気角330度において、ハイサイドオン適用期間T3である。また、波形例19では、電気角0度~電気角60度および電気角330度~電気角360度において、ロウサイドオン適用期間T4である。
As shown in FIG. 32A , in waveform example 19, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, waveform example 19 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 330 degrees. Waveform example 19 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 electrical degrees and at an electrical angle of 330 to 360 electrical degrees. In waveform example 19, the high-side-on application period T3 is at an electrical angle of 60 degrees to 330 electrical degrees. Further, in waveform example 19, the low side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees and at an electrical angle of 330 to 360 electrical degrees.
波形例19では、第1オン固定期間T1は、第1オン固定期間T1uと、第1オン固定期間T1vと、第1オン固定期間T1wとを含む。波形例19では、電気角60度~電気角150度が第1オン固定期間T1uである。波形例19では、電気角150度~電気角270度が第1オン固定期間T1vである。波形例19では、電気角270度~電気角330度が第1オン固定期間T1wである。
In Waveform Example 19, the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w. In waveform example 19, the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees. In waveform example 19, the first fixed ON period T1v is from 150 electrical degrees to 270 electrical degrees. In Waveform Example 19, the first fixed ON period T1w is from 270 electrical degrees to 330 electrical degrees.
波形例19では、第2オン固定期間T2は、第2オン固定期間T2vを含む。波形例19では、波形例19では、電気角0度~電気角60度および電気角330度~電気角360度が第2オン固定期間T2vである。
In waveform example 19, the second fixed ON period T2 includes the second fixed ON period T2v. In waveform example 19, the second fixed ON period T2v is from 0 electrical angle to 60 electrical degrees and from 330 electrical degrees to 360 electrical degrees.
波形例19では、3相のうちU相において、第1オン固定期間T1uが、第1オン固定期間T1vおよび第1オン固定期間T1wと異なる。詳しくは、波形例19では、第1オン固定期間T1uが90度であるのに対し、第1オン固定期間T1vは120度であり、第1オン固定期間T1wは60度である。すなわち、波形例19では、第1オン固定期間T1uが第1オン固定期間T1wよりも長い。したがって、図32Bに示すように、U相の第1半導体スイッチング素子Up(H(ハイサイド))のスイッチング損失がW相に比べて小さくなっている。
In waveform example 19, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 19, the first fixed ON period T1u is 90 degrees, the first fixed ON period T1v is 120 degrees, and the first fixed ON period T1w is 60 degrees. That is, in waveform example 19, the first fixed ON period T1u is longer than the first fixed ON period T1w. Therefore, as shown in FIG. 32B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than that of the W-phase.
波形例19では、第2オン固定期間T2vが、第2オン固定期間T2uおよび第2オン固定期間T2wと異なる。詳しくは、波形例19では、第2オン固定期間T2vが90度であるのに対し、第2オン固定期間T2uおよび第2オン固定期間T2wは無い。すなわち、波形例19では、第2オン固定期間T2vが第2オン固定期間T2uおよび第2オン固定期間T2wよりも長い。したがって、図32Bに示すように、V相の第2半導体スイッチング素子Vn(L(ロウサイド))のスイッチング損失がU相およびW相に比べて小さくなっている。
In waveform example 19, the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in Waveform Example 19, the second fixed ON period T2v is 90 degrees, whereas the second fixed ON period T2u and the second fixed ON period T2w are absent. That is, in Waveform Example 19, the second fixed ON period T2v is longer than the second fixed ON period T2u and the second fixed ON period T2w. Therefore, as shown in FIG. 32B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
以上、図32Aおよび図32Bを参照して説明したように、波形例19においても、波形例1と同様に、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。波形例19では、U相の第1半導体スイッチング素子Upと、V相の第2半導体スイッチング素子Vnとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 32A and 32B , in waveform example 19, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 19, the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
また、波形例19では、図32Bに示すように、V相の第1半導体スイッチング素子Vpと、W相の第1半導体スイッチング素子Wpとの発熱についても同時に抑えることができる。
Further, in waveform example 19, as shown in FIG. 32B, the heat generation of the V-phase first semiconductor switching element Vp and the W-phase first semiconductor switching element Wp can be suppressed at the same time.
図33Aおよび図33Bを参照して、波形例20について説明する。図33Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図33Bは、スイッチング損失を示す図である。
A waveform example 20 will be described with reference to FIGS. 33A and 33B. FIG. 33A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 33B is a diagram showing switching losses.
図33Aに示すように、波形例20は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例20は、電気角60度~電気角150度および電気角300度~電気角330度において、いずれか1相の出力が1に固定される波形である。また、波形例20は、電気角0度~電気角60度、電気角150度~電気角300度および電気角330度~電気角360度において、いずれか1相の出力が0に固定される波形である。波形例20では、電気角60度~電気角150度および電気角300度~電気角330度において、ハイサイドオン適用期間T3である。また、波形例20では、電気角0度~電気角60度、電気角150度~電気角300度および電気角330度~電気角360度において、ロウサイドオン適用期間T4である。
As shown in FIG. 33A, in waveform example 20, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, waveform example 20 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 300 degrees to 330 degrees. In waveform example 20, the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 electrical degrees, 150 to 300 electrical degrees, and 330 to 360 electrical degrees. waveform. In waveform example 20, the high side-on application period T3 occurs at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 300 degrees to 330 degrees. Further, in waveform example 20, the low side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees, 150 to 300 electrical degrees, and 330 to 360 electrical degrees.
波形例20では、第1オン固定期間T1は、第1オン固定期間T1uと、第1オン固定期間T1wとを含む。波形例20では、電気角60度~電気角150度が第1オン固定期間T1uである。波形例20では、電気角300度~電気角330度が第1オン固定期間T1wである。
In waveform example 20, the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1w. In waveform example 20, the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees. In waveform example 20, the first fixed ON period T1w is between 300 electrical degrees and 330 electrical degrees.
波形例20では、第2オン固定期間T2は、第2オン固定期間T2uと、第2オン固定期間T2vと、第2オン固定期間T2wとを含む。波形例20では、電気角210度~電気角300度が第2オン固定期間T2uである。波形例20では、電気角0度~電気角60度および電気角330度~電気角360度が第2オン固定期間T2vである。波形例20では、電気角150度~電気角210度が第2オン固定期間T2wである。
In waveform example 20, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 20, the second fixed ON period T2u is from 210 electrical degrees to 300 electrical degrees. In waveform example 20, the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees. In waveform example 20, the second fixed ON period T2w is from 150 electrical degrees to 210 electrical degrees.
波形例20では、3相のうちU相において、第1オン固定期間T1uが、第1オン固定期間T1vおよび第1オン固定期間T1wと異なる。詳しくは、波形例20では、第1オン固定期間T1uが90度であるのに対し、第1オン固定期間T1vは無く、第1オン固定期間T1wは30度である。すなわち、波形例20では、第1オン固定期間T1uが第1オン固定期間T1vおよび第1オン固定期間T1wよりも長い。したがって、図33Bに示すように、U相の第1半導体スイッチング素子Up(H(ハイサイド))のスイッチング損失がV相およびW相に比べて小さくなっている。
In waveform example 20, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 20, the first fixed ON period T1u is 90 degrees, but the first fixed ON period T1v is absent and the first fixed ON period T1w is 30 degrees. That is, in waveform example 20, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 33B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
波形例20では、第2オン固定期間T2vが、第2オン固定期間T2uおよび第2オン固定期間T2wと異なる。詳しくは、波形例20では、第2オン固定期間T2vが90度であるのに対し、第2オン固定期間T2uは90度であり、第2オン固定期間T2wは60度である。すなわち、波形例20では、第2オン固定期間T2vが第2オン固定期間T2wよりも長い。したがって、図33Bに示すように、V相の第2半導体スイッチング素子Vn(L(ロウサイド))のスイッチング損失がW相に比べて小さくなっている。
In waveform example 20, the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in waveform example 20, the second fixed ON period T2v is 90 degrees, the second fixed ON period T2u is 90 degrees, and the second fixed ON period T2w is 60 degrees. That is, in waveform example 20, the second fixed ON period T2v is longer than the second fixed ON period T2w. Therefore, as shown in FIG. 33B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than that of the W-phase.
以上、図33Aおよび図33Bを参照して説明したように、波形例20においても、波形例1と同様に、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。波形例20では、U相の第1半導体スイッチング素子Upと、V相の第2半導体スイッチング素子Vnとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 33A and 33B, in waveform example 20 as well as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 20, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn.
また、波形例20では、図33Bに示すように、U相の第2半導体スイッチング素子Unと、W相の第1半導体スイッチング素子Wpと、W相の第2半導体スイッチング素子Wnとの発熱についても同時に抑えることができる。
In waveform example 20, as shown in FIG. 33B, the heat generated by the U-phase second semiconductor switching element Un, the W-phase first semiconductor switching element Wp, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
図34Aおよび図34Bを参照して、波形例21について説明する。図34Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図34Bは、スイッチング損失を示す図である。
A waveform example 21 will be described with reference to FIGS. 34A and 34B. FIG. 34A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 34B is a diagram showing switching losses.
図34Aに示すように、波形例21は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例21は、電気角60度~電気角150度および電気角270度~電気角330度において、いずれか1相の出力が1に固定される波形である。また、波形例21は、電気角0度~電気角60度、電気角150度~電気角270度および電気角330度~電気角360度において、いずれか1相の出力が0に固定される波形である。波形例21では、電気角60度~電気角150度および電気角270度~電気角330度において、ハイサイドオン適用期間T3である。また、波形例21では、電気角0度~電気角60度、電気角150度~電気角270度および電気角330度~電気角360度において、ロウサイドオン適用期間T4である。
As shown in FIG. 34A, in waveform example 21, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, waveform example 21 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 270 degrees to 330 degrees. In waveform example 21, the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 electrical degrees, 150 to 270 electrical degrees, and 330 to 360 electrical degrees. waveform. In waveform example 21, the high side-on application period T3 occurs at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 270 degrees to 330 degrees. Further, in waveform example 21, the low side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees, 150 to 270 electrical degrees, and 330 to 360 electrical degrees.
波形例21では、第1オン固定期間T1は、第1オン固定期間T1uと、第1オン固定期間T1wとを含む。波形例21では、電気角60度~電気角150度が第1オン固定期間T1uである。波形例21では、電気角270度~電気角330度が第1オン固定期間T1wである。
In waveform example 21, the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1w. In waveform example 21, the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees. In waveform example 21, the first fixed ON period T1w is from 270 electrical degrees to 330 electrical degrees.
波形例21では、第2オン固定期間T2は、第2オン固定期間T2uと、第2オン固定期間T2vと、第2オン固定期間T2wとを含む。波形例21では、電気角210度~電気角270度が第2オン固定期間T2uである。波形例21では、電気角0度~電気角60度および電気角330度~電気角360度が第2オン固定期間T2vである。波形例21では、電気角150度~電気角210度が第2オン固定期間T2wである。
In waveform example 21, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 21, the second fixed ON period T2u is from 210 electrical degrees to 270 electrical degrees. In waveform example 21, the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees. In waveform example 21, the second fixed ON period T2w is between 150 electrical degrees and 210 electrical degrees.
波形例21では、3相のうちU相において、第1オン固定期間T1uが、第1オン固定期間T1vおよび第1オン固定期間T1wと異なる。詳しくは、波形例21では、第1オン固定期間T1uが90度であるのに対し、第1オン固定期間T1vは無く、第1オン固定期間T1wは60度である。すなわち、波形例21では、第1オン固定期間T1uが第1オン固定期間T1vおよび第1オン固定期間T1wよりも長い。したがって、図34Bに示すように、U相の第1半導体スイッチング素子Up(H(ハイサイド))のスイッチング損失がV相およびW相に比べて小さくなっている。
In waveform example 21, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 21, the first fixed ON period T1u is 90 degrees, but the first fixed ON period T1v is absent and the first fixed ON period T1w is 60 degrees. That is, in waveform example 21, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 34B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
波形例21では、第2オン固定期間T2vが、第2オン固定期間T2uおよび第2オン固定期間T2wと異なる。詳しくは、波形例21では、第2オン固定期間T2vが90度であるのに対し、第2オン固定期間T2uは60度であり、第2オン固定期間T2wは60度である。すなわち、波形例21では、第2オン固定期間T2vが第2オン固定期間T2uおよび第2オン固定期間T2wよりも長い。したがって、図34Bに示すように、V相の第2半導体スイッチング素子Vn(L(ロウサイド))のスイッチング損失がU相およびW相に比べて小さくなっている。
In waveform example 21, the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in waveform example 21, the second fixed ON period T2v is 90 degrees, the second fixed ON period T2u is 60 degrees, and the second fixed ON period T2w is 60 degrees. That is, in waveform example 21, the second fixed ON period T2v is longer than the second fixed ON period T2u and the second fixed ON period T2w. Therefore, as shown in FIG. 34B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
以上、図34Aおよび図34Bを参照して説明したように、波形例21においても、波形例1と同様に、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。波形例21では、U相の第1半導体スイッチング素子Upと、V相の第2半導体スイッチング素子Vnとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 34A and 34B , in waveform example 21, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 21, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn.
また、波形例21では、図34Bに示すように、U相の第2半導体スイッチング素子Unと、W相の第1半導体スイッチング素子Wpと、W相の第2半導体スイッチング素子Wnとの発熱についても同時に抑えることができる。
In waveform example 21, as shown in FIG. 34B, the heat generated by the U-phase second semiconductor switching element Un, the W-phase first semiconductor switching element Wp, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
図35Aおよび図35Bを参照して、波形例22について説明する。図35Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図35Bは、スイッチング損失を示す図である。
A waveform example 22 will be described with reference to FIGS. 35A and 35B. FIG. 35A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 35B is a diagram showing switching losses.
図35Aに示すように、波形例22は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例22は、電気角60度~電気角150度および電気角240度~電気角330度において、いずれか1相の出力が1に固定される波形である。また、波形例22は、電気角0度~電気角60度、電気角150度~電気角240度および電気角330度~電気角360度において、いずれか1相の出力が0に固定される波形である。波形例22では、電気角60度~電気角150度および電気角240度~電気角330度において、ハイサイドオン適用期間T3である。また、波形例22では、電気角0度~電気角60度、電気角150度~電気角240度および電気角330度~電気角360度において、ロウサイドオン適用期間T4である。
As shown in FIG. 35A, in waveform example 22, the output voltage of any one phase is fixed to 1 in a certain electrical angle section, and the output voltage of any one phase is fixed to 1 in another electrical angle section, depending on the electrical angle. is fixed to 0. Specifically, waveform example 22 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 240 degrees to 330 degrees. In waveform example 22, the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 electrical degrees, 150 to 240 electrical degrees, and 330 to 360 electrical degrees. waveform. In waveform example 22, the high side-on application period T3 occurs at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 240 degrees to 330 degrees. In waveform example 22, the low-side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees, 150 to 240 electrical degrees, and 330 to 360 electrical degrees.
波形例22では、第1オン固定期間T1は、第1オン固定期間T1uと、第1オン固定期間T1v、第1オン固定期間T1wとを含む。波形例22では、電気角60度~電気角150度が第1オン固定期間T1uである。波形例22では、電気角240度~電気角270度が第1オン固定期間T1vである。波形例22では、電気角270度~電気角330度が第1オン固定期間T1wである。
In waveform example 22, the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w. In waveform example 22, the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees. In waveform example 22, the first fixed ON period T1v is between 240 electrical degrees and 270 electrical degrees. In waveform example 22, the first fixed ON period T1w is from 270 electrical degrees to 330 electrical degrees.
波形例22では、第2オン固定期間T2は、第2オン固定期間T2uと、第2オン固定期間T2vと、第2オン固定期間T2wとを含む。波形例22では、電気角210度~電気角240度が第2オン固定期間T2uである。波形例22では、電気角0度~電気角60度および電気角330度~電気角360度が第2オン固定期間T2vである。波形例22では、電気角150度~電気角210度が第2オン固定期間T2wである。
In waveform example 22, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 22, the second fixed ON period T2u is from 210 electrical degrees to 240 electrical degrees. In waveform example 22, the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees. In waveform example 22, the second fixed ON period T2w is between 150 electrical degrees and 210 electrical degrees.
波形例22では、3相のうちU相において、第1オン固定期間T1uが、第1オン固定期間T1vおよび第1オン固定期間T1wと異なる。詳しくは、波形例22では、第1オン固定期間T1uが90度であるのに対し、第1オン固定期間T1vは30度であり、第1オン固定期間T1wは60度である。すなわち、波形例22では、第1オン固定期間T1uが第1オン固定期間T1vおよび第1オン固定期間T1wよりも長い。したがって、図35Bに示すように、U相の第1半導体スイッチング素子Up(H(ハイサイド))のスイッチング損失がV相およびW相に比べて小さくなっている。
In waveform example 22, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 22, the first fixed ON period T1u is 90 degrees, the first fixed ON period T1v is 30 degrees, and the first fixed ON period T1w is 60 degrees. That is, in waveform example 22, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 35B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
波形例22では、第2オン固定期間T2vが、第2オン固定期間T2uおよび第2オン固定期間T2wと異なる。詳しくは、波形例22では、第2オン固定期間T2vが90度であるのに対し、第2オン固定期間T2uは30度であり、第2オン固定期間T2wは60度である。すなわち、波形例22では、第2オン固定期間T2vが第2オン固定期間T2uおよび第2オン固定期間T2wよりも長い。したがって、図35Bに示すように、V相の第2半導体スイッチング素子Vn(L(ロウサイド))のスイッチング損失がU相およびW相に比べて小さくなっている。
In waveform example 22, the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in waveform example 22, the second fixed ON period T2v is 90 degrees, the second fixed ON period T2u is 30 degrees, and the second fixed ON period T2w is 60 degrees. That is, in waveform example 22, the second fixed ON period T2v is longer than the second fixed ON period T2u and the second fixed ON period T2w. Therefore, as shown in FIG. 35B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
以上、図35Aおよび図35Bを参照して説明したように、波形例22においても、波形例1と同様に、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。波形例22では、U相の第1半導体スイッチング素子Upと、V相の第2半導体スイッチング素子Vnとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 35A and 35B , in waveform example 22, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 22, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn.
また、波形例22では、図35Bに示すように、U相の第2半導体スイッチング素子Unと、V相の第1半導体スイッチング素子Vpと、W相の第1半導体スイッチング素子Wpと、W相の第2半導体スイッチング素子Wnとの発熱についても同時に抑えることができる。
In waveform example 22, as shown in FIG. 35B, the U-phase second semiconductor switching element Un, the V-phase first semiconductor switching element Vp, the W-phase first semiconductor switching element Wp, and the W-phase semiconductor switching element Wp Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
図36Aおよび図36Bを参照して、波形例23について説明する。図36Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図36Bは、スイッチング損失を示す図である。
A waveform example 23 will be described with reference to FIGS. 36A and 36B. FIG. 36A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 36B is a diagram showing switching losses.
図36Aに示すように、波形例23は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例23は、電気角60度~電気角150度および電気角210度~電気角330度において、いずれか1相の出力が1に固定される波形である。また、波形例23は、電気角0度~電気角60度、電気角150度~電気角210度および電気角330度~電気角360度において、いずれか1相の出力が0に固定される波形である。波形例23では、電気角60度~電気角150度および電気角210度~電気角330度において、ハイサイドオン適用期間T3である。また、波形例23では、電気角0度~電気角60度、電気角150度~電気角210度および電気角330度~電気角360度において、ロウサイドオン適用期間T4である。
As shown in FIG. 36A, in waveform example 23, the output voltage of any one phase is fixed to 1 in a certain electrical angle section, and the output voltage of any one phase is fixed to 1 in another electrical angle section, depending on the electrical angle. is fixed to 0. Specifically, waveform example 23 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 210 degrees to 330 degrees. In waveform example 23, the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 electrical degrees, 150 to 210 electrical degrees, and 330 to 360 electrical degrees. waveform. In waveform example 23, the high side-on application period T3 occurs at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 210 degrees to 330 degrees. Further, in waveform example 23, the low side-on application period T4 is at the electrical angle of 0 to 60 electrical degrees, the electrical angle of 150 to 210 electrical degrees, and the electrical angle of 330 to 360 electrical degrees.
波形例23では、第1オン固定期間T1は、第1オン固定期間T1uと、第1オン固定期間T1vと、第1オン固定期間T1wとを含む。波形例23では、電気角60度~電気角150度が第1オン固定期間T1uである。波形例23では、電気角210度~電気角270度が第1オン固定期間T1vである。波形例23では、電気角270度~電気角330度が第1オン固定期間T1uである。
In waveform example 23, the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w. In waveform example 23, the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees. In waveform example 23, the first fixed ON period T1v is between 210 electrical degrees and 270 electrical degrees. In waveform example 23, the first fixed ON period T1u is from 270 electrical degrees to 330 electrical degrees.
波形例23では、第2オン固定期間T2は、第2オン固定期間T2uと、第2オン固定期間T2vと、第2オン固定期間T2wとを含む。波形例23では、電気角0度~電気角60度および電気角330度~電気角360度が第2オン固定期間T2vである。波形例23では、電気角150度~電気角210度が第2オン固定期間T2wである。
In waveform example 23, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 23, the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees. In waveform example 23, the second fixed ON period T2w is from 150 electrical degrees to 210 electrical degrees.
波形例23では、3相のうちU相において、第1オン固定期間T1uが、第1オン固定期間T1vおよび第1オン固定期間T1wと異なる。詳しくは、波形例23では、第1オン固定期間T1uが90度であるのに対し、第1オン固定期間T1vおよび第1オン固定期間T1wは60度である。すなわち、波形例23では、第1オン固定期間T1uが第1オン固定期間T1vおよび第1オン固定期間T1wよりも長い。したがって、図36Bに示すように、U相の第1半導体スイッチング素子Up(H(ハイサイド))のスイッチング損失がV相およびW相に比べて小さくなっている。
In waveform example 23, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 23, the first fixed ON period T1u is 90 degrees, while the first fixed ON period T1v and the first fixed ON period T1w are 60 degrees. That is, in waveform example 23, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 36B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
波形例23では、第2オン固定期間T2vが、第2オン固定期間T2uおよび第2オン固定期間T2wと異なる。詳しくは、波形例23では、第2オン固定期間T2vが90度であるのに対し、第2オン固定期間T2uは無く、第2オン固定期間T2wは60度である。すなわち、波形例23では、第2オン固定期間T2vが第2オン固定期間T2wよりも長い。したがって、図36Bに示すように、V相の第2半導体スイッチング素子Vn(L(ロウサイド))のスイッチング損失がU相およびW相に比べて小さくなっている。
In waveform example 23, the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in waveform example 23, the second fixed ON period T2v is 90 degrees, whereas the second fixed ON period T2u is absent and the second fixed ON period T2w is 60 degrees. That is, in waveform example 23, the second fixed ON period T2v is longer than the second fixed ON period T2w. Therefore, as shown in FIG. 36B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
以上、図36Aおよび図36Bを参照して説明したように、波形例23においても、波形例1と同様に、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。波形例23では、U相の第1半導体スイッチング素子Upと、V相の第2半導体スイッチング素子Vnとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 36A and 36B, in waveform example 23, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 23, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn.
また、波形例23では、図36Bに示すように、V相の第1半導体スイッチング素子Vpと、W相の第1半導体スイッチング素子Wpと、W相の第2半導体スイッチング素子Wnとの発熱についても同時に抑えることができる。
In waveform example 23, as shown in FIG. 36B, the heat generated by the V-phase first semiconductor switching element Vp, the W-phase first semiconductor switching element Wp, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
図37Aおよび図37Bを参照して、波形例24について説明する。図37Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図37Bは、スイッチング損失を示す図である。
Waveform example 24 will be described with reference to FIGS. 37A and 37B. FIG. 37A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 37B is a diagram showing switching losses.
図37Aに示すように、波形例24は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例24は、電気角60度~電気角150度および電気角180度~電気角330度において、いずれか1相の出力が1に固定される波形である。また、波形例24は、電気角0度~電気角60度、電気角150度~電気角180度および電気角330度~電気角360度において、いずれか1相の出力が0に固定される波形である。波形例24では、電気角60度~電気角150度および電気角180度~電気角330度において、ハイサイドオン適用期間T3である。また、波形例24では、電気角0度~電気角60度、電気角150度~電気角180度および電気角330度~電気角360度において、ロウサイドオン適用期間T4である。
As shown in FIG. 37A, in waveform example 24, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, waveform example 24 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 180 degrees to 330 degrees. In waveform example 24, the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 electrical degrees, 150 to 180 electrical degrees, and 330 to 360 electrical degrees. waveform. In waveform example 24, the high-side-on application period T3 is at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 180 degrees to 330 degrees. Further, in waveform example 24, the low side-on application period T4 is at an electrical angle of 0 to 60 electrical degrees, 150 to 180 electrical degrees, and 330 to 360 electrical degrees.
波形例24では、第1オン固定期間T1は、第1オン固定期間T1uと、第1オン固定期間T1vと、第1オン固定期間T1wとを含む。波形例24では、電気角60度~電気角150度が第1オン固定期間T1uである。波形例24では、電気角180度~電気角270度が第1オン固定期間T1vである。波形例24では、電気角270度~電気角330度が第1オン固定期間T1wである。
In Waveform Example 24, the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w. In waveform example 24, the first ON fixed period T1u is from 60 electrical degrees to 150 electrical degrees. In waveform example 24, the first fixed ON period T1v is from 180 degrees to 270 degrees in electrical angle. In waveform example 24, the first fixed ON period T1w is from 270 electrical degrees to 330 electrical degrees.
波形例24では、第2オン固定期間T2は、第2オン固定期間T2vと、第2オン固定期間T2wとを含む。波形例24では、電気角0度~電気角60度および電気角330度~電気角360度が第2オン固定期間T2vである。波形例24では、電気角150度~電気角180度が第2オン固定期間T2wである。
In waveform example 24, the second fixed ON period T2 includes a second fixed ON period T2v and a second fixed ON period T2w. In waveform example 24, the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees. In waveform example 24, the second fixed ON period T2w is between 150 electrical degrees and 180 electrical degrees.
波形例24では、3相のうちU相において、第1オン固定期間T1uが、第1オン固定期間T1wと異なる。詳しくは、波形例24では、第1オン固定期間T1uが90度であるのに対し、第1オン固定期間T1wは60度である。すなわち、波形例24では、第1オン固定期間T1uが第1オン固定期間T1wよりも長い。なお、第1オン固定期間T1uと、第1オン固定期間T1vとは同じである。したがって、図37Bに示すように、U相の第1半導体スイッチング素子Up(H(ハイサイド))のスイッチング損失がW相に比べて小さくなっている。
In waveform example 24, the first fixed ON period T1u differs from the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 24, the first fixed ON period T1u is 90 degrees, while the first fixed ON period T1w is 60 degrees. That is, in waveform example 24, the first fixed ON period T1u is longer than the first fixed ON period T1w. Note that the first fixed ON period T1u and the first fixed ON period T1v are the same. Therefore, as shown in FIG. 37B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than that of the W-phase.
波形例24では、第2オン固定期間T2vが、第2オン固定期間T2uおよび第2オン固定期間T2wと異なる。詳しくは、波形例24では、第2オン固定期間T2vが90度であるのに対し、第2オン固定期間T2wは30度である。すなわち、波形例24では、第2オン固定期間T2vが第2オン固定期間T2wよりも長い。したがって、図37Bに示すように、V相の第2半導体スイッチング素子Vn(L(ロウサイド))のスイッチング損失がW相に比べて小さくなっている。
In waveform example 24, the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in waveform example 24, the second fixed ON period T2v is 90 degrees, while the second fixed ON period T2w is 30 degrees. That is, in waveform example 24, the second fixed ON period T2v is longer than the second fixed ON period T2w. Therefore, as shown in FIG. 37B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than that of the W-phase.
以上、図37Aおよび図37Bを参照して説明したように、波形例24においても、波形例1と同様に、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。波形例24では、U相の第1半導体スイッチング素子Upと、V相の第2半導体スイッチング素子Vnとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 37A and 37B, in waveform example 24, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In the waveform example 24, the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
また、波形例24では、図37Bに示すように、V相の第1半導体スイッチング素子Vpと、W相の第1半導体スイッチング素子Wpと、W相の第2半導体スイッチング素子Wnとの発熱についても同時に抑えることができる。
In waveform example 24, as shown in FIG. 37B, the heat generated by the V-phase first semiconductor switching element Vp, the W-phase first semiconductor switching element Wp, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
図38Aおよび図38Bを参照して、波形例25について説明する。図38Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図38Bは、スイッチング損失を示す図である。
A waveform example 25 will be described with reference to FIGS. 38A and 38B. FIG. 38A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 38B is a diagram showing switching losses.
図38Aに示すように、波形例25は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例25は、電気角60度~電気角150度、電気角210度~電気角240度および電気角270度~電気角330度において、いずれか1相の出力が1に固定される波形である。また、波形例25は、電気角0度~電気角60度、電気角150度~電気角210度、電気角240度~電気角270度および電気角330度~電気角360度において、いずれか1相の出力が0に固定される波形である。波形例25では、電気角60度~電気角150度、電気角210度~電気角240度および電気角270度~電気角330度において、ハイサイドオン適用期間T3である。また、波形例25では、電気角0度~電気角60度、電気角150度~電気角210度、電気角240度~電気角270度および電気角330度~電気角360度において、ロウサイドオン適用期間T4である。
As shown in FIG. 38A, in waveform example 25, the output voltage of any one phase is fixed to 1 in a certain electrical angle section, and the output voltage of any one phase is fixed to 1 in another electrical angle section, depending on the electrical angle. is fixed to 0. Specifically, in waveform example 25, the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 150 degrees, from 210 degrees to 240 degrees, and from 270 degrees to 330 degrees. waveform. In addition, waveform example 25 is any of the electrical angle of 0 to 60 electrical degrees, 150 to 210 electrical degrees, 240 to 270 electrical degrees, and 330 to 360 electrical degrees. It is a waveform in which the output of one phase is fixed to 0. In waveform example 25, the high-side-on application period T3 occurs at an electrical angle of 60 to 150 electrical degrees, 210 to 240 electrical degrees, and 270 to 330 electrical degrees. In addition, in waveform example 25, the low side This is the ON application period T4.
波形例25では、第1オン固定期間T1は、第1オン固定期間T1uと、第1オン固定期間T1vと、第1オン固定期間T1wとを含む。波形例25では、電気角60度~電気角150度が第1オン固定期間T1uである。波形例25では、電気角210度~電気角240度が第1オン固定期間T1vである。波形例25では、電気角270度~電気角330度が第1オン固定期間T1wである。
In waveform example 25, the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w. In waveform example 25, the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees. In waveform example 25, the first fixed ON period T1v is between 210 electrical degrees and 240 electrical degrees. In waveform example 25, the first fixed ON period T1w is from 270 electrical degrees to 330 electrical degrees.
波形例25では、第2オン固定期間T2は、第2オン固定期間T2uと、第2オン固定期間T2vと、第2オン固定期間T2wとを含む。波形例25では、電気角240度~電気角270度が第2オン固定期間T2uである。波形例25では、電気角0度~電気角60度および電気角330度~電気角360度が第2オン固定期間T2vである。波形例25では、電気角150度~電気角210度が第2オン固定期間T2wである。
In waveform example 25, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 25, the second fixed ON period T2u is from 240 electrical degrees to 270 electrical degrees. In waveform example 25, the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees. In waveform example 25, the second fixed ON period T2w is from 150 electrical degrees to 210 electrical degrees.
波形例25では、3相のうちU相において、第1オン固定期間T1uが、第1オン固定期間T1vおよび第1オン固定期間T1wと異なる。詳しくは、波形例25では、第1オン固定期間T1uが90度であるのに対し、第1オン固定期間T1vは30度であり、第1オン固定期間T1wは60度である。すなわち、波形例25では、第1オン固定期間T1uが第1オン固定期間T1vおよび第1オン固定期間T1wよりも長い。したがって、図38Bに示すように、U相の第1半導体スイッチング素子Up(H(ハイサイド))のスイッチング損失がV相およびW相に比べて小さくなっている。
In waveform example 25, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 25, the first fixed ON period T1u is 90 degrees, the first fixed ON period T1v is 30 degrees, and the first fixed ON period T1w is 60 degrees. That is, in waveform example 25, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 38B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
波形例25では、第2オン固定期間T2vが、第2オン固定期間T2uおよび第2オン固定期間T2wと異なる。詳しくは、波形例25では、第2オン固定期間T2vが90度であるのに対し、第2オン固定期間T2uは30度であり、第2オン固定期間T2wは60度である。すなわち、波形例25では、第2オン固定期間T2vが第2オン固定期間T2uおよび第2オン固定期間T2wよりも長い。したがって、図38Bに示すように、V相の第2半導体スイッチング素子Vn(L(ロウサイド))のスイッチング損失がU相およびW相に比べて小さくなっている。
In waveform example 25, the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in waveform example 25, the second fixed ON period T2v is 90 degrees, the second fixed ON period T2u is 30 degrees, and the second fixed ON period T2w is 60 degrees. That is, in waveform example 25, the second fixed ON period T2v is longer than the second fixed ON period T2u and the second fixed ON period T2w. Therefore, as shown in FIG. 38B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
以上、図38Aおよび図38Bを参照して説明したように、波形例25においても、波形例1と同様に、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。波形例25では、U相の第1半導体スイッチング素子Upと、V相の第2半導体スイッチング素子Vnとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 38A and 38B , in waveform example 25, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In the waveform example 25, the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
また、波形例25では、図38Bに示すように、U相の第2半導体スイッチング素子Unと、V相の第1半導体スイッチング素子Vpと、W相の第1半導体スイッチング素子Wpと、W相の第2半導体スイッチング素子Wnとの発熱についても同時に抑えることができる。
In waveform example 25, as shown in FIG. 38B, the U-phase second semiconductor switching element Un, the V-phase first semiconductor switching element Vp, the W-phase first semiconductor switching element Wp, and the W-phase semiconductor switching element Wp Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
図39Aおよび図39Bを参照して、波形例26について説明する。図39Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図39Bは、スイッチング損失を示す図である。
A waveform example 26 will be described with reference to FIGS. 39A and 39B. FIG. 39A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 39B is a diagram showing switching losses.
図39Aに示すように、波形例26は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例26は、電気角60度~電気角150度、電気角195度~電気角240度および電気角285度~電気角330度において、いずれか1相の出力が1に固定される波形である。また、波形例26は、電気角0度~電気角60度、電気角150度~電気角195度、電気角240度~電気角285度および電気角330度~電気角360度において、いずれか1相の出力が0に固定される波形である。波形例26では、電気角60度~電気角150度、電気角195度~電気角240度および電気角285度~電気角330度において、ハイサイドオン適用期間T3である。また、波形例26では、電気角0度~電気角60度、電気角150度~電気角195度、電気角240度~電気角285度および電気角330度~電気角360度において、ロウサイドオン適用期間T4である。
As shown in FIG. 39A, in waveform example 26, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, in waveform example 26, the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 150 degrees, from 195 degrees to 240 degrees, and from 285 degrees to 330 degrees. waveform. In addition, waveform example 26 is any of the electrical angles of 0 to 60 electrical degrees, 150 to 195 electrical degrees, 240 to 285 electrical degrees, and 330 to 360 electrical degrees. It is a waveform in which the output of one phase is fixed to 0. In waveform example 26, the high-side-on application period T3 is at an electrical angle of 60 to 150 electrical degrees, 195 to 240 electrical degrees, and 285 to 330 electrical degrees. Further, in waveform example 26, the low side This is the ON application period T4.
波形例26では、第1オン固定期間T1は、第1オン固定期間T1uと、第1オン固定期間T1vと、第1オン固定期間T1wとを含む。波形例26では、電気角60度~電気角150度が第1オン固定期間T1uである。波形例26では、電気角195度~電気角240度が第1オン固定期間T1vである。波形例26では、電気角285度~電気角330度が第1オン固定期間T1wである。
In waveform example 26, the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w. In waveform example 26, the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees. In waveform example 26, the first fixed ON period T1v is between an electrical angle of 195 degrees and an electrical angle of 240 degrees. In waveform example 26, the first fixed ON period T1w is between an electrical angle of 285 degrees and an electrical angle of 330 degrees.
波形例26では、第2オン固定期間T2は、第2オン固定期間T2uと、第2オン固定期間T2vと、第2オン固定期間T2wとを含む。波形例26では、電気角240度~電気角285度が第2オン固定期間T2uである。波形例26では、電気角0度~電気角60度および電気角330度~電気角360度が第2オン固定期間T2vである。波形例26では、電気角150度~電気角195度が第2オン固定期間T2wである。
In waveform example 26, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 26, the second fixed ON period T2u is from 240 electrical degrees to 285 electrical degrees. In waveform example 26, the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees. In waveform example 26, the second fixed ON period T2w is from 150 electrical degrees to 195 electrical degrees.
波形例26では、3相のうちU相において、第1オン固定期間T1uが、第1オン固定期間T1vおよび第1オン固定期間T1wと異なる。詳しくは、波形例26では、第1オン固定期間T1uが90度であるのに対し、第1オン固定期間T1vおよび第1オン固定期間T1wは45度である。すなわち、波形例26では、第1オン固定期間T1uが第1オン固定期間T1vおよび第1オン固定期間T1wよりも長い。したがって、図39Bに示すように、U相の第1半導体スイッチング素子Up(H(ハイサイド))のスイッチング損失がV相およびW相に比べて小さくなっている。
In waveform example 26, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 26, the first fixed ON period T1u is 90 degrees, while the first fixed ON period T1v and the first fixed ON period T1w are 45 degrees. That is, in waveform example 26, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 39B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
波形例26では、第2オン固定期間T2vが、第2オン固定期間T2uおよび第2オン固定期間T2wと異なる。詳しくは、波形例26では、第2オン固定期間T2vが90度であるのに対し、第2オン固定期間T2uおよび第2オン固定期間T2wは45度である。すなわち、波形例26では、第2オン固定期間T2vが第2オン固定期間T2uおよび第2オン固定期間T2wよりも長い。したがって、図39Bに示すように、V相の第2半導体スイッチング素子Vn(L(ロウサイド))のスイッチング損失がU相およびW相に比べて小さくなっている。
In waveform example 26, the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in waveform example 26, the second fixed ON period T2v is 90 degrees, while the second fixed ON period T2u and the second fixed ON period T2w are 45 degrees. That is, in waveform example 26, the second fixed ON period T2v is longer than the second fixed ON period T2u and the second fixed ON period T2w. Therefore, as shown in FIG. 39B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
以上、図39Aおよび図39Bを参照して説明したように、波形例26においても、波形例1と同様に、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。波形例26では、U相の第1半導体スイッチング素子Upと、V相の第2半導体スイッチング素子Vnとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 39A and 39B, in waveform example 26, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In the waveform example 26, the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
また、波形例26では、図39Bに示すように、U相の第2半導体スイッチング素子Unと、V相の第1半導体スイッチング素子Vpと、W相の第1半導体スイッチング素子Wpと、W相の第2半導体スイッチング素子Wnとの発熱についても同時に抑えることができる。
In waveform example 26, as shown in FIG. 39B, the U-phase second semiconductor switching element Un, the V-phase first semiconductor switching element Vp, the W-phase first semiconductor switching element Wp, and the W-phase Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
図40Aおよび図40Bを参照して、波形例27について説明する。図40Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図40Bは、スイッチング損失を示す図である。
A waveform example 27 will be described with reference to FIGS. 40A and 40B. FIG. 40A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 40B is a diagram showing switching losses.
図40Aに示すように、波形例27は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例27は、電気角60度~電気角150度、電気角180度~電気角240度および電気角300度~電気角330度において、いずれか1相の出力が1に固定される波形である。また、波形例27は、電気角0度~電気角60度、電気角150度~電気角180度、電気角240度~電気角300度および電気角330度~電気角360度において、いずれか1相の出力が0に固定される波形である。波形例27では、電気角60度~電気角150度、電気角180度~電気角240度および電気角300度~電気角330度において、ハイサイドオン適用期間T3である。また、波形例27では、電気角0度~電気角60度、電気角150度~電気角180度、電気角240度~電気角300度および電気角330度~電気角360度において、ロウサイドオン適用期間T4である。
As shown in FIG. 40A, in waveform example 27, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, in waveform example 27, the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 150 degrees, from 180 degrees to 240 degrees, and from 300 degrees to 330 degrees. waveform. Further, waveform example 27 is any of the electrical angle of 0 to 60 electrical degrees, the electrical angle of 150 to 180 electrical degrees, the electrical angle of 240 to 300 electrical degrees, and the electrical angle of 330 to 360 electrical degrees. It is a waveform in which the output of one phase is fixed to 0. In waveform example 27, the high-side-on application period T3 occurs at an electrical angle of 60 to 150 electrical degrees, 180 to 240 electrical degrees, and 300 to 330 electrical degrees. Further, in waveform example 27, the low side This is the ON application period T4.
波形例27では、第1オン固定期間T1は、第1オン固定期間T1uと、第1オン固定期間T1vと、第1オン固定期間T1wとを含む。波形例27では、電気角60度~電気角150度が第1オン固定期間T1uである。波形例27では、電気角180度~電気角240度が第1オン固定期間T1vである。波形例27では、電気角300度~電気角330度が第1オン固定期間T1wである。
In waveform example 27, the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w. In waveform example 27, the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees. In waveform example 27, the first fixed ON period T1v is from 180 electrical degrees to 240 electrical degrees. In waveform example 27, the first fixed ON period T1w is between 300 electrical degrees and 330 electrical degrees.
波形例27では、第2オン固定期間T2は、第2オン固定期間T2uと、第2オン固定期間T2vと、第2オン固定期間T2wとを含む。波形例27では、電気角240度~電気角300度が第2オン固定期間T2uである。波形例27では、電気角0度~電気角60度および電気角330度~電気角360度が第2オン固定期間T2vである。波形例27では、電気角150度~電気角180度が第2オン固定期間T2wである。
In waveform example 27, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 27, the second fixed ON period T2u is from 240 electrical degrees to 300 electrical degrees. In waveform example 27, the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees. In waveform example 27, the second fixed ON period T2w is between 150 electrical degrees and 180 electrical degrees.
波形例27では、3相のうちU相において、第1オン固定期間T1uが、第1オン固定期間T1vおよび第1オン固定期間T1wと異なる。詳しくは、波形例27では、第1オン固定期間T1uが90度であるのに対し、第1オン固定期間T1vは60度であり、第1オン固定期間T1wは30度である。すなわち、波形例27では、第1オン固定期間T1uが第1オン固定期間T1vおよび第1オン固定期間T1wよりも長い。したがって、図40Bに示すように、U相の第1半導体スイッチング素子Up(H(ハイサイド))のスイッチング損失がV相およびW相に比べて小さくなっている。
In waveform example 27, in the U phase among the three phases, the first fixed ON period T1u is different from the first fixed ON period T1v and the first fixed ON period T1w. Specifically, in waveform example 27, the first fixed ON period T1u is 90 degrees, the first fixed ON period T1v is 60 degrees, and the first fixed ON period T1w is 30 degrees. That is, in waveform example 27, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 40B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
波形例27では、第2オン固定期間T2vが、第2オン固定期間T2uおよび第2オン固定期間T2wと異なる。詳しくは、波形例27では、第2オン固定期間T2vが90度であるのに対し、第2オン固定期間T2uは60度であり、第2オン固定期間T2wは30度である。すなわち、波形例27では、第2オン固定期間T2vが第2オン固定期間T2uおよび第2オン固定期間T2wよりも長い。したがって、図40Bに示すように、V相の第2半導体スイッチング素子Vn(L(ロウサイド))のスイッチング損失がU相およびW相に比べて小さくなっている。
In waveform example 27, the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in waveform example 27, the second fixed ON period T2v is 90 degrees, the second fixed ON period T2u is 60 degrees, and the second fixed ON period T2w is 30 degrees. That is, in waveform example 27, the second fixed ON period T2v is longer than the second fixed ON period T2u and the second fixed ON period T2w. Therefore, as shown in FIG. 40B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
以上、図40Aおよび図40Bを参照して説明したように、波形例27においても、波形例1と同様に、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。波形例27では、U相の第1半導体スイッチング素子Upと、V相の第2半導体スイッチング素子Vnとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 40A and 40B, in waveform example 27, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 27, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn.
また、波形例27では、図40Bに示すように、U相の第2半導体スイッチング素子Unと、V相の第1半導体スイッチング素子Vpと、W相の第1半導体スイッチング素子Wpと、W相の第2半導体スイッチング素子Wnとの発熱についても同時に抑えることができる。
In waveform example 27, as shown in FIG. 40B, the U-phase second semiconductor switching element Un, the V-phase first semiconductor switching element Vp, the W-phase first semiconductor switching element Wp, and the W-phase Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
図41Aおよび図41Bを参照して、波形例28について説明する。図41Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図41Bは、スイッチング損失を示す図である。
A waveform example 28 will be described with reference to FIGS. 41A and 41B. FIG. 41A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 41B is a diagram showing switching losses.
図41Aに示すように、波形例28は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例28は、電気角60度~電気角150度および電気角210度~電気角270度において、いずれか1相の出力が1に固定される波形である。また、波形例28は、電気角0度~電気角60度、電気角150度~電気角210度および電気角270度~電気角360度において、いずれか1相の出力が0に固定される波形である。波形例28では、電気角60度~電気角150度および電気角210度~電気角270度において、ハイサイドオン適用期間T3である。また、波形例28では、電気角0度~電気角60度、電気角150度~電気角210度および電気角270度~電気角360度において、ロウサイドオン適用期間T4である。
As shown in FIG. 41A, in waveform example 28, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. More specifically, waveform example 28 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 210 degrees to 270 degrees. In waveform example 28, the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 electrical degrees, 150 to 210 electrical degrees, and 270 to 360 electrical degrees. waveform. In waveform example 28, the high side-on application period T3 occurs at an electrical angle of 60 degrees to 150 degrees and at an electrical angle of 210 degrees to 270 degrees. Further, in waveform example 28, the low side-on application period T4 is at an electrical angle of 0 to 60 electrical degrees, 150 to 210 electrical degrees, and 270 to 360 electrical degrees.
波形例28では、第1オン固定期間T1は、第1オン固定期間T1uと、第1オン固定期間T1vとを含む。波形例28では、電気角60度~電気角150度が第1オン固定期間T1uである。波形例28では、電気角210度~電気角270度が第1オン固定期間T1vである。
In waveform example 28, the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v. In waveform example 28, the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees. In waveform example 28, the first fixed ON period T1v is between 210 electrical degrees and 270 electrical degrees.
波形例28では、第2オン固定期間T2は、第2オン固定期間T2uと、第2オン固定期間T2vと、第2オン固定期間T2wとを含む。波形例28では、電気角270度~電気角330度が第2オン固定期間T2uである。波形例28では、電気角0度~電気角60度および電気角330度~電気角360度が第2オン固定期間T2vである。波形例28では、電気角150度~電気角210度が第2オン固定期間T2wである。
In Waveform Example 28, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 28, the second fixed ON period T2u is from 270 electrical degrees to 330 electrical degrees. In waveform example 28, the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees. In waveform example 28, the second fixed ON period T2w is from 150 electrical degrees to 210 electrical degrees.
波形例28では、3相のうちU相において、第1オン固定期間T1uが、第1オン固定期間T1vおよび第1オン固定期間T1wと異なる。詳しくは、波形例28では、第1オン固定期間T1uが90度であるのに対し、第1オン固定期間T1vは60度であり、第1オン固定期間T1wは無い。すなわち、波形例28では、第1オン固定期間T1uが第1オン固定期間T1vおよび第1オン固定期間T1wよりも長い。したがって、図41Bに示すように、U相の第1半導体スイッチング素子Up(H(ハイサイド))のスイッチング損失がV相およびW相に比べて小さくなっている。
In waveform example 28, in the U phase among the three phases, the first fixed ON period T1u is different from the first fixed ON period T1v and the first fixed ON period T1w. Specifically, in waveform example 28, the first fixed ON period T1u is 90 degrees, the first fixed ON period T1v is 60 degrees, and there is no first fixed ON period T1w. That is, in waveform example 28, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 41B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
波形例28では、第2オン固定期間T2vが、第2オン固定期間T2uおよび第2オン固定期間T2wと異なる。詳しくは、波形例28では、第2オン固定期間T2vが90度であるのに対し、第2オン固定期間T2uおよび第2オン固定期間T2wは60度である。すなわち、波形例28では、第2オン固定期間T2vが第2オン固定期間T2uおよび第2オン固定期間T2wよりも長い。したがって、図41Bに示すように、V相の第2半導体スイッチング素子Vn(L(ロウサイド))のスイッチング損失がU相およびW相に比べて小さくなっている。
In waveform example 28, the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in waveform example 28, the second fixed ON period T2v is 90 degrees, while the second fixed ON period T2u and the second fixed ON period T2w are 60 degrees. That is, in waveform example 28, the second fixed ON period T2v is longer than the second fixed ON period T2u and the second fixed ON period T2w. Therefore, as shown in FIG. 41B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
以上、図41Aおよび図41Bを参照して説明したように、波形例28においても、波形例1と同様に、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。波形例28では、U相の第1半導体スイッチング素子Upと、V相の第2半導体スイッチング素子Vnとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 41A and 41B , in waveform example 28, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In the waveform example 28, the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
また、波形例28では、図41Bに示すように、U相の第2半導体スイッチング素子Unと、V相の第1半導体スイッチング素子Vpと、W相の第2半導体スイッチング素子Wnとの発熱についても同時に抑えることができる。
In waveform example 28, as shown in FIG. 41B, the heat generated by the U-phase second semiconductor switching element Un, the V-phase first semiconductor switching element Vp, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
図42Aおよび図42Bを参照して、波形例29について説明する。図42Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図42Bは、スイッチング損失を示す図である。
A waveform example 29 will be described with reference to FIGS. 42A and 42B. FIG. 42A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 42B is a diagram showing switching losses.
図42Aに示すように、波形例29は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例29は、電気角60度~電気角210度および電気角270度~電気角330度において、いずれか1相の出力が1に固定される波形である。また、波形例29は、電気角0度~電気角60度、電気角210度~電気角270度および電気角330度~電気角360度において、いずれか1相の出力が0に固定される波形である。波形例29では、電気角60度~電気角210度および電気角270度~電気角330度において、ハイサイドオン適用期間T3である。また、波形例29では、電気角0度~電気角60度、電気角210度~電気角270度および電気角330度~電気角360度において、ロウサイドオン適用期間T4である。
As shown in FIG. 42A, in waveform example 29, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. More specifically, waveform example 29 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 210 degrees and at an electrical angle of 270 degrees to 330 degrees. In waveform example 29, the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 electrical degrees, 210 to 270 electrical degrees, and 330 to 360 electrical degrees. waveform. In waveform example 29, the high-side-on application period T3 occurs at an electrical angle of 60 degrees to 210 degrees and at an electrical angle of 270 degrees to 330 degrees. Further, in waveform example 29, the low side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees, 210 to 270 electrical degrees, and 330 to 360 electrical degrees.
波形例29では、第1オン固定期間T1は、第1オン固定期間T1uと、第1オン固定期間T1vと、第1オン固定期間T1wとを含む。波形例29では、電気角60度~電気角150度が第1オン固定期間T1uである。波形例29では、電気角150度~電気角210度が第1オン固定期間T1vである。波形例29では、電気角270度~電気角330度が第1オン固定期間T1wである。
In Waveform Example 29, the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w. In waveform example 29, the first fixed ON period T1u is from 60 electrical degrees to 150 electrical degrees. In waveform example 29, the first fixed ON period T1v is between 150 electrical degrees and 210 electrical degrees. In waveform example 29, the first fixed ON period T1w is from 270 electrical degrees to 330 electrical degrees.
波形例29では、第2オン固定期間T2は、第2オン固定期間T2uと、第2オン固定期間T2vとを含む。波形例29では、電気角210度~電気角270度が第2オン固定期間T2uである。波形例29では、電気角0度~電気角60度および電気角330度~電気角360度が第2オン固定期間T2vである。
In waveform example 29, the second fixed ON period T2 includes a second fixed ON period T2u and a second fixed ON period T2v. In waveform example 29, the second fixed ON period T2u is from 210 electrical degrees to 270 electrical degrees. In waveform example 29, the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees.
波形例29では、3相のうちU相において、第1オン固定期間T1uが、第1オン固定期間T1vおよび第1オン固定期間T1wと異なる。詳しくは、波形例29では、第1オン固定期間T1uが90度であるのに対し、第1オン固定期間T1vおよび第1オン固定期間T1wは60度である。すなわち、波形例29では、第1オン固定期間T1uが第1オン固定期間T1vおよび第1オン固定期間T1wよりも長い。したがって、図42Bに示すように、U相の第1半導体スイッチング素子Up(H(ハイサイド))のスイッチング損失がV相およびW相に比べて小さくなっている。
In waveform example 29, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 29, the first fixed ON period T1u is 90 degrees, while the first fixed ON period T1v and the first fixed ON period T1w are 60 degrees. That is, in waveform example 29, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 42B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
波形例29では、第2オン固定期間T2vが、第2オン固定期間T2uおよび第2オン固定期間T2wと異なる。詳しくは、波形例29では、第2オン固定期間T2vが90度であるのに対し、第2オン固定期間T2uは60度であり、第2オン固定期間T2wは無い。すなわち、波形例29では、第2オン固定期間T2vが第2オン固定期間T2uおよび第2オン固定期間T2wよりも長い。したがって、図42Bに示すように、V相の第2半導体スイッチング素子Vn(L(ロウサイド))のスイッチング損失がU相およびW相に比べて小さくなっている。
In waveform example 29, the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in waveform example 29, the second fixed ON period T2v is 90 degrees, the second fixed ON period T2u is 60 degrees, and there is no second fixed ON period T2w. That is, in waveform example 29, the second fixed ON period T2v is longer than the second fixed ON period T2u and the second fixed ON period T2w. Therefore, as shown in FIG. 42B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
以上、図42Aおよび図42Bを参照して説明したように、波形例29においても、波形例1と同様に、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。波形例29では、U相の第1半導体スイッチング素子Upと、V相の第2半導体スイッチング素子Vnとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 42A and 42B , in waveform example 29, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In the waveform example 29, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the V-phase second semiconductor switching element Vn.
また、波形例29では、図42Bに示すように、U相の第2半導体スイッチング素子Unと、V相の第1半導体スイッチング素子Vpと、W相の第1半導体スイッチング素子Wpとの発熱についても同時に抑えることができる。
In waveform example 29, as shown in FIG. 42B, the heat generated by the U-phase second semiconductor switching element Un, the V-phase first semiconductor switching element Vp, and the W-phase first semiconductor switching element Wp can be suppressed at the same time.
以上、図3A、図3B、図5A~図15Bおよび図26A~図42Bを参照して説明した波形例1~波形例29では、他の相の第1オン固定期間よりも第1オン固定期間が長い相の第1オン固定期間および他の相の第2オン固定期間よりも第2オン固定期間が長い相の第2オン固定期間がともに、π/nよりも長く、2π/n以下である。好ましくは、1.5π/n~2π/nである。これによって、効果的な発熱の抑制ができる。なお、下限はπ/nから僅かにずれていてもよい。また、上限は2π/nから僅かにずれていてもよい。例えば、波形例1では、第1オン固定期間T1uが、2π/n(=120度)であり、第2オン固定期間T2uが、2π/n(=120度)である。つまり、波形例1~波形例29では、他の相の第1オン固定期間よりも第1オン固定期間が長い相の第1オン固定期間および他の相の第2オン固定期間よりも第2オン固定期間が長い相の第2オン固定期間がともに、2π/nである。また、他の相の第1オン固定期間よりも第1オン固定期間が長い相の第1オン固定期間と他の相の第2オン固定期間よりも第2オン固定期間が長い相の第2オン固定期間とが互いに連続しない。したがって、冷却水路の問題などで特定の相の温度が問題となる場合、その相の発熱を抑制できるので、インバータの信頼性が高まる。あるいは、ストールが発生してある相の第1半導体スイッチング素子と別の相の第2半導体スイッチング素子に連続的に電流が流れ温度上昇した場合、ストールを脱して動作を開始する際にこの動作を行うことで、ストール下で温度上昇した半導体スイッチング素子の発熱を抑え、速やかに温度を下げることができるので、インバータの信頼性が高まる。
In the waveform examples 1 to 29 described above with reference to FIGS. 3A, 3B, 5A to 15B, and 26A to 42B, the first fixed ON period is longer than the first fixed ON period of the other phases. the first fixed ON period of the phase having a longer ON period and the second fixed ON period of the phase having a longer second fixed ON period than the second fixed ON period of the other phase are both longer than π/n and 2π/n or less be. Preferably, it is 1.5π/n to 2π/n. As a result, heat generation can be effectively suppressed. Note that the lower limit may be slightly deviated from π/n. Also, the upper limit may deviate slightly from 2π/n. For example, in waveform example 1, the first fixed ON period T1u is 2π/n (=120 degrees), and the second fixed ON period T2u is 2π/n (=120 degrees). That is, in waveform examples 1 to 29, the first fixed ON period of the phase is longer than the first fixed ON period of the other phase, and the second fixed period is longer than the second fixed ON period of the other phase. The second fixed ON period of the phase with the longer ON fixed period is both 2π/n. Also, the first fixed ON period of the phase whose first fixed ON period is longer than the first fixed ON period of the other phase and the second fixed ON period of the phase whose second fixed ON period is longer than the second fixed ON period of the other phase ON fixed period is not continuous with each other. Therefore, when the temperature of a specific phase becomes a problem due to a problem in the cooling water passage or the like, the heat generation of that phase can be suppressed, thereby increasing the reliability of the inverter. Alternatively, when a stall occurs and current continuously flows through the first semiconductor switching element of a certain phase and the second semiconductor switching element of another phase and the temperature rises, this operation is performed when exiting the stall and starting operation. By doing so, it is possible to suppress the heat generation of the semiconductor switching elements whose temperature has risen under the stall condition, and to quickly lower the temperature, thereby increasing the reliability of the inverter.
図26A~図42Bを参照して説明した波形例13~波形例29では、n相のうち2相において、一方の相の第1オン固定期間と他方の相の第2オン固定期間とが互いに連続している。例えば、波形例13では、3相のうちU相およびV相において、U相の第1オン固定期間T1uとV相の第2オン固定期間T2vとが互いに連続している。一方の相の第1オン固定期間と他方の相の第2オン固定期間との合計が3π/nである。例えば、波形例13では、U相の第1オン固定期間T1uが90度であり、V相の第2オン固定期間T2vが90度であるため、第1オン固定期間T1uとV相の第2オン固定期間T2vとの合計は、180度(3π/n)となる。なお、合計は3π/nからわずかにずれていてもよい。また、一方の相の第1オン固定期間および他方の相の第2オン固定期間とはそれぞれ3π/(2n)である。例えば、波形例13では、U相の第1オン固定期間T1uおよびV相の第2オン固定期間T2vは90度(3π/(2n))である。したがって、波形例13~波形例29では、ストールが発生してある相の第1半導体スイッチング素子と別の相の第2半導体スイッチング素子に連続的に電流が流れ温度上昇した場合、ストールを脱して動作を開始する際にこの動作を行うことで、ストール下で温度上昇した半導体スイッングチ素子の発熱を抑え、速やかに温度を下げることができるので、インバータの信頼性が高まる。
In waveform examples 13 to 29 described with reference to FIGS. 26A to 42B, in two of the n phases, the first fixed ON period of one phase and the second fixed ON period of the other phase are mutually different. Contiguous. For example, in waveform example 13, in the U-phase and the V-phase among the three phases, the U-phase first fixed ON period T1u and the V-phase second fixed ON period T2v are continuous with each other. The sum of the first fixed ON period of one phase and the second fixed ON period of the other phase is 3π/n. For example, in waveform example 13, the first fixed ON period T1u of the U phase is 90 degrees, and the second fixed ON period T2v of the V phase is 90 degrees. The sum with the on-fixed period T2v is 180 degrees (3π/n). Note that the total may deviate slightly from 3π/n. Also, the first fixed ON period of one phase and the second fixed ON period of the other phase are each 3π/(2n). For example, in waveform example 13, the U-phase first fixed ON period T1u and the V-phase second fixed ON period T2v are 90 degrees (3π/(2n)). Therefore, in waveform examples 13 to 29, when a current continuously flows through the first semiconductor switching element of a phase in which a stall occurs and the second semiconductor switching element of another phase and the temperature rises, the stall escapes. By performing this operation when starting the operation, heat generation of the semiconductor switching element whose temperature has risen under the stall can be suppressed, and the temperature can be quickly lowered, so that the reliability of the inverter is improved.
図43を参照して、U相の固定期間およびV相の固定期間を変化させた場合のスイッチング損失について説明する。図43は、スイッチング損失を示す図である。
The switching loss when the U-phase fixed period and the V-phase fixed period are changed will be described with reference to FIG. FIG. 43 is a diagram showing switching loss.
図43に示すように、電気角0度~電気角60度および電気角330度~電気角360度において、第2オン固定期間を適用し、電気角60度~電気角150度において、第1オン固定期間を適用した場合、第1半導体スイッチング素子Up(UH)のスイッチング損失は0.32となる。また、第2半導体スイッチング素子Vn(VL)のスイッチング損失は0.32となる。このときハイサイド側の固定期間は、90度である。
As shown in FIG. 43, the second fixed ON period is applied at an electrical angle of 0 to 60 electrical degrees and from 330 to 360 electrical degrees, and the first fixed period is applied at an electrical angle of 60 to 150 electrical degrees. When the ON fixed period is applied, the switching loss of the first semiconductor switching element Up (UH) is 0.32. Also, the switching loss of the second semiconductor switching element Vn(VL) is 0.32. At this time, the fixed period on the high side is 90 degrees.
電気角0度~電気角70度および電気角330度~電気角360度において、第2オン固定期間を適用し、電気角70度~電気角150度において、第1オン固定期間を適用した場合、第1半導体スイッチング素子Up(UH)のスイッチング損失は0.39となる。また、第2半導体スイッチング素子Vn(VL)のスイッチング損失は0.25となる。このときハイサイド側の固定期間は、80度である。
When the second fixed ON period is applied at an electrical angle of 0 to 70 electrical degrees and from 330 to 360 electrical degrees, and the first fixed ON period is applied at an electrical angle of 70 to 150 electrical degrees. , the switching loss of the first semiconductor switching element Up(UH) is 0.39. Also, the switching loss of the second semiconductor switching element Vn(VL) is 0.25. At this time, the fixed period on the high side is 80 degrees.
電気角0度~電気角80度および電気角330度~電気角360度において、第2オン固定期間を適用し、電気角80度~電気角150度において、第1オン固定期間を適用した場合、第1半導体スイッチング素子Up(UH)のスイッチング損失は0.47となる。また、第2半導体スイッチング素子Vn(VL)のスイッチング損失は0.18となる。このときハイサイド側の固定期間は、70度である。
When the second fixed ON period is applied at an electrical angle of 0 to 80 electrical degrees and from 330 to 360 electrical degrees, and the first fixed ON period is applied at an electrical angle of 80 to 150 electrical degrees. , the switching loss of the first semiconductor switching element Up (UH) is 0.47. Also, the switching loss of the second semiconductor switching element Vn(VL) is 0.18. At this time, the fixed period on the high side is 70 degrees.
電気角0度~電気角90度および電気角330度~電気角360度において、第2オン固定期間を適用し、電気角90度~電気角150度において、第1オン固定期間を適用した場合、第1半導体スイッチング素子Up(UH)のスイッチング損失は0.56となる。また、第2半導体スイッチング素子Vn(VL)のスイッチング損失は0.13となる。このときハイサイド側の固定期間は、60度である。
When the second fixed ON period is applied at an electrical angle of 0 to 90 electrical degrees and from 330 to 360 electrical degrees, and the first fixed ON period is applied at an electrical angle of 90 to 150 electrical degrees. , the switching loss of the first semiconductor switching element Up (UH) is 0.56. Also, the switching loss of the second semiconductor switching element Vn(VL) is 0.13. At this time, the fixed period on the high side is 60 degrees.
以上、図43を参照して説明したように、第1オン固定期間T1uおよび第2オン固定期間T2uは、共に、π/3(60度)よりも長く、2π/3(120度)以下であることが好ましい。より好ましくは、7π/18(70度)よりも長く、2π/3(120度)以下であることが好ましい。
As described above with reference to FIG. 43, both the first fixed ON period T1u and the second fixed ON period T2u are longer than π/3 (60 degrees) and 2π/3 (120 degrees) or less. Preferably. More preferably, it is longer than 7π/18 (70 degrees) and 2π/3 (120 degrees) or less.
次に、図44を参照して、UH_VL保護波形の切り替えについてさらに説明する。図44は、UH_VL保護波形の切り替えを説明するための図である。
Next, switching of the UH_VL protection waveform will be further described with reference to FIG. FIG. 44 is a diagram for explaining switching of the UH_VL protection waveform.
図44において、出力電圧の波形およびスイッチング損失は、左から順に、(n)波形例26(図39Aおよび図39B)、(o)波形例27(図40Aおよび図40B)、(d)波形例16(図29Aおよび図29B)に相当する。
In FIG. 44, the waveform of the output voltage and the switching loss are, from the left, (n) waveform example 26 (FIGS. 39A and 39B), (o) waveform example 27 (FIGS. 40A and 40B), (d) waveform example 16 (FIGS. 29A and 29B).
左の図に示す(n)波形例26は、第1オン固定期間T1v、第1オン固定期間T1w、第2オン固定期間T2uおよび第2オン固定期間T2wを均等にした波形例である。つまり、第1オン固定期間T1u、第2オン固定期間T2v以外を均等にした波形例である。
(n) Waveform example 26 shown in the left diagram is a waveform example in which the first fixed ON period T1v, the first fixed ON period T1w, the second fixed ON period T2u, and the second fixed ON period T2w are made equal. In other words, this is an example of waveforms in which periods other than the first fixed ON period T1u and the second fixed ON period T2v are made uniform.
中央の図に示す(o)波形例27は、第1オン固定期間T1vおよび第2オン固定期間T2uを延長した波形例である。つまり、U相およびV相を重視した波形例である。
(o) Waveform example 27 shown in the middle diagram is a waveform example in which the first fixed ON period T1v and the second fixed ON period T2u are extended. In other words, this is an example of waveforms in which the U-phase and V-phase are emphasized.
右の図に示す(d)波形例16は、第1オン固定期間T1vおよび第2オン固定期間T2uを(o)波形例27よりさらに延長した波形例である。つまり、U相およびV相を重視した波形例である。
(d) Waveform example 16 shown in the right figure is a waveform example in which the first fixed ON period T1v and the second fixed ON period T2u are further extended from (o) Waveform example 27. In other words, this is an example of waveforms in which the U-phase and V-phase are emphasized.
右の図に移行するにつれて、第1オン固定期間T1vおよび第2オン固定期間T2uは長くなる。したがって、右の図に移行するにつれて、V相の第1半導体スイッチング素子Vp(ハイサイド)およびU相の第2半導体スイッチング素子Un(ロウサイド)のスイッチング損失が減少する。
The first fixed ON period T1v and the second fixed ON period T2u become longer as the diagram shifts to the right. Therefore, the switching loss of the V-phase first semiconductor switching element Vp (high side) and the U-phase second semiconductor switching element Un (low side) decreases as the diagram shifts to the right.
次に、図45を参照して、UH_VL保護波形の切り替えについてさらに説明する。図45は、UH_VL保護波形の切り替えを説明するための図である。
Next, switching of the UH_VL protection waveform will be further described with reference to FIG. FIG. 45 is a diagram for explaining switching of the UH_VL protection waveform.
図45において、出力電圧の波形およびスイッチング損失は、左から順に、(n)波形例26(図39Aおよび図39B)、(m)波形例25(図38Aおよび図38B)に相当する。
In FIG. 45, the output voltage waveform and switching loss correspond to (n) waveform example 26 (FIGS. 39A and 39B) and (m) waveform example 25 (FIGS. 38A and 38B) in order from the left.
左の図に示す(n)波形例26は、第1オン固定期間T1v、第1オン固定期間T1w、第2オン固定期間T2uおよび第2オン固定期間T2wを均等にした波形例である。つまり、第1オン固定期間T1u、第2オン固定期間T2v以外を均等にした波形例である。
(n) Waveform example 26 shown in the left diagram is a waveform example in which the first fixed ON period T1v, the first fixed ON period T1w, the second fixed ON period T2u, and the second fixed ON period T2w are made equal. In other words, this is an example of waveforms in which periods other than the first fixed ON period T1u and the second fixed ON period T2v are made uniform.
右の図に示す(m)波形例25は、第1オン固定期間T1wおよび第2オン固定期間T2wを延長した波形例である。つまり、W相を重視した波形例である。
(m) Waveform example 25 shown in the right figure is a waveform example in which the first fixed ON period T1w and the second fixed ON period T2w are extended. That is, it is an example of a waveform in which the W phase is emphasized.
右の図に移行するにつれて、第1オン固定期間T1wおよび第2オン固定期間T2wは長くなる。したがって、右の図に移行するにつれて、W相の第1半導体スイッチング素子Wp(ハイサイド)およびW相の第2半導体スイッチング素子Wn(ロウサイド)のスイッチング損失が減少する。
The first fixed ON period T1w and the second fixed ON period T2w become longer as the diagram shifts to the right. Therefore, the switching loss of the W-phase first semiconductor switching element Wp (high side) and the W-phase second semiconductor switching element Wn (low side) decreases as the drawing shifts to the right side.
次に、図46を参照して、UH_VL保護波形の切り替えについてさらに説明する。図46は、UH_VL保護波形の切り替えを説明するための図である。
Next, switching of the UH_VL protection waveform will be further described with reference to FIG. FIG. 46 is a diagram for explaining switching of the UH_VL protection waveform.
図46において、出力電圧の波形およびスイッチング損失は、左から順に、(g)波形例19(図32Aおよび図32B)、(n)波形例26(図39Aおよび図39B)、(a)波形例13(図26Aおよび図26B)に相当する。
In FIG. 46, the waveform of the output voltage and the switching loss are, from the left, (g) waveform example 19 (FIGS. 32A and 32B), (n) waveform example 26 (FIGS. 39A and 39B), (a) waveform example 13 (FIGS. 26A and 26B).
左の図に示す(g)波形例19は、(n)波形例26の第2オン固定期間T2uおよび第2オン固定期間T2wを減らし、第1オン固定期間T1vおよび第1オン固定期間T1wを増やした波形例である。つまり、ハイサイドを重視した波形例である。
In (g) waveform example 19 shown in the left diagram, the second fixed on period T2u and the second fixed on period T2w of (n) waveform example 26 are reduced, and the first fixed on period T1v and the first fixed on period T1w are reduced. It is an example of increased waveforms. That is, it is an example of a waveform that emphasizes the high side.
中央の図に示す(n)波形例26は、第1オン固定期間T1v、第1オン固定期間T1w、第2オン固定期間T2vおよび第2オン固定期間T2wを均等にした波形例である。つまり、第1オン固定期間T1u、第1オン固定期間T1u以外を均等にした波形例である。
(n) Waveform example 26 shown in the middle diagram is a waveform example in which the first fixed ON period T1v, the first fixed ON period T1w, the second fixed ON period T2v, and the second fixed ON period T2w are equalized. That is, it is a waveform example in which the first fixed ON period T1u and the period other than the first fixed ON period T1u are made uniform.
右の図に示す(a)波形例13は、(n)波形例26の第1オン固定期間T1uおよび第1オン固定期間T1wを減らし、第2オン固定期間T2vおよび第2オン固定期間T2wを増やした波形例である。つまり、ロウサイドを重視した波形例である。
In (a) waveform example 13 shown in the right diagram, the first fixed ON period T1u and first fixed ON period T1w of (n) waveform example 26 are reduced, and the second fixed ON period T2v and second fixed ON period T2w are reduced. It is an example of increased waveforms. That is, it is an example of a waveform that emphasizes the low side.
図47から図49を参照して図21に示したステップS186の詳細な処理について説明する。すなわち、X相上段とY相下段の温度上昇を抑制するようなパターンで変調する場合の処理について説明する。図47は、保護波形の切替方法を示すフローチャートである。図48および図49は、保護波形の切替方法を示す図である。なお、図47~図49は、X相の例としてU相を、Y相の例としてV相を用いた場合の保護波形の切替方法を示している。
The detailed processing of step S186 shown in FIG. 21 will be described with reference to FIGS. 47 to 49. FIG. In other words, the process of modulating in a pattern that suppresses the temperature rise of the X-phase upper stage and the Y-phase lower stage will be described. FIG. 47 is a flow chart showing a protection waveform switching method. 48 and 49 are diagrams showing a method of switching guard waveforms. 47 to 49 show the switching method of the protection waveform when the U phase is used as an example of the X phase and the V phase is used as an example of the Y phase.
ステップS502:信号生成部120は、温度T_3~T_6が閾値T_Thr5以下であるか否かを判定する。温度T_3~T_6が閾値T_Thr5以下でないと、信号生成部120が判定した場合(ステップS502:No)、処理はステップS506に進む。温度T_3~T_6が閾値T_Thr5以下であると、信号生成部120が判定した場合(ステップS502:Yes)、処理はステップS504に進む。
Step S502: The signal generator 120 determines whether the temperatures T_3 to T_6 are equal to or lower than the threshold T_Thr5. When the signal generator 120 determines that the temperatures T_3 to T_6 are not equal to or lower than the threshold value T_Thr5 (step S502: No), the process proceeds to step S506. When the signal generator 120 determines that the temperatures T_3 to T_6 are equal to or lower than the threshold value T_Thr5 (step S502: Yes), the process proceeds to step S504.
ステップS504:信号生成部120は、4つ保護パターンで変調を行う。詳しくは、信号生成部120は、(i)波形例21で変調を行う。処理は終了する。
Step S504: The signal generator 120 modulates with four protection patterns. Specifically, the signal generator 120 performs modulation with (i) waveform example 21 . Processing ends.
ステップS506:信号生成部120は、温度T_5~T_6が閾値T_Thr6以下であるか否かを判定する。温度T_5~T_6が閾値T_Thr6以下でないと、信号生成部120が判定した場合(ステップS506:No)、処理はステップS510に進む。温度T_5~T_6が閾値T_Thr6以下であると、信号生成部120が判定した場合(ステップS506:Yes)、処理はステップS508に進む。
Step S506: The signal generator 120 determines whether the temperatures T_5 to T_6 are equal to or lower than the threshold T_Thr6. When the signal generator 120 determines that the temperatures T_5 to T_6 are not equal to or lower than the threshold value T_Thr6 (step S506: No), the process proceeds to step S510. When the signal generator 120 determines that the temperatures T_5 to T_6 are equal to or lower than the threshold T_Thr6 (step S506: Yes), the process proceeds to step S508.
ステップS508:信号生成部120は、3つ保護パターンと4つ保護パターンとの中間で変調を行う。3つ保護パターンと4つ保護パターンとの中間で変調については、図48を参照して後述する。処理は終了する。
Step S508: The signal generator 120 modulates between the three protection patterns and the four protection patterns. Modulation in between the 3 guard pattern and the 4 guard pattern is described below with reference to FIG. Processing ends.
ステップS510:信号生成部120は、温度T_3~T_5が閾値T_Thr7以下であるか否かを判定する。温度T_3~T_5が閾値T_Thr7以下でないと、信号生成部120が判定した場合(ステップS510:No)、処理はステップS514に進む。温度T_3~T_5が閾値T_Thr7以下であると、信号生成部120が判定した場合(ステップS510:Yes)、処理はステップS512に進む。
Step S510: The signal generator 120 determines whether the temperatures T_3 to T_5 are equal to or lower than the threshold T_Thr7. When the signal generator 120 determines that the temperatures T_3 to T_5 are not equal to or lower than the threshold value T_Thr7 (step S510: No), the process proceeds to step S514. When the signal generator 120 determines that the temperatures T_3 to T_5 are equal to or lower than the threshold T_Thr7 (step S510: Yes), the process proceeds to step S512.
ステップS512:信号生成部120は、3つ保護パターンで変調を行う。詳しくは、信号生成部120は、(i)波形例21、(k)波形例23、(p)波形例28、(q)波形例29のうち、温度がT_3、T_4、T_5となるアーム(半導体スイッチング素子)を保護できるパターンで変調を行う。処理は終了する。
Step S512: The signal generator 120 modulates with three protection patterns. Specifically, the signal generation unit 120 selects the arms (i) waveform example 21, (k) waveform example 23, (p) waveform example 28, and (q) waveform example 29 whose temperatures are T_3, T_4, and T_5. (Semiconductor switching elements) are modulated with a pattern that can protect them. Processing ends.
ステップS514:信号生成部120は、温度T_4~T_5が閾値T_Thr8以下であるか否かを判定する。温度T_4~T_5が閾値T_Thr8以下でないと、信号生成部120が判定した場合(ステップS514:No)、処理はステップS518に進む。温度T_4~T_5が閾値T_Thr8以下であると、信号生成部120が判定した場合(ステップS514:Yes)、処理はステップS516に進む。
Step S514: The signal generator 120 determines whether the temperatures T_4 to T_5 are equal to or lower than the threshold T_Thr8. When the signal generator 120 determines that the temperatures T_4 to T_5 are not equal to or lower than the threshold T_Thr8 (step S514: No), the process proceeds to step S518. When the signal generator 120 determines that the temperatures T_4 to T_5 are equal to or lower than the threshold T_Thr8 (step S514: Yes), the process proceeds to step S516.
ステップS516:信号生成部120は、2つ保護パターンと3つ保護パターンとの中間で変調を行う。2つ保護パターンと3つ保護パターンとの中間で変調については、図49を参照して後述する。処理は終了する。
Step S516: The signal generator 120 modulates between the two protection patterns and the three protection patterns. Modulation in between two guard patterns and three guard patterns is described below with reference to FIG. Processing ends.
ステップS518:信号生成部120は、2つ保護パターンで変調を行う。詳しくは、信号生成部120は、(a)波形例13、(c)波形例15、(e)波形例17、(g)波形例19、(i)波形例21および(p)波形例28のうち、温度がT_3、T_4となるアーム(半導体スイッチング素子)を保護できるパターンで変調を行う。処理は終了する。
Step S518: The signal generator 120 modulates with two protection patterns. Specifically, the signal generator 120 generates (a) waveform example 13, (c) waveform example 15, (e) waveform example 17, (g) waveform example 19, (i) waveform example 21, and (p) waveform example 28. Of these, modulation is performed with a pattern that can protect arms (semiconductor switching elements) whose temperatures are T_3 and T_4. Processing ends.
次に、図48を参照して図47に示したステップS508の詳細な処理について説明する。すなわち、3つ保護パターンと4つ保護パターンとの中間で変調を行う場合の処理について説明する。
Next, the detailed processing of step S508 shown in FIG. 47 will be described with reference to FIG. That is, a description will be given of the processing in the case of performing modulation between the three protection patterns and the four protection patterns.
信号生成部120は、UH(第1半導体スイッチング素子Up)およびVL(第2半導体スイッチング素子Vn)を除いて温度の高い上位3アーム(半導体スイッチング素子)の位置を判定する。以下、図48の説明において、「UH(第1半導体スイッチング素子Up)およびUL(第2半導体スイッチング素子Un)を除いて温度の高い上位3アーム(半導体スイッチング素子)」を、単に「上位3アーム」と記載することがある。なお、上位3アームの温度の順番は問わない。例えば、上位3アームの温度の順番が、UL(第2半導体スイッチング素子Un)、WH(第1半導体スイッチング素子Wp)およびWL(第2半導体スイッチング素子Wn)の順でもよいし、UL(第2半導体スイッチング素子Un)、WL(第2半導体スイッチング素子Wn)およびWH(第1半導体スイッチング素子Wp)の順でもよい。以下、同様の記載についても同様に上位3アームの温度の順番は問わない。
The signal generation unit 120 determines the positions of the three arms (semiconductor switching elements) with the highest temperature, excluding UH (first semiconductor switching element Up) and VL (second semiconductor switching element Vn). Hereinafter, in the description of FIG. 48, "upper three arms (semiconductor switching elements) with higher temperatures excluding UH (first semiconductor switching element Up) and UL (second semiconductor switching element Un)" will be simply referred to as "upper three arms ” may be stated. Note that the order of the temperatures of the top three arms does not matter. For example, the order of the temperatures of the upper three arms may be UL (second semiconductor switching element Un), WH (first semiconductor switching element Wp), and WL (second semiconductor switching element Wn), or UL (second semiconductor switching element Wn). The order of semiconductor switching element Un), WL (second semiconductor switching element Wn), and WH (first semiconductor switching element Wp) is also acceptable. In the same description below, the order of the temperatures of the top three arms is similarly irrelevant.
信号生成部120が、最高温の3アームがUL(第2半導体スイッチング素子Un)、WH(第1半導体スイッチング素子Wp)およびWL(第2半導体スイッチング素子Wn)であると判定した場合、(i)波形例21において、195度~195+45×(T_Thr6-(T_5-T_6))/T_Thr6度を第1オン固定期間、270度~270+15×(T_Thr6-(T_5-T_6))/T_Thr6度を第2オン固定期間に適用したパターンで、信号生成部120は変調を行う。
When the signal generation unit 120 determines that the three arms with the highest temperature are UL (second semiconductor switching element Un), WH (first semiconductor switching element Wp), and WL (second semiconductor switching element Wn), (i ) In waveform example 21, 195 degrees to 195 + 45 x (T_Thr6 - (T_5 - T_6)) / T_Thr6 degrees is the first ON fixed period, 270 degrees to 270 + 15 x (T_Thr6 - (T_5 - T_6)) / T_Thr6 degrees is the second The signal generating section 120 performs modulation with the pattern applied to the ON-fixed period.
信号生成部120が、最高温の3アームがVH(第1半導体スイッチング素子Vp)、WH(第1半導体スイッチング素子Wp)およびWL(第2半導体スイッチング素子Wn)であると判定した場合、(k)波形例23において、195度~195+15×(T_Thr6-(T_5-T_6))/T_Thr6度を第1オン固定期間、240度~240+45×(T_Thr6-(T_5-T_6))/T_Thr6度を第2オン固定期間に適用したパターンで、信号生成部120は変調を行う。
When signal generation unit 120 determines that the three arms with the highest temperature are VH (first semiconductor switching element Vp), WH (first semiconductor switching element Wp), and WL (second semiconductor switching element Wn), (k ) In waveform example 23, 195 degrees to 195 + 15 x (T_Thr6-(T_5-T_6))/T_Thr6 degrees is the first ON fixed period, and 240 degrees to 240 + 45 x (T_Thr6-(T_5-T_6))/T_Thr6 degrees is the second The signal generating section 120 performs modulation with the pattern applied to the ON-fixed period.
信号生成部120が、最高温の3アームがUL(第2半導体スイッチング素子Un)、VH(第1半導体スイッチング素子Vp)およびWL(第2半導体スイッチング素子Wn)であると判定した場合、(p)波形例28において、195度~195+15×(T_Thr6-(T_5-T_6))/T_Thr6度を第1オン固定期間、240度~240+45×(T_Thr6-(T_5-T_6))/T_Thr6を第2オン固定期間、285度~285+45×(T_Thr6-(T_5-T_6))/T_Thr6度を第1オン固定期間に適用したパターンで、信号生成部120は変調を行う。
When signal generation unit 120 determines that the three arms with the highest temperature are UL (second semiconductor switching element Un), VH (first semiconductor switching element Vp), and WL (second semiconductor switching element Wn), (p ) In waveform example 28, 195 degrees to 195 + 15 x (T_Thr6 - (T_5 - T_6))/T_Thr6 degrees is the first ON fixed period, and 240 degrees to 240 + 45 x (T_Thr6 - (T_5 - T_6))/T_Thr6 is the second ON period. The signal generation unit 120 performs modulation with a pattern in which 285 degrees to 285+45×(T_Thr6-(T_5-T_6))/T_Thr6 degrees is applied to the first ON fixed period.
信号生成部120が、最高温の3アームがUL(第2半導体スイッチング素子Un)、VH(第1半導体スイッチング素子Vp)およびWH(第1半導体スイッチング素子Wp)であると判定した場合、(q)波形例29において、150度~150+45×(T_Thr6-(T_5-T_6))/T_Thr6度を第2オン固定期間、210度~210+30×(T_Thr6-(T_5-T_6))/T_Thr6を第1オン固定期間、270度~270+15×(T_Thr6-(T_5-T_6))/T_Thr6度を第2オン固定期間に適用したパターンで、信号生成部120は変調を行う。
When signal generation unit 120 determines that the three arms with the highest temperature are UL (second semiconductor switching element Un), VH (first semiconductor switching element Vp), and WH (first semiconductor switching element Wp), (q ) In waveform example 29, 150 degrees to 150 + 45 x (T_Thr6 - (T_5 - T_6)) / T_Thr6 is the second ON fixed period, 210 degrees to 210 + 30 x (T_Thr6 - (T_5 - T_6)) / T_Thr6 is the first ON The signal generation unit 120 performs modulation with a pattern in which 270 degrees to 270+15×(T_Thr6-(T_5-T_6))/T_Thr6 degrees is applied to the second ON fixed period.
次に、図49を参照して図47に示したステップS516の詳細な処理について説明する。すなわち、2つ保護パターンと3つ保護パターンとの中間で変調を行う場合の処理について説明する。
Next, the detailed processing of step S516 shown in FIG. 47 will be described with reference to FIG. In other words, a description will be given of processing in the case of performing modulation between the two protection patterns and the three protection patterns.
図49に示すように、最高温の2アームの位置、および両者の優先度が、UL>WLの場合であって、温度がT_5となるアームがVHの場合、処理1を行う。処理1では、(a)波形例13において、210度~210+60×(T_Thr8-(T_4-T_5))/T_Thr8度を第1オン固定期間に適用したパターンで、信号生成部120は変調を行う。
As shown in FIG. 49, when the positions of the two arms with the highest temperature and the priority of both are UL>WL and the arm with temperature T_5 is VH, process 1 is performed. In process 1, the signal generator 120 performs modulation with a pattern obtained by applying 210 degrees to 210+60×(T_Thr8-(T_4-T_5))/T_Thr8 degrees in (a) waveform example 13 to the first ON fixed period.
最高温の2アームの位置、および両者の優先度が、UL>WLの場合であって、温度がT_5となるアームがWHの場合、処理1を行う。処理1では、(a)波形例13において、270度~270+60×(T_Thr8-(T_4-T_5))/T_Thr8度を第1オン固定期間に適用したパターンで、信号生成部120は変調を行う。
When the position of the two arms with the highest temperature and the priority of both are UL>WL and the arm with the temperature of T_5 is WH, process 1 is performed. In process 1, the signal generator 120 performs modulation with a pattern obtained by applying 270 degrees to 270+60×(T_Thr8-(T_4-T_5))/T_Thr8 degrees in (a) waveform example 13 to the first ON fixed period.
最高温の2アームの位置、および両者の優先度が、UL<WLの場合であって、温度がT_5となるアームがVHの場合、処理1を行う。処理1では、(a)波形例13において、210度~210+60×(T_Thr8-(T_4-T_5))/T_Thr8度を第1オン固定期間に適用したパターンで、信号生成部120は変調を行う。
When the position of the two arms with the highest temperature and the priority of both are UL<WL and the arm with temperature T_5 is VH, process 1 is performed. In process 1, the signal generator 120 performs modulation with a pattern obtained by applying 210 degrees to 210+60×(T_Thr8-(T_4-T_5))/T_Thr8 degrees in (a) waveform example 13 to the first ON fixed period.
最高温の2アームの位置、および両者の優先度が、UL<WLの場合であって、温度がT_5となるアームがWHの場合、処理2を行う。処理2では、(a)波形例13において、270度~270+60×(T_Thr8-(T_4-T_5))/T_Thr8度を第1オン固定期間に適用したパターンで、信号生成部120は変調を行う。
If the position of the two arms with the highest temperature and the priority of both are UL<WL and the arm with temperature T_5 is WH, process 2 is performed. In process 2, the signal generator 120 performs modulation with a pattern obtained by applying 270 degrees to 270+60×(T_Thr8−(T_4−T_5))/T_Thr8 degrees in (a) waveform example 13 to the first ON fixed period.
最高温の2アームの位置、および両者の優先度が、UL>WHの場合であって、温度がT_5となるアームがVHの場合、処理3を行う。処理3では、(a)波形例13において、150度~150+60×(T_Thr8-(T_4-T_5))/T_Thr8度、270度~270+60×(T_Thr8-(T_4-T_5))/T_Thr8度を第1オン固定期間に適用したパターンで、信号生成部120は変調を行う。
When the position of the two arms with the highest temperature and the priority of both are UL>WH and the arm with temperature T_5 is VH, process 3 is performed. In process 3, (a) in waveform example 13, 150 degrees to 150 + 60 x (T_Thr8 - (T_4 - T_5)) / T_Thr8 degrees, 270 degrees to 270 + 60 x (T_Thr8 - (T_4 - T_5)) / T_Thr8 degrees are the first The signal generating section 120 performs modulation with the pattern applied to the ON-fixed period.
最高温の2アームの位置、および両者の優先度が、UL>WHの場合であって、温度がT_5となるアームがVLの場合、処理2を行う。処理2では、(a)波形例13において、270度~270+60×(T_Thr8-(T_4-T_5))/T_Thr8度を第1オン固定期間に適用したパターンで、信号生成部120は変調を行う。
When the position of the two arms with the highest temperature and the priority of both are UL>WH and the arm with the temperature of T_5 is VL, process 2 is performed. In process 2, the signal generator 120 performs modulation with a pattern obtained by applying 270 degrees to 270+60×(T_Thr8−(T_4−T_5))/T_Thr8 degrees in (a) waveform example 13 to the first ON fixed period.
最高温の2アームの位置、および両者の優先度が、UL>VHの場合であって、温度がT_5となるアームがWHの場合、処理4を行う。処理4では、(c)波形例15において、270度~270+60×(T_Thr8-(T_4-T_5))/T_Thr8度を第1オン固定期間に適用したパターンで、信号生成部120は変調を行う。
When the position of the two arms with the highest temperature and the priority of both are UL>VH and the arm with temperature T_5 is WH, process 4 is performed. In process 4, the signal generator 120 modulates with a pattern obtained by applying 270 degrees to 270+60×(T_Thr8-(T_4-T_5))/T_Thr8 degrees in (c) waveform example 15 to the first ON fixed period.
最高温の2アームの位置、および両者の優先度が、UL>VHの場合であって、温度がT_5となるアームがWLの場合、処理5を行う。処理5では、(c)波形例15において、150度~150+60×(T_Thr8-(T_4-T_5))/T_Thr8度を第2オン固定期間、210度~210+60×(T_Thr8-(T_4-T_5))/T_Thr8度を第1オン固定期間に適用したパターンで、信号生成部120は変調を行う。
If the position of the two arms with the highest temperature and the priority of both are UL>VH and the arm with temperature T_5 is WL, process 5 is performed. In process 5, (c) in waveform example 15, 150 degrees to 150+60×(T_Thr8−(T_4−T_5))/T_Thr8 degrees is the second ON fixed period, 210 degrees to 210+60×(T_Thr8−(T_4−T_5)) The signal generator 120 performs modulation with a pattern in which /T_Thr8 is applied to the first fixed ON period.
最高温の2アームの位置、および両者の優先度が、UL<VHの場合であって、温度がT_5となるアームがWHの場合、処理6を行う。処理6では、(e)波形例17において、210度~210+60×(T_Thr8-(T_4-T_5))/T_Thr8度を第2オン固定期間、270度~270+60×(T_Thr8-(T_4-T_5))/T_Thr8度を第1オン固定期間に適用したパターンで、信号生成部120は変調を行う。
If the position of the two arms with the highest temperature and the priority of both are UL<VH, and if the arm whose temperature is T_5 is WH, process 6 is performed. In process 6, (e) in waveform example 17, 210 degrees to 210+60×(T_Thr8−(T_4−T_5))/T_Thr8 degrees is the second ON fixed period, 270 degrees to 270+60×(T_Thr8−(T_4−T_5)) The signal generator 120 performs modulation with a pattern in which /T_Thr8 is applied to the first fixed ON period.
最高温の2アームの位置、および両者の優先度が、UL<VHの場合であって、温度がT_5となるアームがWLの場合、処理7を行う。処理7では、(e)波形例17において、150度~150+60×(T_Thr8-(T_4-T_5))/T_Thr8度を第2オン固定期間に適用したパターンで、信号生成部120は変調を行う。
When the position of the two arms with the highest temperature and the priority of both are UL<VH, and the arm with the temperature T_5 is WL, process 7 is performed. In process 7, the signal generator 120 modulates with a pattern obtained by applying 150 degrees to 150+60×(T_Thr8-(T_4-T_5))/T_Thr8 degrees in (e) waveform example 17 to the second ON fixed period.
最高温の2アームの位置、および両者の優先度が、VH>WLの場合であって、温度がT_5となるアームがWLの場合、処理7を行う。処理7では、(e)波形例17において、150度~150+60×(T_Thr8-(T_4-T_5))/T_Thr8度を第2オン固定期間に適用したパターンで、信号生成部120は変調を行う。
When the position of the two arms with the highest temperature and the priority of both are VH>WL, and the arm with the temperature of T_5 is WL, process 7 is performed. In process 7, the signal generator 120 modulates with a pattern obtained by applying 150 degrees to 150+60×(T_Thr8-(T_4-T_5))/T_Thr8 degrees in (e) waveform example 17 to the second ON fixed period.
最高温の2アームの位置、および両者の優先度が、VH>WLの場合であって、温度がT_5となるアームがWHの場合、処理8を行う。処理8では、(e)波形例17において、150度~150+60×(T_Thr8-(T_4-T_5))/T_Thr8度を第2オン固定期間、270度~270+60×(T_Thr8-(T_4-T_5))/T_Thr8度を第1オン固定期間に適用したパターンで、信号生成部120は変調を行う。
If the position of the two arms with the highest temperature and the priority of both are VH>WL, and if the arm whose temperature is T_5 is WH, then process 8 is performed. In process 8, (e) in waveform example 17, 150 degrees to 150+60×(T_Thr8−(T_4−T_5))/T_Thr8 degrees is the second ON fixed period, 270 degrees to 270+60×(T_Thr8−(T_4−T_5)) The signal generator 120 performs modulation with a pattern in which /T_Thr8 is applied to the first fixed ON period.
最高温の2アームの位置、および両者の優先度が、VH>WHの場合であって、温度がT_5となるアームがULの場合、処理9を行う。処理9では、(g)波形例19において、210度~210+60×(T_Thr8-(T_4-T_5))/T_Thr8度を第2オン固定期間に適用したパターンで、信号生成部120は変調を行う。
When the position of the two arms with the highest temperature and the priority of both are VH>WH and the arm with the temperature of T_5 is UL, process 9 is performed. In process 9, the signal generator 120 modulates with a pattern obtained by applying 210 degrees to 210+60×(T_Thr8-(T_4-T_5))/T_Thr8 degrees in (g) waveform example 19 to the second ON fixed period.
最高温の2アームの位置、および両者の優先度が、VH>WHの場合であって、温度がT_5となるアームがWLの場合、処理10を行う。処理10では、(g)波形例19において、150度~150+60×(T_Thr8-(T_4-T_5))/T_Thr8度を第2オン固定期間に適用したパターンで、信号生成部120は変調を行う。
When the position of the two arms with the highest temperature and the priority of both are VH>WH and the arm with the temperature of T_5 is WL, process 10 is performed. In process 10, the signal generator 120 modulates with a pattern obtained by applying 150 degrees to 150+60×(T_Thr8−(T_4−T_5))/T_Thr8 degrees in (g) waveform example 19 to the second ON fixed period.
最高温の2アームの位置、および両者の優先度が、VH<WHの場合であって、温度がT_5となるアームがULの場合、処理9を行う。処理9では、(g)波形例19において、210度~210+60×(T_Thr8-(T_4-T_5))/T_Thr8度を第2オン固定期間に適用したパターンで、信号生成部120は変調を行う。
If the position of the two arms with the highest temperature and the priority of both are VH<WH, and if the arm whose temperature is T_5 is UL, process 9 is performed. In process 9, the signal generator 120 modulates with a pattern obtained by applying 210 degrees to 210+60×(T_Thr8-(T_4-T_5))/T_Thr8 degrees in (g) waveform example 19 to the second ON fixed period.
最高温の2アームの位置、および両者の優先度が、VH<WHの場合であって、温度がT_5となるアームがWLの場合、処理10を行う。処理10では、(g)波形例19において、150度~150+60×(T_Thr8-(T_4-T_5))/T_Thr8度を第2オン固定期間に適用したパターンで、信号生成部120は変調を行う。
When the position of the two arms with the highest temperature and the priority of both are VH<WH, and the arm with the temperature of T_5 is WL, process 10 is performed. In process 10, the signal generator 120 modulates with a pattern obtained by applying 150 degrees to 150+60×(T_Thr8−(T_4−T_5))/T_Thr8 degrees in (g) waveform example 19 to the second ON fixed period.
最高温の2アームの位置、および両者の優先度が、UL<WHの場合であって、温度がT_5となるアームがVHの場合、処理11を行う。処理11では、(i)波形例21において、150度~150+60×(T_Thr8-(T_4-T_5))/T_Thr8度を第1オン固定期間に適用したパターンで、信号生成部120は変調を行う。
If the position of the two arms with the highest temperature and the priority of both are UL<WH and the arm with temperature T_5 is VH, process 11 is performed. In process 11, (i) in waveform example 21, the signal generator 120 performs modulation with a pattern in which 150 degrees to 150+60×(T_Thr8-(T_4-T_5))/T_Thr8 degrees is applied to the first ON fixed period.
最高温の2アームの位置、および両者の優先度が、UL<WHの場合であって、温度がT_5となるアームがWLの場合、処理12を行う。処理12では、信号生成部120は(i)波形例21で変調を行う。
If the position of the two arms with the highest temperature and the priority of both are UL<WH and the arm with temperature T_5 is WL, process 12 is performed. In process 12 , the signal generator 120 (i) modulates the waveform example 21 .
最高温の2アームの位置、および両者の優先度が、WH>WLの場合であって、温度がT_5となるアームがULの場合、処理12を行う。処理12では、信号生成部120は(i)波形例21で変調を行う。
If the position of the two arms with the highest temperature and the priority of both are WH>WL, and if the arm whose temperature is T_5 is UL, process 12 is performed. In process 12 , the signal generator 120 (i) modulates the waveform example 21 .
最高温の2アームの位置、および両者の優先度が、WH>WLの場合であって、温度がT_5となるアームがVHの場合、処理13を行う。処理13では、(i)波形例21において、210度~210+60×(T_Thr8-(T_4-T_5))/T_Thr8度を第1オン固定期間に適用したパターンで、信号生成部120は変調を行う。
If the position of the two arms with the highest temperature and the priority of both are WH>WL, and if the arm whose temperature is T_5 is VH, process 13 is performed. In process 13, (i) in waveform example 21, the signal generator 120 performs modulation with a pattern in which 210 degrees to 210+60×(T_Thr8-(T_4-T_5))/T_Thr8 degrees is applied to the first ON fixed period.
最高温の2アームの位置、および両者の優先度が、WH<WLの場合であって、温度がT_5となるアームがULの場合、処理12を行う。処理12では、信号生成部120は(i)波形例21で変調を行う。
If the position of the two arms with the highest temperature and the priority of both are WH<WL, and if the arm whose temperature is T_5 is UL, process 12 is performed. In process 12 , the signal generator 120 (i) modulates the waveform example 21 .
最高温の2アームの位置、および両者の優先度が、VH<WLの場合であって、温度がT_5となるアームがULの場合、処理14を行う。処理14では、信号生成部120は(p)波形例28で変調を行う。
If the position of the two arms with the highest temperature and the priority of both are VH<WL and the arm with temperature T_5 is UL, process 14 is performed. In process 14 , the signal generator 120 performs modulation with (p) waveform example 28 .
最高温の2アームの位置、および両者の優先度が、VH<WLの場合であって、温度がT_5となるアームがWHの場合、処理15を行う。処理15では、(p)波形例28において、270度~270+60×(T_Thr8-(T_4-T_5))/T_Thr8度を第1オン固定期間に適用したパターンで、信号生成部120は変調を行う。
If the position of the two arms with the highest temperature and the priority of both are VH<WL, and if the arm whose temperature is T_5 is WH, process 15 is performed. In process 15, the signal generator 120 performs modulation with a pattern obtained by applying 270 degrees to 270+60×(T_Thr8−(T_4−T_5))/T_Thr8 degrees in (p) waveform example 28 to the first ON fixed period.
以上、図47~図49を参照して説明したように、保護動作モードは、1つの相の第1半導体スイッチング素子と、他の相の第2半導体スイッチング素子とを保護する第2選択保護動作モードを含む。1つの相の第1オン固定期間と他の相の第2オン固定期間とが連続している。第2選択保護動作モードは、1つの相の第1半導体スイッチング素子および他の相の第2半導体スイッチング素子以外の第1半導体スイッチング素子および第2半導体スイッチング素子のうち、k個(kは2n-3以下の自然数)の第1半導体スイッチング素子または第2半導体スイッチング素子を保護する、複数のk個保護動作モードを含み、温度情報に基づいて、k個保護動作モードの選択を行う。したがって、ストールが発生してある相の第1半導体スイッチと別の相の第2半導体スイッチに連続的に電流が流れ温度上昇した場合、ストールを脱して動作を開始する際にこの動作を行うことで、ある相の第1半導体スイッチと別の相の第2半導体スイッチの昇温を最大限に抑制しながら、他の半導体スイッチング素子も温度状況に応じて必要な半導体スイッチング素子の昇温を抑制することで、インバータの信頼性が高まる。
As described above with reference to FIGS. 47 to 49, the protection operation mode is the second selective protection operation that protects the first semiconductor switching element of one phase and the second semiconductor switching element of another phase. Including mode. The first fixed ON period of one phase and the second fixed ON period of another phase are continuous. In the second selective protection operation mode, k (k is 2n− A natural number of 3 or less) includes a plurality of k protection operation modes for protecting the first semiconductor switching elements or the second semiconductor switching elements, and the k protection operation modes are selected based on the temperature information. Therefore, when a current continuously flows through the first semiconductor switch of a certain phase and the second semiconductor switch of another phase due to a stall and the temperature rises, this operation must be performed when the stall is released and the operation is started. Therefore, while suppressing the temperature rise of the first semiconductor switch of a certain phase and the second semiconductor switch of another phase to the maximum, other semiconductor switching elements also suppress the temperature rise of necessary semiconductor switching elements according to the temperature situation. By doing so, the reliability of the inverter is enhanced.
以上、図1~図49を参照して説明したように、モータ駆動回路100は、PWMデューティ波形が異なる複数の動作モードを有するとともに、電力変換中に前記複数の動作モードの切り替えを行う機能を有する。複数の動作モードのうち少なくとも1つは、保護動作モードである。動作モードの切り替えにより、必要に応じた最適な動作モードを採用することで、電力変換器(インバータ)の昇温を効率的に抑制し信頼性を高めることができる。
As described above with reference to FIGS. 1 to 49, the motor drive circuit 100 has a plurality of operation modes with different PWM duty waveforms, and has a function of switching between the plurality of operation modes during power conversion. have. At least one of the plurality of operating modes is a protected operating mode. By switching the operation mode and adopting the optimum operation mode according to need, it is possible to efficiently suppress the temperature rise of the power converter (inverter) and improve the reliability.
保護動作モードは、交流出力の1周期の間に、各相が占める第1オン固定期間および第2オン固定期間のうち少なくとも一方の比率が異なる複数の保護動作パターンを有する。したがって、様々な保護モードに対応することができる。例えば、通常モード(1種類)に加え、各相それぞれを中心的に保護する(複数種類)ことが可能となる。
The protection operation mode has a plurality of protection operation patterns in which the ratio of at least one of the first fixed ON period and the second fixed ON period occupied by each phase differs during one cycle of the AC output. Therefore, various protection modes can be supported. For example, in addition to the normal mode (one type), it is possible to centrally protect each phase (multiple types).
複数の保護動作モードおよび複数の保護動作パターンの切り替えは、第1半導体スイッチング素子または第2半導体スイッチング素子の少なくとも一方の温度情報に基づいて行う。温度情報は、例えば、各半導体スイッチング素子の6つの温度センサ20が取得した温度である。なお、温度センサ20を一部の半導体スイッチング素子の近傍に配置し、温度センサ20が配置されていない半導体スイッチング素子の温度は演算により推定してもよい。あるいは、環境温度をモニタリングし、モータ駆動回路100に設置した電流センサおよび電圧センサ(図示略)の値を用いて温度を推定してよい。環境温度は、例えば、気温、基板の温度および冷却水の温度である。冷却水は、モータ駆動回路100を冷却するための液体である。複数の保護動作モードおよび複数の保護動作パターンの切り替えは、第1半導体スイッチング素子または第2半導体スイッチング素子の少なくとも一方の温度情報に基づいて行うことによって、温度が高くなった半導体スイッチング素子を選択的に発熱抑制して放熱を促進し、電力変換器の信頼性を高めることができる。
A plurality of protection operation modes and a plurality of protection operation patterns are switched based on temperature information of at least one of the first semiconductor switching element and the second semiconductor switching element. The temperature information is, for example, temperatures acquired by the six temperature sensors 20 of each semiconductor switching element. Note that the temperature sensor 20 may be arranged in the vicinity of some of the semiconductor switching elements, and the temperature of the semiconductor switching elements where the temperature sensor 20 is not arranged may be estimated by calculation. Alternatively, the environmental temperature may be monitored and the temperature may be estimated using the values of a current sensor and a voltage sensor (not shown) installed in the motor drive circuit 100 . The ambient temperature is, for example, the ambient temperature, the temperature of the substrate, and the temperature of the cooling water. Cooling water is a liquid for cooling motor drive circuit 100 . Switching between a plurality of protection operation modes and a plurality of protection operation patterns is performed based on temperature information of at least one of the first semiconductor switching element and the second semiconductor switching element, whereby the semiconductor switching element with a high temperature is selectively switched. It is possible to suppress heat generation, promote heat dissipation, and improve the reliability of the power converter.
また、保護動作モードは、少なくとも4種類の保護動作パターンを有する。したがって、様々な保護モードに対応することができる。例えば、通常モード(1種類)に加え、各相それぞれを中心的に保護する(複数種類)ことが可能となる。
Also, the protection operation mode has at least four types of protection operation patterns. Therefore, various protection modes can be supported. For example, in addition to the normal mode (one type), it is possible to centrally protect each phase (multiple types).
図50A~図66Bを参照して、他の波形例について説明する。
Other waveform examples will be described with reference to FIGS. 50A to 66B.
図50Aおよび図50Bを参照して、波形例30について説明する。図50Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図50Bは、スイッチング損失を示す図である。
A waveform example 30 will be described with reference to FIGS. 50A and 50B. FIG. 50A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 50B is a diagram showing switching losses.
図50Aに示すように、波形例30は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例30は、電気角90度~電気角210度において、いずれか1相の出力が1に固定される波形である。また、波形例30は、電気角0度~電気角90度および電気角210度~電気角360度において、いずれか1相の出力が0に固定される波形である。波形例30では、電気角90度~電気角210度において、ハイサイドオン適用期間T3である。また、波形例30では、電気角0度~電気角90度および電気角210度~電気角360度において、ロウサイドオン適用期間T4である。
As shown in FIG. 50A , in waveform example 30, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, waveform example 30 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 90 degrees to 210 electrical degrees. Waveform example 30 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 to 90 degrees and at an electrical angle of 210 to 360 degrees. In the waveform example 30, the high-side-on application period T3 is at an electrical angle of 90 degrees to 210 electrical degrees. Further, in waveform example 30, the low side-on application period T4 occurs at an electrical angle of 0 to 90 electrical degrees and at an electrical angle of 210 to 360 electrical degrees.
波形例30では、第1オン固定期間T1は、第1オン固定期間T1uと、第1オン固定期間T1vとを含む。波形例30では、電気角90度~電気角150度が第1オン固定期間T1uである。波形例30では、電気角150度~電気角210度が第1オン固定期間T1vである。
In waveform example 30, the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v. In waveform example 30, the first fixed ON period T1u is from 90 electrical degrees to 150 electrical degrees. In waveform example 30, the first fixed ON period T1v is between an electrical angle of 150 degrees and an electrical angle of 210 degrees.
波形例30では、第2オン固定期間T2は、第2オン固定期間T2uと、第2オン固定期間T2vとを含む。波形例30では、電気角210度~電気角330度が第2オン固定期間T2uである。波形例30では、電気角0度~電気角90度および電気角330度~電気角360度が第2オン固定期間T2vである。
In waveform example 30, the second fixed ON period T2 includes a second fixed ON period T2u and a second fixed ON period T2v. In waveform example 30, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In waveform example 30, the second fixed ON period T2v is from 0 to 90 electrical degrees and from 330 to 360 electrical degrees.
波形例30では、3相のうちU相において、第1オン固定期間T1uが、第1オン固定期間T1wと異なる。詳しくは、波形例30では、第1オン固定期間T1uが60度であるのに対し、第1オン固定期間T1wは無い。すなわち、波形例30では、第1オン固定期間T1uが第1オン固定期間T1wよりも長い。なお、第1オン固定期間T1vは、第1オン固定期間T1uと同じである。したがって、図50Bに示すように、U相の第1半導体スイッチング素子Up(H(ハイサイド))のスイッチング損失がW相に比べて小さくなっている。
In waveform example 30, the first fixed ON period T1u differs from the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 30, the first fixed ON period T1u is 60 degrees, but there is no first fixed ON period T1w. That is, in waveform example 30, the first fixed ON period T1u is longer than the first fixed ON period T1w. The first fixed ON period T1v is the same as the first fixed ON period T1u. Therefore, as shown in FIG. 50B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than that of the W-phase.
波形例30では、第2オン固定期間T2uが、第2オン固定期間T2uおよび第2オン固定期間T2wと異なる。詳しくは、波形例30では、第2オン固定期間T2uが120度であるのに対し、第2オン固定期間T2wは無い。すなわち、波形例30では、第2オン固定期間T2uが第2オン固定期間T2wよりも長い。なお、第2オン固定期間T2vは、第2オン固定期間T2uと同じである。したがって、図50Bに示すように、U相の第2半導体スイッチング素子Un(L(ロウサイド))のスイッチング損失がW相に比べて小さくなっている。
In waveform example 30, the second fixed ON period T2u is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in waveform example 30, the second fixed ON period T2u is 120 degrees, but there is no second fixed ON period T2w. That is, in waveform example 30, the second fixed ON period T2u is longer than the second fixed ON period T2w. The second fixed ON period T2v is the same as the second fixed ON period T2u. Therefore, as shown in FIG. 50B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than that of the W-phase.
以上、図50Aおよび図50Bを参照して説明したように、波形例30においても、波形例1と同様に、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。波形例30では、U相の第2半導体スイッチング素子Unと、V相の第2半導体スイッチング素子Vnとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 50A and 50B , in waveform example 30, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 30, the heat generation of the U-phase second semiconductor switching element Un and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
また、波形例30では、図50Bに示すように、U相の第1半導体スイッチング素子Upと、V相の第1半導体スイッチング素子Vpとの発熱についても同時に抑えることができる。
Further, in the waveform example 30, as shown in FIG. 50B, the heat generation of the U-phase first semiconductor switching element Up and the V-phase first semiconductor switching element Vp can be suppressed at the same time.
図51Aおよび図51Bを参照して、波形例31について説明する。図51Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図51Bは、スイッチング損失を示す図である。
A waveform example 31 will be described with reference to FIGS. 51A and 51B. FIG. 51A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 51B is a diagram showing switching loss.
図51Aに示すように、波形例31は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例31は、電気角45度~電気角135度および電気角180度~電気角210度において、いずれか1相の出力が1に固定される波形である。また、波形例31は、電気角0度~電気角45度、電気角135度~電気角180度および電気角210度~電気角360度において、いずれか1相の出力が0に固定される波形である。波形例31では、電気角45度~電気角135度および電気角180度~電気角210度において、ハイサイドオン適用期間T3である。また、波形例31では、電気角0度~電気角45度、電気角135度~電気角180度および電気角210度~電気角360度において、ロウサイドオン適用期間T4である。
As shown in FIG. 51A, in waveform example 31, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, the waveform example 31 is a waveform in which the output of any one phase is fixed to 1 in the electrical angle of 45 degrees to 135 electrical degrees and in the electrical angle of 180 degrees to 210 electrical degrees. In waveform example 31, the output of any one phase is fixed to 0 at an electrical angle of 0 to 45 electrical degrees, 135 to 180 electrical degrees, and 210 to 360 electrical degrees. waveform. In waveform example 31, the high-side-on application period T3 occurs at an electrical angle of 45 degrees to 135 degrees and at an electrical angle of 180 degrees to 210 degrees. Further, in waveform example 31, the low side-on application period T4 occurs at an electrical angle of 0 to 45 electrical degrees, 135 to 180 electrical degrees, and 210 to 360 electrical degrees.
波形例31では、第1オン固定期間T1は、第1オン固定期間T1uと、第1オン固定期間T1vとを含む。波形例31では、電気角45度~電気角135度が第1オン固定期間T1uである。波形例31では、電気角180度~電気角210度が第1オン固定期間T1vである。
In waveform example 31, the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v. In waveform example 31, the first fixed ON period T1u is from an electrical angle of 45 degrees to an electrical angle of 135 degrees. In waveform example 31, the first fixed ON period T1v is from 180 degrees to 210 degrees in electrical angle.
波形例31では、第2オン固定期間T2は、第2オン固定期間T2uと、第2オン固定期間T2vと、第2オン固定期間T2wとを含む。波形例31では、電気角210度~電気角330度が第2オン固定期間T2uである。波形例31では、電気角0度~電気角45度および電気角330度~電気角360度が第2オン固定期間T2vである。波形例31では、電気角135度~電気角180度が第2オン固定期間T2wである。
In waveform example 31, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 31, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In waveform example 31, the second fixed ON period T2v is from an electrical angle of 0 degrees to an electrical angle of 45 degrees and from an electrical angle of 330 degrees to an electrical angle of 360 degrees. In waveform example 31, the second fixed ON period T2w is from 135 electrical degrees to 180 electrical degrees.
波形例31では、3相のうちU相において、第1オン固定期間T1uが、第1オン固定期間T1vおよび第1オン固定期間T1wと異なる。詳しくは、波形例31では、第1オン固定期間T1uが90度であるのに対し、第1オン固定期間T1vは、および第1オン固定期間T1wは30度である。すなわち、波形例31では、第1オン固定期間T1uが第1オン固定期間T1vおよび第1オン固定期間T1wよりも長い。したがって、図51Bに示すように、U相の第1半導体スイッチング素子Up(H(ハイサイド))のスイッチング損失がV相およびW相に比べて小さくなっている。
In waveform example 31, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 31, the first fixed ON period T1u is 90 degrees, while the first fixed ON period T1v and the first fixed ON period T1w are 30 degrees. That is, in waveform example 31, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 51B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
波形例31では、第2オン固定期間T2uが、第2オン固定期間T2vおよび第2オン固定期間T2wと異なる。詳しくは、波形例31では、第2オン固定期間T2uが120度であるのに対し、第2オン固定期間T2vは75度であり、第2オン固定期間T2wは45度である。すなわち、波形例31では、第2オン固定期間T2uが第2オン固定期間T2vおよび第2オン固定期間T2wよりも長い。したがって、図51Bに示すように、U相の第2半導体スイッチング素子Un(L(ロウサイド))のスイッチング損失がV相およびW相に比べて小さくなっている。
In waveform example 31, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in waveform example 31, the second fixed ON period T2u is 120 degrees, the second fixed ON period T2v is 75 degrees, and the second fixed ON period T2w is 45 degrees. That is, in waveform example 31, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 51B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
以上、図51Aおよび図51Bを参照して説明したように、波形例31においても、波形例1と同様に、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。波形例31では、U相の第1半導体スイッチング素子Upと、U相の第2半導体スイッチング素子Unとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 51A and 51B , in Waveform Example 31, as in Waveform Example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 31, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un.
また、波形例31では、図51Bに示すように、V相の第1半導体スイッチング素子Vpと、V相の第2半導体スイッチング素子Vnと、W相の第2半導体スイッチング素子Wnとの発熱についても同時に抑えることができる。
Further, in waveform example 31, as shown in FIG. 51B, the heat generated by the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
図52Aおよび図52Bを参照して、波形例32について説明する。図52Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図52Bは、スイッチング損失を示す図である。
A waveform example 32 will be described with reference to FIGS. 52A and 52B. FIG. 52A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 52B is a diagram showing switching losses.
図52Aに示すように、波形例32は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例32は、電気角60度~電気角120度および電気角150度~電気角210度において、いずれか1相の出力が1に固定される波形である。また、波形例32は、電気角0度~電気角60度、電気角120度~電気角150度および電気角210度~電気角360度において、いずれか1相の出力が0に固定される波形である。波形例32では、電気角60度~電気角120度および電気角150度~電気角210度において、ハイサイドオン適用期間T3である。また、波形例32では、電気角0度~電気角60度、電気角120度~電気角150度および電気角210度~電気角360度において、ロウサイドオン適用期間T4である。
As shown in FIG. 52A, in waveform example 32, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. More specifically, waveform example 32 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 120 degrees and at an electrical angle of 150 degrees to 210 degrees. In waveform example 32, the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 electrical degrees, 120 to 150 electrical degrees, and 210 to 360 electrical degrees. waveform. In waveform example 32, the high-side-on application period T3 occurs at an electrical angle of 60 degrees to 120 degrees and at an electrical angle of 150 degrees to 210 degrees. Further, in waveform example 32, the low side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees, 120 to 150 electrical degrees, and 210 to 360 electrical degrees.
波形例32では、第1オン固定期間T1は、第1オン固定期間T1uと、第1オン固定期間T1vとを含む。波形例32では、電気角60度~電気角120度が第1オン固定期間T1uである。波形例32では、電気角150度~電気角210度が第1オン固定期間T1vである。
In waveform example 32, the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v. In waveform example 32, the first fixed ON period T1u is from 60 electrical degrees to 120 electrical degrees. In waveform example 32, the first fixed ON period T1v is between 150 electrical degrees and 210 electrical degrees.
波形例32では、第2オン固定期間T2は、第2オン固定期間T2uと、第2オン固定期間T2vと、第2オン固定期間T2wとを含む。波形例32では、電気角210度~電気角330度が第2オン固定期間T2uである。波形例32では、電気角0度~電気角60度および電気角330度~電気角360度が第2オン固定期間T2vである。波形例32では、電気角120度~電気角150度が第2オン固定期間T2wである。
In waveform example 32, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 32, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In waveform example 32, the second fixed ON period T2v is from 0 to 60 electrical degrees and from 330 to 360 electrical degrees. In waveform example 32, the second fixed ON period T2w is between 120 electrical degrees and 150 electrical degrees.
波形例32では、3相のうちU相において、第1オン固定期間T1uが、第1オン固定期間T1wと異なる。詳しくは、波形例32では、第1オン固定期間T1uが60度であるのに対し、第1オン固定期間T1wは無い。すなわち、波形例32では、第1オン固定期間T1uが第1オン固定期間T1wよりも長い。なお、第1オン固定期間T1vは、第1オン固定期間T1uと同じである。したがって、図52Bに示すように、U相の第1半導体スイッチング素子Up(H(ハイサイド))のスイッチング損失がW相に比べて小さくなっている。
In waveform example 32, the first fixed ON period T1u differs from the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 32, the first fixed ON period T1u is 60 degrees, but there is no first fixed ON period T1w. That is, in waveform example 32, the first fixed ON period T1u is longer than the first fixed ON period T1w. The first fixed ON period T1v is the same as the first fixed ON period T1u. Therefore, as shown in FIG. 52B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than that of the W-phase.
波形例32では、第2オン固定期間T2uが、第2オン固定期間T2vおよび第2オン固定期間T2wと異なる。詳しくは、波形例32では、第2オン固定期間T2uが120度であるのに対し、第2オン固定期間T2vは90度であり、および第2オン固定期間T2wは30度である。すなわち、波形例32では、第2オン固定期間T2uが第2オン固定期間T2vおよび第2オン固定期間T2wよりも長い。したがって、図52Bに示すように、U相の第2半導体スイッチング素子Un(L(ロウサイド))のスイッチング損失がV相およびW相に比べて小さくなっている。
In waveform example 32, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in waveform example 32, the second fixed ON period T2u is 120 degrees, the second fixed ON period T2v is 90 degrees, and the second fixed ON period T2w is 30 degrees. That is, in waveform example 32, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 52B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
以上、図52Aおよび図52Bを参照して説明したように、波形例32においても、波形例1と同様に、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。波形例32では、U相の第1半導体スイッチング素子Upと、U相の第2半導体スイッチング素子Unとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 52A and 52B , in waveform example 32, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 32, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un.
また、波形例32では、図52Bに示すように、V相の第1半導体スイッチング素子Vpと、V相の第2半導体スイッチング素子Vnと、W相の第2半導体スイッチング素子Wnとの発熱についても同時に抑えることができる。
Further, in waveform example 32, as shown in FIG. 52B, the heat generated by the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
図53Aおよび図53Bを参照して、波形例33について説明する。図53Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図53Bは、スイッチング損失を示す図である。
A waveform example 33 will be described with reference to FIGS. 53A and 53B. FIG. 53A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 53B is a diagram showing switching losses.
図53Aに示すように、波形例33は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例33は、電気角60度~電気角120度、電気角180度~電気角210度および電気角330度~電気角360度において、いずれか1相の出力が1に固定される波形である。また、波形例33は、電気角0度~電気角60度、電気角120度~電気角180度および電気角210度~電気角330度において、いずれか1相の出力が0に固定される波形である。波形例33では、電気角60度~電気角120度、電気角180度~電気角210度および電気角330度~電気角360度において、ハイサイドオン適用期間T3である。また、波形例33では、電気角0度~電気角60度、電気角120度~電気角180度および電気角210度~電気角330度において、ロウサイドオン適用期間T4である。
As shown in FIG. 53A, in waveform example 33, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, in waveform example 33, the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 120 degrees, from 180 degrees to 210 degrees, and from 330 degrees to 360 degrees. waveform. In waveform example 33, the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 electrical degrees, 120 to 180 electrical degrees, and 210 to 330 electrical degrees. waveform. In waveform example 33, the high side-on application period T3 is at an electrical angle of 60 to 120 electrical degrees, 180 to 210 electrical degrees, and 330 to 360 electrical degrees. Further, in waveform example 33, the low side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees, 120 to 180 electrical degrees, and 210 to 330 electrical degrees.
波形例33では、第1オン固定期間T1は、第1オン固定期間T1uと、第1オン固定期間T1vと、第1オン固定期間T1wとを含む。波形例33では、電気角60度~電気角120度が第1オン固定期間T1uである。波形例33では、電気角180度~電気角210度が第1オン固定期間T1vである。波形例33では、電気角330度~電気角360度が第1オン固定期間T1wである。
In Waveform Example 33, the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w. In waveform example 33, the first fixed ON period T1u is from 60 electrical degrees to 120 electrical degrees. In waveform example 33, the first fixed ON period T1v is from 180 degrees to 210 degrees in electrical angle. In waveform example 33, the first fixed ON period T1w is from 330 electrical degrees to 360 electrical degrees.
波形例33では、第2オン固定期間T2は、第2オン固定期間T2uと、第2オン固定期間T2vと、第2オン固定期間T2wとを含む。波形例33では、電気角210度~電気角330度が第2オン固定期間T2uである。波形例33では、電気角0度~電気角60度が第2オン固定期間T2vである。波形例33では、電気角120度~電気角180度が第2オン固定期間T2wである。
In waveform example 33, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 33, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In waveform example 33, the second fixed ON period T2v is from 0 electrical angle to 60 electrical degrees. In waveform example 33, the second fixed ON period T2w is from 120 electrical degrees to 180 electrical degrees.
波形例33では、3相のうちU相において、第1オン固定期間T1uが、第1オン固定期間T1vおよび第1オン固定期間T1wと異なる。詳しくは、波形例33では、第1オン固定期間T1uが60度であるのに対し、第1オン固定期間T1vおよび第1オン固定期間T1wは30度である。すなわち、波形例33では、第1オン固定期間T1uが第1オン固定期間T1vおよび第1オン固定期間T1wよりも長い。したがって、図53Bに示すように、U相の第1半導体スイッチング素子Up(H(ハイサイド))のスイッチング損失がV相およびW相に比べて小さくなっている。
In waveform example 33, in the U phase among the three phases, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w. Specifically, in waveform example 33, the first fixed ON period T1u is 60 degrees, while the first fixed ON period T1v and the first fixed ON period T1w are 30 degrees. That is, in waveform example 33, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 53B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
波形例33では、第2オン固定期間T2uが、第2オン固定期間T2vおよび第2オン固定期間T2wと異なる。詳しくは、波形例33では、第2オン固定期間T2uが120度であるのに対し、第2オン固定期間T2vおよび第2オン固定期間T2wは60度である。すなわち、波形例33では、第2オン固定期間T2uが第2オン固定期間T2vおよび第2オン固定期間T2wよりも長い。したがって、図53Bに示すように、U相の第2半導体スイッチング素子Un(L(ロウサイド))のスイッチング損失がV相およびW相に比べて小さくなっている。
In waveform example 33, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in waveform example 33, the second fixed ON period T2u is 120 degrees, while the second fixed ON period T2v and the second fixed ON period T2w are 60 degrees. That is, in waveform example 33, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 53B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
以上、図53Aおよび図53Bを参照して説明したように、波形例33においても、波形例1と同様に、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。波形例33では、U相の第1半導体スイッチング素子Upと、U相の第2半導体スイッチング素子Unとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 53A and 53B , in waveform example 33, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 33, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un.
また、波形例33では、図53Bに示すように、V相の第1半導体スイッチング素子Vpと、V相の第2半導体スイッチング素子Vnと、W相の第1半導体スイッチング素子Wpと、W相の第2半導体スイッチング素子Wnとの発熱についても同時に抑えることができる。
In waveform example 33, as shown in FIG. 53B, the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
図54Aおよび図54Bを参照して、波形例34について説明する。図54Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図54Bは、スイッチング損失を示す図である。
A waveform example 34 will be described with reference to FIGS. 54A and 54B. FIG. 54A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 54B is a diagram showing switching losses.
図54Aに示すように、波形例34は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例34は、電気角75度~電気角105度および電気角150度~電気角240度において、いずれか1相の出力が1に固定される波形である。また、波形例34は、電気角0度~電気角75度、電気角105度~電気角150度および電気角240度~電気角360度において、いずれか1相の出力が0に固定される波形である。波形例34では、電気角75度~電気角105度および電気角150度~電気角240度において、ハイサイドオン適用期間T3である。また、波形例34では、電気角105度~電気角150度および電気角240度~電気角360度において、ロウサイドオン適用期間T4である。
As shown in FIG. 54A, in waveform example 34, the output voltage of any one phase is fixed to 1 in a certain electrical angle section, and the output voltage of any one phase is fixed to 1 in another electrical angle section, depending on the electrical angle. is fixed to 0. More specifically, waveform example 34 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 75 degrees to 105 degrees and at an electrical angle of 150 degrees to 240 degrees. In waveform example 34, the output of any one phase is fixed to 0 at an electrical angle of 0 to 75 electrical degrees, 105 to 150 electrical degrees, and 240 to 360 electrical degrees. waveform. In waveform example 34, the high-side-on application period T3 occurs at an electrical angle of 75 degrees to 105 degrees and at an electrical angle of 150 degrees to 240 degrees. Further, in waveform example 34, the low side-on application period T4 occurs at an electrical angle of 105 degrees to 150 degrees and at an electrical angle of 240 degrees to 360 degrees.
波形例34では、第1オン固定期間T1は、第1オン固定期間T1uと、第1オン固定期間T1vとを含む。波形例34では、電気角75度~電気角105度が第1オン固定期間T1uである。波形例34では、電気角150度~電気角240度が第1オン固定期間T1vである。
In waveform example 34, the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v. In waveform example 34, the first fixed ON period T1u is from 75 electrical degrees to 105 electrical degrees. In waveform example 34, the first fixed ON period T1v is from 150 electrical degrees to 240 electrical degrees.
波形例34では、第2オン固定期間T2は、第2オン固定期間T2uと、第2オン固定期間T2vと、第2オン固定期間T2wとを含む。波形例34では、電気角240度~電気角330度が第2オン固定期間T2uである。波形例34では、電気角0度~電気角75度および電気角330度~電気角360度が第2オン固定期間T2vである。波形例34では、電気角105度~電気角150度が第2オン固定期間T2wである。
In waveform example 34, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 34, the second fixed ON period T2u is from 240 electrical degrees to 330 electrical degrees. In waveform example 34, the second fixed ON period T2v is from an electrical angle of 0 degrees to an electrical angle of 75 degrees and from an electrical angle of 330 degrees to an electrical angle of 360 degrees. In waveform example 34, the second fixed ON period T2w is from 105 electrical degrees to 150 electrical degrees.
波形例34では、3相のうちU相において、第1オン固定期間T1uが、第1オン固定期間T1vおよび第1オン固定期間T1wと異なる。詳しくは、波形例34では、第1オン固定期間T1vが90度であるのに対し、第1オン固定期間T1uは30度であり、第1オン固定期間T1wは無い。すなわち、波形例34では、第1オン固定期間T1vが第1オン固定期間T1uおよび第1オン固定期間T1wよりも長い。したがって、図54Bに示すように、V相の第1半導体スイッチング素子Vp(H(ハイサイド))のスイッチング損失がU相およびW相に比べて小さくなっている。
In waveform example 34, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 34, the first fixed ON period T1v is 90 degrees, the first fixed ON period T1u is 30 degrees, and there is no first fixed ON period T1w. That is, in waveform example 34, the first fixed ON period T1v is longer than the first fixed ON period T1u and the first fixed ON period T1w. Therefore, as shown in FIG. 54B, the switching loss of the V-phase first semiconductor switching element Vp (H (high side)) is smaller than those of the U-phase and W-phase.
波形例34では、第2オン固定期間T2uが、第2オン固定期間T2vおよび第2オン固定期間T2wと異なる。詳しくは、波形例34では、第2オン固定期間T2vが105度であるのに対し、第2オン固定期間T2uが90度あり、第2オン固定期間T2wは45度である。すなわち、波形例34では、第2オン固定期間T2vが第2オン固定期間T2uおよび第2オン固定期間T2wよりも長い。したがって、図54Bに示すように、V相の第2半導体スイッチング素子Vn(L(ロウサイド))のスイッチング損失がU相、W相に比べて小さくなっている。
In waveform example 34, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in waveform example 34, the second fixed ON period T2v is 105 degrees, the second fixed ON period T2u is 90 degrees, and the second fixed ON period T2w is 45 degrees. That is, in waveform example 34, the second fixed ON period T2v is longer than the second fixed ON period T2u and the second fixed ON period T2w. Therefore, as shown in FIG. 54B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
以上、図54Aおよび図54Bを参照して説明したように、波形例34においても、波形例1と同様に、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。波形例34では、V相の第1半導体スイッチング素子Vpと、V相の第2半導体スイッチング素子Vnとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 54A and 54B , in waveform example 34, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 34, the heat generation of the V-phase first semiconductor switching element Vp and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
また、波形例34では、図54Bに示すように、U相の第1半導体スイッチング素子Upと、U相の第2半導体スイッチング素子Unと、W相の第2半導体スイッチング素子Wnとの発熱についても同時に抑えることができる。
In waveform example 34, as shown in FIG. 54B, the heat generated by the U-phase first semiconductor switching element Up, the U-phase second semiconductor switching element Un, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
図55Aおよび図55Bを参照して、波形例35について説明する。図55Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図55Bは、スイッチング損失を示す図である。
A waveform example 35 will be described with reference to FIGS. 55A and 55B. FIG. 55A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 55B is a diagram showing switching losses.
図55Aに示すように、波形例35は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例35は、電気角75度~電気角105度、電気角150度~電気角210度および電気角330度~電気角360度において、いずれか1相の出力が1に固定される波形である。また、波形例35は、電気角0度~電気角75度、電気角105度~電気角150度および電気角210度~電気角330度において、いずれか1相の出力が0に固定される波形である。波形例35では、電気角75度~電気角105度、電気角150度~電気角210度および電気角330度~電気角360度において、ハイサイドオン適用期間T3である。また、波形例35では、電気角0度~電気角75度、電気角105度~電気角150度および電気角210度~電気角330度において、ロウサイドオン適用期間T4である。
As shown in FIG. 55A, in waveform example 35, the output voltage of any one phase is fixed to 1 in a certain electrical angle section, and the output voltage of any one phase is fixed to 1 in another electrical angle section, depending on the electrical angle. is fixed to 0. Specifically, in waveform example 35, the output of any one phase is fixed to 1 at an electrical angle of 75 degrees to 105 degrees, from 150 degrees to 210 degrees, and from 330 degrees to 360 degrees. waveform. In waveform example 35, the output of any one phase is fixed to 0 at an electrical angle of 0 to 75 electrical degrees, 105 to 150 electrical degrees, and 210 to 330 electrical degrees. waveform. In waveform example 35, the high-side-on application period T3 is at an electrical angle of 75 degrees to 105 degrees, an electrical angle of 150 degrees to 210 degrees, and an electrical angle of 330 degrees to 360 degrees. Further, in waveform example 35, the low side-on application period T4 occurs at an electrical angle of 0 to 75 electrical degrees, 105 to 150 electrical degrees, and 210 to 330 electrical degrees.
波形例35では、第1オン固定期間T1は、第1オン固定期間T1uと、第1オン固定期間T1vと、第1オン固定期間T1wとを含む。波形例35では、電気角75度~電気角105度が第1オン固定期間T1uである。波形例35では、電気角150度~電気角210度が第1オン固定期間T1vである。波形例35では、電気角330度~電気角360度が第1オン固定期間T1wである。
In Waveform Example 35, the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w. In waveform example 35, the first fixed ON period T1u is from 75 electrical degrees to 105 electrical degrees. In waveform example 35, the first fixed ON period T1v is from 150 electrical degrees to 210 electrical degrees. In waveform example 35, the first fixed ON period T1w is from 330 electrical degrees to 360 electrical degrees.
波形例35では、第2オン固定期間T2は、第2オン固定期間T2uと、第2オン固定期間T2vと、第2オン固定期間T2wとを含む。波形例35では、電気角210度~電気角330度が第2オン固定期間T2uである。波形例35では、電気角0度~電気角75度が第2オン固定期間T2vである。波形例35では、電気角105度~電気角150度が第2オン固定期間T2wである。
In Waveform Example 35, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 35, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In waveform example 35, the second fixed ON period T2v is from 0 electrical angle to 75 electrical degrees. In waveform example 35, the second fixed ON period T2w is from 105 electrical degrees to 150 electrical degrees.
波形例35では、3相のうちU相において、第1オン固定期間T1vが、第1オン固定期間T1uおよび第1オン固定期間T1wと異なる。詳しくは、波形例35では、第1オン固定期間T1vが60度であるのに対し、第1オン固定期間T1uおよび第1オン固定期間T1wは30度である。すなわち、波形例35では、第1オン固定期間T1vが第1オン固定期間T1uおよび第1オン固定期間T1wよりも長い。したがって、図55Bに示すように、V相の第1半導体スイッチング素子Vp(H(ハイサイド))のスイッチング損失がU相およびW相に比べて小さくなっている。
In waveform example 35, the first fixed ON period T1v differs from the first fixed ON period T1u and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 35, the first fixed ON period T1v is 60 degrees, while the first fixed ON period T1u and the first fixed ON period T1w are 30 degrees. That is, in waveform example 35, the first fixed ON period T1v is longer than the first fixed ON period T1u and the first fixed ON period T1w. Therefore, as shown in FIG. 55B, the switching loss of the V-phase first semiconductor switching element Vp (H (high side)) is smaller than those of the U-phase and W-phase.
波形例35では、第2オン固定期間T2uが、第2オン固定期間T2vおよび第2オン固定期間T2wと異なる。詳しくは、波形例35では、第2オン固定期間T2uが120度であるのに対し、第2オン固定期間T2vは75度であり、第2オン固定期間T2wは45度である。すなわち、波形例35では、第2オン固定期間T2uが第2オン固定期間T2vおよび第2オン固定期間T2wよりも長い。したがって、図55Bに示すように、U相の第2半導体スイッチング素子Un(L(ロウサイド))のスイッチング損失がV相、W相に比べて小さくなっている。
In waveform example 35, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in waveform example 35, the second fixed ON period T2u is 120 degrees, the second fixed ON period T2v is 75 degrees, and the second fixed ON period T2w is 45 degrees. That is, in waveform example 35, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 55B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
以上、図55Aおよび図55Bを参照して説明したように、波形例35においても、波形例1と同様に、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。波形例35では、V相の第1半導体スイッチング素子Vpと、U相の第2半導体スイッチング素子Unとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 55A and 55B , in waveform example 35 as well as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In the waveform example 35, the heat generation of the V-phase first semiconductor switching element Vp and the U-phase second semiconductor switching element Un can be suppressed at the same time.
また、波形例35では、図55Bに示すように、U相の第1半導体スイッチング素子Upと、V相の第2半導体スイッチング素子Vnと、W相の第1半導体スイッチング素子Wpと、W相の第2半導体スイッチング素子Wnとの発熱についても同時に抑えることができる。
In waveform example 35, as shown in FIG. 55B, the U-phase first semiconductor switching element Up, the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
図56Aおよび図56Bを参照して、波形例36について説明する。図56Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図56Bは、スイッチング損失を示す図である。
A waveform example 36 will be described with reference to FIGS. 56A and 56B. FIG. 56A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 56B is a diagram showing switching losses.
図56Aに示すように、波形例36は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例36は、電気角150度~電気角240度および電気角330度~電気角360度において、いずれか1相の出力が1に固定される波形である。また、波形例36は、電気角0度~電気角150度および電気角240度~電気角330度において、いずれか1相の出力が0に固定される波形である。波形例36では、電気角150度~電気角240度および電気角330度~電気角360度において、ハイサイドオン適用期間T3である。また、波形例36では、電気角0度~電気角150度および電気角240度~電気角330度において、ロウサイドオン適用期間T4である。
As shown in FIG. 56A , in waveform example 36, the output voltage of any one phase is fixed to 1 in a certain electrical angle section, and the output voltage of any one phase is fixed to 1 in another electrical angle section, depending on the electrical angle. is fixed to 0. More specifically, waveform example 36 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 150 degrees to 240 degrees and at an electrical angle of 330 degrees to 360 degrees. Waveform example 36 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 degree to 150 electrical degrees and at an electrical angle of 240 degrees to 330 electrical degrees. In waveform example 36, the high side-on application period T3 occurs at an electrical angle of 150 degrees to 240 degrees and at an electrical angle of 330 degrees to 360 degrees. Further, in waveform example 36, the low side-on application period T4 occurs at an electrical angle of 0 to 150 electrical degrees and at an electrical angle of 240 to 330 electrical degrees.
波形例36では、第1オン固定期間T1は、第1オン固定期間T1vと、第1オン固定期間T1wとを含む。波形例36では、電気角150度~電気角240度が第1オン固定期間T1vである。波形例36では、電気角330度~電気角360度が第1オン固定期間T1wである。
In waveform example 36, the first fixed ON period T1 includes a first fixed ON period T1v and a first fixed ON period T1w. In waveform example 36, the first fixed ON period T1v is from 150 electrical degrees to 240 electrical degrees. In waveform example 36, the first fixed ON period T1w is between 330 electrical degrees and 360 electrical degrees.
波形例36では、第2オン固定期間T2は、第2オン固定期間T2uと、第2オン固定期間T2vと、第2オン固定期間T2wとを含む。波形例36では、電気角240度~電気角330度が第2オン固定期間T2uである。波形例36では、電気角0度~電気角90度が第2オン固定期間T2vである。波形例36では、電気角90度~電気角150度が第2オン固定期間T2wである。
In waveform example 36, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 36, the second fixed ON period T2u is from 240 electrical degrees to 330 electrical degrees. In waveform example 36, the second fixed ON period T2v is from 0 electrical angle to 90 electrical degrees. In waveform example 36, the second fixed ON period T2w is from 90 electrical degrees to 150 electrical degrees.
波形例36では、3相のうちV相において、第1オン固定期間T1vが、第1オン固定期間T1uおよび第1オン固定期間T1wと異なる。詳しくは、波形例36では、第1オン固定期間T1vが90度であるのに対し、第1オン固定期間T1uは無く、第1オン固定期間T1wは30度である。すなわち、波形例36では、第1オン固定期間T1vが第1オン固定期間T1uおよび第1オン固定期間T1wよりも長い。したがって、図56Bに示すように、V相の第1半導体スイッチング素子Vp(H(ハイサイド))のスイッチング損失がU相およびW相に比べて小さくなっている。
In waveform example 36, in the V phase among the three phases, the first fixed ON period T1v differs from the first fixed ON period T1u and the first fixed ON period T1w. Specifically, in waveform example 36, the first fixed ON period T1v is 90 degrees, whereas the first fixed ON period T1u is absent and the first fixed ON period T1w is 30 degrees. That is, in waveform example 36, the first fixed ON period T1v is longer than the first fixed ON period T1u and the first fixed ON period T1w. Therefore, as shown in FIG. 56B, the switching loss of the V-phase first semiconductor switching element Vp (H (high side)) is smaller than those of the U-phase and W-phase.
波形例36では、第2オン固定期間T2uが、第2オン固定期間T2vおよび第2オン固定期間T2wと異なる。詳しくは、波形例36では、第2オン固定期間T2uが90度であるのに対し、第2オン固定期間T2wは60度である。すなわち、波形例36では、第2オン固定期間T2uが第2オン固定期間T2wよりも長い。なお、第2オン固定期間T2vは、第2オン固定期間T2uと同じである。したがって、図56Bに示すように、U相の第2半導体スイッチング素子Un(L(ロウサイド))のスイッチング損失がW相に比べて小さくなっている。
In waveform example 36, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in waveform example 36, the second fixed ON period T2u is 90 degrees, while the second fixed ON period T2w is 60 degrees. That is, in waveform example 36, the second fixed ON period T2u is longer than the second fixed ON period T2w. The second fixed ON period T2v is the same as the second fixed ON period T2u. Therefore, as shown in FIG. 56B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than that of the W-phase.
以上、図56Aおよび図56Bを参照して説明したように、波形例36においても、波形例1と同様に、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。波形例36では、V相の第1半導体スイッチング素子Vpと、U相の第2半導体スイッチング素子Unとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 56A and 56B , in waveform example 36, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 36, it is possible to simultaneously suppress the heat generation of the V-phase first semiconductor switching element Vp and the U-phase second semiconductor switching element Un.
また、波形例36では、図56Bに示すように、V相の第2半導体スイッチング素子Vnと、W相の第1半導体スイッチング素子Wpと、W相の第2半導体スイッチング素子Wnとの発熱についても同時に抑えることができる。
In waveform example 36, as shown in FIG. 56B, the heat generated by the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
図57Aおよび図57Bを参照して、波形例37について説明する。図57Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図57Bは、スイッチング損失を示す図である。
A waveform example 37 will be described with reference to FIGS. 57A and 57B. FIG. 57A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 57B is a diagram showing switching losses.
図57Aに示すように、波形例37は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例37は、電気角0度~電気角30度、電気角150度~電気210度および電気角330度~電気360度において、いずれか1相の出力が1に固定される波形である。また、波形例37は、電気角30度~電気角150度および電気角210度~電気角330度において、いずれか1相の出力が0に固定される波形である。波形例37では、電気角0度~電気角30度、電気角150度~電気210度および電気角330度~電気360度において、ハイサイドオン適用期間T3である。また、波形例37では、電気角30度~電気角150度および電気角210度~電気角330度において、ロウサイドオン適用期間T4である。
As shown in FIG. 57A, in waveform example 37, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, waveform example 37 is a waveform in which the output of any one phase is fixed to 1 in the electrical angle of 0 to 30 electrical degrees, the electrical angle of 150 to 210 electrical degrees, and the electrical angle of 330 to 360 electrical degrees. is. Waveform example 37 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 30 degrees to 150 degrees and at an electrical angle of 210 degrees to 330 degrees. In waveform example 37, the high-side-on application period T3 occurs at an electrical angle of 0 to 30 electrical degrees, from 150 to 210 electrical degrees, and from 330 to 360 electrical degrees. In waveform example 37, the low-side-on application period T4 occurs at an electrical angle of 30 degrees to 150 degrees and at an electrical angle of 210 degrees to 330 degrees.
波形例37では、第1オン固定期間T1は、第1オン固定期間T1vと、第1オン固定期間T1wとを含む。波形例37では、電気角150度~電気角210度が第1オン固定期間T1vである。波形例37では、電気角0度~電気角30度および電気角330度~電気角360度が第1オン固定期間T1wである。
In waveform example 37, the first fixed ON period T1 includes a first fixed ON period T1v and a first fixed ON period T1w. In waveform example 37, the first fixed ON period T1v is from 150 electrical degrees to 210 electrical degrees. In waveform example 37, the first fixed ON period T1w is from an electrical angle of 0 degree to an electrical angle of 30 degrees and from an electrical angle of 330 degrees to an electrical angle of 360 degrees.
波形例37では、第2オン固定期間T2は、第2オン固定期間T2uと、第2オン固定期間T2vと、第2オン固定期間T2wとを含む。波形例37では、電気角210度~電気角330度が第2オン固定期間T2uである。波形例37では、電気角30度~電気角90度が第2オン固定期間T2vである。波形例37では、電気角90度~電気角150度が第2オン固定期間T2wである。
In Waveform Example 37, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 37, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In waveform example 37, the second fixed ON period T2v is from 30 electrical degrees to 90 electrical degrees. In waveform example 37, the second fixed ON period T2w is from 90 electrical degrees to 150 electrical degrees.
波形例37では、3相のうちU相において、第1オン固定期間T1vが、第1オン固定期間T1uと異なる。詳しくは、波形例37では、第1オン固定期間T1vが60度であるのに対し、第1オン固定期間T1uは無い。すなわち、波形例37では、第1オン固定期間T1vが第1オン固定期間T1uよりも長い。なお、第1オン固定期間T1wは、第1オン固定期間T1vと同じである。したがって、図57Bに示すように、V相の第1半導体スイッチング素子Up(H(ハイサイド))のスイッチング損失がU相に比べて小さくなっている。
In waveform example 37, the first fixed ON period T1v differs from the first fixed ON period T1u in the U phase among the three phases. Specifically, in waveform example 37, the first fixed ON period T1v is 60 degrees, but there is no first fixed ON period T1u. That is, in waveform example 37, the first fixed ON period T1v is longer than the first fixed ON period T1u. The first fixed ON period T1w is the same as the first fixed ON period T1v. Therefore, as shown in FIG. 57B, the switching loss of the V-phase first semiconductor switching element Up (H (high side)) is smaller than that of the U-phase.
波形例37では、第2オン固定期間T2uが、第2オン固定期間T2vおよび第2オン固定期間T2wと異なる。詳しくは、波形例37では、第2オン固定期間T2uが120度であるのに対し、第2オン固定期間T2vおよび第2オン固定期間T2wは60度である。すなわち、波形例37では、第2オン固定期間T2uが第2オン固定期間T2vおよび第2オン固定期間T2wよりも長い。したがって、図57Bに示すように、U相の第2半導体スイッチング素子Un(L(ロウサイド))のスイッチング損失がV相、W相に比べて小さくなっている。
In waveform example 37, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in Waveform Example 37, the second fixed ON period T2u is 120 degrees, while the second fixed ON period T2v and the second fixed ON period T2w are 60 degrees. That is, in waveform example 37, the second fixed on period T2u is longer than the second fixed on period T2v and the second fixed on period T2w. Therefore, as shown in FIG. 57B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
以上、図57Aおよび図57Bを参照して説明したように、波形例37においても、波形例1と同様に、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。波形例37では、V相の第1半導体スイッチング素子Vpと、U相の第2半導体スイッチング素子Unとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 57A and 57B , in waveform example 37, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 37, it is possible to simultaneously suppress the heat generation of the V-phase first semiconductor switching element Vp and the U-phase second semiconductor switching element Un.
また、波形例37では、図57Bに示すように、V相の第2半導体スイッチング素子Vnと、W相の第1半導体スイッチング素子Wpと、W相の第2半導体スイッチング素子Wnとの発熱についても同時に抑えることができる。
In waveform example 37, as shown in FIG. 57B, the heat generated by the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
図58Aおよび図58Bを参照して、波形例38について説明する。図58Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図58Bは、スイッチング損失を示す図である。
A waveform example 38 will be described with reference to FIGS. 58A and 58B. FIG. 58A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 58B is a diagram showing switching losses.
図58Aに示すように、波形例38は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例38は、電気角45度~電気角135度および電気角150度~電気角240度において、いずれか1相の出力が1に固定される波形である。また、波形例38は、電気角0度~電気角45度、電気角135度~電気角150度および電気角240度~電気角360度において、いずれか1相の出力が0に固定される波形である。波形例38では、電気角45度~電気角135度および電気角150度~電気角240度において、ハイサイドオン適用期間T3である。また、波形例38では、電気角0度~電気角45度、電気角135度~電気角150度および電気角240度~電気角360度において、ロウサイドオン適用期間T4である。
As shown in FIG. 58A , in waveform example 38, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. More specifically, waveform example 38 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 45 degrees to 135 degrees and at an electrical angle of 150 degrees to 240 degrees. In waveform example 38, the output of any one phase is fixed to 0 at an electrical angle of 0 to 45 electrical degrees, 135 to 150 electrical degrees, and 240 to 360 electrical degrees. waveform. In waveform example 38, the high-side-on application period T3 occurs at an electrical angle of 45 degrees to 135 degrees and at an electrical angle of 150 degrees to 240 degrees. Further, in waveform example 38, the low side-on application period T4 occurs at an electrical angle of 0 to 45 electrical degrees, 135 to 150 electrical degrees, and 240 to 360 electrical degrees.
波形例38では、第1オン固定期間T1は、第1オン固定期間T1uと、第1オン固定期間T1vとを含む。波形例38では、電気角45度~電気角135度が第1オン固定期間T1uである。波形例38では、電気角150度~電気角240度が第1オン固定期間T1vである。
In waveform example 38, the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v. In waveform example 38, the first fixed ON period T1u is from 45 electrical degrees to 135 electrical degrees. In waveform example 38, the first fixed ON period T1v is from 150 electrical degrees to 240 electrical degrees.
波形例38では、第2オン固定期間T2は、第2オン固定期間T2uと、第2オン固定期間T2vと、第2オン固定期間T2wとを含む。波形例38では、電気角240度~電気角330度が第2オン固定期間T2uである。波形例38では、電気角0度~電気角45度および電気角330度~電気角360度が第2オン固定期間T2vである。波形例38では、電気角135度~電気角150度が第2オン固定期間T2wである。
In Waveform Example 38, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 38, the second fixed ON period T2u is from 240 electrical degrees to 330 electrical degrees. In waveform example 38, the second fixed ON period T2v is from an electrical angle of 0 degree to an electrical angle of 45 degrees and from an electrical angle of 330 degrees to an electrical angle of 360 degrees. In waveform example 38, the second fixed ON period T2w is from 135 electrical degrees to 150 electrical degrees.
波形例38では、3相のうちU相において、第1オン固定期間T1uが、第1オン固定期間T1wと異なる。詳しくは、波形例38では、第1オン固定期間T1uが90度であるのに対し、第1オン固定期間T1wは無い。すなわち、波形例38では、第1オン固定期間T1uが第1オン固定期間T1wよりも長い。なお、第1オン固定期間T1vは、第1オン固定期間T1uと同じである。したがって、図58Bに示すように、U相の第1半導体スイッチング素子Up(H(ハイサイド))のスイッチング損失がW相に比べて小さくなっている。
In waveform example 38, the first fixed ON period T1u differs from the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 38, the first fixed ON period T1u is 90 degrees, but there is no first fixed ON period T1w. That is, in waveform example 38, the first fixed ON period T1u is longer than the first fixed ON period T1w. The first fixed ON period T1v is the same as the first fixed ON period T1u. Therefore, as shown in FIG. 58B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than that of the W-phase.
波形例38では、第2オン固定期間T2uが、第2オン固定期間T2vおよび第2オン固定期間T2wと異なる。詳しくは、波形例38では、第2オン固定期間T2uが90度であるのに対し、第2オン固定期間T2vは75度であり、第2オン固定期間T2wは15度である。すなわち、波形例38では、第2オン固定期間T2uが第2オン固定期間T2vおよび第2オン固定期間T2wよりも長い。したがって、図58Bに示すように、U相の第2半導体スイッチング素子Un(L(ロウサイド))のスイッチング損失がV相、W相に比べて小さくなっている。
In waveform example 38, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in waveform example 38, the second fixed ON period T2u is 90 degrees, the second fixed ON period T2v is 75 degrees, and the second fixed ON period T2w is 15 degrees. That is, in waveform example 38, the second fixed on period T2u is longer than the second fixed on period T2v and the second fixed on period T2w. Therefore, as shown in FIG. 58B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
以上、図58Aおよび図58Bを参照して説明したように、波形例38においても、波形例1と同様に、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。波形例38では、U相の第1半導体スイッチング素子Upと、U相の第2半導体スイッチング素子Unとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 58A and 58B , in waveform example 38, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 38, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un.
また、波形例38では、図58Bに示すように、V相の第1半導体スイッチング素子Vpと、V相の第2半導体スイッチング素子Vnと、W相の第2半導体スイッチング素子Wnとの発熱についても同時に抑えることができる。
Further, in waveform example 38, as shown in FIG. 58B, the heat generated by the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
図59Aおよび図59Bを参照して、波形例39について説明する。図59Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図59Bは、スイッチング損失を示す図である。
A waveform example 39 will be described with reference to FIGS. 59A and 59B. FIG. 59A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 59B is a diagram showing switching losses.
図59Aに示すように、波形例39は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例39は、電気角45度~電気角135度、電気角150度~電気角210度および電気角330度~電気角360度において、いずれか1相の出力が1に固定される波形である。また、波形例39は、電気角0度~電気角45度、電気角135度~電気角150度および電気角210度~電気角330度において、いずれか1相の出力が0に固定される波形である。波形例39では、電気角45度~電気角135度、電気角150度~電気角210度および電気角330度~電気角360度において、ハイサイドオン適用期間T3である。また、波形例39では、電気角0度~電気角45度、電気角135度~電気角150度および電気角210度~電気角330度において、ロウサイドオン適用期間T4である。
As shown in FIG. 59A, in waveform example 39, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, in waveform example 39, the output of any one phase is fixed to 1 at an electrical angle of 45 degrees to 135 degrees, from 150 degrees to 210 degrees and from 330 degrees to 360 degrees. waveform. In waveform example 39, the output of any one phase is fixed to 0 at an electrical angle of 0 to 45 electrical degrees, 135 to 150 electrical degrees, and 210 to 330 electrical degrees. waveform. In waveform example 39, the high-side-on application period T3 is at an electrical angle of 45 degrees to 135 degrees, at an electrical angle of 150 degrees to 210 degrees, and at an electrical angle of 330 degrees to 360 degrees. Further, in waveform example 39, the low side-on application period T4 occurs at an electrical angle of 0 to 45 electrical degrees, 135 to 150 electrical degrees, and 210 to 330 electrical degrees.
波形例39では、第1オン固定期間T1は、第1オン固定期間T1uと、第1オン固定期間T1vと、第1オン固定期間T1wとを含む。波形例39では、電気角45度~電気角135度が第1オン固定期間T1uである。波形例39では、電気角150度~電気角210度が第1オン固定期間T1vである。波形例39では、電気角330度~電気角360度が第1オン固定期間T1wである。
In Waveform Example 39, the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w. In waveform example 39, the first fixed ON period T1u is from 45 electrical degrees to 135 electrical degrees. In waveform example 39, the first fixed ON period T1v is from 150 electrical degrees to 210 electrical degrees. In waveform example 39, the first fixed ON period T1w is from 330 electrical degrees to 360 electrical degrees.
波形例39では、第2オン固定期間T2は、第2オン固定期間T2uと、第2オン固定期間T2vと、第2オン固定期間T2wとを含む。波形例39では、電気角210度~電気角330度が第2オン固定期間T2uである。波形例39では、電気角0度~電気角45度が第2オン固定期間T2vである。波形例39では、電気角135度~電気角150度が第2オン固定期間T2wである。
In Waveform Example 39, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 39, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In waveform example 39, the second fixed ON period T2v is from 0 electrical angle to 45 electrical degrees. In Waveform Example 39, the second fixed ON period T2w is from 135 electrical degrees to 150 electrical degrees.
波形例39では、3相のうちU相において、第1オン固定期間T1uが、第1オン固定期間T1vおよび第1オン固定期間T1wと異なる。詳しくは、波形例39では、第1オン固定期間T1uが90度であるのに対し、第1オン固定期間T1vは60度であり、第1オン固定期間T1wは30度である。すなわち、波形例39では、第1オン固定期間T1uが第1オン固定期間T1vおよび第1オン固定期間T1wよりも長い。したがって、図59Bに示すように、U相の第1半導体スイッチング素子Up(H(ハイサイド))のスイッチング損失がV相およびW相に比べて小さくなっている。
In waveform example 39, the first fixed ON period T1u differs from the first fixed ON period T1v and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 39, the first fixed ON period T1u is 90 degrees, the first fixed ON period T1v is 60 degrees, and the first fixed ON period T1w is 30 degrees. That is, in waveform example 39, the first fixed ON period T1u is longer than the first fixed ON period T1v and the first fixed ON period T1w. Therefore, as shown in FIG. 59B, the switching loss of the U-phase first semiconductor switching element Up (H (high side)) is smaller than those of the V-phase and W-phase.
波形例39では、第2オン固定期間T2uが、第2オン固定期間T2vおよび第2オン固定期間T2wと異なる。詳しくは、波形例39では、第2オン固定期間T2uが120度であるのに対し、第2オン固定期間T2vは45度であり、第2オン固定期間T2wは15度である。すなわち、波形例39では、第2オン固定期間T2uが第2オン固定期間T2vおよび第2オン固定期間T2wよりも長い。したがって、図59Bに示すように、U相の第2半導体スイッチング素子Un(L(ロウサイド))のスイッチング損失がV相、W相に比べて小さくなっている。
In waveform example 39, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in Waveform Example 39, the second fixed ON period T2u is 120 degrees, the second fixed ON period T2v is 45 degrees, and the second fixed ON period T2w is 15 degrees. That is, in Waveform Example 39, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 59B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
以上、図59Aおよび図59Bを参照して説明したように、波形例39においても、波形例1と同様に、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。波形例39では、U相の第1半導体スイッチング素子Upと、U相の第2半導体スイッチング素子Unとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 59A and 59B , in waveform example 39, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 39, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un.
また、波形例39では、図59Bに示すように、V相の第1半導体スイッチング素子Vpと、V相の第2半導体スイッチング素子Vnと、W相の第1半導体スイッチング素子Wpと、W相の第2半導体スイッチング素子Wnとの発熱についても同時に抑えることができる。
In waveform example 39, as shown in FIG. 59B, the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
図60Aおよび図60Bを参照して、波形例40について説明する。図60Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図60Bは、スイッチング損失を示す図である。
A waveform example 40 will be described with reference to FIGS. 60A and 60B. FIG. 60A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 60B is a diagram showing switching losses.
図60Aに示すように、波形例40は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例40は、電気角60度~電気角120度、電気角150度~電気角240度および電気角330度~電気角360度において、いずれか1相の出力が1に固定される波形である。また、波形例40は、電気角0度~電気角60度、電気角120度~電気角150度および電気角240度~電気角330度において、いずれか1相の出力が0に固定される波形である。波形例40では、電気角60度~電気角120度、電気角150度~電気角240度および電気角330度~電気角360度において、ハイサイドオン適用期間T3である。また、波形例40では、電気角0度~電気角60度、電気角120度~電気角150度および電気角240度~電気角330度において、ロウサイドオン適用期間T4である。
As shown in FIG. 60A, in the waveform example 40, the output voltage of any one phase is fixed to 1 in a certain electrical angle section according to the electrical angle, and the output voltage of any one phase is fixed to 1 in another electrical angle section. is fixed to 0. Specifically, in waveform example 40, the output of any one phase is fixed to 1 at an electrical angle of 60 degrees to 120 degrees, from 150 degrees to 240 degrees, and from 330 degrees to 360 degrees. waveform. Further, in waveform example 40, the output of any one phase is fixed to 0 at an electrical angle of 0 to 60 degrees, 120 to 150 electrical degrees, and 240 to 330 electrical degrees. waveform. In waveform example 40, the high-side-on application period T3 is at an electrical angle of 60 to 120 electrical degrees, 150 to 240 electrical degrees, and 330 to 360 electrical degrees. Further, in waveform example 40, the low side-on application period T4 occurs at an electrical angle of 0 to 60 electrical degrees, 120 to 150 electrical degrees, and 240 to 330 electrical degrees.
波形例40では、第1オン固定期間T1は、第1オン固定期間T1uと、第1オン固定期間T1vと、第1オン固定期間T1wとを含む。波形例40では、電気角60度~電気角120度が第1オン固定期間T1uである。波形例40では、電気角150度~電気角240度が第1オン固定期間T1vである。波形例40では、電気角330度~電気角360度が第1オン固定期間T1wである。
In waveform example 40, the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w. In waveform example 40, the first fixed ON period T1u is from 60 electrical degrees to 120 electrical degrees. In waveform example 40, the first fixed ON period T1v is from 150 electrical degrees to 240 electrical degrees. In waveform example 40, the first fixed ON period T1w is from 330 electrical degrees to 360 electrical degrees.
波形例40では、第2オン固定期間T2は、第2オン固定期間T2uと、第2オン固定期間T2vと、第2オン固定期間T2wとを含む。波形例40では、電気角240度~電気角330度が第2オン固定期間T2uである。波形例40では、電気角0度~電気角60度が第2オン固定期間T2vである。波形例40では、電気角120度~電気角150度が第2オン固定期間T2wである。
In waveform example 40, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 40, the second fixed ON period T2u is from 240 electrical degrees to 330 electrical degrees. In waveform example 40, the second fixed ON period T2v is from 0 electrical angle to 60 electrical degrees. In the waveform example 40, the second fixed ON period T2w is between 120 electrical degrees and 150 electrical degrees.
波形例40では、3相のうちV相において、第1オン固定期間T1vが、第1オン固定期間T1uおよび第1オン固定期間T1wと異なる。詳しくは、波形例40では、第1オン固定期間T1vが90度であるのに対し、第1オン固定期間T1uが60度であり、第1オン固定期間T1wは30度である。すなわち、波形例40では、第1オン固定期間T1vが第1オン固定期間T1uおよび第1オン固定期間T1wよりも長い。したがって、図60Bに示すように、U相の第1半導体スイッチング素子Vp(H(ハイサイド))のスイッチング損失がU相およびW相に比べて小さくなっている。
In waveform example 40, in the V phase among the three phases, the first fixed ON period T1v is different from the first fixed ON period T1u and the first fixed ON period T1w. Specifically, in waveform example 40, the first fixed ON period T1v is 90 degrees, the first fixed ON period T1u is 60 degrees, and the first fixed ON period T1w is 30 degrees. That is, in waveform example 40, the first fixed ON period T1v is longer than the first fixed ON period T1u and the first fixed ON period T1w. Therefore, as shown in FIG. 60B, the switching loss of the U-phase first semiconductor switching element Vp (H (high side)) is smaller than those of the U-phase and W-phase.
波形例40では、第2オン固定期間T2uが、第2オン固定期間T2vおよび第2オン固定期間T2wと異なる。詳しくは、波形例40では、第2オン固定期間T2uが90度であるのに対し、第2オン固定期間T2vは60度、および第2オン固定期間T2wは30度である。すなわち、波形例40では、第2オン固定期間T2uが第2オン固定期間T2vおよび第2オン固定期間T2wよりも長い。したがって、図60Bに示すように、U相の第2半導体スイッチング素子Un(L(ロウサイド))のスイッチング損失がV相、W相に比べて小さくなっている。
In waveform example 40, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in waveform example 40, the second fixed ON period T2u is 90 degrees, the second fixed ON period T2v is 60 degrees, and the second fixed ON period T2w is 30 degrees. That is, in waveform example 40, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 60B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
以上、図60Aおよび図60Bを参照して説明したように、波形例40においても、波形例1と同様に、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。波形例40では、V相の第1半導体スイッチング素子Vpと、U相の第2半導体スイッチング素子Unとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 60A and 60B , in waveform example 40 as well as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In the waveform example 40, the heat generation of the V-phase first semiconductor switching element Vp and the U-phase second semiconductor switching element Un can be suppressed at the same time.
また、波形例40では、図60Bに示すように、U相の第1半導体スイッチング素子Upと、V相の第2半導体スイッチング素子Vnと、W相の第1半導体スイッチング素子Wpと、W相の第2半導体スイッチング素子Wnとの発熱についても同時に抑えることができる。
In waveform example 40, as shown in FIG. 60B, the U-phase first semiconductor switching element Up, the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
図61Aおよび図61Bを参照して、波形例41について説明する。図61Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図61Bは、スイッチング損失を示す図である。
A waveform example 41 will be described with reference to FIGS. 61A and 61B. FIG. 61A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 61B is a diagram showing switching losses.
図61Aに示すように、波形例41は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例41は、電気角0度~電気角30度、電気角60度~電気角120度、電気角150度~電気角210度および電気角330度~電気角360度において、いずれか1相の出力が1に固定される波形である。また、波形例41は、電気角30度~電気角60度、電気角120度~電気角150度および電気角210度~電気角330度において、いずれか1相の出力が0に固定される波形である。波形例41では、電気角0度~電気角30度、電気角60度~電気角120度、電気角150度~電気角210度および電気角330度~電気角360度において、ハイサイドオン適用期間T3である。また、波形例41では、電気角30度~電気角60度、電気角120度~電気角150度および電気角210度~電気角330度において、ロウサイドオン適用期間T4である。
As shown in FIG. 61A, in waveform example 41, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, the waveform example 41 is any of the electrical angles of 0 to 30 electrical degrees, 60 to 120 electrical degrees, 150 to 210 electrical degrees, and 330 to 360 electrical degrees. or is a waveform in which the output of one phase is fixed at 1. In waveform example 41, the output of any one phase is fixed to 0 at an electrical angle of 30 degrees to 60 degrees, from 120 degrees to 150 degrees and from 210 degrees to 330 degrees. waveform. In waveform example 41, high side ON is applied at an electrical angle of 0 to 30 electrical degrees, from 60 to 120 electrical degrees, from 150 to 210 electrical degrees, and from 330 to 360 electrical degrees. It is period T3. Further, in waveform example 41, the low side-on application period T4 is at an electrical angle of 30 to 60 electrical degrees, 120 to 150 electrical degrees, and 210 to 330 electrical degrees.
波形例41では、第1オン固定期間T1は、第1オン固定期間T1uと、第1オン固定期間T1vと、第1オン固定期間T1wとを含む。波形例41では、電気角60度~電気角120度が第1オン固定期間T1uである。波形例41では、電気角150度~電気角210度が第1オン固定期間T1vである。波形例41では、電気角0度~電気角30度および電気角330度~電気角360度が第1オン固定期間T1wである。
In waveform example 41, the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w. In waveform example 41, the first fixed ON period T1u is from 60 electrical degrees to 120 electrical degrees. In waveform example 41, the first fixed ON period T1v is from 150 electrical degrees to 210 electrical degrees. In waveform example 41, the first fixed ON period T1w is from an electrical angle of 0 degrees to an electrical angle of 30 degrees and from an electrical angle of 330 degrees to an electrical angle of 360 degrees.
波形例41では、第2オン固定期間T2は、第2オン固定期間T2uと、第2オン固定期間T2vと、第2オン固定期間T2wとを含む。波形例41では、電気角210度~電気角330度が第2オン固定期間T2uである。波形例41では、電気角30度~電気角60度が第2オン固定期間T2vである。波形例41では、電気角120度~電気角150度が第2オン固定期間T2wである。
In waveform example 41, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 41, the second fixed ON period T2u is from 210 electrical degrees to 330 electrical degrees. In waveform example 41, the second fixed ON period T2v is between 30 electrical degrees and 60 electrical degrees. In waveform example 41, the second fixed ON period T2w is from 120 electrical degrees to 150 electrical degrees.
波形例41では、第1オン固定期間T1uと、第1オン固定期間T1vと、第1オン固定期間T1vとは同じである。詳しくは、波形例41では、第1オン固定期間T1u、第1オン固定期間T1uと、第1オン固定期間T1vと、第1オン固定期間T1vとは60度である。
In waveform example 41, the first fixed ON period T1u, the first fixed ON period T1v, and the first fixed ON period T1v are the same. Specifically, in waveform example 41, the first fixed ON period T1u, the first fixed ON period T1u, the first fixed ON period T1v, and the first fixed ON period T1v are 60 degrees.
波形例41では、第2オン固定期間T2uが、第2オン固定期間T2vおよび第2オン固定期間T2wと異なる。詳しくは、波形例41では、第2オン固定期間T2uが120度であるのに対し、第2オン固定期間T2vおよび第2オン固定期間T2wは30度である。すなわち、波形例41では、第2オン固定期間T2uが第2オン固定期間T2vおよび第2オン固定期間T2wよりも長い。したがって、図61Bに示すように、U相の第2半導体スイッチング素子Un(L(ロウサイド))のスイッチング損失がV相、W相に比べて小さくなっている。
In waveform example 41, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in waveform example 41, the second fixed ON period T2u is 120 degrees, while the second fixed ON period T2v and the second fixed ON period T2w are 30 degrees. That is, in waveform example 41, the second fixed ON period T2u is longer than the second fixed ON period T2v and the second fixed ON period T2w. Therefore, as shown in FIG. 61B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
以上、図61Aおよび図61Bを参照して説明したように、波形例41においても、波形例1と同様に、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。波形例41では、U相の第1半導体スイッチング素子Upと、U相の第2半導体スイッチング素子Unとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 61A and 61B, in waveform example 41, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 41, it is possible to simultaneously suppress the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un.
また、波形例41では、図61Bに示すように、V相の第1半導体スイッチング素子Vpと、V相の第2半導体スイッチング素子Vnと、W相の第1半導体スイッチング素子Wpと、W相の第2半導体スイッチング素子Wnとの発熱についても同時に抑えることができる。
In waveform example 41, as shown in FIG. 61B, the V-phase first semiconductor switching element Vp, the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
図62Aおよび図62Bを参照して、波形例42について説明する。図62Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図62Bは、スイッチング損失を示す図である。
A waveform example 42 will be described with reference to FIGS. 62A and 62B. FIG. 62A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 62B is a diagram showing switching losses.
図62Aに示すように、波形例42は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例42は、電気角75度~電気角105度、電気角150度~電気角270度および電気角330度~電気角360度において、いずれか1相の出力が1に固定される波形である。また、波形例42は、電気角0度~電気角75度、電気角105度~電気角150度および電気角270度~電気角330度において、いずれか1相の出力が0に固定される波形である。波形例42では、電気角75度~電気角105度、電気角150度~電気角270度および電気角330度~電気角360度において、ハイサイドオン適用期間T3である。また、波形例42では、電気角0度~電気角75度、電気角105度~電気角150度および電気角270度~電気角330度において、ロウサイドオン適用期間T4である。
As shown in FIG. 62A , in waveform example 42, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, in waveform example 42, the output of any one phase is fixed to 1 at an electrical angle of 75 degrees to 105 degrees, from 150 degrees to 270 degrees, and from 330 degrees to 360 degrees. waveform. In waveform example 42, the output of any one phase is fixed to 0 at an electrical angle of 0 to 75 electrical degrees, 105 to 150 electrical degrees, and 270 to 330 electrical degrees. waveform. In waveform example 42, the high-side-on application period T3 is at an electrical angle of 75 degrees to 105 degrees, an electrical angle of 150 degrees to 270 degrees, and an electrical angle of 330 degrees to 360 degrees. Further, in waveform example 42, the low side-on application period T4 occurs at an electrical angle of 0 to 75 electrical degrees, 105 to 150 electrical degrees, and 270 to 330 electrical degrees.
波形例42では、第1オン固定期間T1は、第1オン固定期間T1uと、第1オン固定期間T1vと、第1オン固定期間T1wとを含む。波形例42では、電気角75度~電気角105度が第1オン固定期間T1uである。波形例42では、電気角150度~電気角270度が第1オン固定期間T1vである。波形例42では、電気角330度~電気角360度が第1オン固定期間T1wである。
In waveform example 42, the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w. In waveform example 42, the first fixed ON period T1u is from 75 electrical degrees to 105 electrical degrees. In waveform example 42, the first fixed ON period T1v is from 150 electrical degrees to 270 electrical degrees. In waveform example 42, the first fixed ON period T1w is from 330 electrical degrees to 360 electrical degrees.
波形例42では、第2オン固定期間T2は、第2オン固定期間T2uと、第2オン固定期間T2vと、第2オン固定期間T2wとを含む。波形例42では、電気角270度~電気角330度が第2オン固定期間T2uである。波形例42では、電気角0度~電気角75度が第2オン固定期間T2vである。波形例42では、電気角105度~電気角150度が第2オン固定期間T2wである。
In waveform example 42, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 42, the second fixed ON period T2u is from 270 degrees to 330 degrees in electrical angle. In waveform example 42, the second fixed ON period T2v is from 0 electrical angle to 75 electrical degrees. In waveform example 42, the second fixed ON period T2w is from 105 electrical degrees to 150 electrical degrees.
波形例42では、3相のうちV相において、第1オン固定期間T1vが、第1オン固定期間T1uおよび第1オン固定期間T1wと異なる。詳しくは、波形例42では、第1オン固定期間T1vが120度であるのに対し、第1オン固定期間T1uおよび第1オン固定期間T1wは30度である。すなわち、波形例42では、第1オン固定期間T1vが第1オン固定期間T1uおよび第1オン固定期間T1wよりも長い。したがって、図62Bに示すように、V相の第1半導体スイッチング素子Up(H(ハイサイド))のスイッチング損失がU相およびW相に比べて小さくなっている。
In waveform example 42, in the V phase among the three phases, the first fixed ON period T1v differs from the first fixed ON period T1u and the first fixed ON period T1w. Specifically, in waveform example 42, the first fixed ON period T1v is 120 degrees, while the first fixed ON period T1u and the first fixed ON period T1w are 30 degrees. That is, in waveform example 42, the first fixed ON period T1v is longer than the first fixed ON period T1u and the first fixed ON period T1w. Therefore, as shown in FIG. 62B, the switching loss of the V-phase first semiconductor switching element Up (H (high side)) is smaller than those of the U-phase and W-phase.
波形例42では、第2オン固定期間T2vが、第2オン固定期間T2uおよび第2オン固定期間T2wと異なる。詳しくは、波形例42では、第2オン固定期間T2vが75度であるのに対し、第2オン固定期間T2uは60度であり、第2オン固定期間T2wは45度である。すなわち、波形例42では、第2オン固定期間T2vが第2オン固定期間T2uおよび第2オン固定期間T2wよりも長い。したがって、図62Bに示すように、V相の第2半導体スイッチング素子Vn(L(ロウサイド))のスイッチング損失がU相、W相に比べて小さくなっている。
In waveform example 42, the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in waveform example 42, the second fixed ON period T2v is 75 degrees, the second fixed ON period T2u is 60 degrees, and the second fixed ON period T2w is 45 degrees. That is, in waveform example 42, the second fixed ON period T2v is longer than the second fixed ON period T2u and the second fixed ON period T2w. Therefore, as shown in FIG. 62B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
以上、図62Aおよび図62Bを参照して説明したように、波形例42においても、波形例1と同様に、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。波形例42では、V相の第1半導体スイッチング素子Vpと、V相の第2半導体スイッチング素子Vnとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 62A and 62B , in waveform example 42, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 42, the heat generation of the V-phase first semiconductor switching element Vp and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
また、波形例42では、図62Bに示すように、U相の第1半導体スイッチング素子Upと、U相の第2半導体スイッチング素子Unと、W相の第1半導体スイッチング素子Wpと、W相の第2半導体スイッチング素子Wnとの発熱についても同時に抑えることができる。
In waveform example 42, as shown in FIG. 62B, the U-phase first semiconductor switching element Up, the U-phase second semiconductor switching element Un, the W-phase first semiconductor switching element Wp, and the W-phase semiconductor switching element Wp Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
図63Aおよび図63Bを参照して、波形例43について説明する。図63Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図63Bは、スイッチング損失を示す図である。
A waveform example 43 will be described with reference to FIGS. 63A and 63B. FIG. 63A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 63B is a diagram showing switching losses.
図63Aに示すように、波形例43は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例43は、電気角0度~電気角30度、電気角75度~電気角105度、電気角150度~電気角240度および電気角330度~電気角360度において、いずれか1相の出力が1に固定される波形である。また、波形例43は、電気角30度~電気角75度、電気角105度~電気角150度および電気角240度~電気角330度において、いずれか1相の出力が0に固定される波形である。波形例43では、電気角0度~電気角30度、電気角75度~電気角105度、電気角150度~電気角240度および電気角330度~電気角360度において、ハイサイドオン適用期間T3である。また、波形例43では、電気角30度~電気角75度、電気角105度~電気角150度および電気角240度~電気角330度において、ロウサイドオン適用期間T4である。
As shown in FIG. 63A, in waveform example 43, the output voltage of any one phase is fixed to 1 in a certain electrical angle section, and the output voltage of any one phase is fixed to 1 in another electrical angle section, depending on the electrical angle. is fixed to 0. Specifically, the waveform example 43 is any of the electrical angles of 0 to 30 electrical degrees, 75 to 105 electrical degrees, 150 to 240 electrical degrees, and 330 to 360 electrical degrees. or is a waveform in which the output of one phase is fixed at 1. In waveform example 43, the output of any one phase is fixed to 0 at an electrical angle of 30 degrees to 75 degrees, from 105 degrees to 150 degrees, and from 240 degrees to 330 degrees. waveform. In waveform example 43, high side ON is applied at an electrical angle of 0 to 30 electrical degrees, from 75 to 105 electrical degrees, from 150 to 240 electrical degrees, and from 330 to 360 electrical degrees. It is period T3. Further, in waveform example 43, the low side-on application period T4 occurs at an electrical angle of 30 to 75 electrical degrees, 105 to 150 electrical degrees, and 240 to 330 electrical degrees.
波形例43では、第1オン固定期間T1は、第1オン固定期間T1uと、第1オン固定期間T1vと、第1オン固定期間T1wとを含む。波形例43では、電気角75度~電気角105度が第1オン固定期間T1uである。波形例43では、電気角150度~電気角240度が第1オン固定期間T1vである。波形例43では、電気角0度~電気角30度および電気角330度~電気角360度が第1オン固定期間T1wである。
In waveform example 43, the first fixed ON period T1 includes a first fixed ON period T1u, a first fixed ON period T1v, and a first fixed ON period T1w. In waveform example 43, the first fixed ON period T1u is from 75 electrical degrees to 105 electrical degrees. In waveform example 43, the first fixed ON period T1v is from 150 electrical degrees to 240 electrical degrees. In waveform example 43, the first fixed ON period T1w is from an electrical angle of 0 degrees to an electrical angle of 30 degrees and from an electrical angle of 330 degrees to an electrical angle of 360 degrees.
波形例43では、第2オン固定期間T2は、第2オン固定期間T2uと、第2オン固定期間T2vと、第2オン固定期間T2wとを含む。波形例43では、電気角240度~電気角330度が第2オン固定期間T2uである。波形例43では、電気角30度~電気角75度が第2オン固定期間T2vである。波形例43では、電気角105度~電気角150度が第2オン固定期間T2wである。
In waveform example 43, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 43, the second fixed ON period T2u is from 240 degrees to 330 degrees in electrical angle. In waveform example 43, the second fixed ON period T2v is from 30 electrical degrees to 75 electrical degrees. In waveform example 43, the second fixed ON period T2w is from 105 electrical degrees to 150 electrical degrees.
波形例43では、3相のうちV相において、第1オン固定期間T1vが、第1オン固定期間T1uおよび第1オン固定期間T1wと異なる。詳しくは、波形例43では、第1オン固定期間T1vが90度であるのに対し、第1オン固定期間T1uは30度であり、第1オン固定期間T1wは60度である。すなわち、波形例43では、第1オン固定期間T1vが第1オン固定期間T1uおよび第1オン固定期間T1wよりも長い。したがって、図63Bに示すように、V相の第1半導体スイッチング素子Vp(H(ハイサイド))のスイッチング損失がU相およびW相に比べて小さくなっている。
In waveform example 43, in the V phase among the three phases, the first fixed ON period T1v differs from the first fixed ON period T1u and the first fixed ON period T1w. Specifically, in waveform example 43, the first fixed ON period T1v is 90 degrees, the first fixed ON period T1u is 30 degrees, and the first fixed ON period T1w is 60 degrees. That is, in waveform example 43, the first fixed ON period T1v is longer than the first fixed ON period T1u and the first fixed ON period T1w. Therefore, as shown in FIG. 63B, the switching loss of the V-phase first semiconductor switching element Vp (H (high side)) is smaller than those of the U-phase and W-phase.
波形例43では、第2オン固定期間T2uが、第2オン固定期間T2vおよび第2オン固定期間T2wと異なる。詳しくは、波形例43では、第2オン固定期間T2uが90度であるのに対し、第2オン固定期間T2vおよび第2オン固定期間T2wは45度である。すなわち、波形例43では、第2オン固定期間T2uが第2オン固定期間T2vおよび第2オン固定期間T2wよりも長い。したがって、図63Bに示すように、U相の第2半導体スイッチング素子Un(L(ロウサイド))のスイッチング損失がV相、W相に比べて小さくなっている。
In waveform example 43, the second fixed ON period T2u is different from the second fixed ON period T2v and the second fixed ON period T2w. Specifically, in waveform example 43, the second fixed ON period T2u is 90 degrees, while the second fixed ON period T2v and the second fixed ON period T2w are 45 degrees. That is, in waveform example 43, the second fixed on period T2u is longer than the second fixed on period T2v and the second fixed on period T2w. Therefore, as shown in FIG. 63B, the switching loss of the U-phase second semiconductor switching element Un (L (low side)) is smaller than those of the V-phase and W-phase.
以上、図63Aおよび図63Bを参照して説明したように、波形例43においても、波形例1と同様に、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。波形例43では、V相の第1半導体スイッチング素子Vpと、U相の第2半導体スイッチング素子Unとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 63A and 63B , in waveform example 43, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In the waveform example 43, the heat generation of the V-phase first semiconductor switching element Vp and the U-phase second semiconductor switching element Un can be suppressed at the same time.
また、波形例43では、図63Bに示すように、U相の第1半導体スイッチング素子Upと、V相の第2半導体スイッチング素子Vnと、W相の第1半導体スイッチング素子Wpと、W相の第2半導体スイッチング素子Wnとの発熱についても同時に抑えることができる。
In waveform example 43, as shown in FIG. 63B, the U-phase first semiconductor switching element Up, the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase Heat generation with the second semiconductor switching element Wn can also be suppressed at the same time.
図64Aおよび図64Bを参照して、波形例44について説明する。図64Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図64Bは、スイッチング損失を示す図である。
A waveform example 44 will be described with reference to FIGS. 64A and 64B. FIG. 64A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 64B is a diagram showing switching losses.
図64Aに示すように、波形例44は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例44は、電気角0度~電気角30度、電気角150度~電気角270度および電気角330度~電気角360度において、いずれか1相の出力が1に固定される波形である。また、波形例44は、電気角30度~電気角150度、および電気角270度~電気角330度において、いずれか1相の出力が0に固定される波形である。波形例44では、電気角0度~電気角30度、電気角150度~電気角270度および電気角330度~電気角360度において、ハイサイドオン適用期間T3である。また、波形例44では、電気角30度~電気角150度、および電気角270度~電気角330度において、ロウサイドオン適用期間T4である。
As shown in FIG. 64A, in the waveform example 44, the output voltage of any one phase is fixed to 1 in a certain electrical angle section according to the electrical angle, and the output voltage of any one phase is fixed to 1 in another electrical angle section. is fixed to 0. Specifically, in waveform example 44, the output of any one phase is fixed to 1 at an electrical angle of 0 to 30 degrees, from 150 to 270 electrical degrees, and from 330 to 360 electrical degrees. waveform. Waveform example 44 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 30 degrees to 150 degrees and at an electrical angle of 270 degrees to 330 degrees. In waveform example 44, the high-side-on application period T3 occurs at an electrical angle of 0 to 30 electrical degrees, 150 to 270 electrical degrees, and 330 to 360 electrical degrees. Further, in waveform example 44, the low side-on application period T4 occurs at an electrical angle of 30 degrees to 150 degrees and at an electrical angle of 270 degrees to 330 degrees.
波形例44では、第1オン固定期間T1は、第1オン固定期間T1vと、第1オン固定期間T1wとを含む。波形例44では、電気角150度~電気角270度が第1オン固定期間T1vである。波形例44では、電気角0度~電気角30度および電気角330度~電気角360度が第1オン固定期間T1wである。
In waveform example 44, the first fixed ON period T1 includes a first fixed ON period T1v and a first fixed ON period T1w. In waveform example 44, the first fixed ON period T1v is from 150 electrical degrees to 270 electrical degrees. In waveform example 44, the first fixed ON period T1w is from 0 electrical angle to 30 electrical degrees and from 330 electrical degrees to 360 electrical degrees.
波形例44では、第2オン固定期間T2は、第2オン固定期間T2uと、第2オン固定期間T2vと、第2オン固定期間T2wとを含む。波形例44では、電気角270度~電気角330度が第2オン固定期間T2uである。波形例44では、電気角30度~電気角90度が第2オン固定期間T2vである。波形例44では、電気角90度~電気角150度が第2オン固定期間T2wである。
In waveform example 44, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 44, the second fixed ON period T2u is from 270 degrees to 330 degrees in electrical angle. In waveform example 44, the second ON fixed period T2v is from 30 electrical degrees to 90 electrical degrees. In waveform example 44, the second fixed ON period T2w is from 90 electrical degrees to 150 electrical degrees.
波形例44では、3相のうちU相において、第1オン固定期間T1vが、第1オン固定期間T1uおよび第1オン固定期間T1wと異なる。詳しくは、波形例44では、第1オン固定期間T1vが120度であるのに対し、第1オン固定期間T1uは無く、第1オン固定期間T1wは60度である。すなわち、波形例44では、第1オン固定期間T1vが第1オン固定期間T1uおよび第1オン固定期間T1wよりも長い。したがって、図64Bに示すように、V相の第1半導体スイッチング素子Vp(H(ハイサイド))のスイッチング損失がU相およびW相に比べて小さくなっている。
In waveform example 44, the first fixed ON period T1v differs from the first fixed ON period T1u and the first fixed ON period T1w in the U phase among the three phases. Specifically, in waveform example 44, the first fixed ON period T1v is 120 degrees, whereas the first fixed ON period T1u is absent and the first fixed ON period T1w is 60 degrees. That is, in waveform example 44, the first fixed ON period T1v is longer than the first fixed ON period T1u and the first fixed ON period T1w. Therefore, as shown in FIG. 64B, the switching loss of the V-phase first semiconductor switching element Vp (H (high side)) is smaller than those of the U-phase and W-phase.
波形例44では、第2オン固定期間T2uと、第2オン固定期間T2vと、第2オン固定期間T2wとは同じである。詳しくは、波形例44では、第2オン固定期間T2uと、第2オン固定期間T2vと、第2オン固定期間T2wとは60度である。
In waveform example 44, the second fixed ON period T2u, the second fixed ON period T2v, and the second fixed ON period T2w are the same. Specifically, in waveform example 44, the second fixed ON period T2u, the second fixed ON period T2v, and the second fixed ON period T2w are 60 degrees.
以上、図64Aおよび図64Bを参照して説明したように、波形例44においても、波形例1と同様に、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。波形例44では、V相の第1半導体スイッチング素子Vpと、U相の第2半導体スイッチング素子Unとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 64A and 64B, in waveform example 44, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In waveform example 44, it is possible to simultaneously suppress the heat generation of the V-phase first semiconductor switching element Vp and the U-phase second semiconductor switching element Un.
また、波形例44では、図64Bに示すように、V相の第2半導体スイッチング素子Vnと、W相の第1半導体スイッチング素子Wpと、W相の第2半導体スイッチング素子Wnとの発熱についても同時に抑えることができる。
In waveform example 44, as shown in FIG. 64B, the heat generated by the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
図65Aおよび図65Bを参照して、波形例45について説明する。図65Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図65Bは、スイッチング損失を示す図である。
A waveform example 45 will be described with reference to FIGS. 65A and 65B. FIG. 65A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 65B is a diagram showing switching losses.
図65Aに示すように、波形例45は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例45は、電気角0度~電気角30度、電気角150度~電気角240度および電気角300度~電気角360度において、いずれか1相の出力が1に固定される波形である。また、波形例45は、電気角30度~電気角150度、電気角240度~電気角300度において、いずれか1相の出力が0に固定される波形である。波形例45では、電気角0度~電気角30度、電気角150度~電気角240度および電気角300度~電気角360度において、ハイサイドオン適用期間T3である。また、波形例45では、電気角30度~電気角150度、電気角240度~電気角300度において、ロウサイドオン適用期間T4である。
As shown in FIG. 65A , in waveform example 45, the output voltage of any one phase is fixed to 1 in a certain electrical angle interval, and the output voltage of any one phase is fixed to 1 in another electrical angle interval. is fixed to 0. Specifically, in waveform example 45, the output of any one phase is fixed to 1 at an electrical angle of 0 to 30 degrees, from 150 to 240 electrical degrees, and from 300 to 360 electrical degrees. waveform. Waveform example 45 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 30 degrees to 150 degrees and at an electrical angle of 240 degrees to 300 degrees. In waveform example 45, the high-side-on application period T3 occurs at an electrical angle of 0 to 30 electrical degrees, 150 to 240 electrical degrees, and 300 to 360 electrical degrees. Further, in waveform example 45, the low-side-on application period T4 occurs at an electrical angle of 30 degrees to 150 electrical degrees and at an electrical angle of 240 degrees to 300 electrical degrees.
波形例45では、第1オン固定期間T1は、第1オン固定期間T1vと、第1オン固定期間T1wとを含む。波形例45では、電気角150度~電気角240度が第1オン固定期間T1vである。波形例45では、電気角0度~電気角30度および電気角300度~電気角360度が第1オン固定期間T1wである。
In waveform example 45, the first fixed ON period T1 includes a first fixed ON period T1v and a first fixed ON period T1w. In waveform example 45, the first fixed ON period T1v is from 150 electrical degrees to 240 electrical degrees. In waveform example 45, the first fixed ON period T1w is from an electrical angle of 0 degrees to an electrical angle of 30 degrees and from an electrical angle of 300 degrees to an electrical angle of 360 degrees.
波形例45では、第2オン固定期間T2は、第2オン固定期間T2uと、第2オン固定期間T2vと、第2オン固定期間T2wとを含む。波形例45では、電気角240度~電気角300度が第2オン固定期間T2uである。波形例45では、電気角30度~電気角90度が第2オン固定期間T2vである。波形例45では、電気角90度~電気角150度が第2オン固定期間T2wである。
In waveform example 45, the second fixed ON period T2 includes a second fixed ON period T2u, a second fixed ON period T2v, and a second fixed ON period T2w. In waveform example 45, the second fixed ON period T2u is from 240 electrical degrees to 300 electrical degrees. In waveform example 45, the second fixed ON period T2v is from 30 electrical degrees to 90 electrical degrees. In waveform example 45, the second fixed ON period T2w is from 90 electrical degrees to 150 electrical degrees.
波形例45では、3相のうちV相において、第1オン固定期間T1vが、第1オン固定期間T1uおよび第1オン固定期間T1wと異なる。詳しくは、波形例45では、第1オン固定期間T1vが90度であるのに対し、第1オン固定期間T1uは無い。すなわち、波形例45では、第1オン固定期間T1vが第1オン固定期間T1uよりも長い。なお、第1オン固定期間T1wは、第1オン固定期間T1vと同じである。したがって、図65Bに示すように、V相の第1半導体スイッチング素子Up(H(ハイサイド))のスイッチング損失がW相に比べて小さくなっている。
In waveform example 45, in the V phase among the three phases, the first fixed ON period T1v differs from the first fixed ON period T1u and the first fixed ON period T1w. Specifically, in waveform example 45, the first fixed ON period T1v is 90 degrees, but there is no first fixed ON period T1u. That is, in waveform example 45, the first fixed ON period T1v is longer than the first fixed ON period T1u. The first fixed ON period T1w is the same as the first fixed ON period T1v. Therefore, as shown in FIG. 65B, the switching loss of the V-phase first semiconductor switching element Up (H (high side)) is smaller than that of the W-phase.
波形例45では、第2オン固定期間T2uと、第2オン固定期間T2vと、第2オン固定期間T2wとは同じである。詳しくは、波形例45では、第2オン固定期間T2uと、第2オン固定期間T2vと、第2オン固定期間T2wとは60度である。
In waveform example 45, the second fixed ON period T2u, the second fixed ON period T2v, and the second fixed ON period T2w are the same. Specifically, in waveform example 45, the second fixed ON period T2u, the second fixed ON period T2v, and the second fixed ON period T2w are 60 degrees.
以上、図65Aおよび図65Bを参照して説明したように、波形例45においても、波形例1と同様に、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。波形例45では、V相の第1半導体スイッチング素子Vpと、U相の第2半導体スイッチング素子Unとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 65A and 65B , in waveform example 45, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In the waveform example 45, the heat generation of the V-phase first semiconductor switching element Vp and the U-phase second semiconductor switching element Un can be suppressed at the same time.
また、波形例45では、図65Bに示すように、V相の第2半導体スイッチング素子Vnと、W相の第1半導体スイッチング素子Wpと、W相の第2半導体スイッチング素子Wnとの発熱についても同時に抑えることができる。
In waveform example 45, as shown in FIG. 65B, the heat generated by the V-phase second semiconductor switching element Vn, the W-phase first semiconductor switching element Wp, and the W-phase second semiconductor switching element Wn can be suppressed at the same time.
図66Aおよび図66Bを参照して、波形例46について説明する。図66Aは、出力電圧Vu、出力電圧Vvおよび出力電圧Vwを示す図である。図66Bは、スイッチング損失を示す図である。
A waveform example 46 will be described with reference to FIGS. 66A and 66B. FIG. 66A is a diagram showing output voltage Vu, output voltage Vv, and output voltage Vw. FIG. 66B is a diagram showing switching losses.
図66Aに示すように、波形例46は、電気角に応じて、ある電気角区間ではいずれか1相の出力電圧が1に固定され、別のある電気角区間ではいずれか1相の出力電圧が0に固定される波形となっている。詳しくは、波形例46は、電気角90度~電気角270度において、いずれか1相の出力が1に固定される波形である。また、波形例46は、電気角0度~電気角90度および電気角270度~電気角360度において、いずれか1相の出力が0に固定される波形である。波形例46では、電気角90度~電気角270度において、ハイサイドオン適用期間T3である。また、波形例46では、電気角0度~電気角90度および電気角270度~電気角360度において、ロウサイドオン適用期間T4である。
As shown in FIG. 66A, in the waveform example 46, the output voltage of any one phase is fixed to 1 in a certain electrical angle section according to the electrical angle, and the output voltage of any one phase is fixed to 1 in another electrical angle section. is fixed to 0. Specifically, waveform example 46 is a waveform in which the output of any one phase is fixed to 1 at an electrical angle of 90 degrees to 270 electrical degrees. Waveform example 46 is a waveform in which the output of any one phase is fixed to 0 at an electrical angle of 0 to 90 degrees and at an electrical angle of 270 to 360 degrees. In waveform example 46, the high-side-on application period T3 is at an electrical angle of 90 degrees to 270 electrical degrees. Further, in the waveform example 46, the low side-on application period T4 occurs at an electrical angle of 0 to 90 electrical degrees and at an electrical angle of 270 to 360 electrical degrees.
波形例46では、第1オン固定期間T1は、第1オン固定期間T1uと、第1オン固定期間T1vとを含む。波形例46では、電気角90度~電気角150度が第1オン固定期間T1uである。波形例46では、電気角150度~電気角270度が第1オン固定期間T1vである。
In waveform example 46, the first fixed ON period T1 includes a first fixed ON period T1u and a first fixed ON period T1v. In the waveform example 46, the first fixed ON period T1u is from 90 electrical degrees to 150 electrical degrees. In waveform example 46, the first fixed ON period T1v is from 150 electrical degrees to 270 electrical degrees.
波形例46では、第2オン固定期間T2は、第2オン固定期間T2uと、第2オン固定期間T2vとを含む。波形例46では、電気角270度~電気角330度が第2オン固定期間T2uである。波形例46では、電気角0度~電気角90度および電気角330度~電気角360度が第2オン固定期間T2vである。
In the waveform example 46, the second fixed ON period T2 includes a second fixed ON period T2u and a second fixed ON period T2v. In waveform example 46, the second fixed ON period T2u is from 270 electrical degrees to 330 electrical degrees. In waveform example 46, the second fixed ON period T2v is from 0 to 90 electrical degrees and from 330 to 360 electrical degrees.
波形例46では、3相のうちV相において、第1オン固定期間T1vが、第1オン固定期間T1uおよび第1オン固定期間T1wと異なる。詳しくは、波形例46では、第1オン固定期間T1vが120度であるのに対し、第1オン固定期間T1uは60度であり、第1オン固定期間T1wは無い。すなわち、波形例46では、第1オン固定期間T1vが第1オン固定期間T1uおよび第1オン固定期間T1wよりも長い。したがって、図66Bに示すように、U相の第1半導体スイッチング素子Vp(H(ハイサイド))のスイッチング損失がU相およびW相に比べて小さくなっている。
In waveform example 46, the first fixed ON period T1v differs from the first fixed ON period T1u and the first fixed ON period T1w in the V phase among the three phases. Specifically, in waveform example 46, the first fixed ON period T1v is 120 degrees, the first fixed ON period T1u is 60 degrees, and there is no first fixed ON period T1w. That is, in the waveform example 46, the first fixed ON period T1v is longer than the first fixed ON period T1u and the first fixed ON period T1w. Therefore, as shown in FIG. 66B, the switching loss of the U-phase first semiconductor switching element Vp (H (high side)) is smaller than those of the U-phase and W-phase.
波形例46では、第2オン固定期間T2vが、第2オン固定期間T2uおよび第2オン固定期間T2wと異なる。詳しくは、波形例46では、第2オン固定期間T2vが120度であるのに対し、第2オン固定期間T2uは60度であり、第2オン固定期間T2wは無い。すなわち、波形例46では、第2オン固定期間T2vが第2オン固定期間T2uおよび第2オン固定期間T2wよりも長い。したがって、図66Bに示すように、V相の第2半導体スイッチング素子Vn(L(ロウサイド))のスイッチング損失がU相、W相に比べて小さくなっている。
In waveform example 46, the second fixed ON period T2v is different from the second fixed ON period T2u and the second fixed ON period T2w. Specifically, in waveform example 46, the second fixed ON period T2v is 120 degrees, the second fixed ON period T2u is 60 degrees, and there is no second fixed ON period T2w. That is, in waveform example 46, the second fixed ON period T2v is longer than the second fixed ON period T2u and the second fixed ON period T2w. Therefore, as shown in FIG. 66B, the switching loss of the V-phase second semiconductor switching element Vn (L (low side)) is smaller than those of the U-phase and W-phase.
以上、図66Aおよび図66Bを参照して説明したように、波形例46においても、波形例1と同様に、ある相の第1半導体スイッチング素子と、ある相の第2半導体スイッチング素子との発熱を同時に抑えることで、電力変換器(インバータ)の昇温を抑制し信頼性を高めることができる。波形例46では、V相の第1半導体スイッチング素子Vpと、V相の第2半導体スイッチング素子Vnとの発熱を同時に抑えることができる。
As described above with reference to FIGS. 66A and 66B , in waveform example 46, as in waveform example 1, heat is generated by the first semiconductor switching element of a certain phase and the second semiconductor switching element of a certain phase. can be suppressed at the same time, the temperature rise of the power converter (inverter) can be suppressed and the reliability can be improved. In the waveform example 46, the heat generation of the V-phase first semiconductor switching element Vp and the V-phase second semiconductor switching element Vn can be suppressed at the same time.
また、波形例46では、図66Bに示すように、U相の第1半導体スイッチング素子Upと、U相の第2半導体スイッチング素子Unとの発熱についても同時に抑えることができる。
In addition, in the waveform example 46, as shown in FIG. 66B, the heat generation of the U-phase first semiconductor switching element Up and the U-phase second semiconductor switching element Un can be suppressed at the same time.
以上、図面(図1~図66B)を参照しながら本発明の実施形態を説明した。但し、本発明は、上記の実施形態に限られるものではなく、その要旨を逸脱しない範囲で種々の態様において実施することが可能である。図面は、理解しやすくするために、それぞれの構成要素を主体に模式的に示しており、図示された各構成要素の厚み、長さ、個数等は、図面作成の都合上から実際とは異なる。また、上記の実施形態で示す各構成要素の材質や形状、寸法等は一例であって、特に限定されるものではなく、本発明の効果から実質的に逸脱しない範囲で種々の変更が可能である。
The embodiments of the present invention have been described above with reference to the drawings (FIGS. 1 to 66B). However, the present invention is not limited to the above-described embodiments, and can be implemented in various aspects without departing from the gist of the present invention. In order to facilitate understanding, the drawings schematically show each component mainly, and the thickness, length, number, etc. of each component illustrated are different from the actual ones due to the convenience of drawing. . In addition, the material, shape, dimensions, etc. of each component shown in the above embodiment are examples and are not particularly limited, and various changes are possible within a range that does not substantially deviate from the effects of the present invention. be.
図1~図66Bを参照して説明したモータ駆動回路100(電力変換器)は、3相の交流出力を出力していたが本発明はこれに限定されない。例えば、モータ駆動回路100は、5相以上の交流出力を出力してもよい。例えば、モータ駆動回路100は、5相の交流出力を出力することによって、5相のモータMを駆動してもよい。
The motor drive circuit 100 (power converter) described with reference to FIGS. 1 to 66B outputs a three-phase AC output, but the present invention is not limited to this. For example, the motor drive circuit 100 may output AC outputs of five or more phases. For example, the motor drive circuit 100 may drive the 5-phase motor M by outputting a 5-phase AC output.
本発明は、電力変換器およびモータモジュールに好適に利用できる。
The present invention can be suitably used for power converters and motor modules.
100 モータ駆動回路(電力変換器)
102、102u、102v、102w 出力端子
112、112u、112v、112w 直列体
114、114u、114v、114w 接続点
200 モータモジュール
M モータ
N 第2電源端子
P 第1電源端子
T1、T1u、T1v、T1w 第1オン固定期間
T2、T2u、T2v、T2w 第2オン固定期間
Up、Vp、Wp 第1半導体スイッチング素子
Un、Vn、Wn 第2半導体スイッチング素子
V1 第1の電圧
V2 第2の電圧
Vu、Vv、Vw 出力電圧 100 Motor drive circuit (power converter)
102, 102u, 102v, 102w Output terminals 112, 112u, 112v, 112w Series bodies 114, 114u, 114v, 114w Connection point 200 Motor module M Motor N Second power terminal P First power terminals T1, T1u, T1v, T1w One fixed ON period T2, T2u, T2v, T2w Second fixed ON period Up, Vp, Wp First semiconductor switching element Un, Vn, Wn Second semiconductor switching element V1 First voltage V2 Second voltage Vu, Vv, Vw output voltage
102、102u、102v、102w 出力端子
112、112u、112v、112w 直列体
114、114u、114v、114w 接続点
200 モータモジュール
M モータ
N 第2電源端子
P 第1電源端子
T1、T1u、T1v、T1w 第1オン固定期間
T2、T2u、T2v、T2w 第2オン固定期間
Up、Vp、Wp 第1半導体スイッチング素子
Un、Vn、Wn 第2半導体スイッチング素子
V1 第1の電圧
V2 第2の電圧
Vu、Vv、Vw 出力電圧 100 Motor drive circuit (power converter)
102, 102u, 102v,
Claims (14)
- 直流電力をn相の交流電力に変換する電力変換器であって、
n相の出力電圧とn相の出力電流とを出力するn個の出力端子と、
第1の電圧が印加される第1電源端子と、
前記第1の電圧よりも低い第2の電圧が印加される第2電源端子と、
2つの半導体スイッチング素子が直列に接続されているn個の直列体とを備え、
nは、交流出力の相数であって、3以上の奇数であり、
前記n個の直列体は、互いに並列に接続されており、
前記n個の直列体の各々は、一端が前記第1電源端子に接続されており、他端が前記第2電源端子に接続されており、
前記n個の直列体の各々は、
前記第1電源端子に接続される第1半導体スイッチング素子と、
前記第2電源端子に接続される第2半導体スイッチング素子とを有し、
前記第1半導体スイッチング素子と前記第2半導体スイッチング素子とは接続点において接続されており、
前記n個の直列体の各々における前記接続点が、前記n個の出力端子に接続されており、
前記第1半導体スイッチング素子は、前記交流出力の周波数よりも高い周波数でオンとオフとが切り替えられ、
前記第2半導体スイッチング素子は、前記交流出力の周波数よりも高い周波数でオンとオフとが切り替えられ、
n相の交流出力の1周期の間に、前記交流出力のうち少なくとも1相が、前記第1半導体スイッチング素子がオンに固定される第1オン固定期間と、前記第2半導体スイッチング素子がオンに固定される第2オン固定期間との少なくとも一方を有する保護動作モードを有し、
前記保護動作モードにおいて、n相のうち少なくとも1相において、前記第1オン固定期間が、他のいずれか1相の前記第1オン固定期間と異なるか、または前記第2オン固定期間が、他のいずれか1相の前記第2オン固定期間と異なる、電力変換器。 A power converter that converts DC power into n-phase AC power,
n output terminals for outputting n-phase output voltages and n-phase output currents;
a first power supply terminal to which a first voltage is applied;
a second power supply terminal to which a second voltage lower than the first voltage is applied;
and n series bodies in which two semiconductor switching elements are connected in series,
n is the number of phases of the AC output and is an odd number of 3 or more,
The n series bodies are connected in parallel with each other,
Each of the n series bodies has one end connected to the first power terminal and the other end connected to the second power terminal,
Each of the n serial bodies is
a first semiconductor switching element connected to the first power supply terminal;
a second semiconductor switching element connected to the second power supply terminal;
the first semiconductor switching element and the second semiconductor switching element are connected at a connection point,
the connection point in each of the n series bodies is connected to the n output terminals;
The first semiconductor switching element is switched on and off at a frequency higher than the frequency of the AC output,
The second semiconductor switching element is switched on and off at a frequency higher than the frequency of the AC output,
During one cycle of the n-phase AC output, at least one phase of the AC output has a first fixed ON period during which the first semiconductor switching element is fixed ON and the second semiconductor switching element is ON. a protected operation mode having at least one of a fixed second ON fixed period;
In the protection operation mode, in at least one of the n phases, the first fixed ON period is different from the first fixed ON period of any one of the other phases, or the second fixed ON period is different from the first fixed ON period of any other phase. A power converter that is different from the second fixed ON period of any one phase of . - PWMデューティ波形が異なる複数の動作モードを有するとともに、電力変換中に前記複数の動作モードの切り替えを行う機能を有し、
前記複数の動作モードのうち少なくとも1つは、前記保護動作モードである、請求項1に記載の電力変換器。 Having a plurality of operation modes with different PWM duty waveforms, and having a function of switching between the plurality of operation modes during power conversion,
2. The power converter of claim 1, wherein at least one of said plurality of operating modes is said protected operating mode. - 前記保護動作モードは、
前記交流出力の1周期の間に、各相が占める前記第1オン固定期間および前記第2オン固定期間のうち少なくとも一方の比率が異なる複数の保護動作パターンを有する、請求項2に記載の電力変換器。 The protection operation mode is
3. The power according to claim 2, having a plurality of protection operation patterns in which the ratio of at least one of the first fixed ON period and the second fixed ON period occupied by each phase differs during one cycle of the AC output. converter. - 複数の前記保護動作モードおよび前記複数の保護動作パターンの切り替えは、前記第1半導体スイッチング素子または前記第2半導体スイッチング素子の少なくとも一方の温度情報に基づいて行う、請求項3に記載の電力変換器。 4. The power converter according to claim 3, wherein said plurality of protection operation modes and said plurality of protection operation patterns are switched based on temperature information of at least one of said first semiconductor switching element and said second semiconductor switching element. .
- 前記保護動作モードは、少なくとも4種類の保護動作パターンを有する、請求項3または請求項4に記載の電力変換器。 The power converter according to claim 3 or 4, wherein the protection operation mode has at least four types of protection operation patterns.
- 前記交流出力の1周期は複数の期間に分割され、前記複数の期間はそれぞれ、いずれかの相の前記第1オン固定期間またはいずれかの相の前記第2オン固定期間である、請求項1から請求項5のいずれか1項に記載の電力変換器。 2. One cycle of the AC output is divided into a plurality of periods, and each of the plurality of periods is the first fixed ON period of any phase or the second fixed ON period of any phase. 6. A power converter according to any one of claims 1 to 5.
- いずれか1相の前記第1オン固定期間が他の相の前記第1オン固定期間よりも長く、且つ、いずれか1相の前記第2オン固定期間が他の相の前記第2オン固定期間よりも長い、請求項1から請求項6のいずれか1項に記載の電力変換器。 The first fixed ON period of any one phase is longer than the first fixed ON period of the other phase, and the second fixed ON period of any one phase is the second fixed ON period of the other phase 7. A power converter as claimed in any one of claims 1 to 6 which is longer than .
- 他の相の前記第1オン固定期間よりも前記第1オン固定期間が長い相の前記第1オン固定期間および他の相の前記第2オン固定期間よりも前記第2オン固定期間が長い相の前記第2オン固定期間がともに、π/nよりも長く、2π/n以下である、請求項7に記載の電力変換器。 The first fixed ON period of the phase whose first fixed ON period is longer than the first fixed ON period of the other phase and the phase whose second fixed ON period is longer than the second fixed ON period of the other phase 8 . The power converter according to claim 7 , wherein both said second fixed ON periods of are longer than π/n and equal to or less than 2π/n.
- 他の相の前記第1オン固定期間よりも前記第1オン固定期間が長い相の前記第1オン固定期間および他の相の前記第2オン固定期間よりも前記第2オン固定期間が長い相の前記第2オン固定期間がともに、2π/nであり、他の相の前記第1オン固定期間よりも前記第1オン固定期間が長い相の前記第1オン固定期間と他の相の前記第2オン固定期間よりも前記第2オン固定期間が長い相の前記第2オン固定期間とが互いに連続しない、請求項8に記載の電力変換器。 The first fixed ON period of the phase whose first fixed ON period is longer than the first fixed ON period of the other phase and the phase whose second fixed ON period is longer than the second fixed ON period of the other phase are both 2π/n, and the first fixed ON period of the phase whose first fixed ON period is longer than the first fixed ON period of the other phase and the said first fixed ON period of the other phase 9. The power converter according to claim 8, wherein said second fixed ON period of a phase having said second fixed ON period longer than said second fixed ON period is not continuous with each other.
- n相のうち2相において、一方の相の前記第1オン固定期間と他方の相の前記第2オン固定期間とが互いに連続しており、前記一方の相の第1オン固定期間と前記他方の相の前記第2オン固定期間との合計が3π/nである、請求項1から請求項8のいずれか1項に記載の電力変換器。 In two of the n phases, the first fixed ON period of one phase and the second fixed ON period of the other phase are continuous, and the first fixed ON period of one phase and the other fixed ON period are continuous. 9. The power converter according to any one of claims 1 to 8, wherein the sum of the phases of , with the second on-fixed period is 3?/n.
- 前記一方の相の前記第1オン固定期間および前記他方の相の前記第2オン固定期間とはそれぞれ3π/(2n)である、請求項10に記載の電力変換器。 11. The power converter according to claim 10, wherein said first fixed ON period of said one phase and said second fixed ON period of said other phase are each 3π/(2n).
- 直流電力をn相の交流電力に変換する電力変換器であって、
前記保護動作モードは、
1つの相の前記第1半導体スイッチング素子と前記第2半導体スイッチング素子とを保護する第1選択保護動作モードを含み、
前記第1選択保護動作モードは、1つの相以外の相の前記第1半導体スイッチング素子と前記第2半導体スイッチング素子のうち、k個(kは2n-3以下の自然数)の前記第1半導体スイッチング素子または前記第2半導体スイッチング素子を保護する、複数のk個保護動作モードを含み、温度情報に基づいて、前記k個保護動作モードの選択を行う、請求項3から請求項9のいずれか1項に記載の電力変換器。 A power converter that converts DC power into n-phase AC power,
The protection operation mode is
including a first selective protection operation mode that protects the first semiconductor switching element and the second semiconductor switching element of one phase;
In the first selective protection operation mode, k (k is a natural number of 2n−3 or less) first semiconductor switching elements among the first semiconductor switching elements and the second semiconductor switching elements of phases other than one phase. 10. Any one of claims 3 to 9, comprising a plurality of k protection operation modes for protecting the element or the second semiconductor switching element, wherein the k protection operation modes are selected based on temperature information. A power converter as described above. - 直流電力をn相の交流電力に変換する電力変換器であって、
前記保護動作モードは、
1つの相の前記第1半導体スイッチング素子と、他の相の前記第2半導体スイッチング素子とを保護する第2選択保護動作モードを含み、前記1つの相の前記第1オン固定期間と前記他の相の前記第2オン固定期間とが連続しており、
前記第2選択保護動作モードは、前記1つの相の前記第1半導体スイッチング素子および前記他の相の前記第2半導体スイッチング素子以外の前記第1半導体スイッチング素子および前記第2半導体スイッチング素子のうち、k個(kは2n-3以下の自然数)の前記第1半導体スイッチング素子または前記第2半導体スイッチング素子を保護する、複数のk個保護動作モードを含み、温度情報に基づいて、前記k個保護動作モードの選択を行う、請求項3から請求項8および請求項10から請求項11のいずれか1項に記載の電力変換器。 A power converter that converts DC power into n-phase AC power,
The protection operation mode is
a second selective protection operation mode for protecting the first semiconductor switching element of one phase and the second semiconductor switching element of another phase, wherein the first fixed ON period of the one phase and the other the second on-fixed period of the phase is continuous;
In the second selective protection operation mode, of the first semiconductor switching element and the second semiconductor switching element other than the first semiconductor switching element of the one phase and the second semiconductor switching element of the other phase, including a plurality of k protection operation modes for protecting the k first semiconductor switching elements or the second semiconductor switching elements (k is a natural number of 2n−3 or less), and the k protection is based on temperature information; 12. A power converter as claimed in any one of claims 3 to 8 and 10 to 11 to provide operation mode selection. - 請求項1から請求項13のいずれか1項に記載の電力変換器と、
前記電力変換器の出力が入力されるモータとを備える、モータモジュール。 A power converter according to any one of claims 1 to 13;
A motor module to which the output of the power converter is input.
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