WO2021191956A1 - 窒化物半導体装置およびその製造方法 - Google Patents
窒化物半導体装置およびその製造方法 Download PDFInfo
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- 150000004767 nitrides Chemical class 0.000 title claims abstract description 192
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Definitions
- the present disclosure relates to a nitride semiconductor device, and particularly to a nitride semiconductor device having high heat dissipation.
- a semiconductor device operating in a high output region As a semiconductor device operating in a high output region, as an electric field effect transistor using GaN (gallium nitride), AlN (aluminum nitride), InN (indium nitride), or a nitride semiconductor combining these, for example, high electron mobility. Degree transistors (HEMTs: High Electron Mobility Transistors) are known. Such nitride semiconductor devices are used in high-power power amplifiers, high-power switching devices, and the like.
- a nitride semiconductor element In such a nitride semiconductor element, the characteristics and reliability of such a nitride semiconductor device are significantly deteriorated due to a temperature rise during high output operation. Therefore, in order to suppress the temperature rise of the nitride semiconductor element, it is necessary to provide a material having high heat dissipation in the vicinity of the heat generating portion. For example, heat dissipation can be improved by processing a nitride semiconductor layer and joining it with a heat dissipation material.
- diamond is a material having the highest thermal conductivity among solid substances, and has properties suitable as a heat radiating material. Therefore, for example, as disclosed in Patent Document 1, there is known a technique for improving the heat dissipation of a semiconductor element by joining a diamond substrate and a nitride semiconductor layer via an amorphous carbon layer.
- the nitride semiconductor layer used in the nitride semiconductor device having such a configuration is formed on a substrate such as silicon (Si), silicon carbide (SiC), or sapphire (Al 2 O 3 ) by a heteroepitaxial growth technique.
- a heteroepitaxial growth technique for a nitride semiconductor layer on a diamond substrate has not yet been established. Therefore, in order to form the nitride semiconductor layer on the diamond substrate, it is necessary to form the nitride semiconductor layer on the heteroepitaxial growth substrate and then take out only the nitride semiconductor layer and transfer it onto the diamond substrate.
- the manufacturing process includes a step of removing the heteroepitaxially grown substrate of the nitride semiconductor layer by grinding and chemical mechanical polishing (CMP). Therefore, there is a problem that the manufacturing cost increases.
- the present disclosure has been made to solve the above-mentioned problems, and an object of the present disclosure is to provide a nitride semiconductor device having high heat dissipation at low cost.
- the nitride semiconductor device includes a diamond substrate, a first graphene layer provided on the diamond substrate, a second graphene layer provided on the first graphene layer, and the above.
- the first and second graphene layers include a nitride semiconductor layer provided on the second graphene layer and a nitride semiconductor element having an electrode provided on the nitride semiconductor layer. It is provided as an interface layer between the diamond substrate and the nitride semiconductor layer.
- nitride semiconductor device it is possible to realize a nitride semiconductor device in which a nitride semiconductor element is provided on a diamond substrate having extremely high heat dissipation at low cost.
- FIG. 1 It is sectional drawing which shows typically the structure of the nitride semiconductor apparatus which concerns on Embodiment 1.
- FIG. It is sectional drawing explaining the manufacturing method of the nitride semiconductor apparatus which concerns on Embodiment 1.
- FIG. It is sectional drawing explaining the manufacturing method of the nitride semiconductor apparatus which concerns on Embodiment 1.
- FIG. It is sectional drawing explaining the manufacturing method of the nitride semiconductor apparatus which concerns on Embodiment 1.
- FIG. It is sectional drawing explaining the manufacturing method of the nitride semiconductor apparatus which concerns on Embodiment 1.
- FIG. It is sectional drawing explaining the manufacturing method of the nitride semiconductor apparatus which concerns on Embodiment 1.
- FIG. It is sectional drawing explaining the manufacturing method of the nitride semiconductor apparatus which concerns on Embodiment 1.
- FIG. It is sectional drawing explaining the manufacturing method of the
- FIG. 1 It is sectional drawing explaining the manufacturing method of the nitride semiconductor apparatus which concerns on Embodiment 1.
- FIG. It is sectional drawing explaining the manufacturing method of the nitride semiconductor apparatus which concerns on Embodiment 1.
- FIG. 2 It is sectional drawing explaining the manufacturing method of the nitride semiconductor apparatus which concerns on Embodiment 1.
- FIG. It is sectional drawing explaining the manufacturing method of the nitride semiconductor apparatus which concerns on Embodiment 2.
- FIG. It is sectional drawing explaining the manufacturing method of the nitride semiconductor apparatus which concerns on Embodiment 2.
- FIG. 2 It is sectional drawing explaining the manufacturing method of the nitride semiconductor apparatus which concerns on Embodiment 2.
- FIG. 2 It is sectional drawing explaining the manufacturing method of the nitride semiconductor apparatus which concerns on Embodiment 2.
- FIG. It is sectional drawing explaining the manufacturing method of the nitride semiconductor apparatus which concerns on Embodiment 2.
- FIG. 2 It is sectional drawing explaining the manufacturing method of the nitride semiconductor apparatus which concerns on Embodiment 2.
- FIG. It is sectional drawing explaining the manufacturing method of the nitride semiconductor apparatus which concerns on Embodiment 2.
- FIG. 2 It is sectional drawing explaining the manufacturing method of the nitride semiconductor apparatus which concerns on Embodiment 2.
- FIG. It is sectional drawing explaining the manufacturing method of the nitride semiconductor apparatus which concerns on Embodiment 2.
- nitride-based semiconductor is a general term for semiconductors having GaN, AlN, InN and their intermediate compositions.
- the n-type is generally defined as the "first conductive type” and the p-type is generally defined as the "second conductive type", but the opposite definition may be used.
- FIG. 1 is a cross-sectional view schematically showing the configuration of the nitride semiconductor device 100 of the first embodiment.
- the semiconductor device according to the first embodiment includes a diamond substrate 10, a graphene layer 20 (first graphene layer) provided on the diamond substrate 10, and a graphene layer 40 (first graphene layer) provided on the graphene layer 20. 2 graphene layer), the nitride semiconductor layer 50 provided on the graphene layer 40, the source electrode 60 selectively provided on the nitride semiconductor layer 50, and the source electrode 60 are separated from each other and selected.
- a drain electrode 61 provided for the purpose and a gate electrode 62 provided between the source electrode 60 and the drain electrode 61 are provided.
- the nitride semiconductor element composed of the nitride semiconductor layer 50, the source electrode 60, the drain electrode 61, and the gate electrode 62 provided on the nitride semiconductor layer 50 is a HEMT.
- the manufacturing method according to the first embodiment is roughly divided into the following four steps. That is, the step of forming the graphene layer on the diamond substrate, the step of forming the nitride semiconductor layer on the silicon carbide substrate, the silicon carbide substrate and the nitride semiconductor layer are separated, and the nitride semiconductor layer is fixed to the support substrate. It has a step and a step of fixing a nitride semiconductor layer on a diamond substrate to form a nitride semiconductor device.
- the diamond substrate 10 is prepared.
- a single crystal diamond substrate, a polycrystalline diamond substrate, a substrate containing single crystal diamond and polycrystalline diamond, or the like can be used, and those having a thermal conductivity of 1000 W ⁇ m -1 ⁇ K -1 or more can be used. Suitable.
- the upper surface of the diamond substrate 10 is flattened at the atomic layer level by using known methods such as mechanical polishing, chemical mechanical polishing, dry etching, and wet etching, and the surface is uneven.
- the height difference is less than 1.0 nm, more preferably less than 0.5 nm.
- the graphene layer 20 is formed on the diamond substrate 10 as shown in FIG.
- the graphene layer 20 is formed by heat treatment in a temperature range of 800 to 1400 ° C. under a vacuum of 1.333 ⁇ 10 1 Pa (1 ⁇ 10 -1 Torr) or less or in an inert gas atmosphere. do.
- the heating temperature is more preferably in the temperature range of 1000 to 1300 ° C.
- the graphene layer 20 By forming the graphene layer 20 on the diamond substrate 10 by such a method, the graphene layer 20 having a controlled number of layers, high surface flatness, and extremely few lattice defects is provided on the entire surface of the diamond substrate 10. Can be done.
- the thickness of the graphene layer 20 is, for example, 0.6 to 0.7 nm (6 to 7 angstroms).
- Examples of the method for forming the graphene layer 20 include chemical vapor deposition using methane gas as a raw material. However, by using the method using the heat treatment as described above, the graphene layer 20 can be formed more easily than by using chemical vapor deposition.
- the graphene layer formed on the single crystal diamond substrate has a characteristic of having fewer lattice defects than the graphene layer formed on the polycrystalline diamond substrate.
- a substrate containing single crystal diamond and polycrystalline diamond a plurality of single crystal diamond substrates are arranged in a plane, polycrystalline diamond is formed between the substrates by chemical vapor phase growth, and the single crystal diamond substrates are joined together. Can be mentioned.
- the silicon carbide substrate 30 is prepared.
- the silicon carbide substrate 30 has a cubic or hexagonal crystal structure.
- the upper surface of the silicon carbide substrate 30 is flattened at the atomic layer level by using known methods such as mechanical polishing, chemical mechanical polishing, dry etching, and wet etching, and the height difference of the surface irregularities is less than 1.0 nm. More preferably, it is less than 0.5 nm.
- the graphene layer 40 is formed on the silicon carbide substrate 30.
- the graphene layer 40 is formed by subjecting the silicon carbide substrate 30 to a heat treatment under a hydrogen atmosphere and a heat treatment under a vacuum.
- the heat treatment temperature is in the range of 1400 to 1600 ° C, preferably 1550 to 1600 ° C.
- the heat treatment under a hydrogen atmosphere is a preparatory step for forming the graphene layer 40, and the graphene layer is formed by the subsequent heat treatment under vacuum.
- the pressure of hydrogen in the hydrogen atmosphere is, for example, about 3.999 ⁇ 10 3 Pa (30 Torr).
- the graphene layer 40 may be formed by heat treatment under the atmosphere of an inert gas.
- the heat treatment temperature in this case is also in the range of 1400 to 1600 ° C, preferably 1550 to 1600 ° C.
- the silicon atoms on the surface of the silicon carbide substrate 30 are desorbed from the silicon carbide substrate 30, and the remaining carbon atoms form the graphene layer 40 that inherits the crystal structure of the silicon carbide substrate 30.
- the graphene layer 40 By forming the graphene layer on the silicon carbide substrate 30 by such a method, the graphene layer 40 having a controlled number of layers, high surface flatness, and extremely few lattice defects is provided on the entire surface of the silicon carbide substrate 30. be able to.
- the thickness of the graphene layer 40 is, for example, 0.6 to 0.7 nm (6 to 7 angstroms).
- Examples of the method for forming the graphene layer 40 include chemical vapor deposition using methane gas as a raw material. However, by using the method using the heat treatment as described above, the graphene layer 40 can be formed more easily than by using chemical vapor deposition.
- the nitride semiconductor layer 50 is formed on the graphene layer 40 by heteroepitaxial growth.
- a method for forming the nitride semiconductor layer 50 for example, molecular beam epitaxy using metallic gallium and active nitrogen as raw materials, and metalorganic vapor phase growth using trimethylgallium and ammonia as raw materials can be used.
- the nitride semiconductor layer 50 is, for example, a buffer layer 53 (first nitride semiconductor layer) composed of AlN or AlGaN, for example, a channel layer 52 (second nitride semiconductor layer) composed of GaN.
- the barrier layer 51 (third nitride semiconductor layer) composed of AlGaN (aluminum nitride gallium nitride) is laminated on the graphene layer 40 in this order.
- the barrier layer 51 has a thickness of 25 nm
- the channel layer 52 has a thickness of 1 ⁇ m
- the buffer layer 53 has a thickness of 500 nm.
- the channel layer 52 may contain impurities such as Fe (iron) or C (carbon) for the purpose of increasing resistance.
- a heterojunction is formed at the interface between the channel layer 52 and the barrier layer 51, and the barrier layer 51 supplies electrons to this interface to form a two-dimensional electron gas (2DEG) at this interface.
- 2DEG serves as a carrier for the nitride semiconductor device of the present embodiment.
- the buffer layer 53 suppresses crystal defects due to the difference in lattice constant between the silicon carbide substrate 30 and the graphene layer 40 and the nitride semiconductor.
- the source electrode 60, the drain electrode 61, and the gate electrode 62 are selectively formed on the nitride semiconductor layer 50, respectively.
- the source electrode 60 and the drain electrode 61 are, for example, metal electrodes, and are made of, for example, aluminum. It is desirable that ohmic contacts are formed between the source electrode 60 and the drain electrode 61 and the nitride semiconductor layer 50.
- the thickness of the source electrode 60 and the drain electrode 61 is, for example, 1 ⁇ m
- the thickness of the gate electrode 62 is, for example, 200 nm, all of which are formed by vacuum vapor deposition, sputtering, and chemical vapor deposition.
- Ion implantation may be performed so that the semiconductor region under the source electrode 60 (hereinafter referred to as the source electrode region) and the semiconductor region under the drain electrode (drain electrode region) have an n-type conductive type.
- the semiconductor region under the source electrode 60 hereinafter referred to as the source electrode region
- the semiconductor region under the drain electrode drain electrode region
- the dose amount of the n-type impurity is, for example, 1 ⁇ 10 15 cm- 2 .
- heat treatment activates impurities.
- the gate electrode 62 may be made of, for example, a metal such as Ni (nickel) or Pt (platinum), or boron-doped p-type polysilicon, phosphorus-doped n-type polysilicon, or the like.
- Step of separating the silicon carbide substrate and the nitride semiconductor layer Next, the step of separating the silicon carbide substrate and the nitride semiconductor layer will be described with reference to FIGS. 6 and 7. First, in the step shown in FIG. 6, the support substrate 71 is adhered onto the nitride semiconductor layer 50 on the silicon carbide substrate 30 by using the support substrate adhesive layer 70.
- the support substrate adhesive layer 70 is formed by applying an organic adhesive that can be removed with a release liquid or the like, or an adhesive that can be removed by heating or ultraviolet irradiation so as to cover the source electrode 60, the drain electrode 61, and the gate electrode 62. It is preferable to do so. Further, a plurality of adhesive layers may be laminated in two or more layers.
- the support substrate 71 is composed of, for example, Si, sapphire, and glass.
- the nitride semiconductor layer 50 in which the support substrate 71 is adhered is pulled upward or downward while the silicon carbide substrate 30 is fixed to the silicon carbide substrate. 30 and the nitride semiconductor layer 50 are separated.
- the pulling force of the support substrate 71 may be set to either a size that separates the silicon carbide substrate 30 and the graphene layer 40 at the interface, or a size that separates the graphene layer 40 between layers.
- the silicon carbide substrate 30 is fixed to a support (not shown) by using vacuum suction or an adhesive or the like.
- As the force for pulling the support substrate 71 for example, appropriately applying a force in the range of 10N ⁇ mm -2 ⁇ 10000N ⁇ mm -2.
- a tensile force is applied to separate the nitride semiconductor layer 50 and the silicon carbide substrate 30, but at that time, the tensile force is gradually increased from a small value, and the nitride semiconductor layer 50 and the silicon carbide substrate 30 are separated from each other. Stop pulling when separated.
- a force having a magnitude of separating at the interface between the silicon carbide substrate 30 and the graphene layer 40 or a force having a magnitude of separating the graphene layer 40 between layers may be appropriately applied.
- the silicon carbide substrate 30 and the nitride semiconductor layer 50 may be separated by pulling the silicon carbide substrate 30 upward or downward with the support substrate 71 fixed.
- FIG. 7 shows a state in which the graphene layer 40 is delaminated, but the graphene layer 40 is separated at the interface between the silicon carbide substrate 30 and the graphene layer 40, and the graphene layer 40 is all attached to the nitride semiconductor layer 50. Is most preferable.
- the nitride semiconductor layer 50 can be isolated while the silicon carbide substrate 30 remains. That is, since the silicon carbide substrate 30 is not mechanically or chemically removed, the silicon carbide substrate 30 which is a heteroepitaxial substrate of the nitride semiconductor layer 50 can be reused, and the manufacturing cost of the nitride semiconductor device 100 can be reduced. It can be reduced.
- Step of fixing a nitride semiconductor layer on a diamond substrate to form a nitride semiconductor device a step of fixing the nitride semiconductor layer on the diamond substrate to form the nitride semiconductor device will be described with reference to FIGS. 8 and 9.
- the diamond substrate 10 shown in FIG. 2 is bonded to the nitride semiconductor layer 50 separated from the silicon carbide substrate 30.
- the graphene layer 20 on the diamond substrate 10 shown in FIG. 2 has the same atomic arrangement as the graphene layer 40 remaining under the nitride semiconductor layer 50. Therefore, by bringing the graphene layer 20 and the graphene layer 40 into contact with each other, a physical bond is generated between the graphene layer 20 and the graphene layer 40 by van der Waals force, and a bond is formed.
- graphene is a high thermal conductive material, and the graphene layer 20 and the graphene layer 40 have few lattice defects. Therefore, the nitride semiconductor layer 50 and the diamond substrate 10 can be bonded via an interface layer having extremely low thermal resistance, that is, a bonding layer composed of the graphene layer 20 and the graphene layer 40.
- the thermal conductivity of the graphene layer, at room temperature, the in-plane direction 2000 ⁇ 5000W ⁇ m -1 ⁇ K -1 order is the direction perpendicular, for example, 10 W ⁇ m approximately -1 ⁇ K -1 in the plane ..
- the support substrate 71 is separated from the nitride semiconductor layer 50 on the diamond substrate 10.
- the support substrate adhesive layer 70 is made peelable and the support substrate adhesive layer 70 is peeled off.
- the support substrate 71 is separated from the nitride semiconductor layer 50 on the diamond substrate 10 together with the support substrate adhesive layer 70.
- a nitride semiconductor device 100 FIG. 1 having a nitride semiconductor element (HEMT) composed of a nitride semiconductor layer 50, a source electrode 60, a drain electrode 61, and a gate electrode 62. ..
- HEMT nitride semiconductor element
- the nitride semiconductor device 100 has a diamond substrate 10 having a high thermal conductivity. Further, the bonding layer composed of graphene layers 20 and 40 having extremely few lattice defects and high thermal conductivity is formed between the nitride semiconductor layer 50 and the diamond substrate 10 from two or more atomic layers (several atomic layers) to several tens. It has the thickness of an atomic layer. Therefore, for example, the nitride semiconductor layer 50 and diamond are more than the structure having an amorphous carbon layer having a thickness of 10 nm between the nitride semiconductor layer and the diamond substrate disclosed in Japanese Patent Application Laid-Open No. 2018-206955. The nitride semiconductor device has good heat conduction with the substrate 10 and has higher heat dissipation.
- the graphene layer having a thickness of two or more atomic layers (several atomic layers) to several tens of atomic layers is thinner than the amorphous carbon layer having a thickness of 10 nm, and the amorphous carbon generally has a thermal conductivity of 5 Wm. It is less than -1 ⁇ K -1 , and has a lower thermal conductivity than graphene. Further, as described above, graphene has a high thermal conductivity in the in-plane direction and can disperse heat in the in-plane direction, so that the heat dissipation property is much higher than that of amorphous carbon.
- the source electrode 60, the drain electrode 61, and the gate electrode 62 are formed on the nitride semiconductor layer 50, and then the support substrate adhesive layer 70 is used.
- the support substrate 71 was bonded to the support substrate 71.
- the source electrode 60, the drain electrode 61, and the drain electrode 61 are bonded.
- the gate electrode 62 may be formed.
- the method for manufacturing the nitride semiconductor device 200 according to the second embodiment will be described with reference to FIGS. 10 to 15. Since the cross-sectional configuration of the nitride semiconductor device 200 according to the second embodiment is the same as that of FIG. 1, the configuration of FIG. 1 is also used as the nitride semiconductor device 200. Further, with respect to the configuration and the process overlapping with the manufacturing method of the first embodiment described with reference to FIGS. 2 to 9, the overlapping description will be omitted.
- the manufacturing method according to the second embodiment is roughly divided into the following four steps. That is, the step of forming the graphene layer on the diamond substrate, the step of forming the nitride semiconductor layer on the silicon carbide substrate, the silicon carbide substrate and the nitride semiconductor layer are separated, and the nitride semiconductor layer is fixed to the support substrate. It has a step and a step of fixing a nitride semiconductor layer on a diamond substrate to form a nitride semiconductor device.
- the diamond substrate 10 is prepared.
- a single crystal diamond substrate, a polycrystalline diamond substrate, a substrate containing single crystal diamond and polycrystalline diamond, or the like can be used, and the upper surface of the diamond substrate 10 is mechanically polished, chemically mechanically polished, dry etched, or wet. It is flattened at the atomic layer level using a known method such as etching.
- a graphene layer 20 is formed on the diamond substrate 10.
- the method for forming the graphene layer 20 is the same as that in the first embodiment, and the thickness of the graphene layer 20 is, for example, 0.6 to 0.7 nm (6 to 7 angstroms).
- the silicon carbide substrate 30 is prepared.
- the silicon carbide substrate 30 has a cubic or hexagonal crystal structure.
- the upper surface of the silicon carbide substrate 30 is flattened at the atomic layer level by using known methods such as mechanical polishing, chemical mechanical polishing, dry etching, and wet etching.
- the graphene layer 40 is formed on the silicon carbide substrate 30.
- the method for forming the graphene layer 40 is the same as that in the first embodiment, and the thickness of the graphene layer 20 is, for example, 0.6 to 0.7 nm (6 to 7 angstroms).
- the nitride semiconductor layer 50 is formed on the graphene layer 40 by heteroepitaxial growth.
- the method for forming the nitride semiconductor layer 50 is the same as that of the first embodiment, and the buffer layer 53, the channel layer 52, and the barrier layer 51 are laminated on the graphene layer 40 in this order.
- the barrier layer 51 has a thickness of 25 nm
- the channel layer 52 has a thickness of 1 ⁇ m
- the buffer layer 53 has a thickness of 500 nm.
- Step of separating the silicon carbide substrate and the nitride semiconductor layer Next, the step of separating the silicon carbide substrate and the nitride semiconductor layer will be described with reference to FIGS. 13 and 14. First, in the step shown in FIG. 13, the support substrate 71 is adhered onto the nitride semiconductor layer 50 on the silicon carbide substrate 30 by using the support substrate adhesive layer 70.
- the support substrate adhesive layer 70 is preferably formed by applying an organic adhesive that can be removed with a release liquid or the like, or an adhesive that can be removed by heating or ultraviolet irradiation so as to cover the nitride semiconductor layer 50. .. Further, a plurality of adhesive layers may be laminated in two or more layers.
- the support substrate adhesive layer 70 needs to cover the source electrode 60, the drain electrode 61, and the gate electrode 62.
- the support substrate adhesive layer 70 is formed on the flat nitride semiconductor layer 50. Therefore, the thickness of the support substrate adhesive layer 70 may be thinner than the thickness of the source electrode 60, the drain electrode 61, and the gate electrode 62. Further, it is not necessary to use a low-viscosity adhesive for filling between the source electrode 60 and the gate electrode 62 and between the drain electrode 61 and the gate electrode 62.
- the nitride semiconductor layer 50 in which the support substrate 71 is adhered is pulled upward or downward with the silicon carbide substrate 30 fixed, thereby pulling the silicon carbide substrate 71 upward or downward. 30 and the nitride semiconductor layer 50 are separated.
- the pulling force of the support substrate 71 may be set to either a size that separates the silicon carbide substrate 30 and the graphene layer 40 at the interface, or a size that separates the graphene layer 40 between layers.
- FIG. 14 shows a state in which the graphene layer 40 is delaminated, the graphene layer 40 is separated at the interface between the silicon carbide substrate 30 and the graphene layer 40, and the graphene layer 40 is all attached to the nitride semiconductor layer 50. Is most preferable.
- the surface of the graphene layer 40 on the nitride semiconductor layer 50 side after separation becomes flat, and it is in a state suitable for joining with the graphene layer 20 on the diamond substrate 10 in the subsequent steps. Become.
- the nitride semiconductor layer 50 can be isolated while the silicon carbide substrate 30 remains. That is, since the silicon carbide substrate 30 is not mechanically or chemically removed, the silicon carbide substrate 30 which is a heteroepitaxial substrate of the nitride semiconductor layer 50 can be reused, and the manufacturing cost of the nitride semiconductor device 200 can be reduced. It can be reduced.
- Step of fixing a nitride semiconductor layer on a diamond substrate to form a nitride semiconductor device a step of fixing the nitride semiconductor layer on the diamond substrate to form the nitride semiconductor device will be described with reference to FIGS. 15 to 17.
- the diamond substrate 10 shown in FIG. 10 is bonded to the nitride semiconductor layer 50 separated from the silicon carbide substrate 30.
- the graphene layer 20 on the diamond substrate 10 shown in FIG. 10 has an atomic arrangement similar to that of the graphene layer 40 remaining under the nitride semiconductor layer 50, and the graphene layer 20 and the graphene layer 40 are brought into contact with each other. , A physical bond is generated between the graphene layer 20 and the graphene layer 40 by van der Waals force, and a bond is formed.
- the conditions for joining are the same as those in the first embodiment.
- graphene is a high thermal conductive material, and the graphene layer 20 and the graphene layer 40 have few lattice defects. Therefore, the nitride semiconductor layer 50 and the diamond substrate 10 can be bonded via an interface layer having extremely low thermal resistance, that is, a bonding layer composed of the graphene layer 20 and the graphene layer 40.
- the thermal conductivity of the graphene layer, at room temperature, the in-plane direction 2000 ⁇ 5000W ⁇ m -1 ⁇ K -1 order is the direction perpendicular, for example, 10 W ⁇ m approximately -1 ⁇ K -1 in the plane ..
- the support substrate 71 is separated from the nitride semiconductor layer 50 on the diamond substrate 10.
- the support substrate adhesive layer 70 is made peelable and the support substrate adhesive layer 70 is peeled off.
- the support substrate 71 is separated from the nitride semiconductor layer 50 on the diamond substrate 10 together with the support substrate adhesive layer 70.
- the nitride semiconductor device 200 is obtained by selectively forming the source electrode 60, the drain electrode 61, and the gate electrode 62 on the nitride semiconductor layer 50.
- the method and thickness of these electrodes are the same as those in the first embodiment.
- Ion implantation may be performed so that the source electrode region under the source electrode 60 and the drain electrode region under the drain electrode have an n-type conductive type.
- silicon is ion-implanted as an n-type impurity.
- the dose amount of the n-type impurity is, for example, 1 ⁇ 10 15 cm- 2 .
- heat treatment activates impurities.
- the gate electrode 62 may be made of, for example, a metal such as Ni or Pt, p-type polysilicon doped with boron, n-type polysilicon doped with phosphorus, or the like.
- a nitride semiconductor device 200 (FIG. 1) having a nitride semiconductor element (HEMT) composed of a nitride semiconductor layer 50, a source electrode 60, a drain electrode 61, and a gate electrode 62. ..
- HEMT nitride semiconductor element
- the nitride semiconductor device 200 has a diamond substrate 10 having a high thermal conductivity. Further, the bonding layer composed of graphene layers 20 and 40 having extremely few lattice defects and high thermal conductivity is formed between the nitride semiconductor layer 50 and the diamond substrate 10 from two or more atomic layers (several atomic layers) to several tens. It has the thickness of an atomic layer. Therefore, for example, the nitride semiconductor layer 50 and diamond are more than the structure having an amorphous carbon layer having a thickness of 10 nm between the nitride semiconductor layer and the diamond substrate disclosed in Japanese Patent Application Laid-Open No. 2018-206955. The nitride semiconductor device has good heat conduction with the substrate 10 and has higher heat dissipation.
- each embodiment can be freely combined, and each embodiment can be appropriately modified or omitted.
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Abstract
Description
以下、図面を参照しながら実施の形態について説明する。なお、図面は模式的に示されたものであり、図中の各構成要素の水平方向、垂直方向の寸法は、実際の寸法を正確に表したものではなく、寸法比は正確ではない。また、以下の説明では、同様の構成要素には同じ符号を付して図示し、それらの名称および機能も同様のものとする。よって、それらについての詳細な説明を省略する場合がある。
図1は、実施の形態1の窒化物半導体装置100の構成を模式的に示す断面図である。実施の形態1に係る半導体装置は、ダイヤモンド基板10と、ダイヤモンド基板10の上に設けられたグラフェン層20(第1のグラフェン層)と、グラフェン層20の上に設けられたグラフェン層40(第2のグラフェン層)と、グラフェン層40の上に設けられた窒化物半導体層50と、窒化物半導体層50の上に選択的に設けられたソース電極60と、ソース電極60と離間して選択的に設けられたドレイン電極61と、ソース電極60とドレイン電極61の間に設けられたゲート電極62と、を備えている。窒化物半導体層50と、窒化物半導体層50上に設けられたソース電極60、ドレイン電極61およびゲート電極62とで構成される窒化物半導体素子はHEMTとなる。
まず、ダイヤモンド基板上にグラフェン層を形成する工程について、図2を用いて説明する。まず、図2に示すように、ダイヤモンド基板10を準備する。ダイヤモンド基板10は、単結晶ダイヤモンド基板、多結晶ダイヤモンド基板、単結晶ダイヤモンドと多結晶ダイヤモンドとを含む基板等を用いることができ、熱伝導率が1000W・m-1・K-1以上のものが好適である。ダイヤモンド基板10の上面は、機械研磨(Mechanical Polishing)、化学機械研磨(Chemical Mechanical Polishing)、ドライエッチング、ウェットエッチング等の公知の手法を用いて原子層レベルで平坦化されており、表面の凹凸の高低差は1.0nm未満、より好適には0.5nm未満となっている。
次に、炭化珪素基板上に窒化物半導体層を形成する工程について、図3および図4を用いて説明する。まず、図3に示すように、炭化珪素基板30を準備する。炭化珪素基板30は、立方晶系または六方晶系の結晶構造を有している。炭化珪素基板30の上面は、機械研磨、化学機械研磨、ドライエッチング、ウェットエッチング等、公知の手法を用いて原子層レベルで平坦化されており、表面の凹凸の高低差は1.0nm未満、より好適には0.5nm未満となっている。
次に、炭化珪素基板と窒化物半導体層とを分離する工程を、図6および図7を用いて説明する。まず、図6に示す工程において、炭化珪素基板30上の窒化物半導体層50上に、支持基板接着層70を用いて支持基板71を接着させる。
次に、ダイヤモンド基板上に窒化物半導体層を固定して窒化物半導体装置を形成する工程を、図8および図9を用いて説明する。まず、図8に示す工程において、炭化珪素基板30から分離した窒化物半導体層50に、図2に示したダイヤモンド基板10を接合する。
以上説明した実施の形態1に係る窒化物半導体装置100の製造方法においては、窒化物半導体層50上にソース電極60、ドレイン電極61およびゲート電極62を形成した後に、支持基板接着層70を介して支持基板71を接着する工程を有していたが、以下、実施の形態2において説明するように、窒化物半導体層50をダイヤモンド基板10上に接合した後に、ソース電極60、ドレイン電極61およびゲート電極62を形成しても良い。
まず、ダイヤモンド基板上にグラフェン層を形成する工程について、図10を用いて説明する。まず、図10に示すように、ダイヤモンド基板10を準備する。ダイヤモンド基板10は、単結晶ダイヤモンド基板、多結晶ダイヤモンド基板および単結晶ダイヤモンドと多結晶ダイヤモンドと含む基板等を用いることができ、ダイヤモンド基板10の上面は、機械研磨、化学機械研磨、ドライエッチング、ウェットエッチング等の公知の手法を用いて原子層レベルで平坦化されている。
次に、炭化珪素基板上に窒化物半導体層を形成する工程について、図11および図12を用いて説明する。まず、図11に示すように、炭化珪素基板30を準備する。炭化珪素基板30は、立方晶系または六方晶系の結晶構造を有している。炭化珪素基板30の上面は、機械研磨、化学機械研磨、ドライエッチング、ウェットエッチング等、公知の手法を用いて原子層レベルで平坦化されている。
次に、炭化珪素基板と窒化物半導体層とを分離する工程を、図13および図14を用いて説明する。まず、図13に示す工程において、炭化珪素基板30上の窒化物半導体層50上に、支持基板接着層70を用いて支持基板71を接着させる。
次に、ダイヤモンド基板上に窒化物半導体層を固定して窒化物半導体装置を形成する工程を、図15~図17を用いて説明する。まず、図15に示す工程において、炭化珪素基板30から分離した窒化物半導体層50に、図10に示したダイヤモンド基板10を接合する。
Claims (11)
- ダイヤモンド基板と、
前記ダイヤモンド基板の上に設けられた第1のグラフェン層と、
前記第1のグラフェン層の上に設けられた第2のグラフェン層と、
前記第2のグラフェン層の上に設けられた窒化物半導体層と、
前記窒化物半導体層上に設けられた電極を有する窒化物半導体素子と、を備え、
前記第1および第2のグラフェン層は、
前記ダイヤモンド基板と前記窒化物半導体層との界面層として設けられる、窒化物半導体装置。 - 前記ダイヤモンド基板は、
単結晶ダイヤモンド基板、多結晶ダイヤモンド基板および単結晶ダイヤモンドと多結晶ダイヤモンドとを含む基板の何れかで構成される、請求項1記載の窒化物半導体装置。 - 前記第1および第2のグラフェン層は、
2原子層以上の厚みを有する、請求項1記載の窒化物半導体装置。 - 前記第1のグラフェン層は、
前記ダイヤモンド基板を熱処理して形成される、請求項1記載の窒化物半導体装置。 - 前記窒化物半導体層は、
前記第2のグラフェン層上に設けられた第1の窒化物半導体層と、
前記第1の窒化物半導体層上に設けられた第2の窒化物半導体層と、
前記第2の窒化物半導体層上に設けられた前記第3の窒化物半導体層と、を有する、請求項1記載の窒化物半導体装置。 - (a)ダイヤモンド基板上に第1のグラフェン層を形成する工程と、
(b)炭化珪素基板上に第2のグラフェン層を形成する工程と、
(c)前記第1のグラフェン層上に窒化物半導体層をエピタキシャル成長させる工程と、
(d)前記工程(c)の後、前記炭化珪素基板と前記窒化物半導体層を分離する工程と、
(e)前記工程(d)の後、前記第1のグラフェン層を前記窒化物半導体層側として前記ダイヤモンド基板と前記窒化物半導体層とを接合する工程と、
(f)前記窒化物半導体層上に電極を形成し窒化物半導体素子を形成する工程と、を備える窒化物半導体装置の製造方法。 - 前記工程(a)は、
前記ダイヤモンド基板を熱処理して前記第1のグラフェン層を形成する工程を含む、請求項6記載の窒化物半導体装置の製造方法。 - 前記工程(b)は、
前記炭化珪素基板を熱処理して前記第2のグラフェン層を形成する工程を含む、請求項6記載の窒化物半導体装置の製造方法。 - 前記工程(d)は、
前記窒化物半導体層上に前記第2のグラフェン層を残して前記炭化珪素基板を分離し、
前記(e)は、前記第1のグラフェン層と前記第2のグラフェン層とをファンデルワールス力で接合する工程と、を含む、請求項6記載の窒化物半導体装置の製造方法。 - 前記工程(f)は、前記工程(d)の前に実行され、
前記工程(d)は、
前記窒化物半導体層上に前記窒化物半導体素子を覆うように接着層を形成し、前記接着層を介して支持基板を前記窒化物半導体層上に接着する工程と、
前記支持基板と前記炭化珪素基板とを介して前記炭化珪素基板と前記窒化物半導体層とが分離する力を加える工程と、を有し、
前記工程(e)の後に、前記窒化物半導体層上から、前記接着層と共に前記支持基板を除去する工程を備える、請求項6記載の窒化物半導体装置の製造方法。 - 前記工程(d)は、
前記窒化物半導体層上を覆うように接着層を形成し、前記接着層を介して支持基板を前記窒化物半導体層上に接着する工程と、
前記支持基板と前記炭化珪素基板とを介して前記炭化珪素基板と前記窒化物半導体層とが分離する力を加える工程と、を有し、
前記工程(f)は、
前記工程(e)の後であって、前記窒化物半導体層上から、前記接着層と共に前記支持基板を除去した後に実行される、請求項6記載の窒化物半導体装置の製造方法。
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Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009190918A (ja) * | 2008-02-13 | 2009-08-27 | New Japan Radio Co Ltd | 窒化物半導体基板の製造方法及び窒化物半導体装置の製造方法 |
JP2011009268A (ja) * | 2009-06-23 | 2011-01-13 | Oki Data Corp | 窒化物半導体層の剥離方法、半導体装置の製造方法、及び半導体装置 |
US20110108854A1 (en) * | 2009-11-10 | 2011-05-12 | Chien-Min Sung | Substantially lattice matched semiconductor materials and associated methods |
JP2014011301A (ja) * | 2012-06-29 | 2014-01-20 | Toyota Industries Corp | 半導体装置の製造方法 |
JP2018535536A (ja) * | 2015-09-08 | 2018-11-29 | マサチューセッツ インスティテュート オブ テクノロジー | グラフェンベースの層転写のためのシステム及び方法 |
JP2018206955A (ja) | 2017-06-05 | 2018-12-27 | 富士通株式会社 | 半導体装置、電源装置、増幅器及び半導体装置の製造方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20120141799A1 (en) * | 2010-12-03 | 2012-06-07 | Francis Kub | Film on Graphene on a Substrate and Method and Devices Therefor |
JP5681959B2 (ja) * | 2010-12-07 | 2015-03-11 | 国立大学法人金沢大学 | グラフェン・ダイヤモンド積層体 |
JP2015015321A (ja) * | 2013-07-03 | 2015-01-22 | 高槻電器工業株式会社 | 半導体発光素子及びその製造方法 |
CN103779193A (zh) * | 2014-01-27 | 2014-05-07 | 苏州能讯高能半导体有限公司 | 基于金刚石衬底的氮化物半导体器件及其制备方法 |
US10504722B2 (en) * | 2017-07-25 | 2019-12-10 | United States Of America As Represented By The Secretary Of The Air Force | Growth of III-nitride semiconductors on thin van der Waals buffers for mechanical lift off and transfer |
-
2020
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Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009190918A (ja) * | 2008-02-13 | 2009-08-27 | New Japan Radio Co Ltd | 窒化物半導体基板の製造方法及び窒化物半導体装置の製造方法 |
JP2011009268A (ja) * | 2009-06-23 | 2011-01-13 | Oki Data Corp | 窒化物半導体層の剥離方法、半導体装置の製造方法、及び半導体装置 |
US20110108854A1 (en) * | 2009-11-10 | 2011-05-12 | Chien-Min Sung | Substantially lattice matched semiconductor materials and associated methods |
JP2014011301A (ja) * | 2012-06-29 | 2014-01-20 | Toyota Industries Corp | 半導体装置の製造方法 |
JP2018535536A (ja) * | 2015-09-08 | 2018-11-29 | マサチューセッツ インスティテュート オブ テクノロジー | グラフェンベースの層転写のためのシステム及び方法 |
JP2018206955A (ja) | 2017-06-05 | 2018-12-27 | 富士通株式会社 | 半導体装置、電源装置、増幅器及び半導体装置の製造方法 |
Non-Patent Citations (1)
Title |
---|
See also references of EP4131346A4 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2023127527A (ja) * | 2022-03-01 | 2023-09-13 | 鴻創應用科技有限公司 | 複合基板及びその製造方法 |
JP7402553B2 (ja) | 2022-03-01 | 2023-12-21 | 鴻創應用科技有限公司 | 複合基板及びその製造方法 |
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