WO2021169317A1 - 一种芯片共享资源串行测试装置及方法 - Google Patents

一种芯片共享资源串行测试装置及方法 Download PDF

Info

Publication number
WO2021169317A1
WO2021169317A1 PCT/CN2020/120804 CN2020120804W WO2021169317A1 WO 2021169317 A1 WO2021169317 A1 WO 2021169317A1 CN 2020120804 W CN2020120804 W CN 2020120804W WO 2021169317 A1 WO2021169317 A1 WO 2021169317A1
Authority
WO
WIPO (PCT)
Prior art keywords
chip
test
double
test platform
platform
Prior art date
Application number
PCT/CN2020/120804
Other languages
English (en)
French (fr)
Inventor
薛孟锡
Original Assignee
上海御渡半导体科技有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 上海御渡半导体科技有限公司 filed Critical 上海御渡半导体科技有限公司
Publication of WO2021169317A1 publication Critical patent/WO2021169317A1/zh

Links

Images

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
    • G01R31/2834—Automated test systems [ATE]; using microprocessors or computers
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2801—Testing of printed circuits, backplanes, motherboards, hybrid circuits or carriers for multichip packages [MCP]
    • G01R31/2806—Apparatus therefor, e.g. test stations, drivers, analysers, conveyors
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/2851—Testing of integrated circuits [IC]
    • G01R31/2884—Testing of integrated circuits [IC] using dedicated test connectors, test elements or test circuits on the IC under test
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Definitions

  • the invention relates to the field of chip testing, in particular to a device and method for serial testing of chip shared resources.
  • each chip takes up some ATE resources, which makes the ATE test platform unable to achieve optimal resource allocation.
  • the chip needs to wait a long time before the test results can be fed back. For example, the action of erasing the chip takes 2s or more. Long, during the waiting process, the tester will not perform any action on the chip except power supply, which is equivalent to the tester being in an idle state during this time, which causes a waste of time in the test process.
  • the method of sequentially testing chips in the prior art has the following two problems: First, when the chip is in the waiting process of the test item in the prior art, each pin of the chip is connected to the test platform, and these leads The feet are not being tested at this time, but they occupy the resources of the test platform, causing a waste of resources. Second, in the testing process of each chip, some idle time is not used, resulting in a waste of time.
  • the purpose of the present invention is to provide a chip shared resource serial test device and method, which can reduce the resource waste of the test platform in the prior art and can also save the chip test time.
  • a method for serial testing of chip shared resources including the following steps:
  • test platform enters the occupancy time of each test item in each chip
  • test platform controls the double-throw relay to connect to chip A, and the test platform tests chip A.
  • the test platform sends a test command for test item X to chip A and enters step S04; otherwise, the test platform tests each test item of chip A in turn.
  • the test platform controls the double-throw relay to be connected to Chip B, the test platform tests chip B;
  • test platform controls the double-throw relay to be connected to chip B, and the test platform tests one or more test items on chip B;
  • test platform controls the double-throw relay to be connected to the chip A, and the test platform receives the test result of the test item X of the chip A, and returns to step S03.
  • chip A and the chip B are chips of the same batch, and the test items are the same.
  • both the chip A and the chip B include N test pins, a power supply pin and a ground pin, and the same test pins in the chip A and the chip B are connected to the same double-throw relay; N is A positive integer greater than 1.
  • double-throw relays are respectively connected to the test platform through corresponding test channels.
  • the N double-throw relays are all connected to chip A; when the test platform tests chip B, the N double-throw relays are all connected to Chip B.
  • step S03 when the idle time of the test item X of the chip A is greater than the sum of the switching time of the double-throw relay and the test time of one or more test items of the chip B, the test platform Chip A sends the test command of test item X, and enters step S04.
  • the switching time of the double-throw relay includes the time for the double-throw relay to switch to chip B and the time for the double-throw relay to switch back to chip A.
  • test platform is an ATE test platform.
  • test items include one or more of a chip open and short circuit test, a chip leakage test, a function test in the customer mode of the chip, and a function test in the test mode.
  • a serial test device for chip shared resources including chip A and chip B, N double-throw relays, and a test platform, wherein said chip A and chip B include N test pins, said chip A and chip B The same test pin is connected to the test platform through the same double-throw relay, and the test platform is connected to N double-throw relays at the same time; N is a positive integer greater than 1;
  • test platform When the idle time of test item X of chip A is greater than the test time of one or more test items of chip B, the test platform sends a test command of test item X to chip A, and the test platform controls the double-throw relay to be connected to Chip B, the test platform tests one or more test items on chip B, and then the test platform controls the double-throw relay to connect to chip A, the test platform receives the test results of test item X of chip A, and Continue to test chip A.
  • the beneficial effect of the present invention is that in the present invention, two chips of the same batch are connected to the test platform through a double-throw relay, and when a certain test item of one of the chips needs a long time to feedback, through the switching of the double-throw relay, The test platform can perform short-time test items for another chip.
  • the present invention can make use of the waiting time in the test process by switching the double-throw relay. Such repetition can effectively save the chip test time.
  • the present invention enables only one chip to be connected to the test platform at a time through the switching of the double-throw relay, which can avoid the waste of resources of the test platform.
  • Figure 1 is a flowchart of a serial test method for chip shared resources according to the present invention
  • Fig. 2 is a structural diagram of a serial test device for chip shared resources in the second embodiment.
  • a method for serial testing of chip shared resources includes the following steps:
  • chip testing is generally divided into many test items according to different functions of the chip, and each test item is independent of each other.
  • some test items in the chip require a long waiting time. For example, after the erase or programming command of the Flash chip is completed, it is necessary to wait for a while before the chip can fully take effect after the command has just been sent, that is, a long waiting time is required. The erasing or programming process of the chip can be completed and fed back to the test platform.
  • this waiting time except for the need to supply power to the chip, other pins are in the idle stage. Therefore, the core idea of the present invention is to use this idle time and release the resources occupied by the idle pins to other chips.
  • the chip A and the chip B in the present invention are chips of the same batch, and the test items are the same.
  • Both chip A and chip B contain N test pins, a power supply pin, and a ground pin.
  • the same test pins in chip A and chip B are connected to the same double-throw relay.
  • the power pin is used as a power supply pin to supply power to the chip
  • the ground pin is used as a reference ground signal to connect with the reference ground signal of the test platform.
  • the double-throw relays are respectively connected to the test platform through the corresponding test channels.
  • the number of test channels of the test platform, the number of double-throw relays, and the number of test pins of chip A and chip B correspond one-to-one.
  • the test platform is connected to chip A and chip B through a double-throw relay to ensure that after the double-throw relay is converted, the test platform can switch from chip A to chip B through the double-throw relay in time.
  • the test platform in the present invention is an ATE test platform.
  • test platform enters the occupancy time of each test item in each chip; the test platform needs to fully know the occupancy time of each test item of chip A and chip B, as well as the minimum idle time of chip A, to ensure that when the double-throw relay is switched , The time that the test platform resources are released to chip B is less than the minimum idle time of chip A.
  • the test platform is connected to the double-throw relay, and the command to switch the double-throw relay can be issued in time to save the most time.
  • the test items in the present invention include one or more of the chip open and short circuit test, the chip leakage test, the function test in the customer mode of the chip, and the function test in the test mode.
  • test platform controls the double-throw relay to connect to chip A, and the test platform tests chip A.
  • the idle time of test item X of chip A is greater than the test time of one or more test items of chip B
  • the test platform sends the test command of test item X to chip A and enters step S04; otherwise, the test platform tests each test item of chip A in turn.
  • the test platform controls the double-throw relay to connect to chip B, and the test platform Chip B is tested.
  • the test platform when the test platform tests the chip A, the N double-throw relays are all connected to the chip A; when the test platform tests the chip B, the N double-throw relays are all connected to the chip B.
  • the test platform controls double-throw relays to switch, which means to control N double-throw relays to switch at the same time.
  • the idle time of test item X of chip A means that after the test platform sends the instruction of test item X, chip A needs x seconds to complete the instruction, where x seconds is the idle time of test item X of chip A .
  • the test platform can test chip B, and the test time of chip B is less than the idle time of chip A. In this way, when the test platform completes the test on the chip B and switches to the chip A, it is just used to receive the feedback result of the test item X of the chip A.
  • the present invention needs to ensure that: when the idle time of the test item X of chip A is greater than the sum of the switching time of the double-throw relay and the test time of one or more test items of chip B, the test platform sends the test item to chip A X test command, and go to step S04.
  • the switching time of the double-throw relay includes the time for the double-throw relay to switch to chip B and the time for the double-throw relay to switch back to chip A.
  • test platform controls the double-throw relay to be connected to chip B, and the test platform tests one or more test items on chip B.
  • the one or more test items here refer to one or more test items in step S03 "when the idle time of the test item X of chip A is greater than the test time of one or more test items of chip B".
  • test platform controls the double-throw relay to be connected to the chip A, the test platform receives the test result of the test item X of the chip A, and returns to step S03.
  • the invention provides a chip shared resource serial test device, which includes chip A and chip B, N double-throw relays, and a test platform.
  • chip A and chip B include N test pins
  • chip A and chip B The same test pin is connected to the test platform through the same double-throw relay, and the test platform is connected to N double-throw relays at the same time.
  • test platform When the idle time of test item X of chip A is greater than the test time of one or more test items of chip B, the test platform sends a test command of test item X to chip A, and the test platform controls the double-throw relay to connect to chip B and test The platform tests one or more test items on the chip B, and then the test platform controls the double-throw relay to connect to the chip A, the test platform receives the test results of the test item X of the chip A, and continues to test the chip A.
  • test platform is ATE; it includes the following steps:
  • chip A and chip B are chips of the same batch, and the test items are the same.
  • Chip A and Chip B include 6 test pins, a power supply pin, and a ground pin. The same test pins in chip A and chip B are connected to the corresponding test channel of the test platform through the same high-speed single-pole double-throw relay.
  • the test platform enters the occupancy time of each test item in each chip; the test items of the chip include chip open and short circuit test, chip leakage test, chip erasing, and chip programming.
  • the effective time after the chip receives the erase command takes 2s; the effective time after the chip receives the programming command takes 3.2s; the chip open and short circuit test takes 20ms; the chip leakage test takes 30ms ;
  • the switching time of the high-speed single-pole double-throw relay takes 5ms.
  • the test platform controls the high-speed single-pole double-throw relay to connect to chip A, and the test platform first performs chip open and short circuit test on chip A;
  • the test platform performs chip leakage test on chip A
  • the test platform sends an erase command to chip A. At this time, the test platform controls a high-speed single-pole double-throw relay to connect to chip B;
  • the test platform performs a chip open and short circuit test on chip B;
  • the test platform controls the high-speed single-pole double-throw relay to connect to chip A;
  • the test platform performs chip programming on chip A
  • the test platform controls the high-speed single-pole double-throw relay to connect to chip B;
  • the test platform performs chip erasure on chip B;
  • the test platform performs chip programming on chip B. The entire test process took 6.470 seconds.
  • the above-mentioned testing process includes the following procedures:
  • the test platform performs chip leakage test on chip A
  • the test platform performs chip erasure on chip A
  • the test platform performs chip programming on chip A
  • the test platform performs a chip open and short circuit test on chip B;
  • the test platform performs chip erasure on chip B;
  • the test platform performs chip programming on chip B. The entire test process took 10.5 seconds.
  • test platform When the idle time of test item X of chip A is greater than the test time of one or more test items of chip B, the test platform sends a test command of test item X to chip A, and the test platform controls the double-throw relay to connect to chip B, namely The terminal 2 and terminal 1 of the 3 relays are connected; the test platform tests one or more test items on chip B, and then the test platform controls the double-throw relay to connect to chip A, that is, the terminal 2 and terminal of the 3 relays Head 3 is connected, the test platform receives the test result of the test item X of chip A, and continues to test chip A.
  • this embodiment reduces the waste of test resources by more than 40% in the chip serial test process in the prior art, and saves more than 30% of the test time.

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)

Abstract

一种芯片共享资源串行测试方法，包括如下步骤：S01：将芯片A和芯片B通过双掷继电器同时连接至测试平台；S02：测试平台录入每个芯片中各个测试项目的占用时间；S03：测试平台控制双掷继电器连接至芯片A，当芯片A的测试项目X的闲置时间大于芯片B的一个或多个测试项目的测试时间时，进入步骤S04；否则，测试平台对芯片A各个测试项目依次进行测试，测试完成之后，测试平台控制双掷继电器连接至芯片B，测试平台对芯片B进行测试；S04：测试平台控制双掷继电器连接至芯片B，测试平台对芯片B进行一个或多个测试项目的测试；S05：测试平台控制双掷继电器连接至芯片A，返回步骤S03。本方案可以节省芯片测试时间。

Description

一种芯片共享资源串行测试装置及方法
交叉引用
本申请要求2020年2月24日提交的申请号为CN 202010113069.0的中国专利申请的优先权。上述申请的内容以引用方式被包含于此。
技术领域
本发明涉及芯片测试领域，具体涉及一种芯片共享资源串行测试装置及方法。
技术背景
在芯片的测试过程中，常常需要对各种芯片进行不同的功能测试。现有的芯片测试方法均采用排队测试法，即同一批芯片依次进入测试平台(ATE)进行功能测试。
但是在实际应用过程中，每个芯片都要占用一些ATE资源，使得ATE测试平台不能实现最优资源分配。在目前这种依次测试的装置和方法中，当芯片测试时，特别是存储型芯片，有些命令发出以后，芯片内部需要等待很长时间才能反馈测试结果，比如擦除芯片的动作需要2s甚至更长，在等待过程中，测试机不会对该芯片做除供电以外的任何动作，相当于该时间内测试机处于闲置状态，所以造成测试过程中时间的浪费。
因此现有技术中依次测试芯片的方法，存在以下两个问题：第一，现有技术中当芯片处于测试项目的等待过程中时，芯片的每个引脚均连接在测试平台上，这些引脚此时并没有进行测试，却要占用测试平台的资源，造成资源浪费。第二，每个芯片的测试进程中均有些闲置时间没有利用起来，造成时间浪费。
发明概要
本发明的目的是提供一种芯片共享资源串行测试装置及方法，可以减小现有技术中测试平台的资源浪费，还能节省芯片测试时间。
为了实现上述目的，本发明采用如下技术方案：一种芯片共享资源串行测试方法，包括如下步骤：
S01：将芯片A和芯片B通过双掷继电器同时连接至测试平台；
S02：测试平台录入每个芯片中各个测试项目的占用时间；
S03：所述测试平台控制双掷继电器连接至芯片A，所述测试平台对芯片A进行测试，当芯片A的测试项目X的闲置时间大于芯片B的一个或多个测试项目的测试时间时，所述测试平台对芯片A发送测试项目X的测试命令，并进入步骤S04；否则，所述测试平台对芯片A各个测试项目依次进行测试，测试完成之后，所述测试平台控制双掷继电器连接至芯片B，所述测试平台对芯片B进行测试；
S04：所述测试平台控制双掷继电器连接至芯片B，所述测试平台对芯片B进行一个或多个测试项目的测试；
S05：所述测试平台控制双掷继电器连接至芯片A，所述测试平台接收芯片A的测试项目X的测试结果，返回步骤S03。
进一步地，所述芯片A和芯片B为同一批次的芯片，且测试项目相同。
进一步地，所述芯片A和芯片B均包含N个测试引脚，一个电源引脚和一个接地引脚，所述芯片A和芯片B中相同的测试引脚连接同一个双掷继电器；N为大于1的正整数。
进一步地，所述双掷继电器分别通过对应的测试通道连接至所述测试平 台。
进一步地，当所述测试平台对芯片A进行测试时，所述N个双掷继电器均连接至芯片A；当所述测试平台对芯片B进行测试时，所述N个双掷继电器均连接至芯片B。
进一步地，所述步骤S03中，当芯片A的测试项目X的闲置时间大于所述双掷继电器的切换时间与芯片B的一个或多个测试项目的测试时间之和时，所述测试平台对芯片A发送测试项目X的测试命令，并进入步骤S04。
进一步地，所述双掷继电器的切换时间包括双掷继电器切换至芯片B的时间以及双掷继电器切换回芯片A的时间。
进一步地，所述测试平台为ATE测试平台。
进一步地，所述测试项目包括芯片开短路测试，芯片漏电测试，芯片的客户模式下的功能测试和测试模式下的功能测试中的一种或多种。
一种芯片共享资源串行测试装置，包括芯片A和芯片B，N个双掷继电器，以及测试平台，其中，所述芯片A和芯片B包括N个测试引脚，所述芯片A和芯片B中相同的测试引脚通过同一个双掷继电器连接至所述测试平台，所述测试平台同时连接N个双掷继电器；N为大于1的正整数；
当芯片A的测试项目X的闲置时间大于芯片B的一个或多个测试项目的测试时间时，所述测试平台对芯片A发送测试项目X的测试命令，所述测试平台控制双掷继电器连接至芯片B，所述测试平台对芯片B进行一个或多个测试项目的测试，之后所述测试平台控制双掷继电器连接至芯片A，所述测试平台接收芯片A的测试项目X的测试结果，并继续对芯片A进行测试。
本发明的有益效果为：本发明中将同一批次的两个芯片通过双掷继电器连接至测试平台，当其中一个芯片的某个测试项目需要较长时间反馈时，通过双掷继电器的切换，测试平台可以进行另外一个芯片的短时间测试项目，本发明通过双掷继电器的切换，可以使得测试过程中的等待时间均被利用起来，如此反复，可以有效节省芯片测试时间。同时，本发明通过双掷继电器的切换，使得每次只有一个芯片连接至测试平台上，可以避免测试平台的资源浪费。
附图说明
附图1为本发明芯片共享资源串行测试方法的流程图；
附图2为实施例2中芯片共享资源串行测试装置的结构图。
发明内容
为使本发明的目的、技术方案和优点更加清楚，下面结合附图对本发明的具体实施方式做进一步的详细说明。
如附图1所示，本发明提供的一种芯片共享资源串行测试方法，包括如下步骤：
S01：将芯片A和芯片B通过双掷继电器同时连接至测试平台。
在实际应用中，芯片测试一般来说是根据芯片的不同功能而分成很多测试项目，各个测试项目相互之间独立。而芯片中有的测试项目需要较长的等待时间，比如Flash芯片的擦除或编程命令结束后，还需要等待一段时间芯片才能使刚发完的命令完全生效，即需要较长的等待时间，芯片的擦除或者编程过程才能完成并反馈至测试平台。但是在这段等待时间内除了需要给芯片供电以外，其他引脚处于闲置阶段，所以本发明的核心思想在于把这段闲 置时间利用起来，把闲置引脚所占用的资源释放给其他芯片去做一些少于该芯片闲置时间的测试项目。
优选地，本发明中芯片A和芯片B为同一批次的芯片，且测试项目相同。芯片A和芯片B均包含N个测试引脚，一个电源引脚，和一个接地引脚。芯片A和芯片B中相同的测试引脚连接同一个双掷继电器。电源引脚作为供电引脚对芯片进行供电，接地引脚作为参考地信号与测试平台的参考地信号连接在一起。
双掷继电器分别通过对应的测试通道连接至测试平台。
本发明中测试平台的测试通道个数、双掷继电器的个数、芯片A和芯片B的测试引脚个数一一对应。测试平台通过双掷继电器与芯片A和芯片B相连接，确保当双掷继电器转换之后，测试平台能够及时通过双掷继电器从芯片A切换至芯片B。
优选地，本发明中测试平台为ATE测试平台。
S02：测试平台录入每个芯片中各个测试项目的占用时间；测试平台需要完全知道芯片A和芯片B每个测试项目的占用时间，以及芯片A的最小闲置时间，确保在双掷继电器进行切换时，测试平台资源释放给芯片B的时间要小于芯片A的最小闲置时间。本发明中测试平台连接双掷继电器，能够及时发出切换双掷继电器的命令，以节省出最多时间。
本发明中测试项目包括芯片开短路测试，芯片漏电测试，芯片的客户模式下的功能测试和测试模式下的功能测试中的一种或多种。
S03：测试开始时，测试平台控制双掷继电器连接至芯片A，测试平台对芯片A进行测试，当芯片A的测试项目X的闲置时间大于芯片B的一个 或多个测试项目的测试时间时，测试平台对芯片A发送测试项目X的测试命令，并进入步骤S04；否则，测试平台对芯片A各个测试项目依次进行测试，测试完成之后，测试平台控制双掷继电器连接至芯片B，测试平台对芯片B进行测试。
本发明中当测试平台对芯片A进行测试时，N个双掷继电器均连接至芯片A；当测试平台对芯片B进行测试时，N个双掷继电器均连接至芯片B。测试平台控制双掷继电器进行切换，指的是控制N个双掷继电器同时进行切换。
本步骤中芯片A的测试项目X的闲置时间指的是测试平台发送测试项目X的指令之后，芯片A需要x秒才能完成该指令，这里的x秒即为芯片A的测试项目X的闲置时间。在该闲置时间内，测试平台可以对芯片B进行测试，且B的测试时间少于芯片A的闲置时间。如此一来，当测试平台完成对芯片B的测试且切换至芯片A时，刚好用于接收芯片A的测试项项目X的反馈结果。
进一步地，本发明需要确保：当芯片A的测试项目X的闲置时间大于双掷继电器的切换时间与芯片B的一个或多个测试项目的测试时间之和时，测试平台对芯片A发送测试项目X的测试命令，并进入步骤S04。其中，双掷继电器的切换时间包括双掷继电器切换至芯片B的时间以及双掷继电器切换回芯片A的时间。
S04：测试平台控制双掷继电器连接至芯片B，测试平台对芯片B进行一个或多个测试项目的测试。这里的一个或多个测试项目指的是步骤S03中“当芯片A的测试项目X的闲置时间大于芯片B的一个或多个测试项目的 测试时间时”中的一个或多个测试项目。
S05：测试平台控制双掷继电器连接至芯片A，测试平台接收芯片A的测试项目X的测试结果，并返回步骤S03。
本发明中当芯片A测试完成以后，芯片B进行过的一些测试项目则无需再测，只需要测试在上一周期没测的测试项目，如此反复，节省下来的时间是非常可观的。
本发明提供的一种芯片共享资源串行测试装置，包括芯片A和芯片B，N个双掷继电器，以及测试平台，其中，芯片A和芯片B包括N个测试引脚，芯片A和芯片B中相同的测试引脚通过同一个双掷继电器连接至测试平台，测试平台同时连接N个双掷继电器。
当芯片A的测试项目X的闲置时间大于芯片B的一个或多个测试项目的测试时间时，测试平台对芯片A发送测试项目X的测试命令，测试平台控制双掷继电器连接至芯片B，测试平台对芯片B进行一个或多个测试项目的测试，之后测试平台控制双掷继电器连接至芯片A，测试平台接收芯片A的测试项目X的测试结果，并继续对芯片A进行测试。
实施例1
本实施例提供的一种芯片共享资源串行测试方法，本发明中测试平台为ATE；包括如下步骤：
S01：将芯片A和芯片B通过高速单刀双掷继电器同时连接至测试平台。其中，芯片A和芯片B为同一批次的芯片，且测试项目相同。芯片A和芯片B包括6个测试引脚，一个电源引脚，和一个接地引脚。芯片A和芯片B中相同的测试引脚通过同一个高速单刀双掷继电器连接至测试平台对应的 测试通道。
S02：测试平台录入每个芯片中各个测试项目的占用时间；其中，芯片的测试项目包括芯片开短路测试，芯片漏电测试，芯片擦除，芯片编程。其中，芯片接收到擦除命令以后的生效时间需要2s；芯片接收到编程命令以后的生效时间需要3.2s；对芯片进行芯片开短路测试的时间需要20ms；对芯片进行芯片漏电测试的时间需要30ms；高速单刀双掷继电器切换的时间需要5ms。
S03：测试开始时，采用本发明方法时，整个测试过程包括如下流程：
测试平台控制高速单刀双掷继电器连接至芯片A，测试平台先芯片A进行芯片开短路测试；
测试平台对芯片A进行芯片漏电测试；
测试平台发送擦除命令给芯片A，此时，测试平台控制高速单刀双掷继电器连接至芯片B；
测试平台对芯片B进行测芯片开短路测试；
测试平台对芯片B进芯片漏电测试；
测试平台控制高速单刀双掷继电器连接至芯片A；
测试平台对芯片A进行芯片编程；
测试平台控制高速单刀双掷继电器连接至芯片B；
测试平台对芯片B进行芯片擦除；
测试平台对芯片B进行芯片编程。整个测试过程耗时6.470秒。
若采用现有技术中依次测试的方法，上述测试过程包括如下流程：
测试平台先芯片A进行芯片开短路测试；
测试平台对芯片A进行芯片漏电测试；
测试平台对芯片A进行芯片擦除；
测试平台对芯片A进行芯片编程；
测试平台控制高速单刀双掷继电器连接至芯片B；
测试平台对芯片B进行测芯片开短路测试；
测试平台对芯片B进芯片漏电测试；
测试平台对芯片B进行芯片擦除；
测试平台对芯片B进行芯片编程。整个测试过程耗时10.5秒。
实施例2
如附图2所示，本实施例提供的一种芯片共享资源串行测试装置，包括芯片A和芯片B，3个双掷继电器，以及测试平台，其中，芯片A和芯片B包括3个测试引脚，如附图2芯片A和芯片B中1、2、3所示；芯片A和芯片B中相同的测试引脚通过同一个双掷继电器连接至测试平台，测试平台同时连接3个双掷继电器。附图2中3个双掷继电器的端头分别为1、2、3，且端头1连接至芯片B中测试引脚，端头3连接至芯片A中测试引脚，端头2连接至测试平台。
当芯片A的测试项目X的闲置时间大于芯片B的一个或多个测试项目的测试时间时，测试平台对芯片A发送测试项目X的测试命令，测试平台控制双掷继电器连接至芯片B，即3个继电器的端头2和端头1连接；测试平台对芯片B进行一个或多个测试项目的测试，之后测试平台控制双掷继电器连接至芯片A，即3个继电器的端头2和端头3连接，测试平台接收芯片A的测试项目X的测试结果，并继续对芯片A进行测试。
因此，本发明中将同一批次的两个芯片通过双掷继电器连接至测试平台，可以使得测试过程中的等待时间均被利用起来，如此反复，可以有效节省芯片测试时间。本实施例相比现有技术中方法，减少了现有技术中芯片串测过程中40％以上的测试资源浪费，节省30％以上的测试时间。
以上所述仅为本发明的优选实施例，所述实施例并非用于限制本发明的专利保护范围，因此凡是运用本发明的说明书及附图内容所作的等同结构变化，同理均应包含在本发明所附权利要求的保护范围内。

Claims (10)

  1. 一种芯片共享资源串行测试方法，其特征在于，包括如下步骤：
    S01：将芯片A和芯片B通过双掷继电器同时连接至测试平台；
    S02：测试平台录入每个芯片中各个测试项目的占用时间；
    S03：所述测试平台控制双掷继电器连接至芯片A，所述测试平台对芯片A进行测试，当芯片A的测试项目X的闲置时间大于芯片B的一个或多个测试项目的测试时间时，所述测试平台对芯片A发送测试项目X的测试命令，并进入步骤S04；否则，所述测试平台对芯片A各个测试项目依次进行测试，测试完成之后，所述测试平台控制双掷继电器连接至芯片B，所述测试平台对芯片B进行测试；
    S04：所述测试平台控制双掷继电器连接至芯片B，所述测试平台对芯片B进行一个或多个测试项目的测试；
    S05：所述测试平台控制双掷继电器连接至芯片A，所述测试平台接收芯片A的测试项目X的测试结果，返回步骤S03。
  2. 根据权利要求1所述的一种芯片共享资源串行测试方法，其特征在于，所述芯片A和芯片B为同一批次的芯片，且测试项目相同。
  3. 根据权利要求1所述的一种芯片共享资源串行测试方法，其特征在于，所述芯片A和芯片B均包含N个测试引脚，一个电源引脚和一个接地引脚，所述芯片A和芯片B中相同的测试引脚连接同一个双掷继电器；N为大于1的正整数。
  4. 根据权利要求3所述的一种芯片共享资源串行测试方法，其特征在于，所述双掷继电器分别通过对应的测试通道连接至所述测试平台。
  5. 根据权利要求3所述的一种芯片共享资源串行测试方法，其特征在于，当所述测试平台对芯片A进行测试时，所述N个双掷继电器均连接至芯片A；当所述测试平台对芯片B进行测试时，所述N个双掷继电器均连接至芯片B。
  6. 根据权利要求5所述的一种芯片共享资源串行测试方法，其特征在于，所述步骤S03中，当芯片A的测试项目X的闲置时间大于所述双掷继电器的切换时间与芯片B的一个或多个测试项目的测试时间之和时，所述测试平台对芯片A发送测试项目X的测试命令，并进入步骤S04。
  7. 根据权利要求6所述的一种芯片共享资源串行测试方法，其特征在于，所述双掷继电器的切换时间包括双掷继电器切换至芯片B的时间以及双掷继电器切换回芯片A的时间。
  8. 根据权利要求1所述的一种芯片共享资源串行测试方法，其特征在于，所述测试平台为ATE测试平台。
  9. 根据权利要求1所述的一种芯片共享资源串行测试方法，其特征在于，所述测试项目包括芯片开短路测试，芯片漏电测试，芯片的客户模式下的功能测试和测试模式下的功能测试中的一种或多种。
  10. 一种芯片共享资源串行测试装置，其特征在于，包括芯片A和芯片B，N个双掷继电器，以及测试平台，其中，所述芯片A和芯片B包括N个测试引脚，所述芯片A和芯片B中相同的测试引脚通过同一个双掷继电器连接至所述测试平台，所述测试平台同时连接N个双掷继电器；N为大于1的正整数；
    当芯片A的测试项目X的闲置时间大于芯片B的一个或多个测试项目的测试时间时，所述测试平台对芯片A发送测试项目X的测试命令，所述 测试平台控制双掷继电器连接至芯片B，所述测试平台对芯片B进行一个或多个测试项目的测试，之后所述测试平台控制双掷继电器连接至芯片A，所述测试平台接收芯片A的测试项目X的测试结果，并继续对芯片A进行测试。
PCT/CN2020/120804 2020-02-24 2020-10-14 一种芯片共享资源串行测试装置及方法 WO2021169317A1 (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN202010113069.0A CN111273157B (zh) 2020-02-24 2020-02-24 一种芯片共享资源串行测试装置及方法
CN202010113069.0 2020-02-24

Publications (1)

Publication Number Publication Date
WO2021169317A1 true WO2021169317A1 (zh) 2021-09-02

Family

ID=71002316

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/CN2020/120804 WO2021169317A1 (zh) 2020-02-24 2020-10-14 一种芯片共享资源串行测试装置及方法

Country Status (2)

Country Link
CN (1) CN111273157B (zh)
WO (1) WO2021169317A1 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111273157B (zh) * 2020-02-24 2022-07-08 上海御渡半导体科技有限公司 一种芯片共享资源串行测试装置及方法
CN114690025B (zh) * 2022-05-31 2022-10-11 浙江瑞测科技有限公司 一种多工位并行测试方法
CN116482521B (zh) * 2023-06-25 2023-10-20 江西兆驰半导体有限公司 一种芯片测试方法及***

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001004716A (ja) * 1999-06-24 2001-01-12 Matsushita Electric Ind Co Ltd Ｌｓｉの検査方法
US7106073B1 (en) * 2005-05-27 2006-09-12 Lsi Logic Corporation Method and system for area efficient charge-based capacitance measurement
US20070167785A1 (en) * 2005-12-23 2007-07-19 Arm Limited Diagnostic mode switching
WO2008033971A2 (en) * 2006-09-13 2008-03-20 Texas Instruments Incorporated Device test and debug using power and ground terminals
CN102473462A (zh) * 2009-07-02 2012-05-23 晶像股份有限公司 计算机存储器测试结构
CN102869998A (zh) * 2010-01-20 2013-01-09 爱德万测试(新加坡)私人有限公司 用于测试待测装置的方法及设备
US20140074423A1 (en) * 2009-11-13 2014-03-13 Samsung Electronics Co., Ltd. Built-off test device and test system including the same
JP5526910B2 (ja) * 2010-03-25 2014-06-18 日本電気株式会社 タイミング調整回路及びタイミング調整方法
CN104219003A (zh) * 2013-05-30 2014-12-17 展讯通信（上海）有限公司 通信装置、测试***及其测试方法
CN105911462A (zh) * 2015-02-20 2016-08-31 得克萨斯测试公司 用于半导体集成电路器件的功能数字测试的自动测试设备
CN106353667A (zh) * 2015-07-13 2017-01-25 璧典凯 一种快速测试调度方法
CN209117739U (zh) * 2018-10-30 2019-07-16 嘉兴鹏武电子科技有限公司 手机led驱动测试探针卡
CN111273157A (zh) * 2020-02-24 2020-06-12 上海御渡半导体科技有限公司 一种芯片共享资源串行测试装置及方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6591388B1 (en) * 2000-04-18 2003-07-08 International Business Machines Corporation High speed sink/source register to reduce level sensitive scan design test time
CN101995491B (zh) * 2009-08-26 2013-06-19 中芯国际集成电路制造(上海)有限公司 适配板、双工位测试机的改装方法和测试方法
CN102169150B (zh) * 2010-12-30 2013-01-02 成都芯通科技股份有限公司 基于矩阵开关的并行测试***
US20170045579A1 (en) * 2015-08-14 2017-02-16 Texas Instruments Incorporated Cpu bist testing of integrated circuits using serial wire debug

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001004716A (ja) * 1999-06-24 2001-01-12 Matsushita Electric Ind Co Ltd Ｌｓｉの検査方法
US7106073B1 (en) * 2005-05-27 2006-09-12 Lsi Logic Corporation Method and system for area efficient charge-based capacitance measurement
US20070167785A1 (en) * 2005-12-23 2007-07-19 Arm Limited Diagnostic mode switching
WO2008033971A2 (en) * 2006-09-13 2008-03-20 Texas Instruments Incorporated Device test and debug using power and ground terminals
CN102473462A (zh) * 2009-07-02 2012-05-23 晶像股份有限公司 计算机存储器测试结构
US20140074423A1 (en) * 2009-11-13 2014-03-13 Samsung Electronics Co., Ltd. Built-off test device and test system including the same
CN102869998A (zh) * 2010-01-20 2013-01-09 爱德万测试(新加坡)私人有限公司 用于测试待测装置的方法及设备
JP5526910B2 (ja) * 2010-03-25 2014-06-18 日本電気株式会社 タイミング調整回路及びタイミング調整方法
CN104219003A (zh) * 2013-05-30 2014-12-17 展讯通信（上海）有限公司 通信装置、测试***及其测试方法
CN105911462A (zh) * 2015-02-20 2016-08-31 得克萨斯测试公司 用于半导体集成电路器件的功能数字测试的自动测试设备
CN106353667A (zh) * 2015-07-13 2017-01-25 璧典凯 一种快速测试调度方法
CN209117739U (zh) * 2018-10-30 2019-07-16 嘉兴鹏武电子科技有限公司 手机led驱动测试探针卡
CN111273157A (zh) * 2020-02-24 2020-06-12 上海御渡半导体科技有限公司 一种芯片共享资源串行测试装置及方法

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
AGRAWAL V D: "Design of mixed-signal systems for testability", VLSI JOURNAL, no. 26, 31 December 1998 (1998-12-31), ISSN: 0167-9260 *
WANG, LEI: "System Construction and Simulation Evaluation of Distributed ATS", NATIONAL DEFENSE INDUSTRY PRESS, 31 May 2019 (2019-05-31), ISBN: 7-118-11738-7 *

Also Published As

Publication number Publication date
CN111273157B (zh) 2022-07-08
CN111273157A (zh) 2020-06-12

Similar Documents

Publication Publication Date Title
WO2021169317A1 (zh) 一种芯片共享资源串行测试装置及方法
US20080221824A1 (en) Test apparatus, test method and recording medium
US5636227A (en) Integrated circuit test mechansim and method
US20190331732A1 (en) Addressable test access port method and apparatus
US7047463B1 (en) Method and system for automatically determining a testing order when executing a test flow
KR0136054B1 (ko) 피측정소자의 테스트방법 및 테스트시스템
KR100630730B1 (ko) 테스트 타임을 단축할 수 있는 멀티 칩 패키지
KR20010112254A (ko) 플렉서블 선택 스캔 테스트 체인 및 방법, 플렉서블 스캔테스트가능 버스 드라이버 시스템
US7111216B2 (en) Scan controller and integrated circuit including such a controller
US6480979B1 (en) Semiconductor integrated circuits and efficient parallel test methods
CN115061032A (zh) 一种多时钟域芯片的功能测试方法及测试装置
KR20050053093A (ko) 시스템 온 칩의 테스트를 위한 코아 접속 스위치
US6813579B1 (en) Apparatus and method for test mode control
US7089471B2 (en) Scan testing mode control of gated clock signals for flip-flops
JP3606520B2 (ja) システムｌｓｉのテストパターン作成方法，システムｌｓｉのテストパターン作成装置，及びシステムｌｓｉのテスト方法
US5497350A (en) Integrated semiconductor memory device capable of switching from a memory mode to an internal test mode
US7173840B2 (en) Acceleration of the programming of a memory module with the aid of a boundary scan (BSCAN) register
CN112505520B (zh) 一种芯片测试方法、设备及***
JPH0530225B2 (zh)
KR100502123B1 (ko) 다중테스트억세스포트환경에서테스트억세스포트의선택적억세싱
US11340294B2 (en) Boundary test circuit, memory and boundary test method
KR100296327B1 (ko) 플래쉬 메모리 장치의 테스트 회로 및 테스트 방법
CN116338444A (zh) 测试电路及其工作方法
CN112285529A (zh) 一种使用ate测试向量控制继电器的方法
JPS59178374A (ja) 集積回路用試験回路

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 20921210

Country of ref document: EP

Kind code of ref document: A1

NENP Non-entry into the national phase

Ref country code: DE

122 Ep: pct application non-entry in european phase

Ref document number: 20921210

Country of ref document: EP

Kind code of ref document: A1