WO2021108393A1 - Glass wafers for semiconductor device fabrication - Google Patents
Glass wafers for semiconductor device fabrication Download PDFInfo
- Publication number
- WO2021108393A1 WO2021108393A1 PCT/US2020/061990 US2020061990W WO2021108393A1 WO 2021108393 A1 WO2021108393 A1 WO 2021108393A1 US 2020061990 W US2020061990 W US 2020061990W WO 2021108393 A1 WO2021108393 A1 WO 2021108393A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- coating
- glass wafer
- layer
- glass
- silicon
- Prior art date
Links
- 239000011521 glass Substances 0.000 title claims abstract description 198
- 235000012431 wafers Nutrition 0.000 title description 104
- 238000005389 semiconductor device fabrication Methods 0.000 title description 5
- 238000000576 coating method Methods 0.000 claims abstract description 163
- 239000011248 coating agent Substances 0.000 claims abstract description 153
- 239000000758 substrate Substances 0.000 claims abstract description 84
- 238000002834 transmittance Methods 0.000 claims abstract description 60
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 40
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 40
- 239000010703 silicon Substances 0.000 claims abstract description 40
- 239000004065 semiconductor Substances 0.000 claims abstract description 31
- 238000004519 manufacturing process Methods 0.000 claims abstract description 30
- 229910021419 crystalline silicon Inorganic materials 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims abstract description 24
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 51
- 229910021417 amorphous silicon Inorganic materials 0.000 claims description 23
- 239000000377 silicon dioxide Substances 0.000 claims description 21
- 235000012239 silicon dioxide Nutrition 0.000 claims description 21
- 238000002161 passivation Methods 0.000 claims description 19
- 238000012545 processing Methods 0.000 claims description 16
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 14
- 230000003287 optical effect Effects 0.000 claims description 14
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 14
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 3
- 229910004541 SiN Inorganic materials 0.000 claims description 2
- 229910052785 arsenic Inorganic materials 0.000 claims description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 claims description 2
- 229910052681 coesite Inorganic materials 0.000 claims description 2
- 229910052906 cristobalite Inorganic materials 0.000 claims description 2
- 229910052682 stishovite Inorganic materials 0.000 claims description 2
- 229910052905 tridymite Inorganic materials 0.000 claims description 2
- 230000008569 process Effects 0.000 abstract description 15
- 239000000463 material Substances 0.000 description 22
- 238000010438 heat treatment Methods 0.000 description 17
- 238000001816 cooling Methods 0.000 description 14
- 239000005350 fused silica glass Substances 0.000 description 11
- 229910021423 nanocrystalline silicon Inorganic materials 0.000 description 9
- 238000013461 design Methods 0.000 description 8
- 239000000523 sample Substances 0.000 description 8
- 229910017817 a-Ge Inorganic materials 0.000 description 6
- 230000005540 biological transmission Effects 0.000 description 6
- 230000003247 decreasing effect Effects 0.000 description 6
- 238000009826 distribution Methods 0.000 description 6
- 229910052732 germanium Inorganic materials 0.000 description 4
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 4
- 229910052751 metal Inorganic materials 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 238000012546 transfer Methods 0.000 description 4
- 238000007499 fusion processing Methods 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 230000005686 electrostatic field Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 239000000203 mixture Substances 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- XOJVVFBFDXDTEG-UHFFFAOYSA-N Norphytane Natural products CC(C)CCCC(C)CCCC(C)CCCC(C)C XOJVVFBFDXDTEG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 238000005299 abrasion Methods 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 239000003513 alkali Substances 0.000 description 1
- 239000005358 alkali aluminosilicate glass Substances 0.000 description 1
- 239000005407 aluminoborosilicate glass Substances 0.000 description 1
- 239000005354 aluminosilicate glass Substances 0.000 description 1
- 238000004630 atomic force microscopy Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 239000005388 borosilicate glass Substances 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- -1 coatings Substances 0.000 description 1
- 238000012790 confirmation Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 238000003286 fusion draw glass process Methods 0.000 description 1
- 239000006015 fusion formed glass Substances 0.000 description 1
- 230000001939 inductive effect Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 230000001404 mediated effect Effects 0.000 description 1
- 238000006396 nitration reaction Methods 0.000 description 1
- 230000008520 organization Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 230000003595 spectral effect Effects 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
- 238000000427 thin-film deposition Methods 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02367—Substrates
- H01L21/0237—Materials
- H01L21/02422—Non-crystalline insulating materials, e.g. glass, polymers
-
- C—CHEMISTRY; METALLURGY
- C03—GLASS; MINERAL OR SLAG WOOL
- C03C—CHEMICAL COMPOSITION OF GLASSES, GLAZES OR VITREOUS ENAMELS; SURFACE TREATMENT OF GLASS; SURFACE TREATMENT OF FIBRES OR FILAMENTS MADE FROM GLASS, MINERALS OR SLAGS; JOINING GLASS TO GLASS OR OTHER MATERIALS
- C03C17/00—Surface treatment of glass, not in the form of fibres or filaments, by coating
- C03C17/34—Surface treatment of glass, not in the form of fibres or filaments, by coating with at least two coatings having different compositions
- C03C17/3411—Surface treatment of glass, not in the form of fibres or filaments, by coating with at least two coatings having different compositions with at least two coatings of inorganic materials
- C03C17/3429—Surface treatment of glass, not in the form of fibres or filaments, by coating with at least two coatings having different compositions with at least two coatings of inorganic materials at least one of the coatings being a non-oxide coating
- C03C17/3482—Surface treatment of glass, not in the form of fibres or filaments, by coating with at least two coatings having different compositions with at least two coatings of inorganic materials at least one of the coatings being a non-oxide coating comprising silicon, hydrogenated silicon or a silicide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02436—Intermediate layers between substrates and deposited layers
- H01L21/02439—Materials
- H01L21/02488—Insulating materials
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/02521—Materials
- H01L21/02524—Group 14 semiconducting materials
- H01L21/02532—Silicon, silicon germanium, germanium
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/68—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment
- H01L21/681—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for positioning, orientation or alignment using optical controlling means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02518—Deposited layers
- H01L21/0257—Doping during depositing
- H01L21/02573—Conductivity type
- H01L21/02576—N-type
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
- H01L29/1604—Amorphous materials
Definitions
- Embodiments of the present disclosure generally relate to semiconductor fabrication processing and more specifically to glass wafers for semiconductor device fabrication.
- the fabrication tools used in the process of making integrated circuits and other devices include, among other items, automatic loading and unloading equipment (e.g., cassette autoloaders that load and unload into lithographic equipment, etching equipment, and the like).
- cassette autoloaders depend on various sensors to determine the placement, position, and confirmation of location as the wafers move in and out of the tools. This is accomplished by the use of a wafer flat, notch, or other like mechanism positioned at the edge of the wafer, which must be oriented correctly within the tool.
- Silicon is the dominant semiconductor material in use today. In order for glass to be used in a fabrication equipment designed and dedicated to detecting and processing silicon wafers, equipment adjustments would need to be made to semiconductor fabrication equipment to suit glass. For example, one problem is that many of the sensors were designed to sense silicon wafers. Existing sensors are mechanical, optical, and/or inductive/capacitive in nature. While the mechanical-type sensors may work with other materials, the electrical or optical sensors do not always work with other materials. While it is possible to change every sensor on the tools to enable sensing of wafers made of other (i.e., non-silicon) materials, this is undesirable in a manufacturing environment.
- electrostatic chucks which are commonly used in semiconductor fabrication equipment, use electrostatic fields to hold the wafer in place, but the electrostatic chucks as configured for silicon wafer would not work with wafer materials that are not susceptible to electrostatic fields like dielectrics such as glass materials.
- a glass wafer for a semiconductor device includes: a glass substrate comprising: a top surface (102), a bottom surface (104) opposing the top surface, and an edge surface (106) between the top surface and the bottom surface; a first coating (108) disposed atop the glass substrate, wherein the first coating is a doped crystalline silicon coating having a sheet-resistance of 100 to 1,000,000 ohm per square; and a second coating (110) having one or more layers disposed atop the glass substrate, wherein the second coating comprises a silicon containing coating, wherein the glass wafer has an average transmittance (T) of less than 50% over an entire wavelength range of 400 nm to 1000 nm.
- T average transmittance
- a glass wafer for a semiconductor device includes: a glass substrate comprising: a top surface (102), a bottom surface (104) opposing the top surface, and an edge surface (106) between the top surface and the bottom surface; a coating (110) having one or more layers disposed atop the glass wafer, wherein the coating comprises a silicon containing coating, and wherein the glass wafer has an average transmittance (T) of less than 50% over an entire wavelength range of 400 nm to 1000 nm.
- T average transmittance
- a method of fabricating an electronic device includes loading a glass wafer onto a substrate support within a substrate aligner chamber, wherein the substrate aligner comprises a light source, and an optical sensor configured to detect a light beam from the light source, wherein the glass wafer comprises: a glass substrate comprising: a top surface, a bottom surface opposing the top surface, and an edge surface between the top surface and the bottom surface, a first coating disposed atop the glass substrate, wherein the first coating is a doped crystalline silicon coating having a sheet-resistance of 100 to 1,000,000 ohm per square, and a second coating having one or more layers disposed atop the glass substrate, wherein the second coating comprises a silicon containing coating, wherein the glass wafer has an average transmittance (T) of less than 50% over an entire wavelength range of 400 nm to 1000 nm; rotating the substrate support to position the glass wafer in a predetermined position in the substrate aligner chamber, wherein the predetermined position is reached
- a glass wafer for a semiconductor device includes: a glass substrate comprising: a top surface (102), a bottom surface (104) opposing the top surface, and an edge surface (106) between the top surface and the bottom surface; and a silicon containing coating disposed on the glass substrate, wherein the silicon containing coating comprises at least two silicon containing layers, and wherein a difference in the refractive index values of adjacent layers is greater than 0.5.
- FIG. 1 A-1B depicts an exemplary glass substrate in accordance with some embodiments of the present disclosure.
- FIG. 2 depicts an exemplary glass substrate having a passivation coating in accordance with some embodiments of the present disclosure.
- FIG. 3 A-3B depict exemplary glass wafers in accordance with some embodiments of the present disclosure.
- FIG. 4 depicts an exemplary glass wafer in accordance with some embodiments of the present disclosure positioned within an exemplary semiconductor fabrication system in accordance with some embodiments of the present disclosure.
- Figure 5A and 5B shows transmittance vs. wavelength graphs for an exemplary glass wafer in accordance with some embodiments of the present disclosure.
- Figure 6A-6D shows reflectance vs. wavelength graphs for an exemplary glass wafer in accordance with some embodiments of the present disclosure.
- Figure 7A depicts a transmittance versus wavelength graph of the exemplary coating in Table 1 having a 10% thickness variability for each layer.
- Figure 7B depicts a transmittance versus wavelength graph of the exemplary coating in Table
- Figure 8A depicts a transmittance versus wavelength graph of the exemplary coating in Table
- Figure 8B depicts a transmittance versus wavelength graph of the exemplary coating in Table 2 having a 10% thickness variability and a 5% refractive index variability for each layer.
- Figure 9A depicts the transmission of a 300nm thick a-Ge layer on a fused silica substrate.
- Figure 9B depicts the transmission of a combined 300nm thick a-Ge layer with a 50 nm doped nanocrystalline-Si layer on a fused silica substrate.
- the term “and/or,” when used in a list of two or more items, means that any one of the listed items can be employed by itself, or any combination of two or more of the listed items can be employed.
- the composition can contain A alone; B alone; C alone; A and B in combination; A and C in combination; B and C in combination; or A, B, and C in combination.
- Semiconductor devices are made by a sequence of fabrication steps, such as thin film deposition, oxidation or nitration, etching, polishing, and thermal and lithographic processing. Although multiple fabrication steps may be performed in a single processing apparatus, wafers must be transported between different processing tools for at least some of the fabrication steps.
- a common orientation method involves using optical sensors having a light source, which is typically a visible light source, and a detector for generating and detecting a light beam.
- a silicon wafer having a notch along its edge is positioned on a rotating support surface. The surface of the silicon wafer is opaque and will block the passage of the light beam between the source and detector. However, when the silicon wafer is rotated such that the notch is in the location of the light beam, the detector senses the light beam and stops the rotation of the support surface. The stopped support surface, holding the silicon wafer is then in the proper position for transfer to, for example, a lithography device for processing of the wafer to form a circuit.
- the present disclosure describes glass wafers for semiconductor device fabrication that overcome the problems associated with sensors not functioning with glass wafers.
- the term “wafer” refers to a support surface suitable for having an electronic device formed thereon.
- glass has certain unique characteristics that make it ideal for the certain applications. For example, for radio frequency (RF) components, glass offers low RF loss and low nonlinearity in comparison to silicon in general. Products such as RF- switches and antenna tuners can benefit from glass in next generation networks and mobile phones.
- RF radio frequency
- Embodiments of the glass wafer described herein have various coatings formed thereon. For convenience, the term “coating” is intended to include films, coatings, or layers disposed on a surface.
- the coatings disposed on the glass wafer are formed by any known method in the art, including discrete deposition or continuous deposition processes.
- the coatings are deposited via plasma enhanced chemical vapor deposition (PECVD) as commonly used in the art.
- the coatings are deposited via physical vapor deposition (PVD) as commonly used in the art.
- PECVD plasma enhanced chemical vapor deposition
- PVD physical vapor deposition
- the term “dispose” includes coating, depositing and/or forming a material onto a surface using any known method in the art.
- the disposed material may constitute a coating as defined herein.
- the phrase “disposed on” includes the instance of forming a material onto a surface such that the material is in direct contact with the surface and also includes the instance where the material is formed on a surface, where one or more intervening material(s) is between the disposed material and the surface.
- the intervening material(s) may constitute a coating, as defined herein.
- Embodiments of the glass wafer described herein comprises a glass substrate 118 comprising a top surface 102, a bottom surface 104 opposing the top surface 102, and an edge surface 106 between the top surface 102 and the bottom surface 104, a first coating, and a second coating.
- Figure 1 A depicts a glass substrate 118 comprising: a top surface 102, a bottom surface 104 opposing the top surface 102, and an edge surface 106 between the top surface 102 and the bottom surface 104.
- the top surface 102 is the surface of the glass substrate 118 having various coatings, as described herein, disposed thereon.
- the glass substrate 118 may be any size suitable for use with existing semiconductor manufacturing equipment.
- the glass substrate 118 may have a diameter of 300 mm. In some embodiments, the glass substrate 118 may have a diameter of 200 mm. In some embodiments, the glass substrate 118 has a diameter of 300 mm and a thickness of 0.3mm to 1mm, preferably 0.5mm to 0.8 mm, more preferably 0.75mm to 0.8mm. In some embodiments, the glass substrate 118 has a diameter of 300 mm and a thickness of 0.775 mm. In some embodiments, the glass substrate 118 has a diameter of 200 mm and a thickness of 0.725 mm.
- the glass substrate 118 can be a high purity fused silica (HPFS) glass, or an alkali-free silicate glass, or a borosilicate glass, or an alkali aluminosilicate glass, or an alkali aluminoborosilicate glass, or an alkaline-earth boro-aluminosilicate glasses, or the like.
- High purity fused silica such as Corning Incorporated's HPFS® type high purity fused silica 7980 glass
- FEOL front end of line
- the coatings discussed below are silicon bearing materials such as amorphous silicon, poly-silicon, silicon nitride, silicon dioxide, or silicon oxynitride.
- the coatings discussed below may be an amorphous germanium (a-Ge). While interference-based coatings can deliver broadband low transmittance as discussed below, some optical sensors may require extremely low transmission that only reflective or absorptive filters can deliver.
- Germanium While many metals are good reflective materials, they are not FEOL-friendly, and thus not accepted in typical semiconductor fabrication. Germanium, on the other hand, is broadly accepted as a suitable material in the semiconductor fabrication process. Amorphous germanium is an exemplary material with absorption and transmission characteristics that can be used to deliver a coating with low transmittance in the visible spectral window while delivering less than 40% in the near infrared (NIR) window all the way to lOOOnm.
- Figure 9A shows the transmission of a 300nm thick a-Ge layer on a 775 pm fused silica substrate.
- Figure 9B shows the transmission of a combined 300nm thick a-Ge layer with a 50 nm doped nanocrystalline-Si layer on a 775 pm fused silica substrate.
- the latter combination would deliver both the optical and the electrical performance required by a typical semiconductor fab configured for handling Si wafers.
- the 300nm thickness a-Ge layer provides transmittance of less than 0.01% at 650nm, which is a typical sensor wavelength used with LED light sources.
- the glass substrate 118 is a fusion formed glass.
- the fusion draw process may result in a pristine, fire-polished glass surface that reduces surface-mediated distortion to high resolution TFT backplanes and color filters.
- the downdraw sheet drawing processes and, in particular, the fusion process described in U.S. Pat. Nos. 3,338,696 and 3,682,609 (both to Dockerty), which are incorporated by reference, can be used herein. Without being bound by any particular theory of operation, it is believed that the fusion process can produce glass substrates that do not require polishing.
- the glass substrates produced by the fusion process have an average surface roughness as measured by atomic force microscopy of less than 0.2 nm (Ra). Such low roughness facilitates critical applications where bonding to another flat surface is needed.
- the glass substrate 118 may have a passivation coating 112.
- the passivation coating 112 prevents non-silicon glass constituents from migrating out and contaminating the semiconductor fabrication equipment.
- the passivation coating 112 is disposed on the top surface 102, the bottom surface 104, and the edge surface 106 of the glass substrate 118.
- the passivation coating 112 is one of SiN, S1O2, or SiON.
- the thickness of the passivation coating 112 may be adjusted based on density and porosity of the passivation coating and based on the temperature and temperature exposure time of the coating within a semiconductor fabrication process.
- the passivation coating 112 has a thickness of 100 angstroms to 10,000 angstroms, preferably 500 angstroms to 1,000 angstroms.
- Figures 3 A and 3B depict a glass wafer 100 having a glass substrate 118 with an (optional) passivation layer 112 and a first coating 108 and a second coating 110.
- the first coating 108 is a doped crystalline silicon coating with silicon crystal size in the nanometer to micrometer range (nano-crystalline to micro-crystalline range).
- Exemplary dopants that may be used include phosphorus, boron, or arsenic.
- Typical electrostatic chucks in semiconductor fabrication equipment are designed to chuck silicon wafers and accordingly would not be able to chuck glass wafers, without significantly higher operating voltage. Accordingly, the first coating 108, disposed on one side of the glass substrate 118 provides sufficient conductivity for a typical electrostatic chuck (i.e. at an operating voltage suitable for chucking a silicon wafer) to chuck the glass substrate to the electrostatic chuck.
- the doped crystalline silicon coating has a sheet-resistance of 100 ohm per square to 1,000,000 ohm per square, preferably 100 ohm per square to 250,000 ohm per square, and more preferably 100 ohm per square to 50,000 ohm per square.
- sheet resistance denotes the isotropic resistivity of a layer relative to the thickness thereof. Sheet resistance can be measured using the four-point probe method.
- the four-point probe method is a commonly used testing method to measure the resistivity of any semiconductor material.
- the 4-point probe setup consists of four equally spaced tungsten metal tips with finite radius.
- Each tip is supported by springs on the other end to minimize sample damage during probing.
- the four metal tips are part of an auto-mechanical stage which travels up and down during measurements.
- a high impedance current source is used to supply current through the outer two probes; a voltmeter measures the voltage across the inner two probes to determine the sample resistivity.
- Typical probe spacing is about 1 mm.
- the doped crystalline silicon coating 108 has a thickness of at least 100 angstroms, and preferably at least 500 angstroms. In some embodiments, the doped crystalline silicon coating 108 is phosphorus-doped nano-crystalline silicon having a thickness of 500 angstroms and a sheet-resistance of 2000 ohms per square.
- the second coating 110 is a silicon-containing coating composed of one or more layers.
- the second coating 110 comprises a layer of undoped amorphous silicon.
- the second coating 110 comprises a layer of undoped amorphous germanium.
- the second coating 110 comprises a layer of silicon nitride, a layer of undoped amorphous silicon, and a layer of silicon dioxide, where the layer of silicon nitride is disposed atop the layer of undoped amorphous silicon, the layer of undoped amorphous silicon is disposed atop the layer of silicon dioxide, and the layer of silicon dioxide is atop the doped crystalline silicon coating.
- T transmittance
- the total thickness of the second coating 110 and the first coating 108 is less than 5 micron. In some embodiments, the total thickness of the second coating 110 and the first coating 108 is less than 4 micron. In some embodiments, the total thickness of the second coating 110 and the first coating 108 is less than 3 micron. In some embodiments, the total thickness of the second coating 110 and the first coating 108 is less than 2 micron. In some embodiments, the total thickness of the second coating 110 and the first coating 108 is less than 1 micron. In some embodiments, the total thickness of the second coating 110 and the first coating 108 is greater than 0.1 micron to less than 5 micron. In some embodiments, the total thickness of the second coating 110 and the first coating 108 is greater than 0.1 micron to less than 1 micron.
- the doped crystalline silicon coating 108 is disposed on the top surface 102 of the glass substrate 118. In some embodiments, the doped crystalline silicon is disposed on the entire top surface 102 of the glass substrate 118 as show in Figures 3A-3B. In some embodiments, the doped crystalline silicon coating 108 is disposed directly on the top surface 102 of the glass substrate 118 (i.e. no intervening coating between the glass substrate 118 and the doped crystalline silicon coating 108). In some embodiments, as shown in Figure 3 A, the doped crystalline silicon coating 108 is disposed directly on the passivation coating 112.
- the doped crystalline silicon coating 108 may be part of a multi-layer stack formed with the second coating (as described below), where the second coating comprises at least two layers and the first coating 108 is located between the at least two layers of the second coating 110a, lib.
- the second coating 110 is disposed directly on the doped crystalline silicon coating 108.
- the second coating 110 is disposed directly on the glass substrate 100 (i.e. no passivation layer and no first coating).
- the second coating 110 is disposed directly on a passivation layer 112 (i.e. no first coating).
- the second coating 110 covers the entire top surface of the directly underlying layer (e.g. the entire surface of the glass substrate 118). In some embodiments, the second coating 110 covers a portion of the directly underlying surface from the edge to a radial distance 2 mm toward a center of the directly underlying surface.
- Table 1 below depicts an example of a glass wafer in accordance with some embodiments of the current disclosure, where the glass substrate 118 is a high purity fused silica glass having a layer of phosphorus-doped nano-crystalline silicon disposed atop the high purity fused silica glass substrate, a layer of silicon dioxide (SiCh) disposed atop the phosphorus-doped nano-crystalline silicon, a layer of amorphous silicon disposed atop the silicon dioxide layer, a layer of silicon nitride disposed atop the amorphous silicon layer. Table 1 further shows the refractive index of each layer of the silicon containing coating disposed atop the glass substrate.
- SiCh silicon dioxide
- Table 1 further shows the refractive index of each layer of the silicon containing coating disposed atop the glass substrate.
- the coating show in Table 1 has four silicon containing layers, where the difference in refractive index values between adjacent layers is greater than 0.5. In some embodiments, the difference in refractive index values between adjacent layers is greater than 1. In some embodiments, the difference in refractive index values between adjacent layers is greater than 2.
- the outermost layer i.e. the layer the furthest away from the substrate
- the outermost layer is silicon nitride. In some embodiments, the outermost layer may be silicon dioxide or silicon oxynitride. In some embodiments, an outermost layer of silicon nitride or silicon oxynitride provides mechanical abrasion resistance for the glass wafer. Table 1
- Figure 7A depicts a transmittance versus wavelength graph in which the thickness of each layer of the coating in Table 1 is randomly adjusted (e.g. increased or decreased) by a random number corresponding to a Gaussian distribution whose mean value is the layer design thickness and whose variance is 10% of the layer design thickness.
- the transmittance of the randomly adjusted coating is calculated over a wavelength range of 400 nm to 1000 nm. This process is performed 100 times and generates the curves shown in Figure 7A.
- the transmittance for the coating in Table 1 is less than 40% over a wavelength range of 400 nm to lOOOnm for a 10% random thickness variability.
- Figure 7B depicts a transmittance versus wavelength graph in which the thickness of each layer of the coating in Table 1 is randomly adjusted (e.g. increased or decreased) by a random number corresponding to a Gaussian distribution whose mean value is the layer design thickness and whose variance is 10% of the layer design thickness and where the refractive index of each layer is randomly adjusted (e.g. increased or decreased) by a random number corresponding to a Gaussian distribution whose mean value is the layer refractive index and whose variance is 5% of the layer refractive index.
- the transmittance of the randomly adjusted coating is calculated over a wavelength range of 400 nm to 1000 nm. This process is performed 100 times and generates the curves shown in Figure 7B.
- the transmittance for the coating in Table 1 is less than 50% over a wavelength range of 400 nm to lOOOnm for a 10% random thickness variability and a 5% random refractive index variability.
- Table 2 below depicts an example of a glass wafer in accordance with some embodiments of the current disclosure, where the glass substrate 118 is a high purity fused silica glass having a layer of nano-crystalline silicon disposed atop the high purity fused silica glass substrate, a layer of silicon dioxide (SiCh) disposed atop the nano-crystalline silicon, a layer of amorphous silicon disposed atop the silicon dioxide layer, and a layer of silicon dioxide disposed atop the amorphous silicon layer.
- Table 1 further shows the refractive index of each layer of the silicon containing coating disposed atop the glass substrate.
- Figure 8A depicts a transmittance versus wavelength graph in which the thickness of each layer of the coating in Table 2 is randomly adjusted (e.g. increased or decreased) by a random number corresponding to a Gaussian distribution whose mean value is the layer design thickness and whose variance is 10% of the layer design thickness.
- the transmittance of the randomly adjusted coating is calculated over a wavelength range of 400 nm to 1000 nm. This process is performed 100 times and generates the curves shown in Figure 8 A.
- the transmittance for the coating in Table 2 is less than 40% over a wavelength range of 400 nm to lOOOnm for a 10% random thickness variability.
- Figure 8B depicts a transmittance versus wavelength graph in which the thickness of each layer of the coating in Table 2 is randomly adjusted (e.g. increased or decreased) by a random number corresponding to a Gaussian distribution whose mean value is the layer design thickness and whose variance is 10% of the layer design thickness and where the refractive index of each layer is randomly adjusted (e.g. increased or decreased) by a random number corresponding to a Gaussian distribution whose mean value is the layer refractive index and whose variance is 5% of the layer refractive index.
- the transmittance of the randomly adjusted coating is calculated over a wavelength range of 400 nm to 1000 nm. This process is performed 100 times and generates the curves shown in Figure 8B.
- the transmittance for the coating in Table 2 is less than 60% over a wavelength range of 400 nm to lOOOnm for a 10% random thickness variability and a 5% random refractive index variability.
- the glass wafer 100 has an average transmittance (T) value of less than 50%, preferably less than 40%, more preferably less than 30%, over an entire wavelength range of 400 nm to 1000 nm.
- T average transmittance
- “average transmittance value” refers to the sum of the transmittance values at every wavelength in the defined wavelength range divided by the number of wavelengths over the defined wavelength range.
- the glass wafer 100 has an average transmittance (T) value of less than 50%, preferably less than 40%, more preferably less than 30%, over an entire wavelength range of 400 nm to 2500 nm.
- the transmittance value of the glass wafer 100 at every wavelength in the defined wavelength range e.g.
- 400 nm to lOOOnm or 400 nm to 2500 nm is less than 50%, preferably less than 40%, and more preferably less than 30%.
- transmittance is defined as the percentage of incident optical power within a given wavelength range transmitted through the glass wafer 100. In general, transmittance is measured using a specific linewidth.
- Figure 4 depicts an exemplary wafer in accordance with some embodiments of the present disclosure positioned within an exemplary semiconductor fabrication system in accordance with some embodiments of the present disclosure.
- the glass wafer can have a notch along a portion of the edge that is used for orientation within the substrate aligner chamber 408.
- Figure IB depicts a glass wafer 100 having a notch 114 along its edge.
- a method of fabricating an electronic device comprises loading a glass wafer 400, as described in the embodiments above, onto a substrate support (not shown) within a substrate aligner chamber 408.
- the substrate aligner chamber 408 comprises a light source 404 and an optical sensor 406 configured to detect a light beam from the light source 404.
- the glass wafer 404 comprises a top surface, a bottom surface opposing the top side, an edge surface between the top surface and the bottom surface, a first coating as described in the embodiments above and a second coating as described in the embodiments above.
- the glass wafer 404 may also comprise a passivation layer.
- the substrate support rotates the glass wafer 400 to a predetermined position in the substrate aligner chamber.
- the predetermined position is reached when the optical sensor detects the light beam from the light source.
- the optical sensor 406 cannot read the light from the light source 404 due to the second coating 110 disposed on the glass wafer 400.
- the notch 402 reaches the light beam, it is read by the optical sensor 406 and the glass wafer 400 is accordingly in the proper position for transfer to a fabrication tool 410 for further processing.
- the glass wafer may undergo semiconductor fabrication processing in which the glass wafer is heated during the process then allowed to cool to room temperature.
- Embodiments of the glass wafers described herein maintain an average transmittance, and a transmittance at every wavelength in the wavelength range, of less than 50%, preferably less than 30%, following a heat treatment of 350 degrees Celsius for 2 hours and cooling to room temperature (e.g. 25 degrees Celsius) at a cooling rate of 10 degrees Celsius per minute.
- Figure 5A and 5B shows a transmittance vs. wavelength graph for an exemplary glass wafer having a doped nano-crystalline silicon coating disposed directly on the top surface 102 of the glass wafer 100, a layer of silicon nitride, a layer of undoped amorphous silicon, and a layer of silicon dioxide.
- the layer of silicon nitride is disposed atop the layer of undoped amorphous silicon.
- the layer of undoped amorphous silicon is disposed atop the layer of silicon dioxide.
- the layer of silicon dioxide is atop the doped nano-crystalline silicon coating.
- Graph 500 depicted in Figure 5A shows a transmittance curve 504 for the exemplary glass wafer after undergoing a heat treatment of 350 degrees Celsius for 2 hours and cooling to room temperature (e.g. 25 degrees Celsius) at a cooling rate of 10 degrees Celsius per minute (the “heat treatment”) and a transmittance curve 502 for the glass wafer before it undergoes the heat treatment.
- transmittance data is collected from two points along the edge of the glass wafer at the uncoated side.
- Graph 506 depicted in Figure 5B shows a transmittance curve 508 for the exemplary glass wafer after undergoing a heat treatment of 350 degrees Celsius for 2 hours and cooling to room temperature (e.g.
- transmittance data is collected from two points along the edge of the glass wafer at the coated side. Based on graphs 5 A and 5B, the exemplary glass wafer maintains an average transmittance, and a transmittance at every wavelength in the wavelength range, of less than 50% from a wavelength of 400 nm to 1100 nm even after the heating process described above.
- Figure 6A-6D shows reflectance vs. wavelength graphs for an exemplary glass carrier wafer described above with respect to Figures 5A-5B.
- Figure 6A is a reflectance vs. wavelength graph 600 showing a reflectance curve 602 for the glass wafer after undergoing a heat treatment of 350 degrees Celsius for 2 hours and cooling to room temperature (e.g. 25 degrees Celsius) at a cooling rate of 10 degrees Celsius per minute and a reflectance curve 604 for the glass wafer before it undergoes the heat treatment, where reflectance is measured from the uncoated side of the glass wafer at an angle of incidence of 5 degrees.
- Figure 6B is a reflectance vs. wavelength graph 606 showing a reflectance curve 608 for the glass wafer after undergoing a heat treatment of 350 degrees Celsius for 2 hours and cooling to room temperature (e.g. 25 degrees Celsius) at a cooling rate of 10 degrees Celsius per minute and a reflectance curve 610 for the glass wafer before it undergoes the heat treatment, where reflectance is measured from the uncoated side of the glass wafer at an angle of incidence of 45 degrees.
- room temperature e.g. 25 degrees Celsius
- Figure 6C is a reflectance vs. wavelength graph 612 showing a reflectance curve 614 for the glass wafer after undergoing a heat treatment of 350 degrees Celsius for 2 hours and cooling to room temperature (e.g. 25 degrees Celsius) at a cooling rate of 10 degrees Celsius per minute and a reflectance curve 616 for the glass wafer before it undergoes the heat treatment, where reflectance is measured from the coated side of the glass wafer at an angle of incidence of 5 degrees.
- the reflectance values of the glass wafer after it undergoes the heat treatment over a wavelength range of 400nm to 1 lOOnm is substantially similar to the reflectance values prior to the heat treatment.
- Figure 6D is a reflectance vs. wavelength graph 618 showing a reflectance curve 620 for the glass wafer after undergoing a heat treatment of 350 degrees Celsius for 2 hours and cooling to room temperature (e.g. 25 degrees Celsius) at a cooling rate of 10 degrees Celsius per minute and a reflectance curve 622 for the glass wafer before it undergoes the heat treatment, where reflectance is measured from the coated side of the glass wafer at an angle of incidence of 45 degrees.
- room temperature e.g. 25 degrees Celsius
- wafers used in semiconductor processing equipment have a minimum reflectance value to enable the equipment to sense the presence of the wafer.
- Figure 6D shows reflectance values for silicon, a commonly used wafer material, over a wavelength range of 400 nm to 1100 nm.
- the glass wafer with the exemplary coating described has an average reflectance value that meets or exceed that of silicon over a wavelength range of about 510 nm to 1100 nm.
- the reflectance value at every wavelength over a wavelength range of about 510 nm to 1 lOOnm meets or exceed that of silicon.
- “average reflectance value” refers to the sum of the reflectance values at every wavelength in the defined wavelength range (e.g. 510 nm to 1100 nm) divided by the number of wavelengths over the defined wavelength range.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Ceramic Engineering (AREA)
- Life Sciences & Earth Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Geochemistry & Mineralogy (AREA)
- Organic Chemistry (AREA)
- Surface Treatment Of Glass (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020227020968A KR20220106156A (en) | 2019-11-27 | 2020-11-24 | Glass wafers for semiconductor device manufacturing |
JP2022529539A JP2023503576A (en) | 2019-11-27 | 2020-11-24 | Glass wafer for semiconductor device manufacturing |
EP20891614.8A EP4066276A4 (en) | 2019-11-27 | 2020-11-24 | Glass wafers for semiconductor device fabrication |
CN202080082433.XA CN114746981A (en) | 2019-11-27 | 2020-11-24 | Glass wafer for semiconductor device fabrication |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US201962940996P | 2019-11-27 | 2019-11-27 | |
US62/940,996 | 2019-11-27 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2021108393A1 true WO2021108393A1 (en) | 2021-06-03 |
Family
ID=75974244
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US2020/061990 WO2021108393A1 (en) | 2019-11-27 | 2020-11-24 | Glass wafers for semiconductor device fabrication |
Country Status (7)
Country | Link |
---|---|
US (1) | US11948792B2 (en) |
EP (1) | EP4066276A4 (en) |
JP (1) | JP2023503576A (en) |
KR (1) | KR20220106156A (en) |
CN (1) | CN114746981A (en) |
TW (1) | TW202135134A (en) |
WO (1) | WO2021108393A1 (en) |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005032858A (en) * | 2003-07-09 | 2005-02-03 | Toto Ltd | Electrostatic chucking method of glass substrate and electrostatic chuck |
US20120172209A1 (en) * | 2008-11-19 | 2012-07-05 | Ppg Industries Ohio, Inc. | Undercoating layers providing improved photoactive topcoat functionality |
US20120276689A1 (en) * | 2010-11-05 | 2012-11-01 | Joseph Eugene Canale | Glass Wafers for Semiconductor Fabrication Processes and Methods of Making Same |
US20130105806A1 (en) * | 2011-11-01 | 2013-05-02 | Guojun Liu | Structures incorporating silicon nanoparticle inks, densified silicon materials from nanoparticle silicon deposits and corresponding methods |
US20180275318A1 (en) * | 2017-03-21 | 2018-09-27 | Corning Incorporated | Hardcoated glass-ceramic articles |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3338696A (en) | 1964-05-06 | 1967-08-29 | Corning Glass Works | Sheet forming apparatus |
BE757057A (en) | 1969-10-06 | 1971-04-05 | Corning Glass Works | METHOD AND APPARATUS FOR CHECKING THE THICKNESS OF A NEWLY STRETCHED SHEET OF GLASS |
JP4086925B2 (en) * | 1996-12-27 | 2008-05-14 | 株式会社半導体エネルギー研究所 | Active matrix display |
US6291837B1 (en) * | 1997-03-18 | 2001-09-18 | Semiconductor Energy Laboratory Co., Ltd. | Substrate of semiconductor device and fabrication method thereof as well as semiconductor device and fabrication method thereof |
JPH10268280A (en) * | 1997-03-24 | 1998-10-09 | Semiconductor Energy Lab Co Ltd | Substrate for semiconductor device and production thereof |
US6229611B1 (en) | 1999-09-20 | 2001-05-08 | United Microelectronics Corp. | Method of detecting a transparent quartz wafer in a semiconductor equipment |
TWI274396B (en) | 2006-01-11 | 2007-02-21 | Ind Tech Res Inst | Transparent wafer with optical alignment function and fabricating method and alignment method thereof |
JP5156641B2 (en) * | 2006-11-20 | 2013-03-06 | 株式会社カネカ | Substrate with transparent conductive film for photoelectric conversion device and method for manufacturing photoelectric conversion device |
CN102265380A (en) * | 2009-03-09 | 2011-11-30 | 夏普株式会社 | Semiconductor device and method for manufacturing same |
US20110165721A1 (en) * | 2009-11-25 | 2011-07-07 | Venkatraman Prabhakar | Systems, methods and products including features of laser irradiation and/or cleaving of silicon with other substrates or layers |
US8405169B2 (en) | 2010-10-15 | 2013-03-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Handling layer for transparent substrate |
CN102543675B (en) * | 2010-12-31 | 2014-11-05 | 中芯国际集成电路制造(上海)有限公司 | Method for processing glass substrate |
US9058973B2 (en) | 2011-04-13 | 2015-06-16 | International Business Machines Corporation | Passive devices fabricated on glass substrates, methods of manufacture and design structures |
WO2016025773A1 (en) * | 2014-08-13 | 2016-02-18 | Solexel, Inc. | Rear wide band gap passivated perc solar cells |
US10146123B2 (en) * | 2014-12-26 | 2018-12-04 | Hoya Corporation | Mask blank, phase shift mask, method for manufacturing phase shift mask, and method for manufacturing semiconductor device |
US10224297B2 (en) * | 2016-07-26 | 2019-03-05 | Palo Alto Research Center Incorporated | Sensor and heater for stimulus-initiated fracture of a substrate |
JP6863169B2 (en) * | 2017-08-15 | 2021-04-21 | Agc株式会社 | Reflective mask blank, and reflective mask |
-
2020
- 2020-11-24 KR KR1020227020968A patent/KR20220106156A/en unknown
- 2020-11-24 WO PCT/US2020/061990 patent/WO2021108393A1/en unknown
- 2020-11-24 EP EP20891614.8A patent/EP4066276A4/en active Pending
- 2020-11-24 CN CN202080082433.XA patent/CN114746981A/en active Pending
- 2020-11-24 JP JP2022529539A patent/JP2023503576A/en active Pending
- 2020-11-25 US US17/104,723 patent/US11948792B2/en active Active
- 2020-11-26 TW TW109141539A patent/TW202135134A/en unknown
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2005032858A (en) * | 2003-07-09 | 2005-02-03 | Toto Ltd | Electrostatic chucking method of glass substrate and electrostatic chuck |
US20120172209A1 (en) * | 2008-11-19 | 2012-07-05 | Ppg Industries Ohio, Inc. | Undercoating layers providing improved photoactive topcoat functionality |
US20120276689A1 (en) * | 2010-11-05 | 2012-11-01 | Joseph Eugene Canale | Glass Wafers for Semiconductor Fabrication Processes and Methods of Making Same |
US20130105806A1 (en) * | 2011-11-01 | 2013-05-02 | Guojun Liu | Structures incorporating silicon nanoparticle inks, densified silicon materials from nanoparticle silicon deposits and corresponding methods |
US20180275318A1 (en) * | 2017-03-21 | 2018-09-27 | Corning Incorporated | Hardcoated glass-ceramic articles |
Non-Patent Citations (1)
Title |
---|
See also references of EP4066276A4 * |
Also Published As
Publication number | Publication date |
---|---|
KR20220106156A (en) | 2022-07-28 |
JP2023503576A (en) | 2023-01-31 |
EP4066276A1 (en) | 2022-10-05 |
EP4066276A4 (en) | 2024-03-27 |
US20210159076A1 (en) | 2021-05-27 |
US11948792B2 (en) | 2024-04-02 |
CN114746981A (en) | 2022-07-12 |
TW202135134A (en) | 2021-09-16 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US9159587B2 (en) | Glass wafers for semiconductors fabrication processes and methods of making same | |
US10886155B2 (en) | Optical stack deposition and on-board metrology | |
TW201816179A (en) | Methods for thermally calibrating reaction chambers | |
TWI823862B (en) | Reflective mask base and reflective mask | |
WO1999041773A1 (en) | Substrate support for a thermal processing chamber | |
WO2007111067A1 (en) | Method for smoothing a surface of a glass substrate, and substrate for a reflective mask blank used in euv lithography, obtainable by that method | |
US11948792B2 (en) | Glass wafers for semiconductor device fabrication | |
KR20200130058A (en) | Robot hand, wafer transfer robot and wafer transfer apparatus | |
TW201441590A (en) | Pyrometry filter for thermal process chamber | |
Bailey et al. | High rate amorphous and crystalline silicon formation by pulsed DC magnetron sputtering deposition for photovoltaics | |
JP3990575B2 (en) | Monitor wafer for film thickness measurement | |
US20060102975A1 (en) | Semiconductor device structure and fabrication process | |
TWI794530B (en) | Substrate positioning apparatus and methods | |
Zhang et al. | Enabling glass wafers in a Si fab | |
Zhang et al. | Enabling the Use of High-Precision Glass Wafers in a Conventional Si Fab | |
Tamura et al. | Enabling 18nm-particle detection on Si surfaces by conventional laser scattering | |
JP7424785B2 (en) | Temperature sensor film, conductive film and manufacturing method thereof | |
TWI743077B (en) | Mounting components | |
US11262250B2 (en) | Method for measuring a temperature | |
US10775693B2 (en) | Transparent and electrically conductive coatings containing nitrides, borides or carbides | |
JP2000031246A (en) | Substrate processing device | |
JP2006012917A (en) | Evaluation method of condition on surface of wafer, management method of wafer manufacturing process, wafer manufacturing method, and wafer | |
JP2009259891A (en) | Device having electrostatic attraction function |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 20891614 Country of ref document: EP Kind code of ref document: A1 |
|
ENP | Entry into the national phase |
Ref document number: 2022529539 Country of ref document: JP Kind code of ref document: A |
|
ENP | Entry into the national phase |
Ref document number: 20227020968 Country of ref document: KR Kind code of ref document: A |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
ENP | Entry into the national phase |
Ref document number: 2020891614 Country of ref document: EP Effective date: 20220627 |