WO2020147167A1 - 功率半导体模块及电机控制器 - Google Patents

功率半导体模块及电机控制器 Download PDF

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WO2020147167A1
WO2020147167A1 PCT/CN2019/076137 CN2019076137W WO2020147167A1 WO 2020147167 A1 WO2020147167 A1 WO 2020147167A1 CN 2019076137 W CN2019076137 W CN 2019076137W WO 2020147167 A1 WO2020147167 A1 WO 2020147167A1
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Prior art keywords
electrode layer
transistor
electrically connected
semiconductor module
power semiconductor
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PCT/CN2019/076137
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English (en)
French (fr)
Inventor
新居良英
高崎哲
刘莉飞
王庆凯
苟文辉
刘乐
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上海大郡动力控制技术有限公司
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Publication of WO2020147167A1 publication Critical patent/WO2020147167A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/492—Bases or plates or solder therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched

Definitions

  • the embodiments of the present application relate to the field of automotive electronics, for example, to a power semiconductor module and a motor controller.
  • Batteries, motor controllers and motors constitute the "three-electric" system of new energy vehicles, and the motor controller plays a key role in energy conversion, motor torque control and speed control.
  • the power semiconductor module is the core part of the motor controller, which determines the key performance such as the power density of the motor controller.
  • the power semiconductor module in the related art includes two electrodes for providing positive and negative voltages, respectively, the electrode for providing the positive voltage is electrically connected to the positive electrode of the power supply, and the electrode for providing the negative voltage is connected to the negative electrode of the power supply.
  • the electrodes are arranged on the same layer. In this structure, the current loop area is large and the parasitic inductance is large, which affects the performance of the transistors in the power semiconductor module, and further affects the overall performance of the motor controller.
  • This application provides a power semiconductor module and a motor controller to reduce parasitic inductance in the power semiconductor module.
  • the embodiment of the present application provides a power semiconductor module, including:
  • the first insulating layer is located on the substrate
  • the electrode layer is located on the first insulating layer and includes a first electrode layer, a second electrode layer, a third electrode layer, a second insulating layer, and a third insulating layer.
  • the second insulating layer is located on the first electrode
  • the third insulating layer is located between the second electrode layer and the third electrode layer;
  • the first electrode layer is electrically connected to the positive electrode of the power supply through a wire
  • the second electrode layer is electrically connected to the negative electrode of the power supply through a wire
  • the third electrode layer is electrically connected to the output terminal through a wire;
  • the first transistor component includes a first transistor, the collector of the first transistor is electrically connected to the first electrode layer, and the emitter of the first transistor is electrically connected to the third electrode layer through a wire, so The base of the first transistor is electrically connected to the corresponding gate drive circuit through a wire;
  • the second transistor assembly includes a second transistor, the collector of the second transistor is electrically connected to the third electrode layer, and the emitter of the second transistor is electrically connected to the second electrode layer through a wire.
  • the bases of the two transistors are electrically connected to the corresponding gate drive circuit through wires.
  • An embodiment of the present application also provides a motor controller, including the power semiconductor module described in the first aspect.
  • FIG. 1 is a schematic structural diagram of a power semiconductor module provided by an embodiment of the present application.
  • FIG. 2 is a schematic structural diagram of another semiconductor power module provided by an embodiment of the present application.
  • Fig. 3 is a schematic structural diagram of an electrode controller provided by an embodiment of the present application.
  • FIG. 1 is a schematic structural diagram of a power semiconductor module provided by an embodiment of the present application.
  • the power semiconductor module includes a substrate 100, a first insulating layer 500 on the substrate 100, and an electrode layer on the first insulating layer 500, including a first electrode layer 200, a second electrode layer 300, and a third electrode layer.
  • the first electrode layer 200 is electrically connected to the positive electrode (not shown) of the power supply through a wire
  • the second electrode layer 300 is electrically connected to the negative electrode (not shown) of the power source through a wire
  • the third electrode layer 400 is electrically connected to an output terminal (not shown) through a wire.
  • the first transistor assembly 800 includes a first transistor, the collector of the first transistor is electrically connected to the first electrode layer 200, the emitter of the first transistor is electrically connected to the third electrode layer 400 through a wire, and the base of the first transistor It is electrically connected to the corresponding gate drive circuit through a wire.
  • the second transistor assembly 900 includes a second transistor, the collector of the second transistor is electrically connected to the third electrode layer 400, the emitter of the second transistor is electrically connected to the second electrode layer 300 through a wire, and the base of the second transistor It is electrically connected to the corresponding gate drive circuit through a wire.
  • FIG. 1 does not specifically show the first transistor and the second transistor, and only shows the connecting wires between the first transistor and the second transistor and other structures inside the power semiconductor module.
  • FIG. 1 only exemplarily shows a structure of the power semiconductor module, but does not limit the structure of the power semiconductor module.
  • the first electrode layer 200 can be located on the side of the second electrode layer 300 facing the substrate 100, or on the side of the second electrode layer 300 facing away from the substrate 100. There is no specific limitation.
  • transistor components may also include other functional elements, such as diodes, which can be selected according to actual conditions.
  • the substrate 100 is a plate-shaped structure that can play a supporting role.
  • the material and structure of the substrate 100 are not specifically limited in this embodiment.
  • the power semiconductor module includes a substrate 100, a first insulating layer 500 located on the substrate 100, and an electrode layer located on the first insulating layer 500, including a first electrode layer 200, a second electrode layer 300, and a third electrode Layer 400, second insulating layer 600 and third insulating layer 700, the second insulating layer 600 is located between the first electrode layer 200 and the second electrode layer 300, and the third insulating layer 700 is located between the second electrode layer 300 and the third electrode
  • the first electrode layer 200 is electrically connected to the positive electrode (not shown) of the power supply through a wire
  • the second electrode layer 300 is electrically connected to the negative electrode (not shown) of the power source through a wire
  • the first transistor assembly 800 includes a first transistor, the collector of the first transistor is electrically connected to the first electrode layer 200, and the emitter of the first transistor is electrically connected to the output terminal (not shown) through a wire.
  • the three electrode layer 400 is electrically connected.
  • the base of the first transistor is electrically connected to the corresponding gate drive circuit through a wire.
  • the second transistor assembly 900 includes a second transistor.
  • the collector of the second transistor is electrically connected to the third electrode layer 400.
  • the emitter of the second transistor is electrically connected to the second electrode layer 300 through a wire
  • the base of the second transistor is electrically connected to the corresponding gate drive circuit through a wire.
  • the first electrode layer 200 and the second electrode layer 300 respectively used to provide positive and negative voltages are stacked, which reduces the current loop area, thereby reducing the parasitic inductance, so that the transistors in the power semiconductor module The good performance is helpful to the overall performance of the motor controller.
  • the first electrode layer 200 may be located on the side of the second electrode layer 300 facing away from the substrate 100, the first electrode layer 200 and the third electrode layer 400 may be provided in the same layer, and the second insulating layer
  • the layer 600 may be multiplexed as the third insulating layer 700.
  • the arrangement of the first electrode layer 200 and the third electrode layer 400 in the same layer enables the second insulating layer 600 to be multiplexed as the third insulating layer 700, thereby eliminating the need to separately prepare the second insulating layer 600 and the third insulating layer.
  • the layer 700 only needs to form an insulating layer, which reduces the process steps for preparing the power semiconductor module, reduces the difficulty of preparing the power semiconductor module, and facilitates the thinning of the semiconductor power module.
  • first electrode layer 200 and the third electrode layer 400 are arranged in the same layer, they can be formed in the same process step, which further reduces the process steps for preparing the power semiconductor module, reduces the difficulty of preparing the power semiconductor module, and facilitates the thinning of the semiconductor power module. ⁇ .
  • FIG. 2 is a schematic structural diagram of another semiconductor power module provided by an embodiment of the present application.
  • the power semiconductor module includes a substrate 100, a first insulating layer 500 located on the substrate 100, and an electrode layer located on the first insulating layer 500, including a first electrode layer 200, a second electrode layer 300, and a third electrode layer.
  • the electrode layer 400, the second insulating layer 600 and the third insulating layer 700, the second insulating layer 600 is located between the first electrode layer 200 and the second electrode layer 300
  • the third insulating layer 700 is located between the second electrode layer 300 and the third electrode layer.
  • the first transistor assembly 800 includes a first transistor, the collector of the first transistor is electrically connected to the first electrode layer 200, the emitter of the first transistor is electrically connected to the third electrode layer 400 through a wire, and the base of the first transistor It is electrically connected to the corresponding gate drive circuit through a wire.
  • the second transistor assembly 900 includes a second transistor, the collector of the second transistor is electrically connected to the third electrode layer 400, the emitter of the second transistor is electrically connected to the second electrode layer 300 through a wire, and the base of the second transistor It is electrically connected to the corresponding gate drive circuit through a wire.
  • the first electrode layer 200 is located on the side of the second electrode layer 300 facing the substrate 100, and the second electrode layer 300 is located on the side of the third electrode layer 400 facing the substrate 100.
  • this arrangement allows the first electrode layer 200, the second electrode layer 300 and the third electrode layer 400 to be arranged in different layers, and the electrode layers are relatively independent and will not affect each other.
  • the flow path of the current is shown by the broken line in FIG. 2.
  • the current I 1 flows from the positive pole (not shown) of the power supply to the collector of the first transistor 800 through the first wire and the first electrode layer 200, wherein the first wire is connected to the positive pole (not shown) of the power supply and the first transistor 800.
  • the current I 2 flows from the emitter of the first transistor 800 to the third electrode layer 400 through the second wire, then flows to the collector of the second transistor 900 through the third electrode layer 400, and flows to the second transistor through the emitter of the second transistor 900.
  • the electrode layer 300 finally flows to the negative electrode (not shown) of the power supply. It is worth noting that the directions of current I 1 and current I 2 are opposite.
  • the substrate 100 may be a heat dissipation substrate 100.
  • the first transistor and the second transistor may be insulated gate bipolar transistors (IGBT) or metal oxide semiconductor field effect transistors (Metal Oxide Semiconductor-Field Effect Transistor, MOS-FET). ).
  • IGBT insulated gate bipolar transistors
  • MOS-FET Metal Oxide Semiconductor-Field Effect Transistor
  • the first transistor and the second transistor may be silicon carbide-metal oxide semiconductor field effect transistors (Silicon Carbide-Metal Oxide Semiconductor-Field Effect Transistor, SiC-MOS-FET).
  • SiC has the advantages of high withstand voltage, high temperature resistance, high switching speed and low power consumption. Therefore, in order to obtain better device performance, it is better to set the first transistor and the second transistor as SiC-MOS- FET.
  • the first transistor assembly 800 may further include a first freewheeling diode, the anode of the first freewheeling diode is electrically connected to the collector of the first transistor, and the cathode of the first freewheeling diode is connected to the emitter of the first transistor. Extremely electrical connection.
  • the second transistor assembly 900 may further include a second freewheeling diode, the anode of the second freewheeling diode is electrically connected to the collector of the second transistor, and the cathode of the second freewheeling diode is electrically connected to the emitter of the second transistor.
  • the freewheeling diode can short-circuit the corresponding transistor during the power-off process, thereby avoiding the instantaneous high voltage damage to the corresponding transistor during shutdown.
  • the material of the first electrode layer 200, the second electrode layer 300, and the third electrode layer 400 may be copper.
  • the first electrode layer 200, the second electrode layer 300, and the third electrode layer 400 can also be formed of other conductive materials, as long as they have good conductive properties. Used in this embodiment.
  • the first electrode layer 200, the second electrode layer 300, and the third electrode layer 400 may be copper plates or copper films.
  • the hardness of the copper plate is better and will not be easily damaged.
  • the thickness of the copper film is easy to control, and the thickness of the electrode can be controlled more accurately. Based on the above reasons, the corresponding copper material structure can be selected to form the electrode according to actual needs. Floor.
  • Fig. 3 is a schematic structural diagram of an electrode controller provided by an embodiment of the present application. As shown in FIG. 3, the motor controller 10 includes the power semiconductor module 11 described in any embodiment of the present application.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Inverter Devices (AREA)

Abstract

公开了一种功率半导体模块及电机控制器。所述功率半导体模块包括：基板、第一绝缘层、电极层、第一晶体管组件以及第二晶体管组件，其中电极层包括第一电极层、第二电极层、第三电极层、第二绝缘层和第三绝缘层，所述第二绝缘层位于所述第一电极层和所述第二电极层之间，所述第三绝缘层位于所述第二电极层和所述第三电极层之间；所述第一电极层通过导线与供电电源的正极电连接，所述第二电极层通过导线与所述供电电源的负极电连接，所述第三电极层通过导线与输出端电连接。

Description

功率半导体模块及电机控制器
本申请要求在2019年01月18日提交中国专利局、申请号为201910048619.2的中国专利申请的优先权，该申请的全部内容通过引用结合在本申请中。
技术领域
本申请实施例涉及汽车电子领域，例如涉及一种功率半导体模块及电机控制器。
背景技术
电池、电机控制器和电机构成新能源汽车“三电”***，电机控制器承担着能量转换、电机转矩控制和转速控制的关键角色。功率半导体模块是电机控制器的核心部分，决定了电机控制器的功率密度等关键性能。
相关技术中功率半导体模块包括分别用于提供正负电压的两个电极，用于提供正电压的电极与供电电源的正极电连接，用于提供负电压的电极与供电电源的负极连接，上述两个电极同层设置。该结构中，电流回路面积较大，寄生电感较大，影响功率半导体模块中的晶体管性能发挥，进而影响电机控制器的整体性能发挥。
发明内容
本申请提供一种功率半导体模块及电机控制器，以减小功率半导体模块中的寄生电感。
本申请实施例提供了一种功率半导体模块，包括：
基板；
第一绝缘层，位于所述基板上；
电极层，位于所述第一绝缘层上，包括第一电极层、第二电极层、第三电极层、第二绝缘层和第三绝缘层，所述第二绝缘层位于所述第一电极层和所述第二电极层之间，所述第三绝缘层位于所述第二电极层和所述第三电极层之间；所述第一电极层通过导线与供电电源的正极电连接，所述第二电极层通过导线与所述供电电源的负极电连接，所述第三电极层通过导线与输出端电连接；
第一晶体管组件，包括第一晶体管，所述第一晶体管的集电极与所述第一 电极层接触电连接，所述第一晶体管的发射极通过导线与所述第三电极层电连接，所述第一晶体管的基极通过导线与对应的栅极驱动电路电连接；
第二晶体管组件，包括第二晶体管，所述第二晶体管的集电极与第三电极层接触电连接，所述第二晶体管的发射极通过导线与所述第二电极层电连接，所述第二晶体管的基极通过导线与对应的栅极驱动电路电连接。
本申请实施例还提供了一种电机控制器，包括上述第一方面所述的功率半导体模块。
附图概述
下面对描述实施例中所需要用到的附图做一简单介绍。显然，所介绍的附图只是本申请所要描述的一部分实施例的附图，而不是全部的附图，对于本领域普通技术人员，在不付出创造性劳动的前提下，还可以根据这些附图得到其他的附图。
图1是本申请实施例提供的一种功率半导体模块的结构示意图；
图2是本申请实施例提供的又一种半导体功率模块的结构示意图；
图3是本申请实施例提供的一种电极控制器的结构示意图。
具体实施方式
下面结合附图和实施例对本申请作进一步的详细说明。可以理解的是，此处所描述的具体实施例仅仅用于解释本申请，而非对本申请的限定。另外还需要说明的是，为了便于描述，附图中仅示出了与本申请相关的部分而非全部内容。在更加详细地讨论示例性实施例之前应当提到的是，一些示例性实施例被描述成作为流程图描绘的处理或方法。虽然流程图将各项操作(或步骤)描述成顺序的处理，但是其中的许多操作可以被并行地、并发地或者同时实施。此外，各项操作的顺序可以被重新安排。当其操作完成时所述处理可以被终止，但是还可以具有未包括在附图中的附加步骤。所述处理可以对应于方法、函数、规程、子例程、以及子程序等。
图1是本申请实施例提供的一种功率半导体模块的结构示意图。如图1所示，功率半导体模块包括基板100，第一绝缘层500，位于基板100上，电极层，位于第一绝缘层500上，包括第一电极层200、第二电极层300、第三电极层400、 第二绝缘层600和第三绝缘层700，第二绝缘层600位于第一电极层200和第二电极层300之间，第三绝缘层700位于第二电极层300和第三电极层400之间，第一电极层200通过导线与供电电源的正极(未示出)电连接，第二电极层300通过导线与供电电源的负极(未示出)电连接，第三电极层400通过导线与输出端(未示出)电连接。第一晶体管组件800，包括第一晶体管，第一晶体管的集电极与第一电极层200接触电连接，第一晶体管的发射极通过导线与第三电极层400电连接，第一晶体管的基极通过导线与对应的栅极驱动电路电连接。第二晶体管组件900，包括第二晶体管，第二晶体管的集电极与第三电极层400接触电连接，第二晶体管的发射极通过导线与第二电极层300电连接，第二晶体管的基极通过导线与对应的栅极驱动电路电连接。
需要说明的是，图1未具体示出第一晶体管和第二晶体管，仅示出了第一晶体管和第二晶体管与功率半导体模块内部其他结构间的连接导线。
还需要说明的是，图1仅示例性的给出了功率半导体模块的一种结构，而非对功率半导体模块结构的限定。
在本实施例中，根据实际需要，第一电极层200可以位于第二电极层300面向基板100的一侧，也可以位于第二电极层300背向基板100的一侧，本实施例对此不作具体限定。
并且，晶体管组件除包括晶体管外，还可以包括其他功能元件，例如二极管，可根据实际情况按需选择。
此外，基板100为能够起到支撑作用的板型结构，在上述限定范围内，本实施例对基板100的材料及结构等不做具体限定。
本实施例提供的功率半导体模块包括基板100，第一绝缘层500，位于基板100上，电极层，位于第一绝缘层500上，包括第一电极层200、第二电极层300、第三电极层400、第二绝缘层600和第三绝缘层700，第二绝缘层600位于第一电极层200和第二电极层300之间，第三绝缘层700位于第二电极层300和第三电极层400之间，第一电极层200通过导线与供电电源的正极(未示出)电连接，第二电极层300通过导线与供电电源的负极(未示出)电连接，第三电极层400通过导线与输出端(未示出)电连接，第一晶体管组件800，包括第一晶体管，第一晶体管的集电极与第一电极层200接触电连接，第一晶体管的发射极通过导线与第三电极层400电连接，第一晶体管的基极通过导线与对应的栅极驱动电路电连接，第二晶体管组件900，包括第二晶体管，第二晶体管的集 电极与第三电极层400接触电连接，第二晶体管的发射极通过导线与第二电极层300电连接，第二晶体管的基极通过导线与对应的栅极驱动电路电连接。上述结构的功率半导体模块中分别用于提供正负电压的第一电极层200和第二电极层300层叠设置，减小了电流回路面积，进而减小了寄生电感，使得功率半导体模块中的晶体管的性能良好，有助于电机控制器的整体性能发挥。
在一实施例中，继续参见图1，第一电极层200可以位于第二电极层300背向基板100的一侧，第一电极层200和第三电极层400可以同层设置，第二绝缘层600可以复用为第三绝缘层700。
需要说明的是，第一电极层200和第三电极层400的同层设置，使得第二绝缘层600能够复用为第三绝缘层700，进而无需分别制备第二绝缘层600和第三绝缘层700，仅需形成一个绝缘层即可，达到了减少制备功率半导体模块的工艺步骤，降低功率半导体模块制备难度，利于半导体功率模块薄化的有益效果。
此外，由于第一电极层200和第三电极层400同层设置，因此能够在同一工艺步骤中形成，进一步减少制备功率半导体模块的工艺步骤，降低功率半导体模块的制备难度，利于半导体功率模块薄化。
图2是本申请实施例提供的又一种半导体功率模块的结构示意图。如图2所示，功率半导体模块包括基板100，第一绝缘层500，位于基板100上，电极层，位于第一绝缘层500上，包括第一电极层200、第二电极层300、第三电极层400、第二绝缘层600和第三绝缘层700，第二绝缘层600位于第一电极层200和第二电极层300之间，第三绝缘层700位于第二电极层300和第三电极层400之间，第一电极层200通过导线与供电电源的正极(未示出)电连接，第二电极层300通过导线与供电电源的负极(未示出)电连接，第三电极层400通过导线与输出端(未示出)电连接。第一晶体管组件800，包括第一晶体管，第一晶体管的集电极与第一电极层200接触电连接，第一晶体管的发射极通过导线与第三电极层400电连接，第一晶体管的基极通过导线与对应的栅极驱动电路电连接。第二晶体管组件900，包括第二晶体管，第二晶体管的集电极与第三电极层400接触电连接，第二晶体管的发射极通过导线与第二电极层300电连接，第二晶体管的基极通过导线与对应的栅极驱动电路电连接。
在一实施例中，第一电极层200位于第二电极层300面向基板100的一侧，第二电极层300位于第三电极层400面向基板100的一侧。
需要说明的是，这样的设置使得第一电极层200、第二电极层300和第三电 极层400异层设置，各电极层之间相对独立，不会相互影响。
图2中以虚线示意出电流的流动路径。电流I 1从供电电源的正极(未示出)通过第一导线和第一电极层200流向第一晶体管800的集电极，其中，第一导线为连接供电电源的正极(未示出)和第一电极层200的导线。电流I 2从第一晶体管800的发射极通过第二导线流向第三电极层400，再经第三电极层400流向第二晶体管900的集电极，并通过第二晶体管900的发射极流向第二电极层300，最后流至供电电源的负极(未示出)。值得注意的是，电流I 1和电流I 2的方向相反。
在一实施例中，基板100可以为散热基板100。
需要说明的是，这样的设置有利于功率半导体模块的散热，提高了功率半导体模块的散热能力，避免了晶体管组件中的部件因受热而损坏。
在一实施例中，第一晶体管和第二晶体管可以为绝缘栅双极型晶体管(Insulated Gate Bipolar Transistor，IGBT)或金属氧化物半导体型场效应管(Metal Oxide Semiconductor-Field Effect Transistor，MOS-FET)。
需要说明的是，IGBT及MOS-FET的制备工艺纯熟，应用难度低，易获得稳定且良好的性能，本实施例采用上述两种晶体管作为第一晶体管和第二晶体管，使得本实施例的技术方案与相关技术的兼容性较强，有利于降低薄膜晶体管的制备及应用难度。
在一实施例中，第一晶体管和第二晶体管可以为碳化硅金属氧化物半导体型场效应管(Silicon Carbide-Metal Oxide Semiconductor-Field Effect Transistor，SiC-MOS-FET)。
需要说明的是，SiC具有高耐压、高耐温、高开关速度以及低功耗等优点，因此为获得更好的器件性能，较佳的设置第一晶体管和第二晶体管为SiC-MOS-FET。
在一实施例中，第一晶体管组件800还可以包括第一续流二极管，第一续流二极管的阳极与第一晶体管的集电极电连接，第一续流二极管的阴极与第一晶体管的发射极电连接。第二晶体管组件900还可以包括第二续流二极管，第二续流二极管的阳极与第二晶体管的集电极电连接，第二续流二极管的阴极与第二晶体管的发射极电连接。
需要说明的是，续流二极管能够在断电过程中短路对应的晶体管，进而避免关机时的瞬间高电压损坏对应的晶体管。
在一实施例中，第一电极层200、第二电极层300以及第三电极层400的材料可以为铜。
需要说明的是，铜的导电性能良好，且成本相对较低，是较为理想的电极材料。可以理解的是，在本实施例的其他实施方式中，第一电极层200、第二电极层300以及第三电极层400还可以采用其他导电材料形成，只要是具有良好导电性能的材料均可应用于本实施例中。
在一实施例中，第一电极层200、第二电极层300以及第三电极层400可以为铜板或铜薄膜。
需要说明的是，铜板的硬度较好，不会被轻易损坏，铜薄膜的厚度易控制，能够更为精确的控制电极的厚度，基于上述原因，可根据实际需要选择对应的铜材料结构形成电极层。
图3是本申请实施例提供的一种电极控制器的结构示意图。如图3所示，电机控制器10包括本申请任意实施例所述的功率半导体模块11。

Claims (10)

  1. 一种功率半导体模块，包括：
    基板；
    第一绝缘层，位于所述基板上；
    电极层，位于所述第一绝缘层上，包括第一电极层、第二电极层、第三电极层、第二绝缘层和第三绝缘层，所述第二绝缘层位于所述第一电极层和所述第二电极层之间，所述第三绝缘层位于所述第二电极层和所述第三电极层之间；所述第一电极层通过导线与供电电源的正极电连接，所述第二电极层通过导线与所述供电电源的负极电连接，所述第三电极层通过导线与输出端电连接；
    第一晶体管组件，包括第一晶体管，所述第一晶体管的集电极与所述第一电极层接触电连接，所述第一晶体管的发射极通过导线与所述第三电极层电连接，所述第一晶体管的基极通过导线与对应的栅极驱动电路电连接；
    第二晶体管组件，包括第二晶体管，所述第二晶体管的集电极与第三电极层接触电连接，所述第二晶体管的发射极通过导线与所述第二电极层电连接，所述第二晶体管的基极通过导线与对应的栅极驱动电路电连接。
  2. 根据权利要求1所述的功率半导体模块，其中，所述第一电极层位于所述第二电极层背向所述基板的一侧；所述第一电极层和所述第三电极层同层设置，所述第二绝缘层复用为所述第三绝缘层。
  3. 根据权利要求1所述的功率半导体模块，其中，所述第一电极层位于所述第二电极层面向所述基板的一侧，所述第二电极层位于所述第三电极层面向所述基板的一侧。
  4. 根据权利要求1所述的功率半导体模块，其中，所述基板为散热基板。
  5. 根据权利要求1所述的功率半导体模块，其中，所述第一晶体管和所述第二晶体管为绝缘栅双极型晶体管IGBT或金属氧化物半导体型场效应管MOS-FET。
  6. 根据权利要求5所述的功率半导体模块，其中，所述第一晶体管和所述第二晶体管为碳化硅金属氧化物半导体型场效应管SiC-MOS-FET。
  7. 根据权利要求1所述的功率半导体模块，其中，所述第一晶体管组件还包括第一续流二极管，所述第一续流二极管的阳极与所述第一晶体管的集电极电连接，所述第一续流二极管的阴极与所述第一晶体管的发射极电连接；
    所述第二晶体管组件还包括第二续流二极管，所述第二续流二极管的阳极与所述第二晶体管的集电极电连接，所述第二续流二极管的阴极与所述第二晶 体管的发射极电连接。
  8. 根据权利要求1所述的功率半导体模块，其中，所述第一电极层、所述第二电极层以及所述第三电极层的材料为铜。
  9. 根据权利要求8所述的功率半导体模块，其中，所述第一电极层、所述第二电极层以及所述第三电极层为铜板或铜薄膜。
  10. 一种电机控制器，包括上述权利要求1-9任一项所述的功率半导体模块。
PCT/CN2019/076137 2019-01-18 2019-02-26 功率半导体模块及电机控制器 WO2020147167A1 (zh)

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