WO2020098142A1 - 像素补偿电路及显示装置 - Google Patents
像素补偿电路及显示装置 Download PDFInfo
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- WO2020098142A1 WO2020098142A1 PCT/CN2019/071235 CN2019071235W WO2020098142A1 WO 2020098142 A1 WO2020098142 A1 WO 2020098142A1 CN 2019071235 W CN2019071235 W CN 2019071235W WO 2020098142 A1 WO2020098142 A1 WO 2020098142A1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3225—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix
- G09G3/3233—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED] using an active matrix with pixel circuitry controlling the current through the light-emitting element
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/04—Structural and physical details of display devices
- G09G2300/0421—Structural details of the set of electrodes
- G09G2300/043—Compensation electrodes or other additional electrodes in matrix displays related to distortions or compensation signals, e.g. for modifying TFT threshold voltage in column driver
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0819—Several active elements per pixel in active matrix panels used for counteracting undesired variations, e.g. feedback or autozeroing
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0809—Several active elements per pixel in active matrix panels
- G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2300/00—Aspects of the constitution of display devices
- G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
- G09G2300/0876—Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0243—Details of the generation of driving signals
- G09G2310/0251—Precharge or discharge of pixel before applying new pixel voltage
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2320/00—Control of display operating conditions
- G09G2320/02—Improving the quality of display appearance
- G09G2320/0238—Improving the black level
Definitions
- FIG. 3 is a schematic diagram of the conduction of the pixel compensation circuit in the period t1 according to an embodiment of the invention.
- FIG. 7 is a schematic diagram of the conduction of the pixel compensation circuit in the period t2 according to another embodiment of the invention.
- the present invention provides a pixel compensation circuit, including the following circuit devices:
- a second capacitor C2 which is coupled between the second node N2 and the power supply positive voltage signal Vddin;
- the LED XD1 has an anode coupled to the third node N3 and a cathode coupled to a negative power supply voltage signal Vss.
- the third transistor M3 and the fourth transistor M4 are both PMOS transistors. In other embodiments, the third transistor M3 and the fourth transistor M4 may also use other types of transistors, such as NMOS transistors, which are all within the protection scope of the present invention.
- the fifth transistor M5 is a PMOS tube.
- the fifth transistor M5 may also use other types of transistors such as NMOS tubes, which are all within the protection scope of the present invention.
- the fifth transistor M5 may also use a double gate transistor, which can reduce parasitic parameters to increase the cutoff frequency and reduce the influence of leakage.
- the pixel compensation circuit of this embodiment only four transistors (first transistor M1, third transistor M3, fourth transistor M4, and fifth transistor M5) can be used to realize the function of the pixel compensation circuit Compared with the pixel compensation circuit of the prior art, the number of transistors is reduced, and the probability of failure of the pixel compensation circuit and even the display device is reduced.
- FIG. 3 it is a schematic diagram of the conduction of the pixel compensation circuit in the period t1 according to an embodiment of the present invention.
- the scan signal Sn is at a low level
- the first transistor M1 is turned on
- the first node N1 is written with the data signal Vdata
- the fourth transistor M4 is turned off
- the fifth transistor M5 is turned on to clear the residual charge of the third node N3
- the third transistor M3 is turned on, and the data signal Vdata is written to the second node N2.
- FIG. 4 is a schematic diagram of the conduction of the pixel compensation circuit in the period t2 according to an embodiment of the invention.
- the scan signal Sn is at a high level
- the first transistor M1 is turned off
- the fifth transistor M5 is turned off.
- the voltage at the other end VN1 of the first capacitor C1 decreases, and VN1 ⁇ VN2.
- VN1 2Vdata- ⁇ V + Vth_MT3
- the fourth transistor M4 is turned on, and the current flowing through the fourth transistor M4 is:
- the third transistor M3 has a power input positive voltage signal Vddin input to the gate of the third transistor M3 for switching the current path between a second node N2 and a first node N1 in response to the power positive voltage signal Vddin;
- the fourth transistor M4 has a gate connected to the first node N1 for conducting a current path between the power positive voltage signal Vddin and the third node N3 in response to the voltage signal of the first node N1 Switch
- a second capacitor C2 which is coupled between the second node N2 and the power supply positive voltage signal Vddin;
- the LED XD1 has an anode coupled to the third node N3 and a cathode coupled to a negative power supply voltage signal Vss.
- the gate of the first transistor M1 is input with the scan signal Sn for switching the current path between the data signal Vdata and a fourth node N4 in response to the scan signal Sn;
- the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are all PMOS transistors.
- each transistor may also use other types of transistors such as NMOS, which are all within the protection scope of the present invention.
- the circuit further includes a second switch component for responding to the scan signal Sn to perform a current path between an initialization signal Vint and the third node N3 Switch. Specifically, when the second switch component is turned on, it can clear the residual charge of the third node N3, that is, the residual charge of the anode of the light emitting diode XD1.
- the second switch component includes two transistors, namely:
- the fifth transistor M5 has a scan signal Sn input to the gate thereof for switching the current path between the third node N3 and a fifth node N5 in response to the scan signal Sn;
- the sixth transistor M6 has a scan signal Sn input to its gate for switching the current path between the fifth node N5 and the initialization signal Vint in response to the scan signal Sn.
- the fifth transistor M5 and the sixth transistor M6 may form a double-gate transistor, or two independent transistor devices.
- the fifth transistor M5 and the sixth transistor M6 may be PMOS transistors.
- each transistor may also use other types of transistors such as NMOS, which are all within the protection scope of the present invention.
- the driving signal waveform diagram in this embodiment is the same as FIG. 2.
- the working principle of the pixel compensation circuit of this embodiment will be further described below with reference to FIGS. 2, 6 and 7.
- FIG. 6 it is a schematic diagram of the conduction of the pixel compensation circuit in the period t1 according to another embodiment of the present invention.
- the scan signal Sn is at a low level
- the first transistor M1 and the second transistor M2 are turned on
- the first node N1 writes the data signal Vdata
- the fourth transistor M4 is turned off
- the fifth transistor M5 and the sixth transistor M6 are turned on
- the residual charge of the third node N3 is cleared
- the third transistor M3 is turned on
- the data signal Vdata is written into the second node N2.
- FIG. 7 is a schematic diagram of the conduction of the pixel compensation circuit in the period t2 according to another embodiment of the invention.
- the scan signal Sn is at a high level
- the first transistor M1 and the second transistor M2 are turned off
- the fifth transistor M5 and the sixth transistor M6 are turned off.
- the voltage at the other end VN1 of the first capacitor C1 decreases, and VN1 ⁇ VN2.
- the third transistor M3 is still on until the voltage difference Vgs between the gate and the source of the third transistor M3 reaches the cut-off voltage Vth_MT3 of the third transistor M3, at which time the third transistor M3 is turned off and the first capacitor C1
- the voltage VN1 at the other end becomes:
- VN1 2Vdata- ⁇ V + Vth_MT3
- the fourth transistor M4 is turned on, and the current flowing through the fourth transistor M4 is:
- Id 1 / 2 ⁇ Cox W / L (Vgs-Vth_MT4) 2
- Vth_MT4 is the cut-off voltage of the fourth transistor M4.
- the current Id is the driving current that drives the light-emitting diode XD1 to emit light.
- An embodiment of the present invention further provides a display device including the above-mentioned pixel compensation circuit, and the above-mentioned pixel compensation circuit is used to drive the light-emitting diodes in each pixel in the display device.
- the pixel compensation circuit used in the display device may be the circuit of the embodiment shown in FIG. 1 or the circuit of the embodiment shown in FIG. 5, and is not limited to this. Others add or delete other components in the pixel compensation circuit, or The embodiments of deleting the second switching component, or using one transistor for the first switching component, using two transistors for the second switching component, or using two transistors for the first switching component, using one transistor for the second switching component, etc.
- the display device of the present invention can be a display device of different sizes and functions such as a mobile phone, a tablet computer, a computer display screen, a TV, etc., and has a wide range of applications.
- the display device of the present invention can further reduce the probability of failure. Since a display device often has many pixels, each pixel corresponds to a pixel compensation circuit. For the entire display device, the reduction in the number of transistors is very considerable, which not only improves the stability and service life of the display device, but also reduces the display The production cost and maintenance cost of the device.
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Abstract
一种像素补偿电路及显示装置,其中包括第一开关组件,其用于响应于一扫描信号(Sn)而对数据信号(Vdata)和第一节点(N1)之间的电流路径进行切换;第三晶体管(M3),其用于响应于一电源正极电压信号(Vddin)而对第二节点(N2)和第一节点(N1)之间的电流路径进行切换;第四晶体管(M4),其用于响应于第一节点(N1)的电压信号而对电源正极电压信号(Vddin)和第三节点(N3)之间的电流路径进行切换;第一电容器(C1),其耦接于一使能信号(En)和第一节点(N1)之间;第二电容器(C2),其耦接于第二节点(N2)和电源正极电压信号(Vddin)之间;发光二极管(XD1),其阳极耦接第三节点(N3),阴极耦接一电源负极电压信号(Vss)。相比于现有的像素补偿电路,减少了晶体管的数量,降低了像素补偿电路出现故障的几率,降低了显示装置画面显示异常的几率。
Description
本发明涉及显示技术领域,特别是一种像素补偿电路及显示装置。
AMOLED(Active-matrix organic light emitting diode,有源矩阵有机发光二极管)是电流驱动器件,当有驱动电流流过有机发光二极管时,有机发光二极管发光,驱动电流一般由AMOLED像素补偿电路提供,像素补偿电路一般至少包括一个驱动TFT(Thin Film Transistor,薄膜晶体管)、开关TFT和存储电容,开关TFT打开时,数据信号传输至驱动TFT的栅极,并存储于存储电容上,驱动TFT产生驱动电流。由于工艺、老化等原因,驱动TFT的阈值电压发生漂移,会出现画面异常的问题,例如出现画面显示不均匀的问题。
另外,目前AMOLED像素补偿电路一般应用6T1C或7T1C,即6个晶体管加1个电容,或7个晶体管加1个电容。但是,由于像素补偿电路中晶体管的数量较多,一旦某个晶体管的特性出现变异或故障,会影响整个像素补偿电路正常工作,即较多的晶体管增加了像素补偿电路出现故障的几率,容易引起显示装置画面显示异常,同时较多的晶体管也会增加高分辨率显示装置像素布局的难度。
发明内容
针对现有技术中的缺陷,本发明的目的在于提供一种像素补偿电路及显 示装置,克服了现有技术的缺点,降低了晶体管的数量,降低了像素补偿电路乃至显示装置出现故障的几率。
根据本发明的一个方面,提供一种像素补偿电路,包括:
第一开关组件,其用于响应于一扫描信号而对数据信号和第一节点之间的电流路径进行切换;
第三晶体管,其用于响应于一电源正极电压信号而对第二节点和第一节点之间的电流路径进行切换;
第四晶体管,其用于响应于所述第一节点的电压信号而对所述电源正极电压信号和第三节点之间的电流路径进行切换;
第一电容器,其耦接于一使能信号和所述第一节点之间;
第二电容器,其耦接于所述第二节点和所述电源正极电压信号之间;
发光二极管,其阳极耦接所述第三节点,阴极耦接一电源负极电压信号。
可选地,所述第一开关组件包括第一晶体管,所述第一晶体管用于响应于所述扫描信号而对所述数据信号和所述第一节点之间的电流路径进行切换。
可选地,所述第一晶体管为双栅晶体管。
可选地,所述第一开关组件包括:
第一晶体管,其用于响应于所述扫描信号而对所述数据信号和一第四节点之间的电流路径进行切换;
第二晶体管,其用于响应于所述扫描信号而对所述第四节点和所述第一节点之间的电流路径进行切换。
可选地,所述第一晶体管、第二晶体管、第三晶体管和第四晶体管均为 PMOS管。
可选地,所述电路还包括第二开关组件,所述第二开关组件用于响应于所述扫描信号而对一初始化信号和所述第三节点之间的电流路径进行切换。
可选地,所述第二开关组件包括第五晶体管,所述第五晶体管用于响应于所述扫描信号而对所述初始化信号和所述第三节点之间的电流路径进行切换。
可选地,所述第五晶体管为双栅晶体管。
可选地,所述第二开关组件包括:
第五晶体管,其用于响应于所述扫描信号而对所述第三节点和一第五节点之间的电流路径进行切换;
第六晶体管,其用于响应于所述扫描信号而对所述第五节点和所述初始化信号之间的电流路径进行切换。
可选地,所述第五晶体管和第六晶体管均为PMOS管。
本发明实施例还提供一种显示装置,包括所述的像素补偿电路。
与现有技术相比,本发明的像素补偿电路及显示装置相比于现有的像素补偿电路,减少了晶体管的数量,降低了像素补偿电路出现故障的几率,降低了显示装置画面显示异常的几率,并且降低了高分辨率显示装置像素布局的难度,提高显示装置的显示效果和使用寿命,减少生产和维护成本。
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实 施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其它附图。
图1为本发明一实施例的像素补偿电路的结构示意图;
图2为本发明一实施例的驱动波形图;
图3为本发明一实施例的t1时段内像素补偿电路的导通示意图;
图4为本发明一实施例的t2时段内像素补偿电路的导通示意图;
图5为本发明另一实施例的像素补偿电路的结构示意图;
图6为本发明另一实施例的t1时段内像素补偿电路的导通示意图;
图7为本发明另一实施例的t2时段内像素补偿电路的导通示意图。
现在将参考附图更全面地描述示例实施方式。然而,示例实施方式能够以多种形式实施,且不应被理解为限于在此阐述的实施方式;相反,提供这些实施方式使得本发明将全面和完整,并将示例实施方式的构思全面地传达给本领域的技术人员。在图中相同的附图标记表示相同或类似的结构,因而将省略对它们的重复描述。
所描述的特征、结构或特性可以以任何合适的方式结合在一个或更多实施方式中。在下面的描述中,提供许多具体细节从而给出对本发明的实施方式的充分理解。然而,本领域技术人员应意识到,没有特定细节中的一个或更多,或者采用其它的方法、组元、材料等,也可以实践本发明的技术方案。在某些情况下,不详细示出或描述公知结构、材料或者操作以避免模糊本发 明。
为了解决上述技术问题,如图1所示,本发明提供了一种像素补偿电路,包括如下各个电路器件:
第一开关组件,其用于响应于一扫描信号Sn而对数据信号Vdata和第一节点N1之间的电流路径进行切换;
第三晶体管M3,其栅极输入一电源正极电压信号Vddin,用于响应于所述电源正极电压信号Vddin而对一第二节点N2和一第一节点N1之间的电流路径进行切换;
第四晶体管M4,其栅极连接至所述第一节点N1,用于响应于所述第一节点N1的电压信号而对所述电源正极电压信号Vddin和第三节点N3之间的电流路径进行切换;
第一电容器C1,其耦接于一使能信号En和所述第一节点N1之间;
第二电容器C2,其耦接于所述第二节点N2和所述电源正极电压信号Vddin之间;
发光二极管XD1,其阳极耦接所述第三节点N3,阴极耦接一电源负极电压信号Vss。
在该实施例中,所述第一开关组件包括第一晶体管M1,所述第一晶体管M1的栅极连接至所述扫描信号Sn,用于响应于所述扫描信号Sn而对所述数据信号Vdata和所述第一节点N1之间的电流路径进行切换。
在该实施例中,第一晶体管M1可以采用PMOS管。在其他实施方式中,第一晶体管M1也可以采用NMOS管等其他类型的晶体管。或者,第一晶体管M1也可以采用双栅晶体管。双栅晶体管相对于普通晶体管来说,可以减 小寄生参量,以提高截止频率,降低漏电的影响。
在该实施例中,进一步地,所述第三晶体管M3和第四晶体管M4均为PMOS管。在其他实施方式中,第三晶体管M3和第四晶体管M4也可以采用如NMOS管等其他类型的晶体管,均属于本发明的保护范围之内。
在该实施例中,所述电路还包括第二开关组件,所述第二开关组件用于响应于所述扫描信号Sn而对一初始化信号Vint和所述第三节点N3之间的电流路径进行切换。具体地,第二开关组件在导通时,可以清除第三节点N3残留的电荷,即清除发光二极管XD1阳极残留的电荷。在该实施例中,所述第二开关组件包括第五晶体管M5,所述第五晶体管M5的栅极输入所述扫描信号Sn,用于响应于所述扫描信号Sn而对所述初始化信号Vint和所述第三节点N3之间的电流路径进行切换。
同样地,在该实施例中,第五晶体管M5为PMOS管,在其他实施方式中,第五晶体管M5也可以采用如NMOS管等其他类型的晶体管,均属于本发明的保护范围之内。或者,第五晶体管M5也可以采用双栅晶体管,可以减小寄生参量,以提高截止频率,降低漏电的影响。
如图1所示,通过采用该实施例的像素补偿电路,仅采用四个晶体管(第一晶体管M1、第三晶体管M3、第四晶体管M4和第五晶体管M5)即可以实现像素补偿电路的功能,从而相比于现有技术的像素补偿电路减少了晶体管的数量,降低了像素补偿电路乃至显示装置故障的几率。
下面结合图2~图4来具体说明,采用该实施例的像素补偿电路的工作原理。
如图2所示,对像素的驱动过程主要分为t1时段和t2时段,在t1时段, 扫描信号Sn为低电平,使能信号En为高电平,在t2时段,扫描信号Sn为高电平,电压为Vgh,使能信号En从低电平变为高电平,电压从Vgl1变为Vgl2。
如图3所示,为本发明一实施例的t1时段内像素补偿电路的导通示意图。此时,扫描信号Sn为低电平,第一晶体管M1导通,第一节点N1写入数据信号Vdata,第四晶体管M4截止,第五晶体管M5导通,清除第三节点N3的残留电荷,第三晶体管M3导通,数据信号Vdata写入第二节点N2。
图4为本发明一实施例的t2时段内像素补偿电路的导通示意图。此时,扫描信号Sn为高电平,第一晶体管M1截止,第五晶体管M5截止。使能信号En由Vgl1变为Vgl2,第一电容器C1的第一端VEn从Vgh变为Vgl2(Vgl2>Vgl1),则计ΔV=Vgh-Vgl2。第一电容器C1的另一端VN1的电压降低,VN1<VN2。
第三晶体管M3仍为导通状态,直到第三晶体管M3的栅极和源极之间的电压差Vgs达到第二晶体管M3的截止电压Vth_MT3,此时第三晶体管M3截止,第一电容器C1的另一端电压VN1变为:
VN1=2Vdata-ΔV+Vth_MT3
此时第四晶体管M4导通,流经第四晶体管M4的电流为:
Id=1/2μCox W/L(Vgs-Vth_MT4)2
=1/2μCox W/L[2Vdata-ΔV+Vth_MT3-Vth_MT4]2
其中,Vth_MT4为第四晶体管M4的截止电压。电流Id即为驱动发光二极管XD1发光的驱动电流。
如图5所示,本发明还提供了另一实施例的一种像素补偿电路。与图1中示出的像素补偿电路类似地,该像素补偿电路包括如下各个电路器件:
第一开关组件,其用于响应于一扫描信号Sn而对数据信号Vdata和第一节点N1之间的电流路径进行切换;
第三晶体管M3,其栅极输入一电源正极电压信号Vddin,用于响应于所述电源正极电压信号Vddin而对一第二节点N2和一第一节点N1之间的电流路径进行切换;
第四晶体管M4,其栅极连接至所述第一节点N1,用于响应于所述第一节点N1的电压信号而对所述电源正极电压信号Vddin和第三节点N3之间的电流路径进行切换;
第一电容器C1,其耦接于一使能信号En和所述第一节点N1之间;
第二电容器C2,其耦接于所述第二节点N2和所述电源正极电压信号Vddin之间;
发光二极管XD1,其阳极耦接所述第三节点N3,阴极耦接一电源负极电压信号Vss。
与图1中示出的像素补偿电路不同地,在该实施例中,所述第一开关组件包括两个晶体管,即:
第一晶体管M1,其栅极输入所述扫描信号Sn,用于响应于所述扫描信号Sn而对所述数据信号Vdata和一第四节点N4之间的电流路径进行切换;
第二晶体管M2,其栅极输入所述扫描信号Sn,用于响应于所述扫描信号Sn而对所述第四节点N4和所述第一节点N1之间的电流路径进行切换。
第一晶体管M1和第二晶体管M2可以组成一个双栅晶体管,也可以是 两个独立的晶体管器件。
在该实施例中,第一晶体管M1、第二晶体管M2、第三晶体管M3和第四晶体管M4均为PMOS管。在其他实施方式中,各个晶体管也可以采用如NMOS等其他类型的晶体管,均属于本发明的保护范围之内。
在该实施例中,所述电路还包括第二开关组件,所述第二开关组件用于响应于所述扫描信号Sn而对一初始化信号Vint和所述第三节点N3之间的电流路径进行切换。具体地,第二开关组件在导通时,可以清除第三节点N3残留的电荷,即清除发光二极管XD1阳极残留的电荷。
具体地,与图1中示出的实施例不同地,在该实施例中,所述第二开关组件包括两个晶体管,即:
第五晶体管M5,其栅极输入所述扫描信号Sn,用于响应于所述扫描信号Sn而对所述第三节点N3和一第五节点N5之间的电流路径进行切换;
第六晶体管M6,其栅极输入所述扫描信号Sn,用于响应于所述扫描信号Sn而对所述第五节点N5和所述初始化信号Vint之间的电流路径进行切换。
第五晶体管M5和第六晶体管M6可以组成一个双栅晶体管,也可以是两个独立的晶体管器件。在该实施例中,第五晶体管M5和第六晶体管M6可以为PMOS管。在其他实施方式中,各个晶体管也可以采用如NMOS等其他类型的晶体管,均属于本发明的保护范围之内。
该实施例中的驱动信号波形图与图2相同。下面结合图2、图6和图7来进一步介绍该实施例的像素补偿电路的工作原理。
如图6所示,为本发明另一实施例的t1时段内像素补偿电路的导通示意图。此时,扫描信号Sn为低电平,第一晶体管M1和第二晶体管M2导通, 第一节点N1写入数据信号Vdata,第四晶体管M4截止,第五晶体管M5和第六晶体管M6导通,清除第三节点N3的残留电荷,第三晶体管M3导通,数据信号Vdata写入第二节点N2。
图7为本发明另一实施例的t2时段内像素补偿电路的导通示意图。此时,扫描信号Sn为高电平,第一晶体管M1和第二晶体管M2截止,第五晶体管M5和第六晶体管M6截止。使能信号En由Vgl1变为Vgl2,第一电容器C1的第一端VEn从Vgh变为Vgl2(Vgl2>Vgl1),则计ΔV=Vgh-Vgl2。第一电容器C1的另一端VN1的电压降低,VN1<VN2。
第三晶体管M3仍为导通状态,直到第三晶体管M3的栅极和源极之间的电压差Vgs达到第三晶体管M3的截止电压Vth_MT3,此时第三晶体管M3截止,第一电容器C1的另一端电压VN1变为:
VN1=2Vdata-ΔV+Vth_MT3
此时第四晶体管M4导通,流经第四晶体管M4的电流为:
Id=1/2μCox W/L(Vgs-Vth_MT4)2
=1/2μCox W/L[2Vdata-ΔV+Vth_MT3-Vth_MT4]2
其中,Vth_MT4为第四晶体管M4的截止电压。电流Id即为驱动发光二极管XD1发光的驱动电流。
本发明实施例还提供一种显示装置,包括上述的像素补偿电路,采用上述的像素补偿电路对显示装置中的各个像素中的发光二极管进行驱动。显示装置中采用的像素补偿电路可以为图1示出的实施例的电路或图5示出的实施例的电路,且不限于此,其他的在像素补偿电路中增加或删除其他元器件,或删除第二开关组件,或第一开关组件采用一个晶体管、第二开关组件采用 两个晶体管,或第一开关组件采用两个晶体管、第二开关组件采用一个晶体管等等的实施方式,均属于本发明的保护范围之内。本发明的显示装置可以为手机、平板电脑、电脑显示屏、电视等等不同大小和功能的显示装置,具有广泛的应用范围。
通过采用本发明的像素补偿电路,由于晶体管数量的减少,本发明的显示装置也可以进一步降低出现故障的几率。由于一个显示装置往往有很多个像素,每个像素对应一像素补偿电路,对于整个显示装置来说,晶体管数量的减少十分可观,不仅提高了显示装置使用的稳定性和使用寿命,也减少了显示装置的生成成本和维护成本。
与现有技术相比,本发明的像素补偿电路及显示装置相比于现有的像素补偿电路,减少了晶体管的数量,降低了像素补偿电路出现故障的几率,降低了显示装置画面显示异常的几率,并且降低了高分辨率显示装置像素布局的难度,提高显示装置的显示效果和使用寿命,减少生产和维护成本。
基于本发明中的实施例,本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其它实施例,都属于本发明保护的范围。尽管本发明就优选实施方式进行了示意和描述,但本领域的技术人员应当理解,只要不超出本发明的权利要求所限定的范围,可以对本发明进行各种变化和修改。
Claims (11)
- 一种像素补偿电路,其特征在于,包括:第一开关组件,其用于响应于一扫描信号(Sn)而对数据信号(Vdata)和第一节点(N1)之间的电流路径进行切换;第三晶体管(M3),其用于响应于一电源正极电压信号(Vddin)而对第二节点(N2)和第一节点(N1)之间的电流路径进行切换;第四晶体管(M4),其用于响应于所述第一节点(N1)的电压信号而对所述电源正极电压信号(Vddin)和第三节点(N3)之间的电流路径进行切换;第一电容器(C1),其耦接于一使能信号(En)和所述第一节点(N1)之间;第二电容器(C2),其耦接于所述第二节点(N2)和所述电源正极电压信号(Vddin)之间;发光二极管(XD1),其阳极耦接所述第三节点(N3),阴极耦接一电源负极电压信号(Vss)。
- 根据权利要求1所述的像素补偿电路,其特征在于,所述第一开关组件包括第一晶体管(M1),所述第一晶体管(M1)用于响应于所述扫描信号(Sn)而对所述数据信号(Vdata)和所述第一节点(N1)之间的电流路径进行切换。
- 根据权利要求2所述的像素补偿电路,其特征在于,所述第一晶体管(M1)为双栅晶体管。
- 根据权利要求1所述的像素补偿电路,其特征在于,所述第一开关组件包括:第一晶体管(M1),其用于响应于所述扫描信号(Sn)而对所述数据信号(Vdata)和一第四节点(N4)之间的电流路径进行切换;第二晶体管(M2),其用于响应于所述扫描信号(Sn)而对所述第四节点(N4)和所述第一节点(N1)之间的电流路径进行切换。
- 根据权利要求4所述的像素补偿电路,其特征在于,所述第一晶体管(M1)、第二晶体管(M2)、第三晶体管(M3)和第四晶体管(M4)均为PMOS管。
- 根据权利要求1所述的像素补偿电路,其特征在于,所述电路还包括第二开关组件,所述第二开关组件用于响应于所述扫描信号(Sn)而对一初始化信号(Vint)和所述第三节点(N3)之间的电流路径进行切换。
- 根据权利要求6所述的像素补偿电路,其特征在于,所述第二开关组件包括第五晶体管(M5),所述第五晶体管(M5)用于响应于所述扫描信号(Sn)而对所述初始化信号(Vint)和所述第三节点(N3)之间的电流路径进行切换。
- 根据权利要求7所述的像素补偿电路,其特征在于,所述第五晶体管(M5)为双栅晶体管。
- 根据权利要求6所述的像素补偿电路,其特征在于,所述第二开关组件包括:第五晶体管(M5),其用于响应于所述扫描信号(Sn)而对所述第三节点(N3)和一第五节点(N5)之间的电流路径进行切换;第六晶体管(M6),其用于响应于所述扫描信号(Sn)而对所述第五节点(N5)和所述初始化信号(Vint)之间的电流路径进行切换。
- 根据权利要求9所述的像素补偿电路,其特征在于,所述第五晶体管(M5)和第六晶体管(M6)均为PMOS管。
- 一种显示装置,其特征在于,包括权利要求1至10中任一项所述的像素补偿电路。
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