WO2018001187A1 - 电池片、电池片矩阵、太阳能电池及电池片的制备方法 - Google Patents

电池片、电池片矩阵、太阳能电池及电池片的制备方法 Download PDF

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Publication number
WO2018001187A1
WO2018001187A1 PCT/CN2017/089819 CN2017089819W WO2018001187A1 WO 2018001187 A1 WO2018001187 A1 WO 2018001187A1 CN 2017089819 W CN2017089819 W CN 2017089819W WO 2018001187 A1 WO2018001187 A1 WO 2018001187A1
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Prior art keywords
layer
electrode
diffusion layer
silicon substrate
battery
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PCT/CN2017/089819
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English (en)
French (fr)
Inventor
孙翔
姚云江
田野
周云坛
滕美玲
姜占锋
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比亚迪股份有限公司
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Application filed by 比亚迪股份有限公司 filed Critical 比亚迪股份有限公司
Priority to US16/309,794 priority Critical patent/US20190131475A1/en
Priority to EP17819184.7A priority patent/EP3480859A4/en
Priority to KR1020187037705A priority patent/KR20190013927A/ko
Priority to JP2018568331A priority patent/JP2019519939A/ja
Publication of WO2018001187A1 publication Critical patent/WO2018001187A1/zh

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    • H—ELECTRICITY
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/02—Details
    • H01L31/0216—Coatings
    • H01L31/02161—Coatings for devices characterised by at least one potential jump barrier or surface barrier
    • H01L31/02167—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/02168—Coatings for devices characterised by at least one potential jump barrier or surface barrier for solar cells the coatings being antireflective or having enhancing optical properties for the solar cells
    • H—ELECTRICITY
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
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    • H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
    • H01L31/022441—Electrode arrangements specially adapted for back-contact solar cells
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    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H01L31/035272—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
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    • H01L31/042—PV modules or arrays of single PV cells
    • H01L31/05—Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells
    • H01L31/0504—Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells specially adapted for series or parallel connection of solar cells in a module
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    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/042—PV modules or arrays of single PV cells
    • H01L31/05—Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells
    • H01L31/0504—Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells specially adapted for series or parallel connection of solar cells in a module
    • H01L31/0516—Electrical interconnection means between PV cells inside the PV module, e.g. series connection of PV cells specially adapted for series or parallel connection of solar cells in a module specially adapted for interconnection of back-contact solar cells
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    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H—ELECTRICITY
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    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present disclosure relates to the field of solar cell technologies, and in particular, to a method for preparing a battery sheet, a battery chip matrix, a solar battery, and a battery sheet.
  • the backlight surface and the light receiving surface respectively have 2-3 silver main gate lines as the positive and negative electrodes of the battery sheet, and these silver main gate lines not only consume a large amount of silver paste, but also block incident light. This results in a decrease in the efficiency of the battery.
  • the positive and negative electrodes are respectively distributed on the backlight surface and the light receiving surface of the battery sheet, when the battery sheets are connected in series, it is necessary to solder the negative electrode of the light receiving surface of the battery sheet to the positive electrode of the backlight surface of the adjacent battery sheet when the battery sheets are connected in series. As a result, the welding process is cumbersome and the welding material is used more.
  • the battery sheets and the solder ribbon are easily broken during soldering and subsequent lamination processes.
  • the matrix of the battery in the related art is usually composed of 72 pieces or 60 pieces of cells in series, which constitutes three circuits composed of six strings of battery strings. At this time, at least three diodes are generally required to make each circuit.
  • a diode is provided for bypass protection, since the diode is usually disposed in the junction box of the battery, thereby increasing the cost of the integrated junction box, resulting in increased structural complexity of the battery, and, when a series of components connected in series by a plurality of cells When the series is connected again, the amount of the connecting cable is large, and the material is wasted a lot, resulting in an increase in the cost of the power station.
  • the present disclosure is intended to address at least one of the technical problems existing in the prior art. To this end, the present disclosure is directed to a battery sheet that is excellent in leakage resistance and high in power.
  • the present disclosure also proposes a method of preparing the above battery sheet.
  • the present disclosure also proposes a battery chip matrix having the above battery sheets.
  • the present disclosure also proposes a solar cell having the above-described battery chip matrix.
  • a battery sheet comprising: a silicon wafer including a silicon substrate, a front diffusion layer, a side spacer, and a back spacer, wherein the backlight surface of the silicon substrate includes the first a region and a second region, the front diffusion layer is disposed on a light receiving surface of the silicon substrate, the side spacer layer is disposed on a side surface of the silicon substrate, and the back surface layer is disposed only on a cloth Surrounding the first region, wherein at least a portion of at least one of the side spacer and the back spacer is a diffusion layer of the same type as the front diffusion layer; a gate line layer, the gate line Layer on the front side a side electrode, the side electrode is disposed on the side spacer and electrically connected to the gate line layer; the first electrode, the first electrode is disposed on the back surface layer and The side electrode is electrically connected; the backing layer and the second electrode, the backing layer and the second electrode are both disposed on the second region, wherein the backing layer is
  • the battery sheet according to the present disclosure has good leakage resistance and high power.
  • the backside barrier layer is a backside diffusion layer that is overlaid on the first region.
  • the silicon substrate is P-type, and the front diffusion layer and the back diffusion layer are both phosphorus diffusion layers.
  • the outer edge of the first electrode is projected along the thickness of the silicon wafer on the outline of the first region.
  • the first region and the second region are both non-discrete regions.
  • the backing layer is overlying the second region and the second electrode is disposed on the backing layer.
  • the side spacer is a side diffusion layer that is overlaid on the side surface of the silicon substrate.
  • the silicon substrate is P-type, and the front diffusion layer and the side diffusion layer are both phosphorus diffusion layers.
  • the gate line layer includes a plurality of sub-gate lines extending in a direction perpendicular to a length of the side electrode.
  • the silicon wafer has a span of 20 mm to 60 mm in a direction perpendicular to the side electrode.
  • the silicon wafer is a rectangular sheet, and the first electrode and the second electrode are respectively disposed adjacent to two long sides of the silicon wafer and extend along a length of the silicon wafer.
  • the side electrode is provided on a side of the long side of the silicon wafer adjacent to the first electrode.
  • the battery chip further includes: an anti-reflection layer disposed between the gate line layer and the front diffusion layer.
  • the anti-reflective layer is further disposed between the side electrode and the side spacer.
  • a method of producing a battery sheet according to a second aspect of the present invention, for producing a battery sheet according to the first aspect of the present disclosure comprising the steps of: obtaining: the silicon substrate; B: at the silicon base Preparing the front diffusion layer, the side spacer layer and the back spacer layer on the sheet to obtain the silicon wafer; C: preparing the back electrode layer, the second electrode, the first layer on the silicon wafer An electrode, the side electrode, and the gate line layer.
  • the step A is specifically: dividing a square conventional silicon substrate body at least once according to a rule of constant length to obtain a plurality of the silicon substrates.
  • the backside spacer is a back diffusion layer overlying the first region, the side spacer
  • the layer is a side diffusion layer which is covered on the side surface of the silicon substrate, and the step B is specifically: B1: a diffusion layer of the same type is prepared on each surface of the silicon substrate; B2 Coating a portion of the diffusion layer as the front diffusion layer, the side diffusion layer, and the back diffusion layer with a protective layer; B3: disposing the diffusion layer without the protective layer Partial removal; B4: removing the protective layer to obtain a front diffusion layer, the side diffusion layer, and the back diffusion layer.
  • the battery chip matrix according to the third aspect of the present disclosure is formed by series and/or parallel connection of the battery sheets according to the first aspect of the present disclosure.
  • a solar cell according to a fourth aspect of the present disclosure includes a cell sheet matrix according to the third aspect of the present disclosure.
  • FIG. 1 is a schematic view of a light receiving side of a battery sheet according to an embodiment of the present disclosure
  • Figure 2 is a schematic view of the backlight side of the battery chip shown in Figure 1;
  • Figure 3 is a schematic view of the side of the battery chip shown in Figure 2;
  • Figure 4 is a schematic view showing the two battery sheets shown in Figure 1 in series with a conductive strip
  • Figure 5 is a schematic view of the two battery sheets shown in Figure 4 with the conductive strip removed;
  • FIG. 6 is a schematic diagram of a battery chip matrix in accordance with an embodiment of the present disclosure.
  • Figure 7 is a circuit diagram of the battery chip matrix shown in Figure 6.
  • First cell array 100A second cell array 100B; third cell array 100C;
  • Silicon wafer 1 silicon substrate 11; front diffusion layer 12; side diffusion layer 13; back diffusion layer 14, anti-reflection layer 101;
  • the battery chip 100 is a back contact solar cell that converts solar energy into electrical energy.
  • the battery sheet 100 includes: a silicon wafer 1, a gate line layer 2, a side electrode 3, a first electrode 4, a backing layer 6, and a second electrode 5.
  • the silicon wafer 1 includes a silicon substrate 11, a front diffusion layer 12, a side spacer, and a back spacer.
  • the silicon substrate 11 has a sheet shape, and the two surfaces in the thickness direction of the silicon substrate 11 are respectively a light receiving surface and a backlight surface, and the light receiving surface is connected to the backlight surface through the side surface.
  • the front diffusion layer 12 is disposed on the light receiving surface of the silicon substrate 11.
  • the front diffusion layer 12 is covered on the light receiving surface of the silicon substrate 11, thereby reducing front diffusion.
  • the processing difficulty of the layer 12 improves the processing efficiency and reduces the processing cost.
  • the side spacers are provided on the side surface of the silicon substrate 11, and for example, the side spacers may be provided only on one side surface of the silicon substrate 11, or may be provided on a plurality of side surfaces at the same time. Alternatively, the side spacers are provided only on one side surface of the silicon substrate 11 and are covered on the side surfaces. Thereby, the processing and manufacture of the side spacers are facilitated.
  • the side electrode 3 is disposed on the side spacer, that is, the side electrode 3 may be directly or indirectly disposed on the side spacer. At this time, the side electrode 3 is disposed on the side surface of the silicon wafer 1 and corresponds to the side spacer. That is, projected in a direction perpendicular to the side surface of the side spacer, the side electrode 3 does not extend beyond the outline of the side spacer.
  • the side electrodes 3 are provided on the side surface of the silicon wafer 1 and are not embedded in the interior of the silicon wafer 1, the processing difficulty of the entire battery sheet 100 can be reduced, the processing process can be simplified, the processing efficiency can be improved, and the processing cost can be reduced.
  • the backlight surface of the silicon substrate 11 includes a first region and a second region, and the first region and the second region have no intersection.
  • the first area and the second area may be in contact with each other or not in contact with each other, that is, the contour lines of the first area and the contour lines of the second area may or may not contact each other.
  • the portion of the backside barrier that is in contact with or close to the backing layer 6 is an insulating layer
  • the first region and the second region may be in contact with each other, and when the backing barrier is in contact with or close to the backing layer 6.
  • the diffusion layer is of the same type as the front diffusion layer 12, the first region and the second region may not contact each other.
  • the first area may be a non-discrete type, that is, when the first area is arbitrarily divided into a plurality of sub-areas, the plurality of sub-areas may be connected into one continuous first area.
  • the second area may be a non-discrete type, that is, when the second area is arbitrarily divided into a plurality of sub-areas, the plurality of sub-areas may be connected into one continuous second area.
  • the back spacer is disposed only on the first region, that is, the back surface of the backlight surface of the silicon substrate 11 except the first region does not have a back spacer, and further, the back spacer is covered on the first region. So when the first area is non-discrete In the continuous region, the backside barrier may be disposed on the silicon substrate 11 non-discretely, i.e., continuously.
  • the backside spacers are disposed continuously, i.e., non-discretely, on the silicon substrate 11, and are not discretely, i.e., discontinuous, for example, scattered forms such as scatters, zebra strips, etc. are dispersed in the silicon substrate 11 Therefore, the processing difficulty of the back surface layer is greatly reduced, the processing efficiency is improved, the processing cost is reduced, and the power of the battery sheet 100 can be effectively improved.
  • the gate line layer 2 is disposed on the front diffusion layer 12, that is, the gate line layer 2 may be directly or indirectly disposed on the front diffusion layer 12. At this time, the gate line layer 2 is disposed on the light receiving surface of the silicon wafer 1 and The front diffusion layer 12 corresponds, in other words, is projected in the thickness direction of the silicon wafer 1, and the gate line layer 2 does not exceed the outline of the front diffusion layer 12.
  • the silicon wafer 1 may further include an anti-reflection layer 101, and the anti-reflection layer 101 may be disposed on the front diffusion layer 12.
  • the gate line layer 2 can be directly provided on the anti-reflection layer 101.
  • the gate line layer 2 may be directly disposed on the front diffusion layer 12.
  • the first electrode 4 is disposed on the back surface layer, that is, the first electrode 4 can be directly or indirectly disposed on the back surface layer. At this time, the first electrode 4 is disposed on the backlight surface of the silicon wafer 1 and is first. The regions correspond, in other words, are projected in the thickness direction of the silicon wafer 1, and the first electrode 4 does not extend beyond the first region.
  • the first electrode 4 may also be provided indirectly on the backside barrier through a passivation layer.
  • the backing layer 6 and the second electrode 5 are both disposed on the second region, that is, the backing layer 6 and the second electrode 5 may be directly or indirectly disposed on the second region of the backlight surface of the silicon substrate 11.
  • the backing layer 6 and the second electrode 5 are provided on the backlight surface of the silicon wafer 1 and correspond to the second region, that is, projected in the thickness direction of the silicon wafer 1, the back electrode layer 6 and the second electrode. 5 does not exceed the second area.
  • the backing layer 6 and the second electrode 5 may also be provided indirectly on the backlight surface of the silicon substrate 11 through a passivation layer.
  • the first electrode 4 is neither in contact with the backing layer 6 nor in contact with the second electrode 5.
  • the backing layer 6 and the second electrode 5 may not overlap each other and are in contact with each other. At this time, the backing layer 6 and the second electrode 5 are completely disposed respectively.
  • the backlight surface of the silicon wafer 1 is directly in contact with the electrical connection, so that the space can be utilized to improve the power of the battery sheet 100.
  • the backing layer 6 and the second electrode 5 can also overlap each other. In this case, the surface of the back surface of the silicon wafer 1 is disposed on the surface of the back surface of the silicon wafer 1 with the back surface layer 6 and the second electrode 5 stacked.
  • a kind of charge can be collected when the conductive medium is set.
  • Another type of charge can be collected when on the surface of the silicon substrate 11 that does not have the front diffusion layer 12 (e.g., disposed directly or through the anti-reflection layer 101 or passivation layer described herein).
  • the principle that the conductive medium collects charges on the silicon wafer should be well known to those skilled in the art and will not be described in detail herein.
  • the front diffusion layer 12 may be a phosphorus diffusion layer, and the conductive medium disposed on the phosphorus diffusion layer may collect a negative charge, and the conductive medium disposed on the non-phosphorus diffusion layer. Positive charges can be collected.
  • the gate line layer 2 since the gate line layer 2 is provided (for example, directly on or through the anti-reflection layer 101) on the front diffusion layer 12, the gate line layer 2 can collect a first type of charge (for example, a negative charge).
  • the backing layer 6 is disposed on the backlight surface of the silicon substrate 11 (for example, directly or indirectly through the passivation layer), so that the positive back layer 6 can collect a second kind of charge (for example, a positive charge).
  • the anti-reflection layer 101 may also be disposed between the side electrode 3 and the side spacer layer described herein. At this time, the entire light-receiving surface of the silicon wafer 1 and the outer surface of one side surface may have an anti-reflection layer 101. This facilitates processing and manufacturing. Furthermore, it should be noted that the concept of the anti-reflection layer 101 described herein should be well known to those skilled in the art and primarily serves to reduce reflection and enhance charge collection.
  • the material of the anti-reflection layer 101 may include, but is not limited to, TiO2, Al2O3, SiNxOy, SiNxCy.
  • the first electrode 4 is electrically connected to the gate line layer 2 through the side electrode 3, so that the first kind of charge (eg, negative charge) collected by the gate line layer 2 can be transferred to the first electrode 4 (eg, the negative electrode);
  • the electrode 5 is electrically connected to the backing layer 6, so that a second type of charge (eg, a positive charge) collected by the backing layer 6 can be transferred to the second electrode 5 (eg, a positive electrode).
  • the first electrode 4 and the second electrode 5 can output electric energy as positive and negative poles of the battery sheet 100.
  • the side electrode 3 is provided on the side surface of the silicon wafer 1, the gate line layer 2 and the first electrode 4 can be electrically and electrically connected together easily and conveniently through the side electrode 3, ensuring the reliability of the operation of the battery sheet 100.
  • first electrode 4 and the second electrode 5 are electrodes of opposite polarities, that is, they do not conduct each other and do not form an electrical connection with each other.
  • first electrode 4 and the first electrode All components electrically connected to one electrode 4 and the second electrode 5, and all components electrically connected to the second electrode 5 are not directly conductive, and cannot be indirectly conducted through any external conductive medium, for example, may not contact or pass through an insulating material. Isolate or the like to avoid short-circuiting of the first electrode 4 and the second electrode 5.
  • the backside spacer is configured to prevent the first electrode 4 from being short-circuited by the silicon substrate 11 and the second electrode 5, that is, to avoid direct contact between the first electrode 4 and the silicon substrate 11, thereby causing a short circuit
  • the backside layer may be front and back.
  • the diffusion layer and/or the insulating layer of the same type of the diffusion layer 12, that is, the back surface layer may be all of the same diffusion layer as the front diffusion layer 12, or may be all of the insulating layer, or may be partially of the same type as the front diffusion layer 12.
  • the diffusion layer and the remaining part are insulating layers.
  • the first electrode 4 When the first electrode 4 is provided on the silicon substrate 11 through the insulating layer, the first electrode 4 can be directly insulated from the silicon substrate 11 to prevent the first electrode 4 from being collected from the silicon substrate 11 and collected by the second electrode 5.
  • the charge of the same type of charge can effectively prevent the first electrode 4 from being electrically connected to the second electrode 5 through the silicon substrate 11 to cause a short circuit, that is, avoiding direct contact between the first electrode 4 and the silicon substrate 11 to cause a short circuit.
  • the first electrode 4 When the first electrode 4 is provided on the silicon substrate 11 through a diffusion layer of the same type as the front diffusion layer 12, the first electrode 4 can collect the type of charge collected from the gate wiring layer 2 from the diffused silicon substrate 11.
  • the same charge that is, the charge opposite to the type of charge collected by the second electrode 5, can also avoid short circuit between the first electrode 4 and the second electrode 5, and The power of the battery chip 100 can be increased.
  • the side spacer is configured to prevent the side electrode 3 from being short-circuited by the silicon substrate 11 and the second electrode 5, thereby avoiding short circuit between the first electrode 4 and the second electrode 5, that is, avoiding direct contact between the side electrode 3 and the silicon substrate 11 to cause a short circuit.
  • the side spacers may be the same type of diffusion layer and/or insulating layer as the front diffusion layer 12, that is, the side spacers may all be the same diffusion layer as the front diffusion layer 12, or may be all insulating layers. One part is the same diffusion layer as the front diffusion layer 12, and the remaining part is an insulating layer.
  • the side electrode 3 When the side electrode 3 is provided on the silicon substrate 11 through the insulating layer, the side electrode 3 can be directly insulated from the silicon substrate 11, preventing the side electrode 3 from collecting the same type of charge collected from the second substrate 5 from the silicon substrate 11. The electric charge can effectively prevent the side electrode 3 from being electrically connected to the second electrode 5 through the silicon substrate 11 to cause a short circuit, that is, to avoid direct contact between the side electrode 3 and the silicon substrate 11 to cause a short circuit.
  • the side electrode 3 When the side electrode 3 is provided on the silicon substrate 11 through the same diffusion layer as that of the front diffusion layer 12, the side electrode 3 can collect the same type of charge collected from the gate layer 2 from the diffused silicon substrate 11.
  • the charge that is, the charge opposite to the type of charge collected by the second electrode 5, can also avoid short-circuiting of the side electrode 3 and the second electrode 5, that is, avoiding direct contact between the side electrode 3 and the silicon substrate 11 to cause a short circuit, and can improve the battery.
  • the power of the slice 100 The power of the slice 100.
  • At least a portion of at least one of the side spacer and the back spacer is a diffusion layer of the same type as the front diffusion layer 12, that is, at least a portion of the side spacer is The diffusion layer of the same type of the front diffusion layer 12, or at least part of the back spacer is the same type of diffusion layer as the front diffusion layer 12, so that not only the insulation effect of the first electrode 4 and the second electrode 5 but also the battery can be improved.
  • the power of the slice 100 is a diffusion layer of the same type as the front diffusion layer 12, that is, at least a portion of the side spacer is The diffusion layer of the same type of the front diffusion layer 12, or at least part of the back spacer is the same type of diffusion layer as the front diffusion layer 12, so that not only the insulation effect of the first electrode 4 and the second electrode 5 but also the battery can be improved.
  • the power of the slice 100 is a diffusion layer of the same type as the front diffusion layer 12, that is, at least a portion of the side spacer is The diffusion layer of the same type of the front diffusion layer
  • the backside spacers are all of the same type of diffusion layer as the front diffusion layer 12, i.e., the backside spacers are back diffusion layers 14 that are overlying the first regions.
  • the processing is convenient and the insulation reliability is good.
  • the side spacers are all of the same type of diffusion layer as the front diffusion layer 12, that is, the side spacers are side diffusion layers 13 which are covered on the side surface of the silicon substrate 11. Thereby, the processing is convenient and the insulation reliability is good.
  • the concepts of the silicon substrate, the diffusion layer, the anti-reflection layer, the passivation layer, and the like, and the principle that the conductive medium collects charges from the silicon wafer are well known to those skilled in the art and will not be described in detail herein.
  • the gate line layer 2 may be a conductive dielectric layer composed of a plurality of spaced apart conductive thin gate lines, wherein the fine gate lines may be composed of silver material, thereby
  • the conduction rate can be increased, and on the other hand, the shading area can be reduced, thereby increasing the power of the cell 100 in a disguised manner.
  • the backing layer 6 can be an aluminum layer, that is, an aluminum back field, so that on the one hand, the conduction rate can be increased, and on the other hand, the cost can be reduced.
  • the battery sheet 100 of the embodiment of the present disclosure since at least a portion of at least one of the back surface layer and the side spacer layer is the same diffusion layer as the front surface diffusion layer 12, not only the first electrode 4 but also the first electrode 4 can be ensured.
  • the insulation of the two electrodes 5 can also effectively increase the power of the battery sheet 100.
  • the first electrode on the light receiving surface of the conventional battery sheet can be used.
  • the light-receiving side of the silicon wafer migrates to the backlight side to prevent the first electrode from shielding the light-receiving side of the silicon wafer, so that the power of the battery sheet 100 of the present disclosure is higher than that of the existing battery sheet.
  • the first electrode 4 and the second electrode 5 of the cell sheet 100 of the present disclosure are located on the same side of the silicon wafer 1, thereby facilitating electrical connection between the plurality of battery sheets 100, reducing soldering difficulty, reducing solder usage, and reducing soldering. The probability of breakage of the cell sheet 100 during the subsequent and subsequent lamination process.
  • the processing difficulty of the battery sheet 100 is greatly reduced (for example, it is not necessary to process the openings in the silicon wafer 1 and inject a conductive medium into the openings). ), which in turn increases the processing rate and reduces the processing failure rate and processing cost.
  • the side electrode 3 is provided on one side surface in the width direction of the silicon substrate 11, the path of transferring charges from the light receiving side to the backlight side of the silicon wafer 1 can be effectively shortened, and the charge transfer rate can be improved, thereby The power of the battery sheet 100 is increased in a disguised manner.
  • the silicon wafer 1 has a span of 20 mm to 60 mm in a direction perpendicular to the side electrode 3. That is, the silicon wafer 1 includes a pair (two) of oppositely disposed side surfaces, one of which is provided with side electrodes 3 having a distance of 20 mm to 60 mm.
  • the width of the silicon wafer 1 is 20 mm to 60 mm.
  • the silicon wafer 1 is a rectangular sheet and the side electrodes 3 are provided on one wide side surface of the silicon wafer 1, the length of the silicon wafer 1 It is 20mm to 60mm. Thereby, the path of charge transfer from the light receiving surface of the silicon wafer 1 to the backlight surface can be shortened, thereby increasing the charge transfer rate, thereby increasing the power of the battery chip 100.
  • the silicon substrate 11 is a rectangular sheet, that is, a rectangular sheet or a rectangular sheet.
  • the "rectangular sheet” is understood as a broad sense, that is, not limited to a rectangular sheet in a strict sense, such as a generally rectangular sheet, such as a rectangular sheet having rounded or chamfered corners at four corners. Etc. also falls within the scope of protection of the present disclosure. Thereby, the processing of the battery sheet 100 is facilitated, and the connection between the battery sheet 100 and the battery sheet 100 is facilitated.
  • the silicon substrate 11 is a rectangular sheet.
  • the silicon substrate 11 may be divided by a square-sized silicon wafer body in a length-invariant manner (only “separating” rather than “taking a cutting process"), that is, by a square-sized silicon wafer body according to the length.
  • the invariable manner can be divided into a plurality of rectangular wafer-like silicon substrates 11, in which case each of the silicon substrates 11 has a length equal to the length of the square-sized silicon wafer body, and the width of the plurality of silicon substrates 11 The sum is equal to the width of the square-sized silicon wafer body.
  • the first electrode 4 having a larger area may be processed, optionally, projected along the thickness direction of the silicon wafer 1
  • the outer edge of the first electrode 4 falls on the contour line of the first region.
  • the first region can be utilized to the maximum, and the power of the battery sheet 100 can be improved.
  • the "outer edge” refers to its outline, and for the linear member ( For example, in the case of a fine grid line as described herein, the "outer edge” refers to the ends of its ends.
  • the back surface layer 6 having a larger area may be processed.
  • the backing layer 6 is covered on the second region, and the second electrode 5 is disposed on the backing layer 6.
  • the second region can be utilized to the maximum, and the power of the battery sheet 100 can be improved.
  • the gate line layer 2 includes a plurality of sub-gate lines 21 extending in a length direction perpendicular to the side electrodes 3, that is, each sub-gate line 21 is perpendicular to the length direction of the side electrodes 3. .
  • the charge transfer path of the sub-gate lines 21 can be shortened, the charge transfer efficiency can be improved, and the power of the battery chip 100 can be improved.
  • the battery sheet 100 of one embodiment of the present disclosure will be described by taking the silicon wafer 1 as a rectangular sheet as an example.
  • the first region and the second region may both be rectangular, and the lengths of the first region and the second region are equal to the length of the silicon substrate 11, and the sum of the widths of the first region and the second region is smaller than the silicon base.
  • the width of the sheet 11, the first region and the second region are spaced apart in the width direction of the silicon substrate 11, and optionally, the first region and the second region are respectively disposed adjacent to the two long sides of the silicon substrate 11. That is, the silicon substrate 11 can be divided into a first region and a second region on both sides of the two straight lines by two straight lines parallel to the long sides of the silicon substrate 11, and the area between the two straight lines is a gap region between the first region and the second region. Thereby, subsequent processing is facilitated.
  • the present disclosure is not limited thereto, and the shapes of the first region and the second region are not limited, and for example, the first region and the second region may also be formed in a triangular shape, a semicircular shape, or the like.
  • the first electrode 4 and the second electrode 5 are respectively disposed on the two long sides of the silicon wafer 1 and extend along the length direction of the silicon wafer 1 , and the side electrodes 3 are disposed adjacent to the first electrode 4 of the silicon wafer 1 .
  • the side electrode 3 is provided on one side side surface adjacent to the first electrode 4 in the width direction of the silicon wafer 1. That is, the first electrode 4 and the second electrode 5 are spaced apart in the width direction of the silicon wafer 1, and are respectively disposed adjacent to the two long sides of the silicon wafer 1, and the side electrodes 3 are disposed on one long side of the silicon wafer 1.
  • the side surface is provided on one side side surface in the width direction of the silicon wafer 1, and is located on the side close to the first electrode 4.
  • the first electrode 4 and the second electrode 5 may both be rectangular plates and have the same length as the length of the silicon substrate 11, so that the two broad sides and one long side of the first electrode 4 and the second electrode 5 are both The two wide sides and one long side of the silicon substrate 11 can be respectively aligned, so that the space can be fully utilized, the power of the battery sheet 100 can be improved, and the connection of the subsequent battery sheet 100 to the battery sheet 100 can be facilitated.
  • the side electrode 3 may be configured in a sheet shape and occupy one side side surface in the width direction of the silicon wafer 1, so that the power of the battery sheet 100 can be improved.
  • the specific structure of the side electrode 3, the first electrode 4, and the second electrode 5 is not limited thereto.
  • the side electrode 3, the first electrode 4, and the second electrode 5 may also be discretely formed by a plurality of sub-electrodes that are spaced apart from each other. Type of electrode.
  • the preparation method includes the following steps A, B, and C.
  • Step A A silicon substrate 11 is obtained.
  • the square conventional silicon substrate body is constant in length.
  • the silicon substrate 11 is obtained by dividing at least once.
  • Step B A front diffusion layer 12, a side spacer, and a back spacer are formed on the silicon substrate 11, and the silicon wafer 1 is obtained. Specifically, a front diffusion layer 12 is prepared on the light-receiving surface of the silicon substrate 11, a side spacer is processed on the side surface, and a back surface layer is prepared on the backlight surface.
  • the side spacer is of the side diffusion layer 13 of the same type as the front diffusion layer 12 and is overlaid on the side surface, the back spacer being of the same type as the front diffusion layer 12 and being covered first The back diffusion layer 14 on the area.
  • step B is specifically: first, a diffusion layer of the same type is prepared on each surface of the silicon substrate 11; secondly, a portion of the diffusion layer is used as a portion of the front diffusion layer 12, the side diffusion layer 13, and the back diffusion layer 14. Coating a protective layer (for example, a paraffin layer or a water film layer); again, removing a portion of the diffusion layer not coated with the protective layer; finally, removing the protective layer to obtain a front diffusion layer 12, a side diffusion layer 13, and Back diffusion layer 14.
  • a protective layer for example, a paraffin layer or a water film layer
  • the silicon substrate 11 may be made of P-type silicon.
  • the diffusion layer may be a phosphorus diffusion layer.
  • Step C processing the backing layer 6 on the backlight surface of the silicon substrate 11, and processing the second electrode 5 on the backing layer 6; processing the side electrode 3 on the side spacer; processing the first electrode on the back spacer 4; processing the gate line layer 2 on the front diffusion layer 12.
  • the anti-reflection layer 101 may be prepared on the front diffusion layer 12, the anti-reflection layer 101 may be covered with the front diffusion layer 12, and then the gate line layer 2 may be processed.
  • the anti-reflection layer 101 is indirectly processed on the front diffusion layer 12. Thereby, the reflection of the solar cell 100 by the solar cell 100 is reduced by providing the anti-reflection layer 101, so that the power of the cell sheet 100 can be effectively improved.
  • the process is simple, easy to implement, low in difficulty, and low in cost.
  • the battery sheet 100 includes a rectangular sheet-shaped silicon substrate 11, the light-receiving surface of the silicon substrate 11 has a front diffusion layer 12, and the front diffusion layer 12 has an anti-reflection layer 101, and the anti-reflection layer 101 has
  • the gate line layer 2 has a side diffusion layer 13 on one side surface in the width direction of the silicon substrate 11, and a side electrode 3 on the side diffusion layer 13, and the backlight surface of the silicon substrate 11 includes spaced apart first regions and A second region, wherein the first region has a first electrode 4, the second region has a backing layer 6, and the backing layer 6 has a second electrode 5.
  • the shape and arrangement position of the above components are as shown in FIG. 1 to FIG. 3.
  • a square conventional silicon substrate body for example, a conventional silicon substrate having a size of 156 mm*156 mm
  • the bulk silicon substrate 11 (for example, having a length of 156 mm) is then subjected to the subsequent process of fabricating the cell sheet 100.
  • the present disclosure is not limited thereto, and a rectangular sheet-like silicon substrate 11 may be obtained by other means or processes.
  • the square conventional silicon substrate body is divided into 2-8 parts, on the one hand, the charge can be reduced from the light-receiving surface to the backlight surface.
  • the distance makes the collection of charges efficient and easy, thereby increasing the power of the battery sheet 100, and on the other hand, the silicon substrate 11 is easy to be cut, and the subsequent series-parallel battery sheets 100 consume less solder, thereby improving the series and parallel connection of the battery sheets 100.
  • the overall power reducing costs.
  • Cleaning and texturing cleaning removes dirt on each surface of the silicon substrate 11, and the texturing reduces the reflectance of each surface of the silicon substrate 11.
  • the P-N junction is prepared by double-sided diffusion of the silicon substrate 11 by a diffusion furnace, so that each surface of the silicon substrate 11 has the same type of diffusion layer;
  • A3 mask protection: using paraffin to protect the diffusion layer on the first region (ie used as the back diffusion layer 14) and the diffusion layer on the side surface adjacent to the first region (ie used as the side diffusion layer 13);
  • etching removing the side surface of the silicon substrate 11 and the back surface of the backlight surface that is not protected by paraffin;
  • the anti-reflection layer 101 is evaporated on the front diffusion layer 12, the material of the anti-reflection layer 101 includes but is not limited to TiO2, Al2O3, SiNxOy, SiNxCy;
  • A8 screen-printing the gate line layer 2 on the front diffusion layer 12 in the width direction such that each of the gate line layers 2 is perpendicular to the second electrode 5, and drying;
  • the side electrode 3 is screen printed on the side diffusion layer 13 in the longitudinal direction and dried.
  • steps a7, a8, and a9 can be flexibly changed according to actual needs.
  • negative and “back” as referred to herein mean the backlight surface
  • front refers to the light receiving surface.
  • the cell matrix 1000 is formed by a plurality of, that is, at least two, cell sheets 100 according to the first aspect embodiment described above being connected in series and/or in parallel.
  • the cell array 1000 may be the first cell array 100A, the second cell array 100B, or the third cell array 100C, wherein the first cell array 100A is composed of a plurality of cells arranged in a single column and multiple rows of arrays. 100 is connected in series, the second battery array 100B is formed by a plurality of first battery arrays 100A connected in parallel, and the third battery array 100C is formed by connecting a plurality of second battery arrays 100B in series.
  • the battery chip matrix 1000 according to the embodiment of the present disclosure has high power, high energy efficiency, simple structure, simple processing, and low cost.
  • the battery chip matrix 1000 of the embodiment of the present disclosure has high power and does not need to be added with a diode for bypass protection, and the cost is low.
  • the positive and negative junction boxes can be distributed on both sides of the cell matrix 1000, thereby reducing Phase The amount of connecting cables between adjacent components reduces the cost of the power station.
  • the solar cell includes the cell matrix 1000 of the above-described third aspect embodiment.
  • the solar cell may include, in order from the light receiving side to the backlight side, a first panel, a first bonding layer, a cell matrix 1000, a second bonding layer, and a second panel.
  • the first panel is located on the light receiving side of the battery sheet 100 and may be a glass panel made of a glass material to avoid shading
  • the second panel is located on the backlight side of the battery sheet 100 and may be a conventional back panel, or the second panel may also be
  • the solar cell can be a double glass component at this time.
  • the first adhesive layer is disposed between the first panel and the battery sheet 100 and is used for bonding the first panel to the battery sheet 100.
  • the first adhesive layer may adopt EVA (abbreviation of Ethylene Vinyl Acetate, ie, ethylene). - Vinyl acetate copolymer) made of materials or made of transparent silica gel to ensure good light transmission.
  • the second adhesive layer is disposed between the second panel and the battery sheet 100 and is used for bonding the second panel to the battery sheet 100.
  • the second adhesive layer may be EVA (abbreviation of Ethylene Vinyl Acetate, ie, ethylene). - Vinyl acetate copolymer) made of materials or made of transparent silica gel to ensure good light transmission.
  • the solar cell has better power, better energy efficiency, easier processing, and lower cost.
  • the solar cell includes: a first panel disposed from the light receiving side to the backlight side, a first insulating layer, a cell matrix 1000, a second insulating layer, and a second panel, wherein the cell matrix 1000 is the first cell array 100A That is to say, the plurality of battery sheets 100 are sequentially arranged and connected in series in the same arrangement form (for example, the light receiving surfaces are all facing backwards and the side electrodes 3 are all facing downwards).
  • the second electrode 5 of each of the battery sheets 100 is adjacent to the first electrode 4 of the previous one of the battery sheets 100, in other words, each The first electrodes 4 of the battery sheet 100 are each adjacent to the second electrode 5 of the next battery sheet 100, whereby the conductive strips 1001 (e.g., solder ribbons) may be used to adjoin the adjacent two along the length of the silicon wafer 1.
  • the second electrode 5 of the cell 100 and the first electrode 4 are electrically connected together for the purpose of series connection.
  • the present disclosure is not limited thereto, and the conductive strip 1001 (for example, a solder ribbon) may be electrically connected to the second electrode 5 and the first electrode 4 of the adjacent two battery sheets 100 along the width direction of the silicon wafer 1. .
  • the second electrode 5 and the first electrode 4 of the adjacent two battery cells 100 may be serially connected together by using a second panel.
  • the second The insulating layer may have a through hole, and the second panel may include an electrical conductor that penetrates the through hole to connect the adjacent second electrode 5 and the first electrode 4 in series, whereby the electrical conductor on the second panel may be adjacent The two battery sheets 100 are connected in series.
  • the variants are not detailed here.
  • the following steps may be taken: first, the plurality of battery sheets 100 are arranged in a single row and multiple rows, and then the adjacent two battery sheets 100 are connected in series by using the conductive tape 1001 (for example, a solder ribbon). Get the battery together The slice matrix 1000 and leads to the bus bar 1002. Next, a first panel (eg, glass), a first insulating layer (eg, EVA), a cell matrix 1000, a second insulating layer (eg, EVA), and a second panel (eg, a battery) are sequentially laid in order from bottom to top. The back sheet) is laminated in a laminator to realize packaging of the solar cell to obtain a solar cell.
  • a first panel eg, glass
  • a first insulating layer eg, EVA
  • cell matrix 1000 e.g, a cell matrix 1000
  • a second insulating layer eg, EVA
  • a second panel eg, a battery
  • the second embodiment is substantially the same as the embodiment except that the cell matrix 1000 is the third cell array 100C.
  • the first array of cells 100A may be formed into a third array of cells 100C by "first three and then two strings". Therefore, when the back contact battery is packaged, the following steps may be taken: first, the plurality of battery sheets 100 are arranged in a single row and multiple rows, and then the adjacent two battery sheets 100 are replaced by the conductive strip 1001 (for example, a solder ribbon).
  • the first cell array 100A is obtained in series, and then the six first cell arrays 100A are connected in parallel by the bus bar 1002 into two second cell arrays 100B, and then the two second cell arrays 100B are connected in series.
  • the third cell array 100C is formed to obtain a cell wafer matrix 1000, and the positive and negative electrodes are respectively taken out from both ends of the cell wafer matrix 1000.
  • a first panel eg, glass
  • a first insulating layer eg, EVA
  • a cell matrix 1000 e.g., a cell matrix 1000
  • a second insulating layer e.g. EVA
  • a second panel e.g. a battery
  • the installation position of the junction box can be set according to actual requirements to better meet the actual requirements. For example, it can be designed on both edges of the cell matrix 1000, and can also be disposed on the cell matrix 1000. The back of the edge, etc.
  • the battery sheet 100 and the battery chip matrix 1000 according to the embodiments of the present disclosure have the following advantages.
  • the problem of shading of the light receiving surface of the silicon substrate 11 by the first electrode 4 can be effectively solved to improve the solar cell 100.
  • the charge collected by the front gate line layer 2 is transferred to the first electrode 4 on the backlight side by the side electrode 3 disposed on the side surface of the silicon substrate 11.
  • EWT emitter surround back contact battery
  • MWT metal surround back contact battery
  • IBC full back contact battery
  • other back contact batteries although the light receiving surface can be completely free of gate lines or no main Grid lines to reduce frontal shading, but the manufacturing process of back contact batteries such as EWT, MWT, IBC, etc. is quite complicated.
  • MWT batteries and EWT batteries need to be laser-punched on the silicon wafer, and the electrodes or emitters are made through the holes. It is difficult to make the back of the battery, and the cost is high. It takes a lot of solder to make the components.
  • the IBC battery is extremely demanding in the production process and can only be produced on a small scale.
  • the adjacent two battery sheets 100 can be stacked without being stacked. Discharged and directly connected in series, thereby reducing the welding damage rate, and even reducing the amount of solder used by about 2/3 compared to the existing one, thereby greatly reducing the lead
  • the heat loss of the electrical tape 1001 (for example, a solder ribbon) effectively increases the power of the cell matrix 1000, and since the second electrode 5 and the first electrode 4 of the adjacent two battery cells 100 can be connected on the backlight side of the battery chip 100.
  • the gap between the adjacent two battery sheets 100 is reduced, and the bus bar 1002 can be directly taken out from the battery sheet 100, thereby reducing the overall area of the battery array 1000 and increasing the effective area of the battery matrix 1000.
  • the power of the cell matrix 1000 is further increased.
  • the cell matrix 1000 can adopt a combination of series and parallel combination, so that the production cost can be effectively reduced, so that the positive and negative junction boxes can be distributed on both sides of the cell matrix 1000, reducing the amount of cables and reducing the cost of the power station.
  • the terms “installation”, “connected”, “connected”, “fixed” and the like should be understood broadly, and may be directly connected or indirectly through intermediaries, unless expressly stated otherwise. Connected, it can be the internal communication of two components or the interaction of two components.
  • the specific meanings of the above terms in the present disclosure can be understood by those skilled in the art on a case-by-case basis.
  • the first feature "on” or “under” the second feature may be a direct contact of the first and second features, or the first and second features may be indirectly through an intermediate medium, unless otherwise explicitly stated and defined. contact.

Abstract

一种电池片（100）、电池片矩阵（1000）、太阳能电池及电池片的制备方法，电池片包括：硅片（1）、栅线层（2）、侧电极（3）、第一电极（4）、背电层（6）和第二电极（5），硅片包括硅基片（11）、正面扩散层（12）、侧面隔层以及背面隔层，侧面隔层和背面隔层中的至少一个的至少部分为与正面扩散层类型相同的扩散层，栅线层设在正面扩散层上，侧电极设在侧面隔层上且与栅线层电连接，第一电极设在背面隔层上且与侧电极电连接，背电层和第二电极均设在硅片的背光面上，其中，背电层与第二电极电连接且与第一电极不接触。

Description

电池片、电池片矩阵、太阳能电池及电池片的制备方法 技术领域
本公开涉及太阳能电池技术领域，尤其是涉及一种电池片、电池片矩阵、太阳能电池及电池片的制备方法。
背景技术
相关技术中的晶体硅太阳能电池片，背光面和受光面分别有2-3根银主栅线作为电池片的正负极，这些银主栅线不仅消耗大量的银浆，而且因为遮挡入射光从而造成了电池片的效率下降。另外，由于正负极分别分布在电池片的背光面和受光面上，当电池片串联时，需要采用焊带将电池片受光面的负电极焊接到相邻电池片背光面的正电极上，从而造成焊接工艺繁琐，焊接材料使用较多的问题。而且，焊接时和后续层压工艺中电池片及焊带容易破损。
另外，相关技术中的电池片矩阵通常是由72片或者60片电池片依次串联组成，构成六串电池串组成的三个回路，此时，一般至少需要三个二极管，以使每个回路上设置一个二极管进行旁路保护，由于二极管通常设置于电池的接线盒内，从而增加了集成接线盒的成本，致使电池的结构复杂性提高，而且，当由多个电池片串联而成的串联组件再次进行串联时，连接电缆用量很大，材料浪费很多，致使电站成本增高。
发明内容
本公开旨在至少解决现有技术中存在的技术问题之一。为此，本公开在于提出一种电池片，所述电池片防漏电性好，功率高。
本公开还提出一种上述电池片的制备方法。
本公开还提出一种具有上述电池片的电池片矩阵。
本公开还提出一种具有上述电池片矩阵的太阳能电池。
根据本公开第一方面的电池片，包括：硅片，所述硅片包括硅基片、正面扩散层、侧面隔层、以及背面隔层，其中，所述硅基片的背光面包括第一区域和第二区域，所述正面扩散层设在所述硅基片的受光面上、所述侧面隔层设在所述硅基片的侧表面上、所述背面隔层仅设在且布满在所述第一区域上，其中，所述侧面隔层和所述背面隔层中的至少一个的至少部分为与所述正面扩散层类型相同的扩散层；栅线层，所述栅线层设在所述正面扩 散层上；侧电极，所述侧电极设在所述侧面隔层上且与所述栅线层电连接；第一电极，所述第一电极设在所述背面隔层上且与所述侧电极电连接；背电层和第二电极，所述背电层和所述第二电极均设在所述第二区域上，其中，所述背电层与所述第二电极电连接且与所述第一电极不接触。
根据本公开的电池片，防漏电性好、功率高。
在一些实施例中，所述背面隔层为布满在所述第一区域上的背面扩散层。
在一些实施例中，所述硅基片为P型，所述正面扩散层和所述背面扩散层均为磷扩散层。
在一些实施例中，沿所述硅片的厚度方向投影、所述第一电极的外边缘均落在所述第一区域的轮廓线上。
在一些实施例中，所述第一区域与所述第二区域均为非离散区域。
在一些实施例中，所述第一区域与所述第二区域之间具有间隙。
在一些实施例中，所述背电层布满在所述第二区域上，所述第二电极设在所述背电层上。
在一些实施例中，所述侧面隔层为布满在所述硅基片的所述侧表面上的侧面扩散层。
在一些实施例中，所述硅基片为P型，所述正面扩散层和所述侧面扩散层均为磷扩散层。
在一些实施例中，所述栅线层包括沿垂直于所述侧电极长度方向延伸上多条子栅线。
在一些实施例中，所述硅片在垂直于所述侧电极方向上的跨度为20mm～60mm。
在一些实施例中，所述硅片为长方形片体，所述第一电极和所述第二电极分别贴靠所述硅片的两条长边设置且均沿所述硅片的长度方向延伸，所述侧电极设在所述硅片的邻近所述第一电极的一侧长边侧表面上。
在一些实施例中，所述电池片还包括：减反层，所述减反层设在所述栅线层与所述正面扩散层之间。
在一些实施例中，所述减反层还设在所述侧电极与所述侧面隔层之间。
根据本公开第二方面的电池片的制备方法，用于制备根据本公开第一方面的电池片，所述制备方法包括如下步骤：A：获取所述硅基片；B：在所述硅基片上制备所述正面扩散层、所述侧面隔层和所述背面隔层得到所述硅片；C：在所述硅片上制备所述背电层、所述第二电极、所述第一电极、所述侧电极和所述栅线层。
在一些实施例中，所述步骤A具体为：将正方形常规硅基片本体按照长度不变的规则分割至少一次，以得到多个所述硅基片。
在一些实施例中，所述背面隔层为布满在所述第一区域上的背面扩散层，所述侧面隔 层为布满在所述硅基片的所述侧表面上的侧面扩散层，所述步骤B具体为：B1：在所述硅基片的每个表面上均制备同一类型的扩散层；B2：将所述扩散层的用作为所述正面扩散层、所述侧面扩散层和所述背面扩散层的部分上涂覆保护层；B3：将所述扩散层的未涂覆有所述保护层的部分去除；B4：将所述保护层去除，以得到正面扩散层、所述侧面扩散层和所述背面扩散层。
根据本公开第三方面的电池片矩阵，由根据本公开第一方面所述的电池片串联和/或并联而成。
根据本公开第四方面的太阳能电池，包括根据本公开第三方面电池片矩阵。
本公开的附加方面和优点将在下面的描述中部分给出，部分将从下面的描述中变得明显，或通过本公开的实践了解到。
附图说明
图1是根据本公开实施例的电池片的受光侧的示意图；
图2是图1中所示的电池片的背光侧的示意图；
图3是图2中所示的电池片的侧面的示意图；
图4是图1中所示的两个电池片采用导电带串联的示意图；
图5是图4中所示的两个电池片去除导电带的示意图；
图6是根据本公开实施例的电池片矩阵的示意图；
图7是图6中所示的电池片矩阵的电路示意图。
附图标记：
电池片矩阵1000；焊带1001；汇流条1002；
第一电池片阵列100A；第二电池片阵列100B；第三电池片阵列100C；
电池片100；
硅片1；硅基片11；正面扩散层12；侧面扩散层13；背面扩散层14；减反层101；
栅线层2；子栅线21；侧电极3；第一电极4；第二电极5；
背电层6。
具体实施方式
下面详细描述本公开的实施例，所述实施例的示例在附图中示出，其中自始至终相同或类似的标号表示相同或类似的元件或具有相同或类似功能的元件。下面通过参考附图描述的实施例是示例性的，旨在用于解释本公开，而不能理解为对本公开的限制。
下文提供了许多不同的实施例或例子用来实现本公开的不同结构。为了简化本公开， 下文中对特定例子的部件和设置进行描述。当然，它们仅仅为示例，并且目的不在于限制本公开。此外，本公开可以在不同例子中重复参考数字和/或字母。这种重复是为了简化和清楚的目的，其本身不指示所讨论各种实施例和/或设置之间的关系。此外，本公开提供了的各种特定的工艺和材料的例子，但是本领域普通技术人员可以意识到其他工艺的可应用性和/或其他材料的使用。
下面，参考附图描述根据本公开第一方面实施例的电池片100。其中，电池片100为将太阳能转化为电能的背接触式太阳能电池片。
根据本公开实施例的电池片100，包括：硅片1、栅线层2、侧电极3、第一电极4、背电层6以及第二电极5。其中，硅片1包括硅基片11、正面扩散层12、侧面隔层、以及背面隔层。
硅基片11为片体状，且硅基片11的厚度方向上的两个表面分别为受光面和背光面，受光面与背光面通过侧表面相连。其中，正面扩散层12设在硅基片11的受光面上，例如在本公开的一个可选实施例中，正面扩散层12布满在硅基片11的受光面上，从而降低了正面扩散层12的加工难度，提高了加工效率，降低了加工成本。
侧面隔层设在硅基片11的侧表面上，例如，侧面隔层可以仅设在硅基片11的一个侧表面上、也可以同时设在多个侧表面上。可选地，侧面隔层仅设在硅基片11的一个侧表面上且布满在该侧表面上。由此，方便侧面隔层的加工和制造。
侧电极3设在侧面隔层上，也就是说，侧电极3可以直接或者间接设在侧面隔层上，此时，侧电极3设在硅片1的侧表面上且与侧面隔层相对应，也就是说，沿垂直于侧面隔层所在侧表面方向投影，侧电极3不超出侧面隔层的轮廓线。
由于侧电极3设在硅片1的侧表面上，而并不是嵌设在硅片1的内部的，从而可以降低电池片100整体的加工难度、简化加工工艺、提高加工效率、降低加工成本。
硅基片11的背光面包括第一区域和第二区域，第一区域和第二区域无交集。其中，第一区域与第二区域可以互相接触或者互不接触，也就是说，第一区域的轮廓线与第二区域的轮廓线可以互相接触或者互不接触。例如，当背面隔层的与背电层6相接触或接近的部分为绝缘层时，第一区域和第二区域可以互相接触，而当背面隔层的与背电层6相接触或接近的部分为与正面扩散层12类型相同的扩散层时，第一区域与第二区域可以互不接触。
其中，第一区域可以为非离散型区域，即当将第一区域任意划分成多个子区域时，多个子区域都可以连通成一个连续的第一区域。第二区域可以为非离散型区域，即当将第二区域任意划分成多个子区域时，多个子区域都可以连通成一个连续的第二区域。
背面隔层仅设在第一区域上，即硅基片11的背光面上的除第一区域以外的其余表面上都不具有背面隔层，进一步地，背面隔层布满在第一区域上，这样，当第一区域为非离散 的连续区域时，背面隔层可以非离散、即连续地布置在硅基片11上。
由此，由于背面隔层连续、即非离散地布置在硅基片11上，而并不是离散地、即不连续地，例如呈现散点状、斑马条状等离散形式散布在硅基片11上，从而极大地降低了背面隔层的加工难度，提高了加工效率，降低了加工成本，且可以有效地提高电池片100的功率。
栅线层2设在正面扩散层12上，也就是说，栅线层2可以直接或者间接设在正面扩散层12上，此时，栅线层2设在硅片1的受光面上且与正面扩散层12相对应，换言之，沿硅片1的厚度方向投影，栅线层2不超出正面扩散层12的轮廓线。
例如，在本公开一些实施例中，硅片1还可以包括减反层101，减反层101可以设在正面扩散层12上。这样，当硅片1包括减反层101时，栅线层2可以直接设在减反层101上。而当硅片1不包括减反层101时，栅线层2可以直接设在正面扩散层12上。
第一电极4设在背面隔层上，也就是说，第一电极4可以直接或者间接设在背面隔层上，此时，第一电极4设在硅片1的背光面上且与第一区域相对应，换言之，沿硅片1的厚度方向投影，第一电极4不超出第一区域。例如，第一电极4还可以通过钝化层间接设在背面隔层上。
背电层6和第二电极5均设在第二区域上，也就是说，背电层6和第二电极5可以直接或者间接设在硅基片11的背光面上的第二区域上，此时，背电层6和第二电极5设在硅片1的背光面上且与第二区域相对应，也就是说，沿硅片1的厚度方向投影，背电层6和第二电极5不超出第二区域。例如，背电层6和第二电极5还可以通过钝化层间接设在硅基片11的背光面上。其中，第一电极4既不与背电层6接触、也不与第二电极5接触。
另外，需要说明的是，在本公开的一些实施例中，背电层6和第二电极5可以互不叠置且接触相连，此时，背电层6和第二电极5分别完全设在硅片1的背光面上且直接接触电连接，从而可以充分地利用空间，提高电池片100的功率；在本公开的另外一些实施例中，背电层6和第二电极5还可以相互叠置，此时，背电层6和第二电极5以其两者叠置后的并集表面设在硅片1的背光面上。
这里，需要说明的是，当将导电介质设在(例如直接设在或通过本文所述的减反层101间接设在)正面扩散层12上时可以收集一个种类的电荷，当将导电介质设在(例如直接设在或通过本文所述的减反层101或钝化层间接设在)硅基片11上的不具有正面扩散层12的表面上时，可以收集另一个种类的电荷。这里，需要说明的是，导电介质在硅片上收集电荷的原理应为本领域技术人员所熟知，这里不再详述。
例如，当硅基片11为P型硅时，正面扩散层12可以为磷扩散层，此时设置在磷扩散层上的导电介质可以收集负电荷，而设在非磷扩散层上的导电介质可以收集正电荷。
这样，由于栅线层2设在(例如直接设在或通过减反层101间接设在)正面扩散层12上，从而栅线层2可以收集第一种类的电荷(例如负电荷)。而背电层6设在(例如直接设在或通过钝化层间接设在)硅基片11的背光面上，从而正背电层6可以收集第二种类的电荷(例如正电荷)。
另外，减反层101还可以设在本文所述的侧电极3与侧面隔层之间，此时，硅片1的整个受光面和一个侧表面的外表面上均可以具有减反层101，从而方便加工和制造。此外，需要说明的是，本文所述的减反层101的概念应为本领域技术人员所熟知，其主要起减少反射、加强电荷收集的作用。例如，减反层101的材料可以包括但不限于TiO2、Al2O3、SiNxOy、SiNxCy。
具体地，第一电极4通过侧电极3电连接至栅线层2，从而栅线层2收集的第一种类电荷(例如负电荷)可以传递给第一电极4(例如负电极)；第二电极5电连接至背电层6，从而背电层6收集的第二种类电荷(例如正电荷)可以传递给第二电极5(例如正电极)。由此，第一电极4和第二电极5可以作为电池片100的正负两极输出电能。另外，由于侧电极3设在硅片1的侧面，从而可以简单方便地通过侧电极3将栅线层2和第一电极4有效地电连接在一起，确保电池片100工作的可靠性。
本领域技术人员可以理解的是，第一电极4与第二电极5为极性相反的电极，即互不导通、相互之间不构成电连接，此时，第一电极4、以及与第一电极4电连接的所有部件与第二电极5、以及与第二电极5电连接的所有部件均不能直接导通、也不能通过任何外界导电介质间接导通，例如可以不接触或通过绝缘材料隔离开等，从而避免第一电极4与第二电极5短路。
背面隔层构造成避免第一电极4通过硅基片11与第二电极5短路，也就是说，避免第一电极4与硅基片11直接接触造成短路，例如，背面隔层可以为与正面扩散层12类型相同的扩散层和/或绝缘层，即背面隔层可以全部为与正面扩散层12类型相同的扩散层，也可以全部为绝缘层，也可以一部分为与正面扩散层12类型相同的扩散层、其余一部分为绝缘层。
当将第一电极4通过绝缘层设在硅基片11上时，第一电极4可以直接与硅基片11绝缘，避免第一电极4从硅基片11上收集与第二电极5收集的电荷类型相同的电荷，从而可以有效地避免第一电极4通过硅基片11与第二电极5导通导致短路，即避免第一电极4与硅基片11直接接触造成短路。
当将第一电极4通过与正面扩散层12类型相同的扩散层设在硅基片11上时，第一电极4可以从扩散后的硅基片11上收集与栅线层2收集的电荷类型相同的电荷、即与第二电极5收集的电荷类型相反的电荷，从而也可以避免第一电极4与第二电极5的短路，而且 可以提高电池片100的功率。
其中，侧面隔层构造成避免侧电极3通过硅基片11与第二电极5短路，从而避免第一电极4与第二电极5短路，即避免侧电极3与硅基片11直接接触造成短路。例如，侧面隔层可以为与正面扩散层12类型相同的扩散层和/或绝缘层，即侧面隔层可以全部为与正面扩散层12类型相同的扩散层，也可以全部为绝缘层，也可以一部分为与正面扩散层12类型相同的扩散层、其余一部分为绝缘层。
当将侧电极3通过绝缘层设在硅基片11上时，侧电极3可以直接与硅基片11绝缘，避免侧电极3从硅基片11上收集与第二电极5收集的电荷类型相同的电荷，从而可以有效地避免侧电极3通过硅基片11与第二电极5导通导致短路，即避免侧电极3与硅基片11直接接触造成短路。
当将侧电极3通过与正面扩散层12类型相同的扩散层设在硅基片11上时，侧电极3可以从扩散后的硅基片11上收集与栅线层2收集的电荷类型相同的电荷、即与第二电极5收集的电荷类型相反的电荷，从而也可以避免侧电极3与第二电极5的短路，即避免侧电极3与硅基片11直接接触造成短路，而且可以提高电池片100的功率。
具体地，在本公开的实施例中，侧面隔层和背面隔层中的至少一个的至少部分为与正面扩散层12类型相同的扩散层，也就是说，要么侧面隔层的至少部分为与正面扩散层12类型相同的扩散层，要么背面隔层的至少部分为与正面扩散层12类型相同的扩散层，从而不但可以确保第一电极4与第二电极5的绝缘效果，还可以提高电池片100的功率。
可选地，背面隔层全部为与正面扩散层12类型相同的扩散层，即背面隔层为布满在第一区域上的背面扩散层14。由此，方便加工且绝缘可靠性好。可选地，侧面隔层全部为与正面扩散层12类型相同的扩散层，即侧面隔层为布满在硅基片11的侧表面上的侧面扩散层13。由此，方便加工且绝缘可靠性好。
这里，需要说明的是，硅基片、扩散层、减反层、钝化层等概念、以及导电介质从硅片上收集电荷的原理均为本领域技术人员所熟知，这里不再详述。
另外，在本公开的可选实施例中，栅线层2可以为由多条间隔开设置的可导电细栅线构成的导电介质层，其中，细栅线可以由银材构成，从而一方面可以提高导电速率，另一方面可以缩小遮光面积，从而变相增加电池片100的功率。背电层6可以为铝制层，即铝背场，从而一方面可以提高导电速率，另一方面可以降低成本。
综上，根据本公开实施例的电池片100，由于背面隔层和侧面隔层中的至少一个的至少部分为与正面扩散层12类型相同的扩散层，从而不但可以确保第一电极4与第二电极5的绝缘，还可以有效地提高电池片100的功率。
而且，通过在硅基片11的侧面设置侧电极3，可以将现有电池片受光面上的第一电极 由硅片的受光侧迁移至背光侧，以防止第一电极对硅片的受光侧遮光，从而本公开的电池片100的功率相较现有电池片更高。且本公开电池片100的第一电极4和第二电极5位于硅片1的同一侧，从而便于多个电池片100之间的电连接，降低焊接难度，减少焊料使用量，同时降低了焊接时及后续层压工艺中电池片100的破损几率。
另外，通过将侧电极3设在硅片1的侧表面上，从而极大地降低了电池片100的加工难度(例如无需在硅片1上加工开孔并向开孔内注入导电介质等加工工序)，进而提高了加工速率，降低了加工失败率和加工成本。另外，当将侧电极3设在硅基片11的宽度方向上的一侧侧表面上时，可以有效地缩短从硅片1的受光侧向背光侧传递电荷的路径，提高电荷传递速率，从而变相地提高了电池片100的功率。
在本公开的一个实施例中，硅片1在垂直于侧电极3方向上的跨度为20mm～60mm。也就是说，硅片1包括一组(两个)相对设置的侧表面，其中一个侧表面上设有侧电极3，这组侧表面之间的距离为20mm～60mm。例如在图2和图3所示的示例中，当硅片1为长方形片体、且侧电极3设在硅片1的一个长边侧表面上时，硅片1的宽度为20mm～60mm。例如在本公开的另一个示例中(图未示出该示例)，当硅片1为长方形片体、且侧电极3设在硅片1的一个宽边侧表面上时，硅片1的长度为20mm～60mm。由此，可以缩短电荷从硅片1的受光面向背光面传输的路径，从而提高了电荷的传递速率，进而提高了电池片100的功率。
例如在本公开的一个可选示例中，硅基片11为矩形片体、即长方形片体或矩形片体。这里，需要说明的是，“矩形片体”当作广义理解，即不限于严格意义上的矩形片体，例如大体矩形片体、如四个顶角处具有圆角或倒角的矩形片体等也落入本公开的保护范围之内。由此，方便电池片100的加工，且方便电池片100与电池片100之间的连接。
可选地，硅基片11为长方形片体。例如，硅基片11可以由正方形规格硅片本体按照长度不变的方式分割(仅指“分开”而非特指“采取切割工艺”)而成，也就是说，由正方形规格硅片本体按照长度不变的方式可以分割成多个长方形片体状的硅基片11，此时，每个硅基片11的长度均与正方形规格硅片本体的长度相等、且多个硅基片11的宽度之和与正方形规格硅片本体的宽度相等。
可选地，当第一区域和第二区域均为非离散区域、且无交集、互不接触时，可以加工面积较大的第一电极4，可选地，沿硅片1的厚度方向投影、第一电极4的外边缘落在第一区域的轮廓线上。由此，可以最大化地利用第一区域，提高电池片100的功率。这里，需要说明的是，对于面形部件(例如本文所述的矩形片体状的第一电极4和第二电极5)而言，“外边缘”指的是其轮廓线，对于线形部件(例如本文所述的细栅线)而言，“外边缘”指的是其两端端点。
可选地，当第一区域和第二区域均为非离散区域、且无交集、互不接触时，可以加工面积较大的背电层6。可选地，背电层6布满在第二区域上，第二电极5设在背电层6上。由此，可以最大化地利用第二区域，提高电池片100的功率。
在本公开的一个可选实施例中，栅线层2包括沿垂直于侧电极3长度方向延伸的多条子栅线21，也就是说，每个子栅线21均垂直于侧电极3的长度方向。由此，可以缩短子栅线21的电荷传输路径，提高电荷传输效率，提高电池片100的功率。
下面，仅以硅片1为长方形片体为例进行说明本公开一个具体实施例的电池片100。
可选地，第一区域和第二区域可以均为矩形，且第一区域和第二区域的长度均与硅基片11的长度相等，第一区域和第二区域的宽度之和小于硅基片11的宽度，第一区域和第二区域在硅基片11的宽度方向上间隔开，可选地，第一区域和第二区域分别贴靠硅基片11的两条长边设置。也就是说，可以通过两条与硅基片11的长边平行的直线将硅基片11划分成位于该两条直线两侧的第一区域和第二区域，两条直线之间的区域为第一区域和第二区域之间的缝隙区域。由此，方便后续加工。当然，本公开不限于此，第一区域和第二区域的形状不限，例如第一区域和第二区域还可以形成为三角形、半圆形等等。
可选地，第一电极4和第二电极5分别贴靠硅片1的两条长边设置且均沿硅片1的长度方向延伸，侧电极3设在硅片1的邻近第一电极4的一侧长边侧表面上(如图2和图3所示)，也就是说，侧电极3设在硅片1宽度方向上的邻近第一电极4的一侧侧表面上。也就是说，第一电极4和第二电极5在硅片1的宽度方向上间隔开，且分别贴靠硅片1的两条长边设置，侧电极3设在硅片1的一个长边侧表面上、即设在硅片1的宽度方向上的一侧侧表面上，且位于靠近第一电极4的一侧。由此，电荷的传输路径更短，电池片100的功率更高，且电池片100的加工更加简便，更加便于电池片100与电池片100之间的连接。
可选地，第一电极4和第二电极5可以均为矩形片体且长度与硅基片11的长度相等，从而第一电极4和第二电极5的两条宽边和一条长边均可以与硅基片11的两条宽边和一条长边分别对齐，进而可以充分地利用空间，提高电池片100的功率，且方便后续电池片100与电池片100的连接。
另外，侧电极3也可以构造为片体状且占满硅片1宽度方向上的一侧侧表面上，从而可以提高电池片100的功率。当然，侧电极3、第一电极4和第二电极5的具体结构不限于此，例如，侧电极3、第一电极4和第二电极5还可以分别由间隔开分布的多个子电极组成离散型的电极。
下面，参考附图描述根据本公开第二方面实施例的电池片100的制备方法。
具体地，制备方法包括如下步骤A、步骤B、步骤C。
步骤A：获取硅基片11。例如，可以采用将正方形常规硅基片本体按照长度不变的规 则分割至少一次的方式，得到多个硅基片11。
步骤B：在硅基片11上制备正面扩散层12、侧面隔层、背面隔层，得到所述硅片1。具体地，在硅基片11的受光面上制备正面扩散层12、侧表面上加工侧面隔层、背光面上制备背面隔层。
例如在本公开的一个示例中，侧面隔层为与正面扩散层12类型相同且布满在侧表面上的侧面扩散层13，背面隔层为与正面扩散层12类型相同且布满在第一区域上的背面扩散层14。
上述步骤B具体为：首先，在硅基片11的每个表面上均制备同一类型的扩散层；其次，将扩散层的用作为正面扩散层12、侧面扩散层13以及背面扩散层14的部分上涂覆保护层(例如石蜡层或者水膜层)；再次，将扩散层的未涂覆有保护层的部分去除；最后，将保护层去除，以得到正面扩散层12、侧面扩散层13以及背面扩散层14。
其中，可选地，硅基片11可以为P型硅制成，此时，上述扩散层可以为磷扩散层。
步骤C：在硅基片11的背光面上加工背电层6，并在背电层6上加工第二电极5；在侧面隔层上加工侧电极3；在背面隔层上加工第一电极4；在正面扩散层12加工栅线层2。
这里，需要说明的是，为了进一步提高电池片100的功率，可以在正面扩散层12上制备减反层101，使减反层101布满正面扩散层12，然后再将栅线层2加工在减反层101上以间接加工在正面扩散层12上。由此，通过设置减反层101来减小电池片100对太阳光的反射，从而可以有效地提高电池片100的功率。
由此，根据本公开实施例的电池片100的制备方法，工序简单、易实现、难度低、成本低。
下面，参考附图，简要描述根据本公开一个具体实施例的电池片100及其制备方法。
如图1所示，电池片100包括长方形片体状的硅基片11，硅基片11的受光面具有正面扩散层12，正面扩散层12上具有减反层101，减反层101上具有栅线层2，硅基片11宽度方向上的一侧侧表面上具有侧面扩散层13，侧面扩散层13上具有侧电极3，硅基片11的背光面包括间隔开的第一区域和第二区域，其中，第一区域上具有第一电极4，第二区域上具有背电层6，背电层6上具有第二电极5。其中，上述部件的形状及布置位置如图1-图3所示。
具体地，在制备该电池片100时，首先可以通过激光将正方形常规硅基片本体(例如规格为156mm*156mm的常规硅基片)等分并切割成2-8份长度不变的长方形片体状的硅基片11(例如长度均为156mm)，然后再进行后续的电池片100制作工序。当然，本公开不限于此，还可以采用其他方式或工艺获得长方形片体状的硅基片11。这里，需要说明的是，当正方形常规硅基片本体均分成2-8份时，一方面可以减短电荷由受光面向背光面迁移的 距离，使电荷的收集高效容易，从而提高电池片100的功率，另一方面使得硅基片11容易切割加工，且后续串并联电池片100消耗的焊料较少，从而提高电池片100串并联后的整体功率，降低成本。
下面，以硅基片11为P型硅为例进行说明电池片100的制备方法。
a1、清洗制绒：清洗去除硅基片11各个表面的污垢，制绒降低硅基片11各个表面的反射率；
a2、扩散制结：通过扩散炉对硅基片11进行双面扩散制备P-N结，使硅基片11的各个表面都具有同一类型的扩散层；
a3、掩膜保护：用石蜡保护第一区域上的扩散层(即用作为背面扩散层14)以及与第一区域相邻的侧表面上的扩散层(即用作为侧面扩散层13)；
a4、蚀刻：去除硅基片11侧表面以及背光面上的未被石蜡保护的背结；
a5、去除石蜡保护，去除磷硅玻璃，从而得到石蜡保护下的背面扩散层14和侧面扩散层13；
a6、在正面扩散层12上蒸镀减反层101，减反层101的材料包括但不限于TiO2、Al2O3、SiNxOy、SiNxCy；
a7、在第二区域沿长度方向丝网印刷背电层6、在背电层6上沿长度方向丝网印刷第二电极5、在背面扩散层14上沿长度方向丝网印刷第一电极4、并烘干，其中，第一电极4正好与背面扩散层14重合，背电层6与第一电极4之间存在一定安全距离，避免短路；
a8、在正面扩散层12上沿宽度方向丝网印刷栅线层2以使栅线层2中的每条子栅线21均垂直于第二电极5，并烘干；
a9、在侧面扩散层13上沿长度方向丝网印刷侧电极3，并烘干。这里，需要说明的是，步骤a7、a8、a9的执行顺序可以根据实际需要灵活调换。另外，本文中提及的“反面”、“背面”均指背光面，“正面”指受光面。
下面，描述根据本公开第三方面实施例的电池片矩阵1000。
电池片矩阵1000由多个、即至少两个根据上述第一方面实施例的电池片100串联和/或并联而成。例如，电池片矩阵1000可以为第一电池片阵列100A、第二电池片阵列100B、或第三电池片阵列100C，其中，第一电池片阵列100A由单列多行阵列排布的多个电池片100串联而成，第二电池片阵列100B由多个第一电池片阵列100A并联而成，第三电池片阵列100C由多个第二电池片阵列100B串联而成。
由此，根据本公开实施例的电池片矩阵1000的功率好、能效高、结构简单、加工简便、成本低。具体而言，本公开实施例的电池片矩阵1000的功率高，且不需要加入二极管进行旁路保护，成本低，另外，正负接线盒可以分布在电池片矩阵1000的两侧，从而减少了相 邻组件之间连接电缆的用量，降低了电站成本。
下面，描述根据本公开第四方面实施例的太阳能电池。
太阳能电池包括上述第三方面实施例的电池片矩阵1000。例如，太阳能电池从受光侧到背光侧依次可以包括：第一面板、第一粘结层、电池片矩阵1000、第二粘结层、以及第二面板。其中，第一面板位于电池片100的受光侧且可以为由玻璃材料制成的玻璃面板以避免遮光，第二面板位于电池片100的背光侧且可以为常规背板，或者第二面板也可以为由玻璃材料制成的玻璃面板，此时太阳能电池可以为双玻组件。第一粘结层设在第一面板与电池片100之间且用于将第一面板粘结至电池片100，此时，第一粘结层可以采用EVA(Ethylene Vinyl Acetate的缩写，即乙烯-乙酸乙烯共聚物)材料制成或者采用透明硅胶等材料制成，以确保良好的透光效果。第二粘结层设在第二面板与电池片100之间且用于将第二面板粘结至电池片100，此时，第二粘结层可以采用EVA(Ethylene Vinyl Acetate的缩写，即乙烯-乙酸乙烯共聚物)材料制成或者采用透明硅胶等材料制成，以确保良好的透光效果。由此，太阳能电池的功率更好、能效更好、加工更加简便、成本更低。
下面，简要描述根据本公开两个具体实施例的太阳能电池。
实施例一
太阳能电池包括：从受光侧到背光侧依次设置的第一面板、第一绝缘层、电池片矩阵1000、第二绝缘层和第二面板，其中，电池片矩阵1000为上述第一电池片阵列100A，也就是说，多个电池片100按照同样的摆放形式(例如受光面均朝后、侧电极3均朝下的摆放形式)、依次排列并串接相连。
此时，由于单列中的多个电池片100按照同样形式的摆放，因此，每个电池片100的第二电极5均与其上一个电池片100的第一电极4相邻，换言之，每个电池片100的第一电极4均与其下一个电池片100的第二电极5相邻，由此，可以采用导电带1001(例如焊带)沿着硅片1的长度方向将相邻的两个电池片100的第二电极5和第一电极4电连接在一起，以达到串联的目的。
当然，本公开不限于此，还可以将导电带1001(例如焊带)沿着硅片1的宽度方向将相邻的两个电池片100的第二电极5和第一电极4电连接在一起。当然，还不限于此，例如，还可以采用第二面板将相邻的两个电池片100的第二电极5和第一电极4串接在一起，具体地，在该实施例中，第二绝缘层上可以具有穿孔，第二面板可以包括透过穿孔以将相邻的第二电极5和第一电极4串联导通的导电体，由此，第二面板上的导电体可以将相邻的两个电池片100串接在一起。这里不再详述变形方案。
由此，在封装上述电池时，可以采用如下步骤：首先，将多个电池片100单列多行阵列排布，然后采用导电带1001(例如焊带)将相邻的两个电池片100串联在一起得到电池 片矩阵1000，并引出汇流条1002。接着，按照从下到上的顺序，依次铺设第一面板(例如玻璃)、第一绝缘层(例如EVA)、电池片矩阵1000、第二绝缘层(例如EVA)、以及第二面板(例如电池背板)，并放入层压机层压，从而实现太阳能电池的封装，得到太阳能电池。
实施例二
实施例二与实施例一大体相同，不同之处仅在于：电池片矩阵1000为第三电池片阵列100C。例如可以采用“先三并再两串”的方式将第一电池片阵列100A组成第三电池片阵列100C。由此，在封装上述背接触电池时，可以采用如下步骤：首先，将多个电池片100单列多行阵列排布，然后采用导电带1001(例如焊带)将相邻的两个电池片100串联在一起得到第一电池片阵列100A，然后采用汇流条1002将六个第一电池片阵列100A三三并联成两个第二电池片阵列100B，然后再将两个第二电池片阵列100B串联成第三电池片阵列100C，从而得到电池片矩阵1000，再将正负极分别从电池片矩阵1000的两端引出。
接着，按照从下到上的顺序，依次铺设第一面板(例如玻璃)、第一绝缘层(例如EVA)、电池片矩阵1000、第二绝缘层(例如EVA)、以及第二面板(例如电池背板或玻璃)，并放入层压机层压，安装接线盒和边框，从而实现太阳能电池的封装及制作，得到太阳能电池。这里，需要说明的是，接线盒的设置位置可以根据实际要求设置，以更好地满足实际要求，例如可以设计在电池片矩阵1000两个边缘、还可以设置在电池片矩阵1000两个靠近的边缘的背面等。
综上所述，根据本公开实施例的电池片100及电池片矩阵1000，具有以下几方面优势。
第一、由于第一电极4和第二电极5均位于硅基片11的背光侧，从而可以有效地解决第一电极4对硅基片11的受光面的遮光问题，以提高电池片100的功率、降低银浆用量、降低生产成本，同时由于采用在硅基片11的侧表面上设置侧电极3的方式将正面栅线层2收集的电荷传递给背光侧的第一电极4，从而极大地简化了电池片100的生产工艺，降低了电池片100的制作难度和生产成本，使得电池片100可以大规模量产。
然而，在现有技术中，EWT(发射极环绕背接触电池)、MWT(金属环绕背接触电池)、IBC(全背接触电池)等背接触电池，虽然受光面可以完全没有栅线或没有主栅线以减少正面遮光，但是，EWT、MWT、IBC等背接触电池的制作工艺相当复杂，如MWT电池和EWT电池需要在硅片上进行激光打孔，并将电极或者发射区穿过孔制做到电池背面，制作难度大，成本高，制作组件也需要耗费大量的焊料，而IBC电池对制作工艺要求极高，只能小规模生产。
第二、由于第二电极5和第一电极4均位于电池片100的背光侧且分别位于硅基片11宽度方向上的两侧，从而相邻的两个电池片100可以无需叠置、依次排开、直接串联，从而减少了焊接损坏率，甚至可以减少相比现有约2/3的焊料使用量、进而极大地降低了导 电带1001(例如焊带)热损耗，有效提高了电池片矩阵1000的功率，而且，由于相邻两个电池片100的第二电极5和第一电极4可以在电池片100的背光侧连接，从而减小了相邻两个电池片100之间的间隙，而且汇流条1002可以直接从电池片100引出，进而减少了电池片矩阵1000的总体面积，增加了电池片矩阵1000的有效面积，进而增加了电池片矩阵1000的功率。
然而，在现有技术中，具有按照瓦片式铺排方式用锡膏将电池片的背面电极与相邻电池片的正面电极重叠串联的连接工艺，然而，此种方式虽然可以省去了大量的焊接材料，降低了热损耗，但是，瓦片式铺排方式制作组件的方法很容易在焊接过程和后续的层压工艺中造成电池片的破碎损伤，而且层叠位置处的电池片无法参与发电，造成浪费，影响组件功率。
第三、由于电池片矩阵1000可以采用串联和并联相组合的结构，进而可以有效地降低生产成本，使得正负接线盒可以分布在电池片矩阵1000的两边，减少电缆用量，降低电站成本。
然而，在现有技术中，电池片矩阵中的所有电池片均需依次串联，从而需要额外加入二极管进行旁路保护，不但可靠性不高、结构复杂、而且生产成本高，不利于大批量投入生产。
在本公开的描述中，需要理解的是，术语“上”、“下”、“前”、“后”等指示的方位或位置关系为基于附图所示的方位或位置关系，仅是为了便于描述本公开和简化描述，而不是指示或暗示所指的装置或元件必须具有特定的方位、以特定的方位构造和操作，因此不能理解为对本公开的限制。
在本公开中，除非另有明确的规定和限定，术语“安装”、“相连”、“连接”、“固定”等术语应做广义理解，例如，可以是直接相连，也可以通过中间媒介间接相连，可以是两个元件内部的连通或两个元件的相互作用关系。对于本领域的普通技术人员而言，可以根据具体情况理解上述术语在本公开中的具体含义。在本公开中，除非另有明确的规定和限定，第一特征在第二特征“上”或“下”可以是第一和第二特征直接接触，或第一和第二特征通过中间媒介间接接触。
在本说明书的描述中，参考术语“一个实施例”、“一些实施例”、“示例”、“具体示例”、或“一些示例”等的描述意指结合该实施例或示例描述的具体特征、结构、材料或者特点包含于本公开的至少一个实施例或示例中。在本说明书中，对上述术语的示意性表述不必须针对的是相同的实施例或示例。而且，描述的具体特征、结构、材料或者特点可以在任一个或多个实施例或示例中以合适的方式结合。此外，在不相互矛盾的情况下，本领域的技术人员可以将本说明书中描述的不同实施例或示例以及不同实施例或示例的特征进行结 合和组合。
尽管已经示出和描述了本公开的实施例，本领域的普通技术人员可以理解：在不脱离本公开的原理和宗旨的情况下可以对这些实施例进行多种变化、修改、替换和变型，本公开的范围由权利要求及其等同物限定。

Claims (19)

  1. 一种电池片(100)，其特征在于，包括：
    硅片(1)，所述硅片(1)包括硅基片(11)、正面扩散层(12)、侧面隔层、以及背面隔层，其中，所述硅基片(11)的背光面包括第一区域和第二区域，所述正面扩散层(12)设在所述硅基片(11)的受光面上、所述侧面隔层设在所述硅基片(11)的侧表面上、所述背面隔层仅设在且布满在所述第一区域上，其中，所述侧面隔层和所述背面隔层中的至少一个的至少部分为与所述正面扩散层(12)类型相同的扩散层；
    栅线层(2)，所述栅线层(2)设在所述正面扩散层(12)上；
    侧电极(3)，所述侧电极(3)设在所述侧面隔层上且与所述栅线层(2)电连接；
    第一电极(4)，所述第一电极(4)设在所述背面隔层上且与所述侧电极(3)电连接；
    背电层(6)和第二电极(5)，所述背电层(6)和所述第二电极(5)均设在所述第二区域上，其中，所述背电层(6)与所述第二电极(5)电连接且与所述第一电极(4)不接触。
  2. 根据权利要求1所述的电池片(100)，其特征在于，所述背面隔层为布满在所述第一区域上的背面扩散层(14)。
  3. 根据权利要求2所述的电池片(100)，其特征在于，所述硅基片(11)为P型，所述正面扩散层(12)和所述背面扩散层(14)均为磷扩散层。
  4. 根据权利要求1所述的电池片(100)，其特征在于，沿所述硅片(1)的厚度方向投影、所述第一电极(4)的外边缘均落在所述第一区域的轮廓线上。
  5. 根据权利要求1所述的电池片(100)，其特征在于，所述第一区域与所述第二区域均为非离散区域。
  6. 根据权利要求1所述的电池片(100)，其特征在于，所述第一区域与所述第二区域之间具有间隙。
  7. 根据权利要求6所述的电池片(100)，其特征在于，所述背电层(6)布满在所述第二区域上，所述第二电极(5)设在所述背电层(6)上。
  8. 根据权利要求1所述的电池片(100)，其特征在于，所述侧面隔层为布满在所述硅基片(11)的所述侧表面上的侧面扩散层(13)。
  9. 根据权利要求8所述的电池片(100)，其特征在于，所述硅基片(11)为P型，所述正面扩散层(12)和所述侧面扩散层(13)均为磷扩散层。
  10. 根据权利要求1所述的电池片(100)，其特征在于，所述栅线层(2)包括沿垂直于所述侧电极(3)长度方向延伸的多条子栅线(21)。
  11. 根据权利要求1所述的电池片(100)，其特征在于，所述硅片(1)在垂直于所述侧电极(3)方向上的跨度为20mm～60mm。
  12. 根据权利要求11所述的电池片(100)，其特征在于，所述硅片(1)为长方形片体，所述第一电极(4)和所述第二电极(5)分别贴靠所述硅片(1)的两条长边设置且均沿所述硅片(1)的长度方向延伸，所述侧电极设在所述硅片(1)的邻近所述第一电极(4)的一侧长边侧表面上。
  13. 根据权利要求1-12中任一项所述的电池片(100)，其特征在于，还包括：
    减反层(101)，所述减反层(101)设在所述栅线层(2)与所述正面扩散层(12)之间。
  14. 根据权利要求13所述的电池片(100)，其特征在于，所述减反层(101)还设在所述侧电极(3)与所述侧面隔层之间。
  15. 一种电池片(100)的制备方法，其特征在于，用于制备根据权利要求1-14中任一项所述的电池片(100)，所述制备方法包括如下步骤：
    A：获取所述硅基片(11)；
    B：在所述硅基片(11)上制备所述正面扩散层(12)、所述侧面隔层和所述背面隔层得到所述硅片(1)；
    C：在所述硅片(1)上制备所述背电层(6)、所述第二电极(5)、所述第一电极(4)、所述侧电极(3)和所述栅线层(2)。
  16. 根据权利要求15所述的电池片(100)的制备方法，其特征在于，所述步骤A具体为：
    将正方形常规硅基片本体按照长度不变的规则分割至少一次，以得到多个所述硅基片(11)。
  17. 根据权利要求15所述的电池片(100)的制备方法，其特征在于，所述背面隔层为布满在所述第一区域上的背面扩散层(14)，所述侧面隔层为布满在所述硅基片(11)的所述侧表面上的侧面扩散层(13)，所述步骤B具体为：
    B1：在所述硅基片(11)的每个表面上均制备同一类型的扩散层；
    B2：将所述扩散层的用作为所述正面扩散层(12)、所述侧面扩散层(13)和所述背面扩散层(14)的部分上涂覆保护层；
    B3：将所述扩散层的未涂覆有所述保护层的部分去除；
    B4：将所述保护层去除，以得到正面扩散层(12)、所述侧面扩散层(13)和所述背面扩散层(14)。
  18. 一种电池片矩阵(1000)，其特征在于，由多个根据权利要求1-14中任一项所述 的电池片(100)串联和/或并联而成。
  19. 一种太阳能电池，其特征在于，包括根据权利要求18中所述的电池片矩阵(1000)。
PCT/CN2017/089819 2016-06-30 2017-06-23 电池片、电池片矩阵、太阳能电池及电池片的制备方法 WO2018001187A1 (zh)

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