WO2017128212A1 - Circuit board and memory using same - Google Patents
Circuit board and memory using same Download PDFInfo
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- WO2017128212A1 WO2017128212A1 PCT/CN2016/072583 CN2016072583W WO2017128212A1 WO 2017128212 A1 WO2017128212 A1 WO 2017128212A1 CN 2016072583 W CN2016072583 W CN 2016072583W WO 2017128212 A1 WO2017128212 A1 WO 2017128212A1
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- heat dissipation
- memory
- circuit board
- dissipation layer
- layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
Definitions
- the present invention relates to a circuit board, and to a memory to which the circuit board is applied.
- the heat dissipation efficiency of the existing PCB inner layer is usually low.
- a memory stick when a memory bar operates at a high frequency, a large amount of heat accumulation in the memory strip PCB cannot be quickly discharged, and the temperature of the memory stick rises rapidly. When the memory module temperature rises to a critical value, the memory module will not be able to continue to maintain high frequency operation.
- a circuit board comprising parallel first and second surfaces, wherein the first surface and the second surface are connected by a side surface, the circuit board further comprising a first heat dissipation layer disposed on the first surface and disposed on the first surface a second heat dissipation layer of the second surface, the first heat dissipation layer and the second heat dissipation layer including a plurality of heat dissipation holes.
- the first surface includes a first heat dissipation region and a first component region, and the first heat dissipation layer is disposed in the first heat dissipation region.
- a first isolation trench is disposed between the first heat dissipation region and the first component region.
- the second surface includes a second heat dissipation region and a second component region, and the second heat dissipation layer is disposed in the second heat dissipation region.
- a second isolation trench is disposed between the second heat dissipation region and the second component region.
- a memory comprising a circuit board and a plurality of chips, the circuit board comprising parallel first and second surfaces, the first surface and the second surface being connected by a side surface, the circuit board further comprising a first heat dissipation layer on the first surface and a second heat dissipation layer disposed on the second surface, the first heat dissipation layer and the second heat dissipation layer including a plurality of heat dissipation holes.
- the memory includes an interface located at a first end of the memory.
- the memory comprises a heat sink, and the heat sink is closely connected to the plurality of chips, the first heat dissipation layer and the second heat dissipation layer.
- the heat sink is for detachably socketed to the second end of the memory.
- the memory is a memory module.
- heat in the circuit board can be quickly discharged to lower the temperature of the circuit board.
- FIG. 1 is a schematic view of a preferred embodiment of a circuit board of the present invention.
- FIG. 2 is a cross-sectional view of a preferred embodiment of the circuit board of FIG. 1.
- FIG. 3 is a schematic diagram of a preferred embodiment of a memory of the present invention.
- FIG. 4 is another schematic diagram of a preferred embodiment of a memory of the present invention.
- FIG. 5 is a partial schematic view of another preferred embodiment of the memory of the present invention.
- Circuit board 100 First surface 11 Second surface 12 Side surface 13 First heat dissipation layer 110 Second heat dissipation layer 120 Vents twenty one First heat dissipation zone 31 Second heat dissipation zone 32 First component area 41 Second component area 42 First isolation slot 51 Second isolation slot 52 level one 61 Second floor 62 middle layer 60 Memory 200 heat sink 300 Memory chip 71, 91 interface 81
- the circuit board 100 in a preferred embodiment of the circuit board 100 of the present invention, includes a first surface 11 and a second surface 12 that are opposite to each other, and the first surface 11 and the second surface 12 are 12 Connected by side surfaces 13.
- the circuit board 100 further includes a first heat dissipation layer 110 disposed on the first surface 11 and a second heat dissipation layer 120 disposed on the second surface 12 .
- the first heat dissipation layer 110 includes a plurality of heat dissipation holes 21 .
- the second heat dissipation layer 120 includes a plurality of heat dissipation holes.
- the first surface 11 of the circuit board 100 includes a first heat dissipation region 31 and a first component region 41.
- a first isolation trench 51 is disposed between the first heat dissipation region 31 and the first component region 41.
- the first heat dissipation layer 110 is disposed in the first heat dissipation region 31.
- the second surface 12 of the circuit board 100 includes a second heat dissipation region 32 (not shown) and a second component region 42 (not shown).
- a second isolation trench 52 is disposed between the second heat dissipation region 32 and the second component region 42.
- the second heat dissipation layer 120 is disposed in the second heat dissipation region 32. Since the second surface 12 and the first surface 11 are symmetrically designed in the embodiment, the second heat dissipation region 32, the second component region 42, and the second isolation trench 52 are not shown in the drawing.
- the first heat dissipation layer 110 may be disposed on the first surface 11 of the circuit board 100 in an irregular shape, for example, around the pads of the first component region 41, without limitation. In the first heat dissipation zone 31.
- the second heat dissipation layer 120 may be disposed on the second surface 12 of the circuit board 100 in an irregular shape, for example, around each pad of the second component region 42 without being limited to the first Two heat dissipation zones 32.
- first heat dissipation layer 110 and the second heat dissipation layer 120 may be asymmetrically designed.
- the first isolation trench 51 and the second isolation trench 52 are used to prevent the heat dissipation layer from contacting the pad.
- the circuit board 100 includes a first layer 61, a second layer 62, and an intermediate layer 60.
- the first layer 61 is a copper foil layer
- the second layer 62 is a base material layer
- the intermediate layer 60 is an inner film layer.
- the intermediate layer 60 may be made of a material such as resin, epoxy glass fiber or the like.
- the plurality of heat dissipation holes 21 are all through holes.
- the plurality of heat dissipation holes 21 sequentially penetrate the first heat dissipation layer 110 , the first layer 61 , the intermediate layer 60 , the second layer 62 , and the second heat dissipation layer 120 .
- the first heat dissipation layer 110 is a copper foil.
- the copper foil in the region where the first heat dissipation layer 110 is located is not etched to form the first heat dissipation layer 110.
- the trace of the first heat dissipation layer 110 and the first component region 41 is divided by the first isolation trench 51 to avoid signal interference.
- the second heat dissipation layer 120 may be formed by a copper foil layer not being etched, and the traces of the second heat dissipation layer 120 and the second component region 42 may be divided by the second isolation trench 52. To avoid signal interference.
- first heat dissipation layer 110 and the second heat dissipation layer 120 are formed by a copper foil layer without etching, the first heat dissipation layer 110 and the second heat dissipation layer 120 may be applied to an inner layer of the multilayer circuit board.
- one end of the trace of the first component region 41 is located near the first isolation trench 51.
- one end of the trace of the second component region 42 is located near the second isolation trench 52.
- the plurality of louvers 21 may be filled with a specific metal to assist in heat dissipation, including but not limited to copper.
- the plurality of heat dissipation holes 21 may be partially through holes and partially open to specific positions.
- the plurality of heat dissipation holes 21 may also be completely opened to a specific position, such as all of the openings to the intermediate layer 60 without penetrating the intermediate layer 60.
- the memory 200 of the present invention includes a multi-layer circuit board and a plurality of memory chips 71.
- the multilayer circuit board includes the circuit board 100.
- the memory 200 further includes an interface 81 and a heat sink 300.
- the interface 81 is located at a first end of the memory 200.
- the heat sink 300 is detachably sleeved on the second end of the memory 200.
- the heat sink 300 is closely connected to the plurality of memory chips 71, the first heat dissipation layer 110, and the second heat dissipation layer 120.
- the heat sink 300 is configured to dissipate heat for the first heat dissipation layer 110, the second heat dissipation layer 120, and the plurality of memory chips 71.
- the first end of the memory 200 is parallel to the second end of the memory 200.
- the heat sink 300 can also be sleeved at the third end of the memory 200.
- the third end of the memory 200 is perpendicular to the first end of the memory 200.
- the heat sink 300 may also be soldered to the first heat dissipation layer 110 or the second heat dissipation layer 120.
- the heat sink 300 may be made of a metal material or other material having a good thermal conductivity. In the present embodiment, the heat sink 300 is made of aluminum.
- the memory 200 is a memory module.
- the interface 81 is a gold finger extending from the first end of the circuit board 100.
- the interface 81 is used to connect to a memory slot.
- the memory 200 includes a multi-layer circuit board (not shown) and at least one memory chip 91.
- the first surface of the multilayer circuit board includes a first isolation trench 51, an interface 81, a first heat dissipation layer 110, and heat dissipation ends A1-A8.
- the first isolation trench 51 is between the first heat dissipation layer 110 and the heat dissipation ends A1 - A8.
- the memory chip 91 includes pins 1-8.
- the pin 1 of the memory chip 91 is connected to the pin 1 of the interface 81.
- the pin 2 of the memory chip 91 is connected to the pin 2 of the interface 81.
- the pin 3 of the memory chip 91 is connected to the pin 3 of the interface 81.
- the pin 4 of the memory chip 91 is connected to the pin 4 of the interface 81.
- the pin 5 of the memory chip 91 is connected to the pin 5 of the interface 81.
- the pin 6 of the memory chip 91 is connected to the pin 6 of the interface 81.
- the pin 7 of the memory chip 91 is connected to the pin 7 of the interface 81.
- the pin 8 of the memory chip 91 is connected to the pin 8 of the interface 81.
- the pin 1 of the memory chip 91 is also connected to the heat dissipation end A1 of the memory 200.
- the pin 2 of the memory chip 91 is also connected to the heat dissipation end A2 of the memory 200.
- the pin 3 of the memory chip 91 is also connected to the heat dissipation end A3 of the memory 200.
- the pin 4 of the memory chip 91 is also connected to the heat dissipation end A4 of the memory 200.
- the pin 5 of the memory chip 91 is also connected to the heat dissipation end A5 of the memory 200.
- the pin 6 of the memory chip 91 is also connected to the heat dissipation end A6 of the memory 200.
- the pin 7 of the memory chip 91 is also connected to the heat dissipation end A7 of the memory 200.
- the pin 8 of the memory chip 91 is also connected to the heat dissipation end A8 of the memory 200.
- the heat dissipating ends A1 - A8 are disposed on the first side of the first isolation trench 51 .
- the first heat dissipation layer 110 is disposed on a second side of the first isolation trench 51 .
- the distance from the heat dissipation end A1-A8 to the first isolation groove 51 is not greater than the first predetermined distance. In this embodiment, the first preset distance is 20 mils.
- the pin wiring of the memory chip 91 is located at different signal layers of the multilayer circuit board.
- At least one of the pins 1-8 of the memory chip 91 is correspondingly connected to the heat dissipation ends A1 - A8.
- the pin 1 and the pin 2 of the memory chip 91 are data pins, and the pin 1 of the memory chip 91 is connected to the heat dissipation end A1, and the pin of the memory chip 91 2 is connected to the heat dissipation end A2. Pins 4-8 of the memory chip 91 are not connected to the heat sink end due to less heat generation.
- the memory 200 further includes a plurality of memory chips and a plurality of heat dissipation ends.
- the pins of the plurality of memory chips are correspondingly connected to the plurality of heat dissipation ends.
- the memory 200 further includes a plurality of sets of inner heat dissipation ends located within the inner layer of the multilayer circuit board.
- each inner layer trace is correspondingly connected to the plurality of inner heat dissipation ends.
- heat accumulated in the circuit board 100 can be quickly discharged to lower the temperature of the circuit board 100.
- the memory 200 further accelerates the heat discharge speed of the circuit board 100 through the heat sink 300, and the heat sink 300 can also be used for heat dissipation on the plurality of memory chips 71.
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Abstract
Disclosed are a circuit board (100) and a memory (200) using the circuit board (100). The circuit board (100) comprises a first surface (11) and a second surface (12) which are parallel and opposite. The first surface (11) and the second surface (12) are connected via a side surface (13). The circuit board (100) further comprises a first heat dissipation layer (110) arranged at the first surface (11) and a second heat dissipation layer (120) arranged at the second surface (12). The first heat dissipation layer (110) and the second heat dissipation layer (120) comprise a plurality of heat dissipation holes (21). By means of the heat dissipation layers (110, 120) and the heat dissipation holes (21), the heat from the circuit board (100) can be rapidly dissipated, so as to reduce the temperature of the circuit board (100).
Description
本发明涉及一种电路板，还涉及一种应用该电路板的存储器。The present invention relates to a circuit board, and to a memory to which the circuit board is applied.
现有的PCB内层的散热效率通常较低。以内存条为例，在内存条高频率工作时内存条PCB中大量热量聚集无法迅速排出，内存条温度会迅速上升。当内存条温度上升到临界值时，内存条将无法继续维持高频率工作状态。The heat dissipation efficiency of the existing PCB inner layer is usually low. Taking a memory stick as an example, when a memory bar operates at a high frequency, a large amount of heat accumulation in the memory strip PCB cannot be quickly discharged, and the temperature of the memory stick rises rapidly. When the memory module temperature rises to a critical value, the memory module will not be able to continue to maintain high frequency operation.
鉴于此，有必要提供一种可提供迅速散热的电路板及应用该电路板的存储器。In view of this, it is necessary to provide a circuit board that can provide rapid heat dissipation and a memory to which the circuit board is applied.
一种电路板，包括平行相对的第一表面及第二表面，所述第一表面及第二表面通过侧表面连接，所述电路板还包括设于第一表面的第一散热层及设于第二表面的第二散热层，所述第一散热层及第二散热层包括若干散热孔。A circuit board comprising parallel first and second surfaces, wherein the first surface and the second surface are connected by a side surface, the circuit board further comprising a first heat dissipation layer disposed on the first surface and disposed on the first surface a second heat dissipation layer of the second surface, the first heat dissipation layer and the second heat dissipation layer including a plurality of heat dissipation holes.
优选地，所述第一表面包括第一散热区及第一元器件区，所述第一散热层设于所述第一散热区。Preferably, the first surface includes a first heat dissipation region and a first component region, and the first heat dissipation layer is disposed in the first heat dissipation region.
优选地，所述第一散热区及第一元器件区之间设有第一隔离槽。Preferably, a first isolation trench is disposed between the first heat dissipation region and the first component region.
优选地，所述第二表面包括第二散热区及第二元器件区，所述第二散热层设于所述第二散热区。Preferably, the second surface includes a second heat dissipation region and a second component region, and the second heat dissipation layer is disposed in the second heat dissipation region.
优选地，所述第二散热区及第二元器件区之间设有第二隔离槽。Preferably, a second isolation trench is disposed between the second heat dissipation region and the second component region.
一种存储器，包括一电路板及若干芯片，所述电路板包括平行相对的第一表面及第二表面，所述第一表面及第二表面通过侧表面连接，所述电路板还包括设于第一表面的第一散热层及设于第二表面的第二散热层，所述第一散热层及第二散热层包括若干散热孔。A memory comprising a circuit board and a plurality of chips, the circuit board comprising parallel first and second surfaces, the first surface and the second surface being connected by a side surface, the circuit board further comprising a first heat dissipation layer on the first surface and a second heat dissipation layer disposed on the second surface, the first heat dissipation layer and the second heat dissipation layer including a plurality of heat dissipation holes.
优选地，所述存储器包括一接口，所述接口位于所述存储器的第一端。Preferably, the memory includes an interface located at a first end of the memory.
优选地，所述存储器包括一散热器，所述散热器紧贴连接于所述若干芯片、所述第一散热层及所述第二散热层。Preferably, the memory comprises a heat sink, and the heat sink is closely connected to the plurality of chips, the first heat dissipation layer and the second heat dissipation layer.
优选地，所述散热器用于可拆卸地套接于所述存储器的第二端。Preferably, the heat sink is for detachably socketed to the second end of the memory.
优选地，所述存储器为一内存条。Preferably, the memory is a memory module.
通过所述散热层及散热孔，电路板中的热量可以迅速排出以降低电路板温度。Through the heat dissipation layer and the heat dissipation holes, heat in the circuit board can be quickly discharged to lower the temperature of the circuit board.
图1为本发明电路板的较佳实施方式的示意图。1 is a schematic view of a preferred embodiment of a circuit board of the present invention.
图2为图1中所述电路板的较佳实施方式的剖视图。2 is a cross-sectional view of a preferred embodiment of the circuit board of FIG. 1.
图3为本发明存储器的较佳实施方式的示意图。3 is a schematic diagram of a preferred embodiment of a memory of the present invention.
图4为本发明存储器的较佳实施方式的另一示意图。4 is another schematic diagram of a preferred embodiment of a memory of the present invention.
图5为本发明存储器的另一较佳实施方式的局部示意图。FIG. 5 is a partial schematic view of another preferred embodiment of the memory of the present invention.
|
电路板 |
100100 |
|
第一表面 |
1111 |
|
第二表面 |
1212 |
|
侧表面 |
1313 |
|
第一散热层First |
110110 |
|
第二散热层Second |
120120 |
| 散热孔Vents | 21twenty one |
|
第一散热区First |
3131 |
| 第二散热区Second heat dissipation zone | 3232 |
|
第一元器件区 |
4141 |
| 第二元器件区Second component area | 4242 |
|
第一隔离槽 |
5151 |
|
第二隔离槽 |
5252 |
| 第一层level one | 6161 |
|
第二层 |
6262 |
|
中间层 |
6060 |
|
存储器 |
200200 |
|
散热器 |
300300 |
|
存储芯片 |
71、9171, 91 |
|
接口 |
8181 |
如下具体实施方式将结合上述附图进一步说明本发明。The invention will be further illustrated by the following detailed description in conjunction with the accompanying drawings.
请参考图1及图2，本发明电路板100的较佳实施方式中，所述电路板100包括平行相对的第一表面11及第二表面12，所述第一表面11及第二表面12通过侧表面13连接。所述电路板100还包括设于第一表面11的第一散热层110及设于第二表面12的第二散热层120。所述第一散热层110包括若干散热孔21。所述第二散热层120包括若干散热孔。Referring to FIG. 1 and FIG. 2, in a preferred embodiment of the circuit board 100 of the present invention, the circuit board 100 includes a first surface 11 and a second surface 12 that are opposite to each other, and the first surface 11 and the second surface 12 are 12 Connected by side surfaces 13. The circuit board 100 further includes a first heat dissipation layer 110 disposed on the first surface 11 and a second heat dissipation layer 120 disposed on the second surface 12 . The first heat dissipation layer 110 includes a plurality of heat dissipation holes 21 . The second heat dissipation layer 120 includes a plurality of heat dissipation holes.
本实施方式中，所述电路板100的第一表面11包括第一散热区31及第一元器件区41。所述第一散热区31及第一元器件区41之间设有第一隔离槽51。所述第一散热层110设于所述第一散热区31。In this embodiment, the first surface 11 of the circuit board 100 includes a first heat dissipation region 31 and a first component region 41. A first isolation trench 51 is disposed between the first heat dissipation region 31 and the first component region 41. The first heat dissipation layer 110 is disposed in the first heat dissipation region 31.
本实施方式中，所述电路板100的第二表面12包括第二散热区32（未示出）及第二元器件区42（未示出）。所述第二散热区32及第二元器件区42之间设有第二隔离槽52。所述第二散热层120设于所述第二散热区32。由于在本实施方式中所述第二表面12与所述第一表面11呈对称设计，所述第二散热区32、第二元器件区42及第二隔离槽52未在图中示出。In this embodiment, the second surface 12 of the circuit board 100 includes a second heat dissipation region 32 (not shown) and a second component region 42 (not shown). A second isolation trench 52 is disposed between the second heat dissipation region 32 and the second component region 42. The second heat dissipation layer 120 is disposed in the second heat dissipation region 32. Since the second surface 12 and the first surface 11 are symmetrically designed in the embodiment, the second heat dissipation region 32, the second component region 42, and the second isolation trench 52 are not shown in the drawing.
在其他实施方式中，所述第一散热层110可以呈不规则形状设于所述电路板100的所述第一表面11上，例如第一元器件区41各焊盘周围，而不需要局限于第一散热区31。类似地，所述第二散热层120可以呈不规则形状设于所述电路板100的所述第二表面12上，例如第二元器件区42的各焊盘周围，而不需要局限于第二散热区32。In other embodiments, the first heat dissipation layer 110 may be disposed on the first surface 11 of the circuit board 100 in an irregular shape, for example, around the pads of the first component region 41, without limitation. In the first heat dissipation zone 31. Similarly, the second heat dissipation layer 120 may be disposed on the second surface 12 of the circuit board 100 in an irregular shape, for example, around each pad of the second component region 42 without being limited to the first Two heat dissipation zones 32.
在其他实施方式中，所述第一散热层110与所述第二散热层120可以为非对称设计。In other embodiments, the first heat dissipation layer 110 and the second heat dissipation layer 120 may be asymmetrically designed.
本实施方式中，所述第一隔离槽51及第二隔离槽52用于防止散热层与焊盘接触。In the embodiment, the first isolation trench 51 and the second isolation trench 52 are used to prevent the heat dissipation layer from contacting the pad.
图2为本发明电路板100的截面示意图。本实施方式中，所述电路板100包括第一层61、第二层62及中间层60。2 is a schematic cross-sectional view of a circuit board 100 of the present invention. In the embodiment, the circuit board 100 includes a first layer 61, a second layer 62, and an intermediate layer 60.
本实施方式中，所述第一层61为铜箔层，所述第二层62为基材层，所述中间层60为内膜层。所述中间层60可由树脂、环氧玻璃纤维等材料制成。In this embodiment, the first layer 61 is a copper foil layer, the second layer 62 is a base material layer, and the intermediate layer 60 is an inner film layer. The intermediate layer 60 may be made of a material such as resin, epoxy glass fiber or the like.
本实施方式中，所述若干散热孔21均为通孔。所述若干散热孔21依次贯穿所述第一散热层110、所述第一层61、所述中间层60、所述第二层62及所述第二散热层120。In this embodiment, the plurality of heat dissipation holes 21 are all through holes. The plurality of heat dissipation holes 21 sequentially penetrate the first heat dissipation layer 110 , the first layer 61 , the intermediate layer 60 , the second layer 62 , and the second heat dissipation layer 120 .
在其他实施方式中，所述第一散热层110为铜箔，当对电路板铜箔蚀刻时，所述第一散热层110所处区域铜箔未经蚀刻形成所述第一散热层110，所述第一散热层110与所述第一元器件区41之走线通过所述第一隔离槽51进行分割，以避免信号干扰。类似地，所述第二散热层120可以由铜箔层未经蚀刻形成，所述第二散热层120与所述第二元器件区42之走线通过所述第二隔离槽52进行分割，以避免信号干扰。In other embodiments, the first heat dissipation layer 110 is a copper foil. When the copper foil of the circuit board is etched, the copper foil in the region where the first heat dissipation layer 110 is located is not etched to form the first heat dissipation layer 110. The trace of the first heat dissipation layer 110 and the first component region 41 is divided by the first isolation trench 51 to avoid signal interference. Similarly, the second heat dissipation layer 120 may be formed by a copper foil layer not being etched, and the traces of the second heat dissipation layer 120 and the second component region 42 may be divided by the second isolation trench 52. To avoid signal interference.
相应地，若所述第一散热层110及第二散热层120由铜箔层未经蚀刻形成，所述第一散热层110及第二散热层120可以应用于多层电路板的内层。Correspondingly, if the first heat dissipation layer 110 and the second heat dissipation layer 120 are formed by a copper foil layer without etching, the first heat dissipation layer 110 and the second heat dissipation layer 120 may be applied to an inner layer of the multilayer circuit board.
本实施方式中，所述第一元器件区41之走线均有一端位于所述第一隔离槽51附近。类似地，所述第二元器件区42之走线均有一端位于所述第二隔离槽52附近。In this embodiment, one end of the trace of the first component region 41 is located near the first isolation trench 51. Similarly, one end of the trace of the second component region 42 is located near the second isolation trench 52.
在其他实施方式中，所述若干散热孔21可以灌有特定金属以协助散热，所述特定金属包括但不限于铜。In other embodiments, the plurality of louvers 21 may be filled with a specific metal to assist in heat dissipation, including but not limited to copper.
在其他实施方式中，所述若干散热孔21可以部分为通孔，部分为开孔至特定位置。所述若干散热孔21还可全部开孔至特定位置，如全部开孔至中间层60而不贯穿所述中间层60。In other embodiments, the plurality of heat dissipation holes 21 may be partially through holes and partially open to specific positions. The plurality of heat dissipation holes 21 may also be completely opened to a specific position, such as all of the openings to the intermediate layer 60 without penetrating the intermediate layer 60.
请参考图3及图4，本发明存储器200包括一多层电路板及若干存储芯片71。所述多层电路板的一种较佳实施方式中所述多层电路板包括所述电路板100。所述存储器200还包括一接口81及一散热器300。所述接口81位于所述存储器200的第一端。Referring to FIG. 3 and FIG. 4, the memory 200 of the present invention includes a multi-layer circuit board and a plurality of memory chips 71. In a preferred embodiment of the multilayer circuit board, the multilayer circuit board includes the circuit board 100. The memory 200 further includes an interface 81 and a heat sink 300. The interface 81 is located at a first end of the memory 200.
本实施方式中，所述散热器300可拆卸地套接于所述存储器200的第二端。当所述散热器300套接于所述存储器200的第二端时，所述散热器300紧贴连接于所述若干存储芯片71、所述第一散热层110及所述第二散热层120。所述散热器300用于针对第一散热层110、所述第二散热层120及所述若干存储芯片71进行散热。In this embodiment, the heat sink 300 is detachably sleeved on the second end of the memory 200. When the heat sink 300 is sleeved on the second end of the memory 200, the heat sink 300 is closely connected to the plurality of memory chips 71, the first heat dissipation layer 110, and the second heat dissipation layer 120. . The heat sink 300 is configured to dissipate heat for the first heat dissipation layer 110, the second heat dissipation layer 120, and the plurality of memory chips 71.
本实施方式中，所述存储器200的第一端与所述存储器200的第二端平行。In this embodiment, the first end of the memory 200 is parallel to the second end of the memory 200.
在其他实施方式中，所述散热器300还可以套接于所述存储器200的第三端。所述存储器200的第三端与所述存储器200的第一端垂直。In other embodiments, the heat sink 300 can also be sleeved at the third end of the memory 200. The third end of the memory 200 is perpendicular to the first end of the memory 200.
在其他实施方式中，所述散热器300还可以焊接于所述第一散热层110或第二散热层120上。In other embodiments, the heat sink 300 may also be soldered to the first heat dissipation layer 110 or the second heat dissipation layer 120.
所述散热器300可由金属材料或其他拥有良好导热性材料制成。本实施方式中，所述散热器300的制作材料为铝。The heat sink 300 may be made of a metal material or other material having a good thermal conductivity. In the present embodiment, the heat sink 300 is made of aluminum.
本实施方式中，所述存储器200为一内存条。所述接口81为所述电路板100的第一端延伸出的金手指。所述接口81用于连接一内存插槽。In this embodiment, the memory 200 is a memory module. The interface 81 is a gold finger extending from the first end of the circuit board 100. The interface 81 is used to connect to a memory slot.
请参考图5，本发明所述存储器200的另一较佳实施方式中，所述存储器200包括一多层电路板（未示出）及至少一存储芯片91。所述多层电路板的的第一表面包括第一隔离槽51、接口81、第一散热层110及散热端A1-A8。所述第一隔离槽51处于所述第一散热层110及所述散热端A1-A8之间。所述存储芯片91包括引脚1-8。所述存储芯片91的引脚1连接于所述接口81的引脚1。所述存储芯片91的引脚2连接于所述接口81的引脚2。所述存储芯片91的引脚3连接于所述接口81的引脚3。所述存储芯片91的引脚4连接于所述接口81的引脚4。所述存储芯片91的引脚5连接于所述接口81的引脚5。所述存储芯片91的引脚6连接于所述接口81的引脚6。所述存储芯片91的引脚7连接于所述接口81的引脚7。所述存储芯片91的引脚8连接于所述接口81的引脚8。Referring to FIG. 5, in another preferred embodiment of the memory 200 of the present invention, the memory 200 includes a multi-layer circuit board (not shown) and at least one memory chip 91. The first surface of the multilayer circuit board includes a first isolation trench 51, an interface 81, a first heat dissipation layer 110, and heat dissipation ends A1-A8. The first isolation trench 51 is between the first heat dissipation layer 110 and the heat dissipation ends A1 - A8. The memory chip 91 includes pins 1-8. The pin 1 of the memory chip 91 is connected to the pin 1 of the interface 81. The pin 2 of the memory chip 91 is connected to the pin 2 of the interface 81. The pin 3 of the memory chip 91 is connected to the pin 3 of the interface 81. The pin 4 of the memory chip 91 is connected to the pin 4 of the interface 81. The pin 5 of the memory chip 91 is connected to the pin 5 of the interface 81. The pin 6 of the memory chip 91 is connected to the pin 6 of the interface 81. The pin 7 of the memory chip 91 is connected to the pin 7 of the interface 81. The pin 8 of the memory chip 91 is connected to the pin 8 of the interface 81.
本实施方式中，所述存储芯片91的引脚1还连接于所述存储器200的散热端A1。所述存储芯片91的引脚2还连接于所述存储器200的散热端A2。所述存储芯片91的引脚3还连接于所述存储器200的散热端A3。所述存储芯片91的引脚4还连接于所述存储器200的散热端A4。所述存储芯片91的引脚5还连接于所述存储器200的散热端A5。所述存储芯片91的引脚6还连接于所述存储器200的散热端A6。所述存储芯片91的引脚7还连接于所述存储器200的散热端A7。所述存储芯片91的引脚8还连接于所述存储器200的散热端A8。In the embodiment, the pin 1 of the memory chip 91 is also connected to the heat dissipation end A1 of the memory 200. The pin 2 of the memory chip 91 is also connected to the heat dissipation end A2 of the memory 200. The pin 3 of the memory chip 91 is also connected to the heat dissipation end A3 of the memory 200. The pin 4 of the memory chip 91 is also connected to the heat dissipation end A4 of the memory 200. The pin 5 of the memory chip 91 is also connected to the heat dissipation end A5 of the memory 200. The pin 6 of the memory chip 91 is also connected to the heat dissipation end A6 of the memory 200. The pin 7 of the memory chip 91 is also connected to the heat dissipation end A7 of the memory 200. The pin 8 of the memory chip 91 is also connected to the heat dissipation end A8 of the memory 200.
所述散热端A1-A8均紧贴所述第一隔离槽51设置于所述第一隔离槽51的第一侧。所述第一散热层110设置于所述第一隔离槽51的第二侧。所述散热端A1-A8到所述第一隔离槽51的距离不大于第一预设距离。本实施方式中，所述第一预设距离为20密尔。The heat dissipating ends A1 - A8 are disposed on the first side of the first isolation trench 51 . The first heat dissipation layer 110 is disposed on a second side of the first isolation trench 51 . The distance from the heat dissipation end A1-A8 to the first isolation groove 51 is not greater than the first predetermined distance. In this embodiment, the first preset distance is 20 mils.
本实施方式中，所述存储芯片91的引脚布线位于所述多层电路板不同信号层。In this embodiment, the pin wiring of the memory chip 91 is located at different signal layers of the multilayer circuit board.
在其他实施方式中，所述存储芯片91的引脚1-8中至少一引脚对应连接于所述散热端A1-A8。In other embodiments, at least one of the pins 1-8 of the memory chip 91 is correspondingly connected to the heat dissipation ends A1 - A8.
在另一实施方式中，所述存储芯片91的引脚1及引脚2为数据引脚，所述存储芯片91的引脚1对应连接所述散热端A1，所述存储芯片91的引脚2对应连接所述散热端A2。所述存储芯片91的引脚4-8由于热量产生较少而未被连接至散热端。In another embodiment, the pin 1 and the pin 2 of the memory chip 91 are data pins, and the pin 1 of the memory chip 91 is connected to the heat dissipation end A1, and the pin of the memory chip 91 2 is connected to the heat dissipation end A2. Pins 4-8 of the memory chip 91 are not connected to the heat sink end due to less heat generation.
本实施方式中，所述存储器200还包括若干存储芯片及若干散热端。所述若干存储芯片的引脚对应连接于所述若干散热端。In this embodiment, the memory 200 further includes a plurality of memory chips and a plurality of heat dissipation ends. The pins of the plurality of memory chips are correspondingly connected to the plurality of heat dissipation ends.
在其他实施方式中，所述存储器200还包括位于所述多层电路板内层的若干组内层散热端。在内层走线中，每一内层走线均对应连接至所述若干组内层散热端。In other embodiments, the memory 200 further includes a plurality of sets of inner heat dissipation ends located within the inner layer of the multilayer circuit board. In the inner layer traces, each inner layer trace is correspondingly connected to the plurality of inner heat dissipation ends.
通过所述第一散热层110及第二散热层120及所述若干散热孔21，所述电路板100中积累的热量可以迅速排出以降低所述电路板100的温度。类似地，所述存储器200进一步通过所述散热器300加快所述电路板100的热量排出速度，所述散热器300还可以用于所述若干存储芯片71上进行散热。Through the first heat dissipation layer 110 and the second heat dissipation layer 120 and the plurality of heat dissipation holes 21, heat accumulated in the circuit board 100 can be quickly discharged to lower the temperature of the circuit board 100. Similarly, the memory 200 further accelerates the heat discharge speed of the circuit board 100 through the heat sink 300, and the heat sink 300 can also be used for heat dissipation on the plurality of memory chips 71.
最后应说明的是，以上实施例仅用以说明本发明的技术方案而非限制，尽管参照较佳实施例对本发明进行了详细说明，本领域的普通技术人员应当理解，可以对本发明的技术方案进行修改或等同替换，而不脱离本发明技术方案的精神和范围。It should be noted that the above embodiments are only for explaining the technical solutions of the present invention and are not intended to be limiting, and the present invention will be described in detail with reference to the preferred embodiments. Modifications or equivalents are made without departing from the spirit and scope of the invention.
Claims (10)
- 一种电路板，包括平行相对的第一表面及第二表面，所述第一表面及第二表面通过侧表面连接，其特征在于：A circuit board comprising parallel first and second surfaces, wherein the first surface and the second surface are connected by a side surface, wherein:所述电路板还包括设于第一表面的第一散热层及设于第二表面的第二散热层，所述第一散热层及第二散热层包括若干散热孔。The circuit board further includes a first heat dissipation layer disposed on the first surface and a second heat dissipation layer disposed on the second surface, the first heat dissipation layer and the second heat dissipation layer including a plurality of heat dissipation holes.
- 如权利要求1所述的电路板，其特征在于：所述第一表面包括第一散热区及第一元器件区，所述第一散热层设于所述第一散热区。The circuit board according to claim 1, wherein the first surface comprises a first heat dissipation region and a first component region, and the first heat dissipation layer is disposed in the first heat dissipation region.
- 如权利要求2所述的电路板，其特征在于：所述第一散热区及第一元器件区之间设有第一隔离槽。The circuit board according to claim 2, wherein a first isolation trench is disposed between the first heat dissipation region and the first component region.
- 如权利要求1所述的电路板，其特征在于：所述第一散热层为铜箔，当所述电路板进行蚀刻时，所述第一散热层所处区域铜箔未经蚀刻形成所述第一散热层。The circuit board according to claim 1, wherein the first heat dissipation layer is a copper foil, and when the circuit board is etched, the copper foil in the region where the first heat dissipation layer is located is not etched to form the The first heat dissipation layer.
- 如权利要求1所述的电路板，其特征在于：所述若干散热孔包括至少一通孔。The circuit board according to claim 1, wherein said plurality of heat dissipation holes comprise at least one through hole.
- 一种存储器，包括一电路板及若干芯片，所述电路板包括平行相对的第一表面及第二表面，所述第一表面及第二表面通过侧表面连接，其特征在于：A memory comprising a circuit board and a plurality of chips, the circuit board comprising parallel first and second surfaces, wherein the first surface and the second surface are connected by a side surface, wherein:所述电路板还包括设于第一表面的第一散热层及设于第二表面的第二散热层，所述第一散热层及第二散热层包括若干散热孔。The circuit board further includes a first heat dissipation layer disposed on the first surface and a second heat dissipation layer disposed on the second surface, the first heat dissipation layer and the second heat dissipation layer including a plurality of heat dissipation holes.
- 如权利要求6所述的存储器，其特征在于：所述存储器包括若干散热端，所述若干芯片的引脚对应连接所述若干散热端。The memory of claim 6, wherein the memory comprises a plurality of heat dissipation ends, and the pins of the plurality of chips are correspondingly connected to the plurality of heat dissipation ends.
- 如权利要求6所述的存储器，其特征在于：所述第一表面包括第一隔离槽，所述第一散热层设置于所述第一隔离槽的第一侧，所述若干散热端设置于所述第一隔离槽的第二侧，所述若干散热端与所述第一隔离槽的距离不大于第一预设距离。The memory according to claim 6, wherein the first surface comprises a first isolation trench, the first heat dissipation layer is disposed on a first side of the first isolation trench, and the plurality of heat dissipation ends are disposed on a second side of the first isolation trench, the distance between the plurality of heat dissipation ends and the first isolation trench is not greater than a first predetermined distance.
- 如权利要求6所述的存储器，其特征在于：所述存储器包括一散热器，所述散热器紧贴连接于所述若干芯片、所述第一散热层及所述第二散热层。A memory according to claim 6, wherein said memory comprises a heat sink, said heat sink being closely attached to said plurality of chips, said first heat dissipation layer and said second heat dissipation layer.
- 如权利要求8所述的存储器，其特征在于：所述存储器包括一散热器，所述散热器用于套接于所述存储器的第二端。The memory of claim 8 wherein said memory includes a heat sink for socketing to the second end of said memory.
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| PCT/CN2016/072583 WO2017128212A1 (en) | 2016-01-28 | 2016-01-28 | Circuit board and memory using same |
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