WO2017009964A1 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
- Publication number
- WO2017009964A1 WO2017009964A1 PCT/JP2015/070234 JP2015070234W WO2017009964A1 WO 2017009964 A1 WO2017009964 A1 WO 2017009964A1 JP 2015070234 W JP2015070234 W JP 2015070234W WO 2017009964 A1 WO2017009964 A1 WO 2017009964A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- film
- semiconductor device
- opening
- sio
- insulating film
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims description 53
- 238000004519 manufacturing process Methods 0.000 title claims description 43
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims abstract description 68
- 239000000758 substrate Substances 0.000 claims abstract description 51
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 41
- 229910052814 silicon oxide Inorganic materials 0.000 claims abstract description 39
- 239000000463 material Substances 0.000 claims abstract description 30
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 22
- 239000010703 silicon Substances 0.000 claims abstract description 22
- 238000001039 wet etching Methods 0.000 claims abstract description 15
- 229910052751 metal Inorganic materials 0.000 claims description 49
- 239000002184 metal Substances 0.000 claims description 49
- 238000000034 method Methods 0.000 claims description 20
- 238000004140 cleaning Methods 0.000 claims 1
- 239000012528 membrane Substances 0.000 claims 1
- 238000005530 etching Methods 0.000 abstract description 7
- 229910052681 coesite Inorganic materials 0.000 abstract 1
- 229910052906 cristobalite Inorganic materials 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- 229910052682 stishovite Inorganic materials 0.000 abstract 1
- 229910052905 tridymite Inorganic materials 0.000 abstract 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 66
- 230000001681 protective effect Effects 0.000 description 59
- 230000002093 peripheral effect Effects 0.000 description 27
- 230000000052 comparative effect Effects 0.000 description 6
- 239000012535 impurity Substances 0.000 description 5
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 5
- 238000009792 diffusion process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- 229910018125 Al-Si Inorganic materials 0.000 description 1
- 229910018520 Al—Si Inorganic materials 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000002547 anomalous effect Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 238000000926 separation method Methods 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02041—Cleaning
- H01L21/02057—Cleaning during device manufacture
- H01L21/0206—Cleaning during device manufacture during, before or after processing of insulating layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/868—PIN diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30604—Chemical etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3157—Partial encapsulation or coating
- H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
Definitions
- the present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a semiconductor device using wet etching.
- a Si substrate In a method of manufacturing a semiconductor device, it may be necessary to clean the surface of a Si (silicon) substrate. Specifically, it may be necessary to remove the natural oxide film or foreign matter from the surface of the Si substrate. For example, foreign matter on the Si surface can cause anomalous diffusion at the time of impurity addition.
- Patent Document 1 a SiO 2 film (silicon oxide film) is formed on a Si substrate. Then, an SiO x film (x> 2) is formed on the silicon oxide film. Then, an opening is formed in the laminated structure of the silicon oxide film and the SiO x film. A native oxide film is formed on the Si substrate at the opening along with the step of forming the opening. This native oxide film is removed using hydrofluoric acid. This results in a hydrogen-terminated clean Si surface at the opening.
- the surface of the silicon oxide film is protected from etching by hydrofluoric acid by being covered with the SiO x film (x> 2).
- the SiO x film can be separated from the silicon oxide film by the entry of hydrofluoric acid along the interface between the silicon oxide film and the SiO x film.
- a silicon oxide film is provided on a Si substrate.
- a structure made of a material that is less likely to be etched by hydrofluoric acid than the silicon oxide film is provided.
- the structure is formed by the hydrofluoric acid penetrating along the interface between the silicon oxide film and the structure. Can peel from the silicon oxide film. This peeling leads to a reduction in yield if it occurs during the manufacture of semiconductor devices, and a reduction in product life if it occurs after manufacture.
- the present invention has been made to solve the problems as described above, and an object thereof is to suppress peeling of a structure provided on a silicon oxide film in etching using hydrofluoric acid. It is an object of the present invention to provide a method of manufacturing a semiconductor device that can be performed.
- the method of manufacturing a semiconductor device of the present invention has the following steps.
- a silicon oxide film having at least one opening is formed on a silicon substrate.
- a structure is provided which is provided on the silicon oxide film, reaches the silicon substrate at the opening, and is made of a material less susceptible to etching by hydrofluoric acid as compared to the silicon oxide film.
- Wet etching using hydrofluoric acid is performed on a silicon substrate provided with a silicon oxide film and a structure. In the wet etching process, the interface between the silicon oxide film and the structure is exposed to hydrofluoric acid.
- the structure provided on the silicon oxide film reaches the silicon substrate at the opening of the silicon oxide film.
- corrugation by an opening part is provided in the surface where a structure is provided.
- a structure made of a material less susceptible to etching by hydrofluoric acid as compared to a silicon oxide film extends into the opening of the silicon oxide film.
- FIG. 1 is a partial cross sectional view schematically showing a configuration of a semiconductor device in a first embodiment of the present invention.
- FIG. 5 is a flow diagram schematically showing a configuration of a method of manufacturing a semiconductor device in the first embodiment of the present invention.
- FIG. 8 is a partial cross sectional view schematically showing one step of a method of manufacturing a semiconductor device in the first embodiment of the present invention.
- FIG. 8 is a partial cross sectional view schematically showing one step of a method of manufacturing a semiconductor device in the first embodiment of the present invention.
- FIG. 16 is a partial cross sectional view schematically showing one step of a method of manufacturing a semiconductor device of a comparative example.
- FIG. 16 is a partial cross sectional view schematically showing one step of a method of manufacturing a semiconductor device of a comparative example.
- FIG. 16 is a partial cross sectional view schematically showing one step of a method of manufacturing a semiconductor device of a comparative example.
- FIG. 16 is a partial cross sectional view schematically showing a configuration of a semiconductor device in a second embodiment of the present invention.
- FIG. 16 is a partial cross sectional view schematically showing one step of a method of manufacturing a semiconductor device in a second embodiment of the present invention.
- FIG. 16 is a partial cross sectional view schematically showing one step of a method of manufacturing a semiconductor device in a second embodiment of the present invention.
- FIG. 16 is a partial cross sectional view schematically showing one step of a method of manufacturing a semiconductor device in a second embodiment of the present invention.
- FIG. 18 is a partial cross sectional view schematically showing a configuration of a semiconductor device in a third embodiment of the present invention.
- FIG. 16 is a partial cross sectional view schematically showing one step of a method of manufacturing a semiconductor device in a third embodiment of the present invention.
- FIG. 16 is a partial cross sectional view schematically showing one step of a method of manufacturing a semiconductor device in a third embodiment of the present invention.
- FIG. 18 is a partial cross sectional view schematically showing a configuration of a semiconductor device in a fourth embodiment of the present invention.
- FIG. 21 is a partial cross sectional view schematically showing a step of a method of manufacturing a semiconductor device in a fourth embodiment of the present invention.
- FIG. 16 is a partial cross sectional view schematically showing one step of a method of manufacturing a semiconductor device in a third embodiment of the present invention.
- FIG. 16 is a partial cross sectional view schematically showing one step of a method of manufacturing a semiconductor device in a third embodiment of the
- FIG. 21 is a partial cross sectional view schematically showing a step of a method of manufacturing a semiconductor device in a fourth embodiment of the present invention.
- FIG. 18 is a partial cross sectional view schematically showing a configuration of a semiconductor device in a fifth embodiment of the present invention.
- FIG. 21 is a partial cross sectional view schematically showing a step of a method of manufacturing a semiconductor device in a fifth embodiment of the present invention.
- FIG. 21 is a partial cross sectional view schematically showing a step of a method of manufacturing a semiconductor device in a fifth embodiment of the present invention.
- FIG. 21 is a partial cross sectional view schematically showing a configuration of a semiconductor device in a sixth embodiment of the present invention.
- FIG. 26 is a partial cross sectional view schematically showing a step of a method of manufacturing a semiconductor device in a sixth embodiment of the present invention.
- FIG. 26 is a partial cross sectional view schematically showing a step of a method of manufacturing a semiconductor device in a sixth embodiment of the present invention. It is a fragmentary sectional view which shows roughly the structure of the semiconductor device in Embodiment 7 of this invention.
- FIG. 21 is a partial cross sectional view schematically showing a step of a method of manufacturing a semiconductor device in a seventh embodiment of the present invention.
- FIG. 21 is a partial cross sectional view schematically showing a step of a method of manufacturing a semiconductor device in a seventh embodiment of the present invention.
- FIG. 26 is a partial cross sectional view schematically showing a step of a method of manufacturing a semiconductor device in a seventh embodiment of the present invention.
- FIG. 21 is a partial cross sectional view schematically showing a configuration of a semiconductor device in an eighth embodiment of the present invention.
- FIG. 26 is a partial cross sectional view schematically showing a step of a method of manufacturing a semiconductor device in an eighth embodiment of the present invention.
- FIG. 26 is a partial cross sectional view schematically showing a step of a method of manufacturing a semiconductor device in an eighth embodiment of the present invention.
- FIG. 35 is a partial cross sectional view schematically showing a configuration of a semiconductor device in a ninth embodiment of the present invention.
- FIG. 21 is a partial cross sectional view schematically showing a step of a method of manufacturing a semiconductor device in a ninth embodiment of the present invention.
- FIG. 21 is a partial cross sectional view schematically showing a step of a method of manufacturing a semiconductor device in a ninth embodiment of the present invention.
- FIG. 1 is a partial cross-sectional view schematically showing a configuration of a diode 91 (semiconductor device) in the present embodiment.
- the diode 91 is a pin diode as a power semiconductor device.
- the diode 91 includes a Si substrate 10 (silicon substrate), an anode layer 11, a cathode layer 12, an anode electrode film 21, a cathode electrode film 22, an SiO 2 film 31 (silicon oxide film), and a protective structure 41. And (structure).
- the Si substrate 10 is a single crystal substrate made of Si.
- the anode layer 11 is a p-type impurity diffusion layer provided on the central portion (left side in the drawing) of the upper surface (one surface) of the Si substrate 10.
- the cathode layer 12 is an n-type impurity diffusion layer provided on the lower surface (the other surface) of the Si substrate 10.
- the anode electrode film 21 is provided on the anode layer 11.
- the end of the anode electrode film 21 is separated from the end (the right end in the figure) of the Si substrate 10.
- the cathode electrode film 22 is provided on the cathode layer 12.
- the material of the anode electrode film 21 and the cathode electrode film 22 is preferably that which can obtain good ohmic contact with Si, and is, for example, Al (aluminum) or an aluminum alloy such as Al-Si.
- a SiO 2 film 31 is provided on the outer peripheral part around the central part where the anode layer 11 is provided among the upper surface of the Si substrate 10.
- the SiO 2 film 31 has an opening OP.
- the opening OP may extend linearly or may be configured by a local hole.
- the protective structure 41 is provided on the SiO 2 film 31 and extends onto the end of the anode electrode film 21. Thus, the protective structure 41 partially covers the anode electrode film 21, and specifically covers the outer peripheral portion of the anode electrode film 21. The protective structure 41 reaches the Si substrate 10 at the opening OP. Of the protective structure 41, the portion in contact with the anode electrode film 21 is preferably made of an insulator. The exposed surface (upper surface in the drawing) of the protective structure 41 is preferably made of an insulator. In the present embodiment, the entire protective structure 41 is formed of one insulating film 41i.
- FIG. 2 is a flow chart schematically showing a configuration of a method of manufacturing the diode 91. As shown in FIG.
- FIGS. 3 and 4 is a partial cross-sectional view schematically showing one step of a method of manufacturing diode 91.
- anode layer 11 is formed on the upper surface of Si substrate 10 (FIG. 2: step S10).
- An SiO 2 film 31 is formed on the Si substrate 10 (FIG. 2: step S20).
- a thermal oxidation method or a deposition method can be used to form the SiO 2 film 31.
- thermal oxidation natural oxidation may be used.
- an opening OP is formed in the SiO 2 film 31 (FIG. 2: step S30).
- An anode electrode film 21 is formed on the anode layer 11 (FIG. 2: step S40).
- An insulating film 41i as the protective structure 41 is formed (FIG. 2: step S50).
- the insulating film 41i as the protective structure 41 is provided on the SiO 2 film 31 and reaches the Si substrate 10 at the opening OP. The interface between the SiO 2 film 31 and the protective structure 41 is exposed at a point PA located at the end of the protective structure 41.
- the insulating film 41i as the protective structure 41 is made of a material that is less susceptible to etching by hydrofluoric acid than the SiO 2 film 31, and is made of, for example, silicon nitride or glass.
- step S60 wet etching using hydrofluoric acid is performed on Si substrate 10 provided with SiO 2 film 31 and protective structure 41 (FIG. 2: step S60).
- the lower surface of the Si substrate 10 is cleaned. Specifically, the natural oxide film 50 on the lower surface of the Si substrate 10 is removed by the etchant 60 containing hydrofluoric acid.
- the SiO 2 film 31 is also etched to some extent by being exposed to hydrofluoric acid (in the figure, the portion to be etched is schematically shown by a two-dot chain line portion 31E).
- the interface between the SiO 2 film 31 and the insulating film 41i is exposed to hydrofluoric acid at point PA, whereby the SiO 2 film 31 is etched at point PA.
- a gap of about several angstroms is generated between the SiO 2 film 31 and the protective structure 41.
- hydrofluoric acid infiltrates from the point PA along the interface.
- the entry of hydrofluoric acid can stop at a point PB located at the edge of the opening OP, as shown in FIG.
- a point PB located at the edge of the opening OP
- further intrusion occurs at point PC located at the bottom of opening OP. Since it is inhibited, it is difficult to cause the entry to the point PD located on the opposite side of the opening OP. This is because both the protective structure 41 and the Si substrate 10 forming the interface at the bottom of the opening OP are made of a material that is not easily etched by hydrofluoric acid.
- the cathode layer 12 is formed on the lower surface of the Si substrate by the addition of the impurity (FIG. 2: step S70).
- the cathode electrode film 22 is formed on the cathode layer 12 (FIG. 2: step S80).
- the diode 91 is obtained.
- the SiO 2 film 30 of the comparative example does not have the opening OP, unlike the SiO 2 film 31 (FIG. 3). Therefore, unlike the protective structure 41 (FIG. 3), the protective structure 40 is formed on the flat surface of the SiO 2 film 30.
- the interface between SiO 2 film 30 and protective structure 40 is exposed to hydrofluoric acid at point PA.
- the SiO 2 film 30 is etched to form a gap of about several angstroms between the SiO 2 film 30 and the protective structure 40. As a result, hydrofluoric acid infiltrates from the point PA along the interface.
- FIG. 5 the SiO 2 film 30 of the comparative example does not have the opening OP, unlike the SiO 2 film 31 (FIG. 3). Therefore, unlike the protective structure 41 (FIG. 3), the protective structure 40 is formed on the flat surface of the SiO 2 film 30.
- the interface between SiO 2 film 30 and protective structure 40 is exposed to hydrofluoric acid at point PA.
- the SiO 2 film 30 is etched to
- FIG. 6 shows the state in which hydrofluoric acid invades to the point PZ.
- no particular structure is provided to prevent the progress of the intrusion, and therefore hydrofluoric acid is likely to penetrate deep from point PA.
- hydrofluoric acid results penetrates deep into the interface between the protective structure 40 and the SiO 2 film 30, the bonding area between the SiO 2 film 30 and the protective structure 40 is reduced. Thereby, peeling of the protective structure 40 from the SiO 2 film 30 (see the arrow in the figure) is likely to occur.
- the first, protective structure 41 provided on the SiO 2 film 31 has reached the Si substrate 10 in the opening OP of the SiO 2 film 31.
- corrugation by the opening part OP is provided in the surface in which the protective structure 41 is provided.
- peeling of the protective structure 41 from the SiO 2 film 31 is suppressed.
- the protective structure 41 made of hard material is etched in hydrofluoric acid than the SiO 2 film 31 extends into the opening OP of the SiO 2 film 31.
- the progress of the hydrofluoric acid entering from the interface between the SiO 2 film 31 and the protective structure 41 is inhibited by the protective structure 41 in the opening OP. That is, the progress of separation of the interface between the SiO 2 film 31 and the protective structure 41 is inhibited.
- peeling of the protective structure 41 from the SiO 2 film 31 is further suppressed.
- FIG. 8 is a partial cross sectional view schematically showing a configuration of a diode 92 in the present embodiment.
- Diode 92, SiO 2 film 31 and the protective structure 41 instead respectively (Fig. 1 Embodiment 1), and a SiO 2 film 32 (silicon oxide film) and a protection structure 42 (structure) .
- the protective structure 42 is constituted by one insulating film 42i.
- the SiO 2 film 32 includes more than one opening OP.
- the insulating film 42i as the protective structure 42 is provided on the SiO 2 film 32, and reaches the Si substrate 10 in each of the openings OP. Referring to each of FIGS. 9 and 10, diode 92 can be manufactured by substantially the same process as that of FIGS.
- 2-dot chain line portion of the SiO 2 film 32 32E (FIG. 10), similar to the two-dot chain line portion 31E of the SiO 2 film 31 (FIG. 4), shows a portion to be etched schematically.
- the SiO 2 film 32 is provided with more than one opening OP. Thereby, the effect of suppressing the peeling of the protective structure 42 from the SiO 2 film 32 is enhanced.
- FIG. 11 is a partial cross sectional view schematically showing a configuration of a diode 93 in the present embodiment.
- the diode 93 has a protective structure 43 (structure) instead of the protective structure 41 (FIG. 1: Embodiment 1).
- the protective structure 43 has an insulating film 43i and a metal film 43m.
- the metal film 43 m reaches the Si substrate 10 at the opening OP of the SiO 2 film 31.
- the metal film 43m preferably penetrates the opening OP. More preferably, the thickness dimension is larger than the depth dimension of the opening OP. Still more preferably, the metal film 43m has a T-shaped cross-sectional shape. Thus, the metal film 43m has a portion protruding from the opening OP on the SiO 2 film 31.
- the insulating film 43i covers the metal film 43m.
- the insulating film 43i is disposed on the SiO 2 film 31 provided with the metal film 43m, and extends over the end of the anode electrode film 21.
- the insulating film 43i partially covers the anode electrode film 21.
- the insulating film 43i covers the outer peripheral portion of the anode electrode film 21.
- the portion of the protective structure 43 in contact with the anode electrode film 21 is made of the insulating film 43i.
- the exposed surface (upper surface in the drawing) of the protective structure 43 is constituted by the insulating film 43i.
- diode 93 can be manufactured by a process similar to the process of FIGS. 3 and 4 in the first embodiment.
- the metal film 43m is formed before the insulating film 43i is formed.
- the material of the metal film 43m may be the same as the material of the anode electrode film 21.
- the metal film 43m can be formed simultaneously in the step of forming the anode electrode film 21 (FIG. 2: step S40). .
- FIG. 14 is a partial cross sectional view schematically showing a configuration of a diode 94 in the present embodiment.
- Diode 94, SiO 2 film 31 and the protective structure 43 instead each (FIG. 11 Embodiment 3 of) has SiO 2 film 32 and the protective structure 44 (structure).
- the SiO 2 film 32 is the same as that in the second embodiment (FIG. 8), and more than one opening OP is provided.
- the protective structure 44 includes an insulating film 44i and more than one metal film 44m. Each of the metal films 44m is similar to the metal film 43m.
- diode 94 can be manufactured by substantially the same process as the process of FIGS. 12 and 13 in the third embodiment.
- the SiO 2 film 32 is provided with more than one opening OP. Thereby, the effect of suppressing the peeling of the protective structure 44 from the SiO 2 film 32 is enhanced.
- FIG. 17 is a partial cross sectional view schematically showing a configuration of a diode 95 in the present embodiment.
- the diode 95 has a protective structure 45 (structure) instead of the protective structure 41 (FIG. 1: Embodiment 1).
- the protective structure 45 has an outer insulating film 45i and an inner insulating film 45j.
- the outer insulating film 45i is made of polyimide in the present embodiment.
- the material of the internal insulating film 45j is different from the material of the external insulating film 45i, and may be the same as that of the insulating film 41i (FIG. 1: Embodiment 1).
- the internal insulating film 45 j is disposed on the SiO 2 film 31 and extends onto the end of the anode electrode film 21.
- the external insulating film 45i is disposed on the SiO 2 film 31 provided with the internal insulating film 45j, covers the internal insulating film 45j, and extends onto the end of the anode electrode film 21.
- the outer insulating film 45i reaches the Si substrate 10 at the opening OP.
- diode 95 can be manufactured by substantially the same process as that of FIGS. 3 and 4 in the first embodiment. Specifically, instead of the step of forming the insulating film 41i (FIG. 3) (step S50), the step of forming the internal insulating film 45j and the subsequent step of forming the external insulating film 45i are performed. The formation of the outer insulating film 45i can be performed by a coating method. In this case, the opening OP can be easily filled.
- FIG. 20 is a partial cross sectional view schematically showing a configuration of a diode 96 in the present embodiment.
- the diode 96 is replaced with the SiO 2 film 31 and the protective structure 45 (FIG. 17: Embodiment 5), and the SiO 2 film 32 (FIG. 8) described in Embodiment 2 and the protective structure 46 (structure) And.
- the protective structure 46 has an external insulating film 46i instead of the external insulating film 45i (FIG. 17).
- the outer insulating film 46i is provided on the SiO 2 film 32, and reaches the Si substrate 10 in each of the openings OP.
- diode 96 can be manufactured by substantially the same process as that of FIGS. 18 and 19 in the fifth embodiment.
- the SiO 2 film 32 is provided with more than one opening OP. Thereby, the effect of suppressing the peeling of the protective structure 46 from the SiO 2 film 32 is enhanced.
- FIG. 23 is a partial cross sectional view schematically showing a configuration of a diode 97 in the present embodiment.
- the diode 97 has a protective structure 47 (structure) instead of the protective structure 46 (FIG. 20: sixth embodiment).
- the protective structure 47 has an outer insulating film 47i and a metal film 47m instead of the outer insulating film 46i (FIG. 20).
- Each of the metal films 47m is the same as the metal film 43m (FIG. 11: Embodiment 3).
- the metal film 47m is covered by the outer insulating film 47i.
- diode 97 can be manufactured by a process similar to the process of FIGS. 21 and 22 in the sixth embodiment.
- the metal film 47m is formed before the outer insulating film 47i is formed.
- the material of the metal film 47m may be the same as the material of the anode electrode film 21.
- the metal film 47m can be simultaneously formed in the step of forming the anode electrode film 21 (FIG. 2: step S40) .
- FIG. 26 is a partial cross sectional view schematically showing a configuration of a diode 98 in the present embodiment.
- the protective structure 48 includes an insulating film having an external insulating film 48i (first film) similar to the external insulating film 46i (FIG. 20) and an internal insulating film 48j (second film).
- the material (first material) of the outer insulating film 48i is polyimide in the present embodiment.
- the material (second material) of the inner insulating film 48j is different from the material of the outer insulating film 48i, and may be the same as the insulating film 41i (FIG. 1: Embodiment 1).
- Each of the outer insulating film 48i and the inner insulating film 48j reaches the Si substrate 10 at the outer peripheral opening OQ and the inner peripheral opening OR.
- An internal insulating film 48 j is disposed on the SiO 2 film 33 and extends onto the end of the anode electrode film 21.
- the external insulating film 48i is disposed on the SiO 2 film 33 provided with the internal insulating film 48j, covers the internal insulating film 48j, and extends onto the end of the anode electrode film 21.
- diode 98 can be manufactured by substantially the same process as that of FIGS. 21 and 22 in the sixth embodiment.
- the two-dot chain line portion 33E (FIG. 28) of the SiO 2 film 33 schematically shows a portion to be etched in the same manner as the two-dot chain line portion 31E (FIG. 4) of the SiO 2 film 31.
- FIG. 29 is a partial cross sectional view schematically showing a configuration of a diode 99 in the present embodiment.
- the diode 99 has a protective structure 49 (structure) instead of the protective structure 48 (FIG. 26: eighth embodiment).
- the protective structure 49 includes an insulating film having an outer insulating film 49i (first film) and an inner insulating film 49j (second film), an outer peripheral metal film 49m (first metal portion) and an inner peripheral metal film 49n. And a metal film having a (second metal portion).
- the outer peripheral metal film 49m and the inner peripheral metal film 49n respectively reach the Si substrate 10 at the outer peripheral opening OQ and the inner peripheral opening OR.
- Each of the outer peripheral metal film 49m and the inner peripheral metal film 49n is the same as the metal film 43m (FIG. 11: Embodiment 3).
- the respective materials of the outer insulating film 49i and the inner insulating film 49j are the same as the materials of the outer insulating film 48i and the inner insulating film 48j (FIG. 26: eighth embodiment).
- Each of the outer insulating film 49i and the inner insulating film 49j covers the outer peripheral metal film 49m and the inner peripheral metal film 49n.
- An internal insulating film 49 j is disposed on the SiO 2 film 33 and extends onto the end of the anode electrode film 21.
- the external insulating film 49i is disposed on the SiO 2 film 33 provided with the internal insulating film 49j, covers the internal insulating film 49j, and extends onto the end of the anode electrode film 21.
- diode 99 can be manufactured by a process similar to the process of FIGS. 27 and 28 in the eighth embodiment.
- the inner peripheral metal film 49n is formed before the inner insulating film 49j is formed, and the outer peripheral metal film 49m is formed before the outer insulating film 49i is formed.
- the material of the outer peripheral metal film 49m and the inner peripheral metal film 49n may be the same as the material of the anode electrode film 21.
- the outer peripheral metal film 49m and the inner peripheral metal film 49n form the anode electrode film 21. (FIG. 2: Step S40) It can form simultaneously.
- the semiconductor device is not limited to the diodes, and may be, for example, a transistor.
- the surface to be cleaned by wet etching is the opposite surface (the lower surface in FIG. 6) to the surface (the upper surface in FIG. 6) of the silicon substrate on which the silicon oxide film is disposed is described, the silicon substrate is cleaned
- the relationship between the position to be formed and the position of the silicon oxide film can be appropriately selected depending on the structure of the manufactured semiconductor device.
- the removal of the natural oxide film on the silicon substrate by wet etching has been described, the material to be removed by wet etching is not limited to the natural oxide film, and other foreign matter on the silicon substrate may be used.
- each embodiment can be freely combined, or the embodiment can be appropriately modified or omitted.
- the present invention has been described in detail, the above description is an exemplification in all aspects, and the present invention is not limited thereto. It is understood that countless variations not illustrated are conceivable without departing from the scope of the present invention.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Electrodes Of Semiconductors (AREA)
- Weting (AREA)
Abstract
Description
図1は、本実施の形態におけるダイオード91(半導体装置)の構成を概略的に示す部分断面図である。ダイオード91は、具体的には、電力用半導体装置としてのpinダイオードである。ダイオード91は、Si基板10(シリコン基板)と、アノード層11と、カソード層12と、アノード電極膜21と、カソード電極膜22と、SiO2膜31(シリコン酸化膜)と、保護構造体41(構造体)とを有している。
図8は、本実施の形態におけるダイオード92の構成を概略的に示す部分断面図である。ダイオード92は、SiO2膜31および保護構造体41(図1:実施の形態1)のそれぞれに代わり、SiO2膜32(シリコン酸化膜)および保護構造体42(構造体)を有している。本実施の形態においては、保護構造体42は一の絶縁膜42iによって構成されている。SiO2膜32は1つよりも多い開口部OPを含んでいる。保護構造体42としての絶縁膜42iは、SiO2膜32上に設けられ、開口部OPの各々においてSi基板10に達している。図9および図10のそれぞれを参照して、ダイオード92は、実施の形態1における図3および図4の工程とほぼ同様の工程によって製造し得る。なおSiO2膜32の2点鎖線部32E(図10)は、SiO2膜31の2点鎖線部31E(図4)と同様に、エッチングされる部分を模式的に示す。
図11は、本実施の形態におけるダイオード93の構成を概略的に示す部分断面図である。ダイオード93は、保護構造体41(図1:実施の形態1)に代わり、保護構造体43(構造体)を有している。保護構造体43は、絶縁膜43iと、金属膜43mとを有している。金属膜43mは、SiO2膜31の開口部OPにおいてSi基板10に達している。金属膜43mは、好ましくは、開口部OPを貫通している。より好ましくは、開口部OPの深さ寸法よりも大きな厚さ寸法を有している。さらにより好ましくは、金属膜43mはT字状の断面形状を有している。これにより金属膜43mは、開口部OPから張り出した部分をSiO2膜31上に有している。
図14は、本実施の形態におけるダイオード94の構成を概略的に示す部分断面図である。ダイオード94は、SiO2膜31および保護構造体43(図11:実施の形態3)のそれぞれに代わり、SiO2膜32および保護構造体44(構造体)を有している。SiO2膜32は、実施の形態2におけるもの(図8)と同様のものであり、1つよりも多い開口部OPが設けられている。保護構造体44は、絶縁膜44iと、1つよりも多い金属膜44mとを含んでいる。金属膜44mの各々は、金属膜43mと同様のものである。
図17は、本実施の形態におけるダイオード95の構成を概略的に示す部分断面図である。ダイオード95は、保護構造体41(図1:実施の形態1)に代わり、保護構造体45(構造体)を有している。保護構造体45は、外部絶縁膜45iと、内部絶縁膜45jとを有している。外部絶縁膜45iは、本実施の形態においてはポリイミドから作られている。内部絶縁膜45jの材料は、外部絶縁膜45iの材料と異なるものであり、絶縁膜41i(図1:実施の形態1)と同様のものであってもよい。内部絶縁膜45jはSiO2膜31上に配置されており、アノード電極膜21の端部上へ延びている。外部絶縁膜45iは、内部絶縁膜45jが設けられたSiO2膜31上に配置されており、内部絶縁膜45jを覆っており、アノード電極膜21の端部上へ延びている。外部絶縁膜45iは開口部OPにおいてSi基板10に達している。
図20は、本実施の形態におけるダイオード96の構成を概略的に示す部分断面図である。ダイオード96は、SiO2膜31および保護構造体45(図17:実施の形態5)に代わり、実施の形態2で説明したSiO2膜32(図8)と、保護構造体46(構造体)とを有している。保護構造体46は、外部絶縁膜45i(図17)に代わり、外部絶縁膜46iを有している。外部絶縁膜46iは、SiO2膜32上に設けられ、開口部OPの各々においてSi基板10に達している。図21および図22のそれぞれを参照して、ダイオード96は、実施の形態5における図18および図19の工程とほぼ同様の工程によって製造し得る。
図23は、本実施の形態におけるダイオード97の構成を概略的に示す部分断面図である。ダイオード97は、保護構造体46(図20:実施の形態6)に代わり、保護構造体47(構造体)を有している。保護構造体47は、外部絶縁膜46i(図20)に代わり、外部絶縁膜47iおよび金属膜47mを有している。金属膜47mの各々は、金属膜43m(図11:実施の形態3)と同様のものである。金属膜47mは外部絶縁膜47iによって被覆されている。
図26は、本実施の形態におけるダイオード98の構成を概略的に示す部分断面図である。ダイオード98は、SiO2膜32および保護構造体46(図20:実施の形態6)に代わり、SiO2膜33(シリコン酸化膜)および保護構造体48(構造体)を有している。
図29は、本実施の形態におけるダイオード99の構成を概略的に示す部分断面図である。ダイオード99は、保護構造体48(図26:実施の形態8)に代わり、保護構造体49(構造体)を有している。保護構造体49は、外部絶縁膜49i(第1の膜)および内部絶縁膜49j(第2の膜)を有する絶縁膜と、外周金属膜49m(第1の金属部分)および内周金属膜49n(第2の金属部分)を有する金属膜とを含んでいる。外周金属膜49mおよび内周金属膜49nのそれぞれは、外周開口部OQおよび内周開口部ORにおいてSi基板10に達している。外周金属膜49mおよび内周金属膜49nの各々は、金属膜43m(図11:実施の形態3)と同様のものである。
Claims (9)
- シリコン基板(10)上に、少なくとも1つの開口部(OP,OQ,OR)を有するシリコン酸化膜(31~33)を形成する工程と、
前記シリコン酸化膜上に設けられ、前記開口部において前記シリコン基板に達し、前記シリコン酸化膜に比してフッ化水素酸にエッチングされにくい材料から作られた構造体(41~49)を形成する工程と、
前記シリコン酸化膜および前記構造体が設けられた前記シリコン基板に対して、フッ化水素酸を用いたウェットエッチングを行う工程と、
を備え、前記ウェットエッチングを行う工程において、前記シリコン酸化膜と前記構造体との界面がフッ化水素酸にさらされる、
半導体装置(91~99)の製造方法。 - 前記構造体は絶縁膜を含み、
前記ウェットエッチングを行う工程において、前記シリコン酸化膜と前記絶縁膜との界面がフッ化水素酸にさらされる、請求項1に記載の半導体装置(91~99)の製造方法。 - 前記絶縁膜は前記開口部において前記シリコン基板に達している、請求項2に記載の半導体装置(91,92,95,96,98)の製造方法。
- 前記少なくとも1つの開口部は複数の開口部を含む、請求項3に記載の半導体装置(92,96,98)の製造方法。
- 前記絶縁膜は、第1の材料から作られた第1の膜(48i)と、前記第1の材料と異なる第2の材料から作られた第2の膜(48j)とを含み、
前記第1の膜および前記第2の膜のそれぞれは、前記複数の開口部に含まれる第1の開口部(OQ)および第2の開口部(OR)において前記シリコン基板に達している、
請求項4に記載の半導体装置(98)の製造方法。 - 前記構造体は、前記開口部において前記シリコン基板に達する金属膜を含む、請求項2に記載の半導体装置(93,94,97,99)の製造方法。
- 前記少なくとも1つの開口部は複数の開口部を含む、請求項6に記載の半導体装置(94,97,99)の製造方法。
- 前記金属膜は、前記複数の開口部に含まれる第1の開口部(OQ)および第2の開口部(OR)のそれぞれにおいて前記シリコン基板に達する第1の金属部分(49m)および第2の金属部分(49n)を含み、
前記絶縁膜は、第1の材料から作られ前記第1の金属部分を覆う第1の膜(49i)と、前記第1の材料と異なる第2の材料から作られ前記第2の金属部分を覆う第2の膜(49j)とを含む、
請求項7に記載の半導体装置(99)の製造方法。 - 前記ウェットエッチングを行う工程は、前記シリコン基板を清浄化する工程を含む、請求項1から8のいずれか1項に記載の半導体装置(91~99)の製造方法。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017528067A JP6289760B2 (ja) | 2015-07-15 | 2015-07-15 | 半導体装置の製造方法 |
CN201580081702.XA CN107851574B (zh) | 2015-07-15 | 2015-07-15 | 半导体装置的制造方法 |
PCT/JP2015/070234 WO2017009964A1 (ja) | 2015-07-15 | 2015-07-15 | 半導体装置の製造方法 |
DE112015006705.1T DE112015006705B4 (de) | 2015-07-15 | 2015-07-15 | Verfahren zum Herstellen einer Halbleiteranordnung |
US15/738,507 US10340133B2 (en) | 2015-07-15 | 2015-07-15 | Method for fabricating semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2015/070234 WO2017009964A1 (ja) | 2015-07-15 | 2015-07-15 | 半導体装置の製造方法 |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US15/738,507 Continuation US10340133B2 (en) | 2015-07-15 | 2015-07-15 | Method for fabricating semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2017009964A1 true WO2017009964A1 (ja) | 2017-01-19 |
Family
ID=57757948
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2015/070234 WO2017009964A1 (ja) | 2015-07-15 | 2015-07-15 | 半導体装置の製造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US10340133B2 (ja) |
JP (1) | JP6289760B2 (ja) |
CN (1) | CN107851574B (ja) |
DE (1) | DE112015006705B4 (ja) |
WO (1) | WO2017009964A1 (ja) |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08335705A (ja) * | 1995-06-06 | 1996-12-17 | Nippondenso Co Ltd | 半導体力学量センサの製造方法 |
JP2014011342A (ja) * | 2012-06-29 | 2014-01-20 | Denso Corp | 炭化珪素半導体装置 |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03133161A (ja) | 1989-10-19 | 1991-06-06 | Toshiba Corp | 半導体装置 |
JPH08339996A (ja) | 1995-06-12 | 1996-12-24 | Toshiba Corp | 半導体装置の製造方法 |
JP2005101181A (ja) | 2003-09-24 | 2005-04-14 | Matsushita Electric Ind Co Ltd | 半導体装置のおよびその製造方法 |
US7361958B2 (en) * | 2004-09-30 | 2008-04-22 | Intel Corporation | Nonplanar transistors with metal gate electrodes |
JP2010147077A (ja) * | 2008-12-16 | 2010-07-01 | Renesas Electronics Corp | 半導体装置 |
CN101826465B (zh) * | 2009-03-04 | 2012-05-30 | 中芯国际集成电路制造(上海)有限公司 | 在自对准硅化物过程中防止侧壁阻挡层下方缝隙的方法 |
CN101673682B (zh) * | 2009-09-25 | 2012-07-04 | 上海宏力半导体制造有限公司 | 晶片刻蚀方法 |
KR101164575B1 (ko) * | 2009-12-23 | 2012-07-11 | 주식회사 효성 | 붕소의 디플리션 현상을 이용한 선택적 에미터 형성방법 및 그 태양전지 제조방법 |
CN103021840B (zh) * | 2011-09-23 | 2015-11-04 | 中国科学院微电子研究所 | 防止钝化层过刻蚀的方法 |
US8828839B2 (en) | 2013-01-29 | 2014-09-09 | GlobalFoundries, Inc. | Methods for fabricating electrically-isolated finFET semiconductor devices |
CN103258733A (zh) * | 2013-03-15 | 2013-08-21 | 上海华力微电子有限公司 | 防止光刻胶在湿法刻蚀中产生缺陷的工艺方法 |
KR102086365B1 (ko) | 2013-04-19 | 2020-03-09 | 삼성전자주식회사 | 반도체 발광소자 |
US10170332B2 (en) * | 2014-06-30 | 2019-01-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | FinFET thermal protection methods and related structures |
-
2015
- 2015-07-15 DE DE112015006705.1T patent/DE112015006705B4/de active Active
- 2015-07-15 CN CN201580081702.XA patent/CN107851574B/zh active Active
- 2015-07-15 US US15/738,507 patent/US10340133B2/en active Active
- 2015-07-15 JP JP2017528067A patent/JP6289760B2/ja active Active
- 2015-07-15 WO PCT/JP2015/070234 patent/WO2017009964A1/ja active Application Filing
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08335705A (ja) * | 1995-06-06 | 1996-12-17 | Nippondenso Co Ltd | 半導体力学量センサの製造方法 |
JP2014011342A (ja) * | 2012-06-29 | 2014-01-20 | Denso Corp | 炭化珪素半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
US20180190508A1 (en) | 2018-07-05 |
DE112015006705B4 (de) | 2022-02-24 |
CN107851574A (zh) | 2018-03-27 |
CN107851574B (zh) | 2021-08-13 |
DE112015006705T5 (de) | 2018-04-05 |
US10340133B2 (en) | 2019-07-02 |
JPWO2017009964A1 (ja) | 2017-11-09 |
JP6289760B2 (ja) | 2018-03-07 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN102396051B (zh) | 使绝缘体上硅衬底减薄的方法 | |
TWI612563B (zh) | 金屬閘極結構與其製作方法 | |
JP4816278B2 (ja) | 半導体装置の製造方法 | |
JP2009010387A (ja) | 垂直型シーモスイメージセンサーの製造方法 | |
JP6787212B2 (ja) | 半導体装置の製造方法 | |
JP3676185B2 (ja) | 半導体装置 | |
JP6299412B2 (ja) | 半導体装置および半導体装置の製造方法 | |
TWI670845B (zh) | 柔性顯示面板及其製作方法 | |
JP2010003796A (ja) | 半導体装置及びその製造方法 | |
JP2007123548A (ja) | 半導体装置の製造方法 | |
WO2017009964A1 (ja) | 半導体装置の製造方法 | |
TWI689980B (zh) | 切割晶圓的方法及晶粒 | |
JP2009272530A (ja) | 半導体装置とその製造方法 | |
JP2006332180A (ja) | 炭化珪素半導体装置の製造方法 | |
CN107799386B (zh) | 半导体装置及其制造方法 | |
JP2008053559A (ja) | 半導体装置およびその製造方法 | |
US9793105B1 (en) | Fabricating method of fin field effect transistor (FinFET) | |
JP5365179B2 (ja) | 固体撮像装置の製造方法及び固体撮像装置 | |
WO2015027656A1 (zh) | 氮化镓基发光二极管的制作方法及氮化镓基发光二极管 | |
WO2023286692A1 (ja) | 半導体ウェハ | |
JP6905391B2 (ja) | 半導体装置の製造方法および半導体装置 | |
JP2004055665A (ja) | 基板のマーキング方法 | |
JP2008103458A (ja) | 半導体装置の製造方法 | |
JP2006319282A (ja) | 半導体装置の製造方法 | |
JP4786900B2 (ja) | ショットキーバリアダイオードおよびそれを具備する半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 15898276 Country of ref document: EP Kind code of ref document: A1 |
|
ENP | Entry into the national phase |
Ref document number: 2017528067 Country of ref document: JP Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 112015006705 Country of ref document: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 15898276 Country of ref document: EP Kind code of ref document: A1 |