WO2016035696A1 - 積層構造体およびその製造方法、半導体装置ならびに結晶膜 - Google Patents
積層構造体およびその製造方法、半導体装置ならびに結晶膜 Download PDFInfo
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- WO2016035696A1 WO2016035696A1 PCT/JP2015/074380 JP2015074380W WO2016035696A1 WO 2016035696 A1 WO2016035696 A1 WO 2016035696A1 JP 2015074380 W JP2015074380 W JP 2015074380W WO 2016035696 A1 WO2016035696 A1 WO 2016035696A1
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Definitions
- the present invention relates to a laminated structure useful for a semiconductor device, a manufacturing method thereof, a semiconductor device comprising the laminated structure, and a crystal film.
- a semiconductor device using gallium oxide (Ga 2 O 3 ) having a large band gap has been attracting attention as a next-generation switching element that can realize high breakdown voltage, low loss, and high heat resistance.
- Power semiconductor devices such as inverters (power) Device
- the gallium oxide can control the band gap by using mixed crystals of indium and aluminum, respectively.
- Patent Document 1 describes a highly crystalline conductive ⁇ -Ga 2 O 3 thin film to which a dopant (tetravalent tin) is added.
- a dopant tetravalent tin
- the thin film described in Patent Document 1 cannot maintain sufficient pressure resistance, and contains a large amount of carbon impurities, and the semiconductor characteristics including conductivity are still not satisfactory. It was still difficult to use in the device.
- Non-Patent Document 2 describes that an ⁇ -Ga 2 O 3 thin film can be formed on sapphire by MBE.
- the crystal grows up to a film thickness of 100 nm at a temperature of 450 ° C. or lower, it is described that the crystal quality deteriorates when the film thickness is larger than that, and a film having a film thickness of 1 ⁇ m or more cannot be obtained. Therefore, an ⁇ -Ga 2 O 3 thin film having a film thickness of 1 ⁇ m or more and no deterioration in crystal quality has been awaited.
- Patent Document 2 describes a method of manufacturing an oxide crystal thin film by mist CVD using gallium or indium bromide or iodide.
- Patent Documents 3 to 5 describe a multilayer structure in which a semiconductor layer having a corundum crystal structure and an insulating film having a corundum crystal structure are stacked on a base substrate having a corundum crystal structure.
- Patent Documents 2 to 5 are all patents or patent publications by the present applicant.
- JP 2013-28480 A Japanese Patent No. 5398794 Japanese Patent No. 5343224 Japanese Patent No. 5399795 JP 2014-72533 A
- An object of the present invention is to provide a laminated structure having excellent crystallinity, a semiconductor device of the laminated structure having good mobility, and a crystal film having excellent crystallinity.
- a crystalline film containing a crystalline oxide having a corundum structure as a main component is directly or via another layer on a crystal substrate having a corundum structure.
- the crystalline substrate has an off angle of 0.2 ° to 12.0 °
- the crystalline oxide is selected from indium, aluminum, and gallium. It has been found that a laminated structure containing a seed or two or more metals has good semiconductor properties, particularly mobility.
- the present inventors have further studied and completed the present invention.
- the present invention relates to the following inventions.
- a stacked structure in which a crystal film containing a crystalline oxide having a corundum structure as a main component is stacked on a crystal substrate having a corundum structure directly or via another layer, the crystal The substrate has an off angle of 0.2 ° to 12.0 °, and the crystalline oxide contains one or more metals selected from indium, aluminum, and gallium.
- Laminated structure [2] The laminated structure according to [1], wherein the crystal substrate has an off angle of 1 ° to 8 °.
- a mist is generated by atomizing the raw material solution, then a carrier gas is supplied to the mist, the mist is supplied to the substrate by the carrier gas, and the mist is thermally reacted to cause a mist on the substrate surface.
- a manufacturing method characterized by having an off angle of 0.0 ° and the raw material solution containing one or more metals selected from indium, aluminum and gallium.
- the center line average roughness (Ra) of the film surface of the crystal film measured using an atomic force microscope is 10 nm or less, and the maximum height difference (PV value) is 100 nm or less [13] ] To [16].
- a semiconductor device comprising at least the crystal film according to [18] or [19] and an electrode.
- the stacked structure of the present invention has excellent crystallinity, the semiconductor device of the stacked structure has good mobility, and the crystal film has excellent crystallinity.
- FIG. 1 It is a figure which shows typically a suitable example of the Schottky barrier diode (SBD) of this invention. It is a figure which shows typically a suitable example of the Schottky barrier diode (SBD) of this invention. It is a figure which shows typically a suitable example of the Schottky barrier diode (SBD) of this invention. It is a figure which shows typically a suitable example of the Schottky barrier diode (SBD) of this invention. It is a figure which shows typically a suitable example of the metal semiconductor field effect transistor (MESFET) of this invention. It is a figure which shows typically a suitable example of the high electron mobility transistor (HEMT) of this invention. It is a figure which shows typically a suitable example of the metal oxide film semiconductor field effect transistor (MOSFET) of this invention.
- FIG. 1 shows typically a suitable example of the Schottky barrier diode (SBD) of this invention. It is a figure which shows typically a suitable example of the Schottky
- FIG. 7 is a schematic diagram for explaining a part of the manufacturing process of the metal oxide semiconductor field effect transistor (MOSFET) of FIG. 6. It is a figure which shows typically an example of the metal oxide film semiconductor field effect transistor (MOSFET) of this invention. It is a figure which shows typically a suitable example of the electrostatic induction transistor (SIT) of this invention. It is a figure which shows typically a suitable example of the Schottky barrier diode (SBD) of this invention. It is a figure which shows typically a suitable example of the Schottky barrier diode (SBD) of this invention. It is a figure which shows typically a suitable example of the high electron mobility transistor (HEMT) of this invention.
- MOSFET metal oxide semiconductor field effect transistor
- MOSFET metal oxide film semiconductor field effect transistor
- JFET junction field effect transistor
- IGBT insulated gate bipolar transistor
- LED light emitting element
- LED light emitting element
- FIG. 1 It is a figure which shows the relationship of the cross-sectional area of a susceptor and the supply pipe
- the AFM image of the crystal film in an Example is shown.
- the AFM image of the crystal film in an Example is shown.
- the AFM image of the crystal film in an Example is shown.
- the multilayer structure of the present invention is a multilayer structure in which a crystal film containing a crystalline oxide having a corundum structure as a main component is laminated directly or via another layer on a crystal substrate having a corundum structure.
- the crystal substrate has an off angle of 0.2 ° to 12.0 °, and the crystalline oxide contains one or more metals selected from indium, aluminum, and gallium. It is characterized by that.
- the crystal substrate is not particularly limited as long as it has a corundum structure and further has an off angle of 0.2 ° to 12.0 °.
- the crystal substrate having a corundum structure is not particularly limited as long as it can support the crystal film and further has a corundum structure in all or part of the substrate.
- the presence or absence of a corundum structure can be identified by an X-ray diffractometer.
- Examples of the crystal substrate include a substrate containing a crystal having a corundum structure as a main component.
- the substrate containing a crystal having a corundum structure as a main component is not particularly limited as long as the composition ratio in the substrate includes 50% or more of the crystal having a corundum structure, but in the present invention, 70% or more.
- the substrate whose main component is a crystal having a corundum structure examples include a sapphire substrate (eg, c-plane sapphire substrate), an ⁇ -type gallium oxide substrate, and the like.
- the thickness of the crystal substrate is not particularly limited in the present invention, but is preferably 50 to 2000 ⁇ m, more preferably 200 to 800 ⁇ m.
- the crystal substrate is a sapphire substrate (eg, c-plane sapphire substrate, m-plane sapphire substrate, a-plane sapphire substrate, r-plane sapphire substrate) or ⁇ -type gallium oxide substrate.
- a sapphire substrate eg, c-plane sapphire substrate, m-plane sapphire substrate, a-plane sapphire substrate, r-plane sapphire substrate
- the carbon content, carrier concentration, and half-value width of impurities in the crystalline semiconductor film can be further reduced as compared with the case of using another substrate.
- the crystal substrate has an off angle of about 0.2 ° to 12.0 °.
- the off angle is preferably about 1 ° to 8 °, about 2 °. More preferably, the angle is 5 ° to 5 °.
- the “off angle” in the crystal substrate refers to an angle formed by the substrate surface and the crystal growth surface.
- a crystal substrate having an off angle can be produced according to a conventional method.
- an off angle may be given to the crystal substrate using a known means such as polishing.
- you may perform a well-known process further. Examples of such treatment include providing a multi-step structure by arranging micropores or microprotrusions after polishing and then performing heat treatment.
- a crystal film containing a crystalline oxide having a corundum structure as a main component is laminated directly or via another layer on a crystal substrate having a corundum structure.
- the crystal film is not particularly limited as long as it contains a crystalline oxide having a corundum structure as a main component, but is preferably an epitaxial film formed by epitaxial growth.
- the crystalline oxide contains one or more metals selected from indium, aluminum and gallium as a main component, but more preferably contains at least indium and / or gallium as a main component. Preferably, it contains at least gallium as a main component.
- the “main component” means that the crystalline oxide having the corundum structure is preferably 50% or more, more preferably 70% or more with respect to all components of the crystal film in terms of atomic ratio. More preferably, it means that it is contained 90% or more, which means that it may be 100%.
- the crystal film since the crystal film is formed by epitaxial growth on the crystal substrate, it has an off angle of about 0.2 ° to 12.0 °. In the present invention, the off angle is about 1 It is preferably from 0 ° to 8 °, more preferably from about 2 ° to 5 °. By having a preferable off angle, the semiconductor characteristics of the crystal film, particularly the mobility, are further improved.
- the “off angle” in the crystal film refers to an angle formed between the crystal film surface and the crystal growth surface.
- the crystalline oxide is preferably a semiconductor, and the crystal film preferably further contains a dopant.
- the crystalline oxide is a semiconductor, it has excellent semiconductor characteristics, particularly mobility.
- the crystalline oxide may not be a semiconductor.
- the crystalline film may further contain a dopant, and the absorption wavelength is increased by doping. It can be changed or an optical crystal.
- the semiconductor examples include a crystalline oxide semiconductor containing one or more metals selected from indium, aluminum, and gallium as a main component.
- a crystalline oxide semiconductor containing one or more metals selected from indium, aluminum, and gallium as a main component.
- the present invention preferably, at least indium or / and / or It is a crystalline oxide semiconductor having a corundum structure containing gallium as a main component, and more preferably a crystalline oxide semiconductor having a corundum structure containing at least gallium as a main component.
- the total atomic ratio of gallium, indium and aluminum in the metal element contained in the crystal film is preferably 0.5 or more, and more preferably 0.8 or more.
- the preferable composition in the case where the crystalline oxide semiconductor contains gallium is such that the atomic ratio of gallium in the metal element contained in the crystal film is preferably 0.5 or more, and is 0.8 or more. Is more preferable.
- the dopant examples include n-type dopants such as tin, germanium, silicon, titanium, zirconium, vanadium or niobium, or p-type dopants.
- the concentration of the dopant may usually be about 1 ⁇ 10 16 / cm 3 to 1 ⁇ 10 22 / cm 3 , and the concentration of the dopant is set to a low concentration of about 1 ⁇ 10 17 / cm 3 or less, for example.
- an n-type dopant an n-type semiconductor or the like can be used.
- the dopant can be contained at a high concentration of about 1 ⁇ 10 20 / cm 3 or more, for example, in the case of an n-type dopant, an n + -type semiconductor or the like can be obtained.
- the n-type dopant is preferably tin, germanium, silicon, titanium, zirconium, vanadium or niobium, and more preferably tin, germanium or silicon.
- the concentration of the n-type dopant in the crystal film is preferably about 1 ⁇ 10 13 to 5 ⁇ 10 17 / cm 3 , and is about 1 ⁇ 10 15 to 1 ⁇ 10 3.
- the concentration of the n-type dopant in the crystal film is preferably about 1 ⁇ 10 17 / cm 3 or more, and about 3 ⁇ 10 17 / cm 3. More preferably, it is set to ⁇ 3 ⁇ 10 19 / cm 3 . As described above, by adding a dopant to the crystal film, a crystal film having excellent electrical characteristics can be obtained.
- the crystal film may be formed directly on the crystal substrate or may be formed via another layer.
- a corundum structure crystal thin film having a different composition, a crystal thin film other than the corundum structure, an amorphous thin film, or the like can be given.
- the structure may be a single layer structure or a multi-layer structure. Two or more crystal phases may be mixed in the same layer.
- the crystal film is configured by laminating an insulating thin film and a conductive thin film, for example, but is not limited to this in the present invention.
- the composition of an insulating thin film and an electroconductive thin film may be the same, or may mutually differ.
- the ratio of the thickness of the insulating thin film to the conductive thin film is not particularly limited.
- the ratio of (thickness of the conductive thin film) / (thickness of the insulating thin film) is 0.001 to 100. 0.1 to 5 is more preferable.
- This more preferable ratio is specifically, for example, 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 1, 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9, 2, 3, 4, 5 and illustrated here It may be within a range between any two of the numerical values.
- the crystal film can be laminated on the crystal substrate as it is or via another layer by a mist / epitaxy method.
- the mist epitaxy method includes a step (1) of atomizing a raw material solution to generate a mist, a step of supplying a carrier gas to the mist, and a step of transporting the mist to a crystal substrate by the carrier gas (2), There is no particular limitation as long as it is a film forming method including the step (3) of thermally reacting the mist to deposit a crystalline film made of a crystalline oxide on a part or all of the substrate surface. More specific examples of the mist / epitaxy method include a mist CVD method.
- the raw material solution is atomized to generate mist.
- a mist generator that atomizes the raw material solution to generate mist can be used.
- the mist generator is not particularly limited as long as it can atomize the raw material solution to generate the mist, and may be a known one, but in the present invention, the raw material is atomized by ultrasonic to produce the mist. Preferably it is generated.
- the raw material solution will be described later.
- a carrier gas is supplied to the mist, and the mist is transferred to the crystal substrate by the carrier gas.
- the carrier gas is not particularly limited as long as it is a gas that can transport mist generated by atomizing the raw material solution onto the crystal substrate.
- reducing gas such as inert gas, such as oxygen gas, nitrogen gas, and argon gas, forming gas, hydrogen gas, etc. are mentioned.
- the mist is thermally reacted to deposit a crystal film on a part or all of the substrate surface.
- a tubular furnace capable of transporting mist to the crystal substrate with a carrier gas and forming a film in a supply pipe can be suitably used.
- the reaction temperature is not particularly limited as long as the raw material solution undergoes thermal reaction, but in the present invention, the thermal reaction is preferably performed at a temperature of 400 ° C. to 700 ° C., and at a temperature of 500 ° C. to 700 ° C. More preferably.
- a susceptor shown in FIG. 19 or 20 as the susceptor.
- FIG. 19 shows one mode of the susceptor.
- a susceptor 51 shown in FIG. 19 includes a mist acceleration unit 52, a substrate holding unit 53, and a support unit 54.
- the support portion 54 has a rod shape, and is configured to change the angle in the middle so that the contact angle of the support portion 54 with the supply pipe 55 is about 90 °. With such a configuration, the stability of the susceptor 51 is improved, but in the present invention, the shape of the support portion 54 is not particularly limited, and various shapes can be used as appropriate.
- FIG. 19 (a) shows a cross section inside the supply pipe from the upstream of the mist to the downstream direction until reaching the crystal substrate, and the outer peripheral shape of the substrate side surface of the supply pipe is substantially semicircular, It can be seen that the shapes are substantially the same along the inner circumference of the supply pipe.
- FIG. 19B shows a cross section of the supply pipe, the crystal substrate, and the susceptor when the upstream of the mist is on the left and the downstream is on the right.
- the susceptor 101 is provided with an inclined mist accelerating portion 102 so that the settled mist can be accelerated and transported to the crystal substrate 103. Yes.
- FIG. 20 shows the region of the susceptor and crystal substrate shown in FIG. 19 as the substrate / susceptor region 61 and the region where unreacted mist is discharged as the discharge region 62 in the supply pipe 55.
- the relationship between the total area with the substrate and the area of the discharge region can be understood.
- the susceptor region and the The total area with the crystal substrate is preferably larger than the area of the discharge region.
- a doping process can be performed using a dopant when forming the crystal film.
- the doping treatment is performed by including an abnormal grain inhibitor in the raw material solution.
- a crystal film having excellent surface smoothness can be obtained by doping the raw material solution with an abnormal grain inhibitor.
- the doping amount is not particularly limited as long as it does not hinder the object of the present invention, but is preferably 0.01 to 10%, more preferably 0.1 to 5% in terms of molar ratio in the raw material.
- the abnormal grain inhibitor refers to an agent having an effect of suppressing generation of particles by-produced in the film formation process, and is not particularly limited as long as the surface roughness (Ra) of the crystal film can be set to 0.1 ⁇ m or less, for example.
- the abnormal particle inhibitor is at least one selected from Br, I, F and Cl. Introducing Br or I into the film as an abnormal grain inhibitor for stable film formation can suppress the deterioration of the surface roughness due to abnormal grain growth.
- the amount of the abnormal grain inhibitor added is not particularly limited as long as abnormal grains can be suppressed.
- the volume ratio in the raw material solution is preferably 50% or less, more preferably 30% or less, and more preferably 1 to 30%. Most preferably within the range. By using an abnormal grain inhibitor in such a preferable range, it can function as an abnormal grain inhibitor, and thus the growth of abnormal grains in the crystal film can be suppressed and the surface can be smoothed.
- the method for forming the crystal film is not particularly limited as long as the object of the present invention is not hindered.
- a raw material in which a gallium compound and, if desired, an indium compound or an aluminum compound are combined in accordance with the composition of the crystal film are reacted. It can be formed. That is, the raw material solution contains one or more metals selected from indium, aluminum, and gallium.
- the crystal film can be grown on the crystal substrate from the substrate side.
- the gallium compound may be a gallium compound that is changed to a gallium compound immediately before film formation using gallium metal as a starting material.
- gallium compound examples include organometallic complexes of gallium (e.g., acetylacetonate complex) and halides (e.g., fluoride, chloride, bromide, iodide, etc.).
- halides e.g., fluoride, chloride, bromide, iodide, etc.
- a halide e.g, fluoride, chloride, bromide or iodide.
- raw material fine particles generated from a raw material solution in which the raw material compound is dissolved are supplied to the film forming chamber, and the raw material compound is thermally reacted in the film forming chamber using the susceptor.
- the solvent of the raw material solution is not particularly limited, but is preferably water, hydrogen peroxide solution or an organic solvent.
- the above raw material compound is usually reacted in the presence of a dopant raw material.
- the dopant raw material is preferably included in the raw material solution and finely divided together with the raw material compound or separately.
- the crystal film contains less carbon than the dopant, and preferably, the crystal film can be substantially free of carbon.
- the crystalline film of the present invention contains halogen (preferably Br) because it exhibits good semiconductor characteristics.
- halogen preferably Br
- the dopant raw material include tin, germanium, silicon, titanium, zirconium, vanadium, or niobium, which are simple metals or compounds (eg, halides, oxides, etc.).
- the film thickness can be made 1 ⁇ m or more, preferably 3 ⁇ m or more without impairing the crystallinity.
- annealing may be performed after film formation.
- the annealing temperature is not particularly limited, but is preferably 700 ° C. or less, more preferably 300 ° C. to 700 ° C., and most preferably 300 ° C. to 550 ° C. By performing the annealing process at such a preferable temperature, the carrier concentration of the crystal film can be adjusted more suitably.
- the annealing treatment time is not particularly limited as long as the object of the present invention is not impaired, but is preferably 10 seconds to 10 hours, more preferably 10 seconds to 1 hour.
- the stacked structure can be used for a semiconductor device as it is or after being further processed as desired.
- it when used in a semiconductor device, it may be used in a semiconductor device as it is, or another layer (for example, an insulator layer, a semi-insulator layer, a conductor layer, a semiconductor layer, a buffer layer, or other intermediate layers), etc. May be formed.
- the laminated structure of the present invention is useful for various semiconductor devices, and particularly useful for power devices.
- the semiconductor device is classified into a horizontal element in which electrodes are formed on one side of a semiconductor layer (horizontal device) and a vertical element (vertical device) having electrodes on both sides of the semiconductor layer.
- the laminated structure can be suitably used for both a horizontal device and a vertical device.
- the semiconductor device examples include a Schottky barrier diode (SBD), a metal semiconductor field effect transistor (MESFET), a high electron mobility transistor (HEMT), a metal oxide semiconductor field effect transistor (MOSFET), and an electrostatic induction transistor ( SIT), junction field effect transistor (JFET), insulated gate bipolar transistor (IGBT), or light emitting diode.
- the semiconductor device is preferably an SBD, MOSFET, SIT, JFET or IGBT, and more preferably an SBD, MOSFET or SIT.
- the semiconductor device may not include a p-type semiconductor layer.
- n-type semiconductor layer such as an n + type semiconductor or an n ⁇ type semiconductor
- n + type semiconductor or an n ⁇ type semiconductor such as an n + type semiconductor or an n ⁇ type semiconductor
- other layers for example, an insulator layer, a semi-insulator layer, a conductor layer, a semiconductor layer, a buffer layer, or other intermediate layers
- buffer layer buffer layer and the like may be omitted as appropriate.
- FIG. 1 shows an example of a Schottky barrier diode (SBD) according to the present invention.
- the SBD of FIG. 1 includes an n ⁇ type semiconductor layer 101a, an n + type semiconductor layer 101b, a Schottky electrode 105a, and an ohmic electrode 105b.
- the material of the Schottky electrode and the ohmic electrode may be a known electrode material.
- the electrode material include Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Metals such as Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd or Ag, or alloys thereof, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), oxidation
- a metal oxide conductive film such as zinc indium (IZO), an organic conductive compound such as polyaniline, polythiophene, or polypyrrole, or a mixture thereof.
- the formation of the Schottky electrode and the ohmic electrode can be performed by a known means such as a vacuum deposition method or a sputtering method. More specifically, for example, when forming a Schottky electrode, a layer made of Mo and a layer made of Al are stacked, and patterning using a photolithography technique is performed on the layer made of Mo and the layer made of Al. Can be done.
- the SBD using the semiconductor structure is excellent for high withstand voltage and large current, has a high switching speed, and is excellent in withstand voltage and reliability.
- FIG. 2 shows an example of a Schottky barrier diode (SBD) according to the present invention.
- the SBD of FIG. 2 further includes an insulator layer 104 in addition to the configuration of the SBD of FIG. More specifically, an n ⁇ type semiconductor layer 101a, an n + type semiconductor layer 101b, a Schottky electrode 105a, an ohmic electrode 105b, and an insulator layer 104 are provided.
- Examples of the material of the insulator layer 104 include GaO, AlGaO, InAlGaO, AlInZnGaO 4 , AlN, Hf 2 O 3 , SiN, SiON, Al 2 O 3 , MgO, GdO, SiO 2, and Si 3 N 4. However, in the present invention, it preferably has a corundum structure. By using an insulator having a corundum structure for the insulator layer, a function of semiconductor characteristics at the interface can be satisfactorily exhibited.
- the insulator layer 104 is provided between the n ⁇ type semiconductor layer 101 and the Schottky electrode 105a.
- the insulator layer can be formed by known means such as sputtering, vacuum deposition, or CVD.
- the formation and material of the Schottky electrode and the ohmic electrode are the same as those in the case of the SBD in FIG. 1.
- a sputtering method a vacuum evaporation method, a pressure bonding method, a CVD method
- Metals such as Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, or Ag Or alloys thereof, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), metal oxide conductive films such as zinc indium oxide (IZO), organic conductive compounds such as polyaniline, polythiophene or polypyrrole, or An electrode made of a mixture of these can be formed.
- the SBD of FIG. 3 is an example of a Schottky barrier diode (SBD) according to the present invention.
- the SBD of FIG. 3 differs greatly from the configuration of the SBD of FIGS. 1 and 2 in that it has a trench structure and includes a semi-insulator layer 103.
- the SBD of FIG. 3 includes an n ⁇ type semiconductor layer 101a, an n + type semiconductor layer 101b, a Schottky electrode 105a, an ohmic electrode 105b, and a semi-insulator layer 103, and greatly reduces leakage current while maintaining withstand voltage. The on-resistance can be greatly reduced.
- the semi-insulator layer 103 only needs to be formed of a semi-insulator.
- the semi-insulator include magnesium (Mg), ruthenium (Ru), iron (Fe), beryllium (Be), and cesium ( Cs), those containing a semi-insulating dopant such as strontium and barium, and those not subjected to doping treatment.
- FIG. 4 shows an example of a metal semiconductor field effect transistor (MESFET) according to the present invention.
- the MESFET in FIG. 4 includes an n ⁇ type semiconductor layer 111a, an n + type semiconductor layer 111b, a buffer layer (buffer layer) 118, a semi-insulator layer 114, a gate electrode 115a, a source electrode 115b, and a drain electrode 115c.
- the material of the gate electrode, the drain electrode and the source electrode may be a known electrode material.
- the electrode material include Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Metals such as Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd, or Ag, or alloys thereof, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO) And metal oxide conductive films such as zinc indium oxide (IZO), organic conductive compounds such as polyaniline, polythiophene, and polypyrrole, or mixtures thereof.
- the gate electrode, the drain electrode, and the source electrode can be formed by a known means such as a vacuum deposition method or a sputtering method.
- the semi-insulator layer 114 may be any semi-insulator, and examples of the semi-insulator include magnesium (Mg), ruthenium (Ru), iron (Fe), beryllium (Be), cesium ( Cs), those containing a semi-insulating dopant such as strontium and barium, and those not subjected to doping treatment.
- the semi-insulator include magnesium (Mg), ruthenium (Ru), iron (Fe), beryllium (Be), cesium ( Cs), those containing a semi-insulating dopant such as strontium and barium, and those not subjected to doping treatment.
- FIG. 5 shows an example of a photoelectron mobility transistor (HEMT) according to the present invention.
- the HEMT in FIG. 5 includes an n-type semiconductor layer 121a having a wide band gap, an n-type semiconductor layer 121b having a narrow band gap, an n + type semiconductor layer 121c, a semi-insulator layer 124, a buffer layer 128, a gate electrode 125a, a source electrode 125b, A drain electrode 125c is provided.
- the material of the gate electrode, the drain electrode and the source electrode may be a known electrode material, and examples of the electrode material include Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, and Ti. , Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd or Ag, or alloys thereof, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO ), A metal oxide conductive film such as zinc indium oxide (IZO), an organic conductive compound such as polyaniline, polythiophene or polypyrrole, or a mixture thereof.
- the gate electrode, the drain electrode, and the source electrode can be formed by a known means such as a vacuum deposition method or a sputtering method.
- the n-type semiconductor layer under the gate electrode is composed of at least a wide band gap layer 121a and a narrow layer 121b, and the semi-insulator layer 124 only needs to be composed of a semi-insulator.
- the semi-insulator include those containing a semi-insulator dopant such as ruthenium (Ru) and iron (Fe) and those not subjected to doping treatment.
- Ru ruthenium
- Fe iron
- MOSFET Metal Organic Semiconductor
- FIG. 6 An example in which the semiconductor device of the present invention is a MOSFET is shown in FIG.
- the MOSFET in FIG. 6 is a trench type MOSFET and includes an n ⁇ type semiconductor layer 131a, n + type semiconductor layers 131b and 131c, a gate insulating film 134, a gate electrode 135a, a source electrode 135b, and a drain electrode 135c.
- an n + type semiconductor layer 131c is formed on the n ⁇ type semiconductor layer 131a, and a source electrode 135b is formed on the n + type semiconductor layer 131c.
- a plurality of trenches are formed in the n ⁇ type semiconductor layer 131a and the n + type semiconductor layer 131c so as to penetrate the n + semiconductor layer 131c and reach the middle of the n ⁇ type semiconductor layer 131a. ing.
- a gate electrode 135a is embedded through a gate insulating film 134 having a thickness of 10 nm to 1 ⁇ m.
- the n ⁇ type is applied.
- a channel layer is formed on the side surface of the semiconductor layer 131a, and electrons are injected into the n ⁇ type semiconductor layer 131a and turned on.
- the voltage of the gate electrode is set to 0 V, the channel layer cannot be formed, and the n ⁇ type semiconductor layer 131a is filled with the depletion layer, and the turn-off is performed.
- FIG. 7 shows a part of the manufacturing process of the MOSFET of FIG.
- an etching mask is provided in predetermined regions of the n ⁇ type semiconductor layer 131a and the n + type semiconductor layer 131c, and the reactive ions are further formed using the etching mask as a mask.
- a trench groove having a depth reaching from the surface of the n + type semiconductor layer 131c to the middle of the n ⁇ type semiconductor layer 131a is formed by performing anisotropic etching by an etching method or the like. .
- a gate having a thickness of, for example, 50 nm to 1 ⁇ m is formed on the side and bottom surfaces of the trench groove by using known means such as a thermal oxidation method, a vacuum deposition method, a sputtering method, and a CVD method.
- a gate electrode material such as polysilicon, for example, is formed in the trench groove below the thickness of the n ⁇ type semiconductor layer 131a by using a CVD method, a vacuum deposition method, a sputtering method or the like.
- a source electrode 135b is formed on the n + type semiconductor layer 131c, and a drain electrode 135c is formed on the n + type semiconductor layer 131b.
- a power MOSFET can be manufactured.
- the electrode material of the source electrode and the drain electrode may be a known electrode material, and examples of the electrode material include Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, and Ti.
- tin oxide zinc oxide, indium oxide, indium tin oxide (ITO ), A metal oxide conductive film such as zinc indium oxide (IZO), an organic conductive compound such as polyaniline, polythiophene or polypyrrole, or a mixture thereof.
- IZO zinc indium oxide
- organic conductive compound such as polyaniline, polythiophene or polypyrrole, or a mixture thereof.
- FIG. 6 shows an example of a trench type vertical MOSFET, the present invention is not limited to this and can be applied to various MOSFET forms.
- the trench resistance in FIG. 6 may be dug down to a depth reaching the bottom surface of the n ⁇ type semiconductor layer 131a to reduce the series resistance.
- An example of a lateral MOSFET is shown in FIG.
- n ⁇ type semiconductor layer 131a includes an n ⁇ type semiconductor layer 131a, a first n + type semiconductor layer 131b, a second n + type semiconductor layer 131c, a gate insulating film 134, a gate electrode 135a, a source electrode 135b, a drain electrode 135c, and a buffer layer. 138 and a semi-insulator layer 139. As shown in FIG. 8, by burying the n + type semiconductor layer in the n ⁇ type semiconductor layer, it is possible to flow a current better than other lateral MOSFETs.
- FIG. 9 shows an example where the semiconductor device of the present invention is SIT.
- the SIT in FIG. 9 includes an n ⁇ type semiconductor layer 141a, n + type semiconductor layers 141b and 141c, a gate electrode 145a, a source electrode 145b, and a drain electrode 145c.
- an n + type semiconductor layer 141c is formed on the n ⁇ type semiconductor layer 141a, and a source electrode 145b is formed on the n + type semiconductor layer 141c.
- a plurality of trench grooves are formed in the n ⁇ type semiconductor layer 141a so as to penetrate the n + semiconductor layer 141c and reach a depth halfway through the n ⁇ semiconductor layer 141a.
- a gate electrode 145a is formed on the n ⁇ type semiconductor layer in the trench. 9, when a voltage is applied between the source electrode 145b and the drain electrode 145c and a positive voltage is applied to the gate electrode 145a with respect to the source electrode 145b, the n ⁇ type is applied.
- a channel layer is formed in the semiconductor layer 141a, and electrons are injected into the n ⁇ type semiconductor layer 141a and turned on. In the off state, when the voltage of the gate electrode is set to 0V, the channel layer is not formed, and the n ⁇ type semiconductor layer 141a is filled with the depletion layer, and the turn-off is performed.
- a well-known means can be used for manufacture of SIT shown by FIG.
- an etching mask is provided in predetermined regions of the n ⁇ type semiconductor layer 141a and the n + type semiconductor layer 141c in the same manner as the MOSFET manufacturing process shown in FIG.
- anisotropic etching is performed by, for example, reactive ion etching or the like to form a trench groove having a depth reaching from the surface of the n + type semiconductor layer 141c to the middle of the n ⁇ type semiconductor layer.
- a gate electrode material such as polysilicon, for example, is formed in the trench groove below the thickness of the n ⁇ type semiconductor layer 141a by CVD, vacuum deposition, sputtering, or the like. Then, by using a known means such as a vacuum deposition method, a sputtering method, a CVD method or the like, a source electrode 145b is formed on the n + type semiconductor layer 141c, and a drain electrode 145c is formed on the n + type semiconductor layer 141b, respectively.
- the SIT shown in FIG. 9 can be manufactured.
- the electrode material of the source electrode and the drain electrode may be a known electrode material, and examples of the electrode material include Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, and Ti. , Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd or Ag, or alloys thereof, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO ), A metal oxide conductive film such as zinc indium oxide (IZO), an organic conductive compound such as polyaniline, polythiophene or polypyrrole, or a mixture thereof.
- the electrode material include Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, and Ti. , Au, Pt, V, Mn, Ni, Cu, Hf, W, Ir, Zn, In, Pd, Nd or Ag, or alloys thereof, tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO ),
- a p-type semiconductor is not used.
- the present invention is not limited to this, and a p-type semiconductor may be used. Examples using p-type semiconductors are shown in FIGS. These semiconductor devices can be manufactured in the same manner as in the above example.
- the p-type semiconductor is the same material as the n-type semiconductor and may include a p-type dopant or may be a different p-type semiconductor.
- FIG. 10 shows a suitable Schottky barrier diode (SBD) including an n ⁇ type semiconductor layer 101a, an n + type semiconductor layer 101b, a p type semiconductor layer 102, an insulator layer 104, a Schottky electrode 105a, and an ohmic electrode 105b.
- SBD Schottky barrier diode
- FIG. 11 shows a preferred example of a trench Schottky barrier diode (SBD) including an n ⁇ type semiconductor layer 101a, an n + type semiconductor layer 101b, a p type semiconductor layer 102, a Schottky electrode 105a, and an ohmic electrode 105b. Show. According to the trench type SBD, the leakage current can be greatly reduced while maintaining the withstand voltage, and the on-resistance can be significantly reduced.
- SBD trench Schottky barrier diode
- HEMT high electron mobility transistor
- FIG. 13 shows an n ⁇ type semiconductor layer 131a, a first n + type semiconductor layer 131b, a second n + type semiconductor layer 131c, a p type semiconductor layer 132, a p + type semiconductor layer 132a, a gate insulating film 134, a gate electrode 135a,
- MOSFET metal oxide semiconductor field effect transistor
- the p + type semiconductor layer 132a may be a p type semiconductor layer or the same as the p type semiconductor layer 132.
- FIG. 14 includes an n ⁇ type semiconductor layer 141a, a first n + type semiconductor layer 141b, a second n + type semiconductor layer 141c, a p type semiconductor layer 142, a gate electrode 145a, a source electrode 145b, and a drain electrode 145c.
- JFET junction field effect transistor
- FIG. 15 shows an n-type semiconductor layer 151, an n-type semiconductor layer 151a, an n + -type semiconductor layer 151b, a p-type semiconductor layer 152, a gate insulating film 154, a gate electrode 155a, an emitter electrode 155b, and a collector electrode 155c.
- IGBT gate type bipolar transistor
- the semiconductor light emitting element of FIG. 16 includes an n-type semiconductor layer 161 on the second electrode 165b, and a light-emitting layer 163 is stacked on the n-type semiconductor layer 161.
- a p-type semiconductor layer 162 is stacked on the light emitting layer 163.
- a light-transmitting electrode 167 that transmits light generated by the light-emitting layer 163 is provided over the p-type semiconductor layer 162, and a first electrode 165 a is stacked over the light-transmitting electrode 167.
- 16 may be covered with a protective layer except for the electrode portion.
- an oxide conductive material containing indium (In) or titanium (Ti) can be given. More specifically, for example, In 2 O 3 , ZnO, SnO 2 , Ga 2 O 3 , TiO 2 , CeO 2, a mixed crystal of two or more thereof, or a material doped with these may be used.
- a translucent electrode can be formed by providing these materials by known means such as sputtering. Moreover, after forming the translucent electrode, thermal annealing for the purpose of making the translucent electrode transparent may be performed.
- the first electrode 165a is a positive electrode and the second electrode 165b is a negative electrode, and a current is passed through the p-type semiconductor layer 162, the light-emitting layer 163, and the n-type semiconductor layer 161 through both of them.
- the light emitting layer 163 emits light.
- Examples of the material of the first electrode 165a and the second electrode 165b include Al, Mo, Co, Zr, Sn, Nb, Fe, Cr, Ta, Ti, Au, Pt, V, Mn, Ni, Cu, Metals such as Hf, W, Ir, Zn, In, Pd, Nd, or Ag or alloys thereof, metal oxides such as tin oxide, zinc oxide, indium oxide, indium tin oxide (ITO), and zinc indium oxide (IZO) Examples thereof include a conductive film, an organic conductive compound such as polyaniline, polythiophene, or polypyrrole, or a mixture thereof.
- the electrode formation method is not particularly limited, and is a wet method such as a printing method, a spray method or a coating method, a physical method such as a vacuum deposition method, a sputtering method or an ion plating method, a CVD method or a plasma CVD method. It can be formed on the substrate according to a method appropriately selected in consideration of suitability with the material from among chemical methods such as the above.
- FIG. 17 Another mode of the light-emitting element is shown in FIG.
- an n-type semiconductor layer 161 is stacked on a substrate 169, and the n-type semiconductor exposed by cutting out part of the p-type semiconductor layer 162, the light-emitting layer 163, and the n-type semiconductor layer 161.
- a second electrode 165b is stacked on a portion of the layer 161 on the exposed surface of the semiconductor layer.
- the mist CVD apparatus 19 used in this example will be described with reference to FIG.
- the mist CVD apparatus 19 includes a susceptor 21 on which the substrate 20 is placed, a carrier gas supply means 22 for supplying a carrier gas, and a flow rate adjusting valve 23 for adjusting the flow rate of the carrier gas sent from the carrier gas supply means 22.
- a mist generating source 24 for storing the raw material solution 24a, a container 25 for containing water 25a, an ultrasonic transducer 26 attached to the bottom surface of the container 25, a supply pipe 27 made of a quartz tube having an inner diameter of 40 mm,
- a heater 28 is provided around the supply pipe 27.
- the susceptor 21 is made of quartz, and the surface on which the substrate 20 is placed is inclined from the horizontal plane. Both the supply pipe 27 and the susceptor 21 are made of quartz, so that impurities derived from the apparatus are prevented from being mixed into the film formed on the substrate 20.
- a susceptor 51 shown in FIG. 19 was used as the susceptor 21. Note that the inclination angle of the susceptor is 45 °, and the total area of the substrate and the susceptor in the supply pipe is set so that the susceptor region gradually increases and the discharge region gradually decreases as shown in FIG. As shown in FIG. 20, the susceptor region was configured to be larger than the discharge region.
- the ultrasonic vibrator 26 was vibrated at 2.4 MHz, and the vibration was propagated to the raw material solution 24a through the water 25a, whereby the raw material solution 24a was atomized to generate raw material fine particles.
- the raw material fine particles are introduced into the supply pipe 27 by the carrier gas, react in the supply pipe 27, and a film is laminated on the crystal substrate 20 by the CVD reaction on the film formation surface of the crystal substrate 20.
- the obtained crystal film was not cloudy and was a clean crystal. Moreover, the phase of the obtained crystal film was identified. Identification was performed by performing 2 ⁇ / ⁇ scanning at an angle of 15 to 95 degrees using an XRD diffractometer. The measurement was performed using CuK ⁇ rays. As a result, the obtained film was ⁇ -Ga 2 O 3 . The obtained crystalline semiconductor film had a thickness of 3.5 ⁇ m.
- Hall effect measurement was performed by the van der pauw method.
- the frequency of the applied magnetic field was 50 mHz at room temperature.
- the mobility was 2 (cm 2 / V ⁇ s).
- Example 2 A laminated structure was obtained in the same manner as in Example 1 except that a c-plane sapphire substrate having an off angle of 0.6 ° was used as the crystal substrate.
- the obtained crystal film had no white turbidity and was a clean crystal.
- the phase of the obtained crystal film was identified in the same manner as in Example 1.
- the obtained film was ⁇ -Ga 2 O 3 .
- the mobility was 2 (cm 2 / V ⁇ s).
- Example 3 A laminated structure was obtained in the same manner as in Example 1 except that a c-plane sapphire substrate having an off angle of 1 ° was used as the crystal substrate and the film formation temperature was 600 ° C.
- the obtained crystal film had no white turbidity and was a clean crystal. Further, the phase of the obtained crystal film was identified in the same manner as in Example 1. As a result, the obtained film was ⁇ -Ga 2 O 3 . Further, when the Hall effect measurement was performed in the same manner as in Example 1, the mobility was 2 (cm 2 / V ⁇ s).
- Example 4 A laminated structure was obtained in the same manner as in Example 1 except that a c-plane sapphire substrate having an off angle of 2 ° was used as the crystal substrate and the film formation temperature was 600 ° C.
- the obtained crystal film had no white turbidity and was a clean crystal.
- the phase of the obtained crystal film was identified in the same manner as in Example 1.
- the obtained film was ⁇ -Ga 2 O 3 .
- the mobility was 4 (cm 2 / V ⁇ s).
- Example 5 A laminated structure was obtained in the same manner as in Example 1 except that a c-plane sapphire substrate having an off angle of 4 ° was used as the crystal substrate and the film formation temperature was 600 ° C.
- the obtained crystal film had no white turbidity and was a clean crystal.
- the phase of the obtained crystal film was identified in the same manner as in Example 1.
- the obtained film was ⁇ -Ga 2 O 3 .
- the mobility was 12 (cm 2 / V ⁇ s).
- Example 6> A laminated structure was obtained in the same manner as in Example 1 except that a c-plane sapphire substrate having an off angle of 5 ° was used as the crystal substrate and the film formation temperature was 600 ° C.
- the obtained crystal film had no white turbidity and was a clean crystal. Further, the phase of the obtained crystal film was identified in the same manner as in Example 1. As a result, the obtained film was ⁇ -Ga 2 O 3 . Further, when the Hall effect measurement was performed in the same manner as in Example 1, the mobility was 4 (cm 2 / V ⁇ s).
- Example 7 A laminated structure was obtained in the same manner as in Example 1 except that a c-plane sapphire substrate having an off angle of 6 ° was used as the crystal substrate.
- the obtained crystal film had no white turbidity and was a clean crystal. Further, the phase of the obtained crystal film was identified in the same manner as in Example 1. As a result, the obtained film was ⁇ -Ga 2 O 3 . Further, when the Hall effect measurement was performed in the same manner as in Example 1, the mobility was 4 (cm 2 / V ⁇ s).
- Example 1 A laminated structure was obtained in the same manner as in Example 1 except that a c-plane sapphire substrate having no off-angle was used as the crystal substrate and the film formation temperature was 600 ° C. The resulting crystal film was partially clouded. However, when the phase of the obtained crystal film was identified in the same manner as in Example 1, the obtained film was ⁇ -Ga 2 O 3 . Further, when the Hall effect measurement was performed in the same manner as in Example 1, the mobility was not measurable.
- ⁇ Comparative example 2> A laminated structure was obtained in the same manner as in Example 1 except that a c-plane sapphire substrate having an off angle of 16 ° was used as the crystal substrate and the film formation temperature was 600 ° C. The obtained crystal film was cloudy. However, when the phase of the obtained crystal film was identified in the same manner as in Example 1, the obtained film was ⁇ -Ga 2 O 3 . Further, when the Hall effect measurement was performed in the same manner as in Example 1, the mobility was not measurable.
- Example 4 A laminated structure was obtained in the same manner as in Example 1 except that a c-plane sapphire substrate having an off angle of 20 ° was used as the crystal substrate and the film formation temperature was 600 ° C.
- the obtained crystal film was cloudy.
- the phase of the obtained crystal film was identified in the same manner as in Example 1, the obtained film was ⁇ -Ga 2 O 3 .
- the Hall effect measurement was performed in the same manner as in Example 1, the mobility was not measurable.
- ⁇ Comparative Example 5> A laminated structure was obtained in the same manner as in Comparative Example 4 except that the film formation temperature was 500 ° C. The obtained crystal film was cloudy. However, when the phase of the obtained crystal film was identified in the same manner as in Example 1, the obtained film was ⁇ -Ga 2 O 3 . Further, when the Hall effect measurement was performed in the same manner as in Example 1, the mobility was not measurable.
- Example 8 A laminated structure was obtained in the same manner as in Example 5. The surface of the obtained crystal film was observed using AFM. The observation result is shown in FIG. 21 as an AFM image. The center line average roughness was 1.125 ⁇ 10 ⁇ 1 nm, and the maximum height difference (PV value) was 8.118 ⁇ 10 ⁇ 1 nm. Further, in the same manner as described above, a laminated structure was manufactured again, and the Ra and PV values on the surface of the crystal film were measured using AFM. As a result, the center line average roughness was 1.042 ⁇ 10 ⁇ 1 nm, and the maximum height difference (PV value) was 1.050 nm. From these results, it can be seen that the crystal film of the present invention is excellent in surface smoothness.
- Example 9 Gallium acetylacetonate (0.05 mol / L) was used instead of gallium bromide, and stannous chloride dihydrate was used instead of germanium oxide and the atomic ratio of tin to gallium was 1: 0.001. Used, so that 1.5% by volume of 36% hydrochloric acid was used instead of the 48% hydrobromic acid solution, and nitrogen was used as the first carrier gas instead of oxygen as the carrier gas. Nitrogen gas (0.5 L / min) as the second carrier gas was used as the gas (1.0 L / min), the film formation temperature was 500 ° C., and the film formation time was 3 hours. Other than that was carried out similarly to Example 5, and obtained the laminated structure. When the phase of the obtained crystal film was identified, the obtained film was ⁇ -Ga 2 O 3 . Further, when the Hall effect measurement was performed in the same manner as in Example 1, the mobility was 24 (cm 2 / V ⁇ s).
- Example 10 A laminated structure was obtained in the same manner as in Example 1 except that an m-plane sapphire substrate having an off angle of 0.4 ° was used as the crystal substrate.
- the obtained crystal film had no white turbidity and was a clean crystal. Further, the phase of the obtained crystal film was identified in the same manner as in Example 1. As a result, the obtained film was ⁇ -Ga 2 O 3 .
- Example 6 A laminated structure was obtained in the same manner as in Example 10 except that an m-plane sapphire substrate having no off-angle was used as the crystal substrate.
- the obtained crystal film was cloudy. However, when the phase of the obtained crystal film was identified in the same manner as in Example 1, the obtained film was ⁇ -Ga 2 O 3 .
- Example 11 A laminated structure was obtained in the same manner as in Example 1 except that an a-plane sapphire substrate having an off angle of 0.4 ° was used as the crystal substrate.
- the obtained crystal film had no white turbidity and was a clean crystal. Further, the phase of the obtained crystal film was identified in the same manner as in Example 1. As a result, the obtained film was ⁇ -Ga 2 O 3 .
- Example 7 A laminated structure was obtained in the same manner as in Example 10 except that an a-plane sapphire substrate having no off-angle was used as the crystal substrate.
- the obtained crystal film was cloudy. However, when the phase of the obtained crystal film was identified in the same manner as in Example 1, the obtained film was ⁇ -Ga 2 O 3 .
- Example 12 A laminated structure was obtained in the same manner as in Example 1 except that an r-plane sapphire substrate having an off angle of 0.4 ° was used as the crystal substrate.
- the obtained crystal film had no white turbidity and was a clean crystal. Further, the phase of the obtained crystal film was identified in the same manner as in Example 1. As a result, the obtained film was ⁇ -Ga 2 O 3 .
- Example 8 A laminated structure was obtained in the same manner as in Example 10 except that an r-plane sapphire substrate having no off-angle was used as the crystal substrate.
- the obtained crystal film was cloudy. However, when the phase of the obtained crystal film was identified in the same manner as in Example 1, the obtained film was ⁇ -Ga 2 O 3 .
- Example 13> The laminated structure was the same as in Example 1 except that a c-plane sapphire substrate having an off angle of 8 ° was used as the crystal substrate, the film formation temperature was 580 ° C., and the film formation time was 130 minutes. Got the body.
- the obtained crystal film had no white turbidity and was a clean crystal. Further, the phase of the obtained crystal film was identified in the same manner as in Example 1. As a result, the obtained film was ⁇ -Ga 2 O 3 . Further, the surface of the obtained crystal film was subjected to AFM measurement. The results are shown in FIG.
- Example 14> The laminated structure was the same as in Example 1 except that a c-plane sapphire substrate having an off angle of 12 ° was used as the crystal substrate, the film formation temperature was 580 ° C., and the film formation time was 130 minutes. Got the body.
- the obtained crystal film had no white turbidity and was a clean crystal. Further, the phase of the obtained crystal film was identified in the same manner as in Example 1. As a result, the obtained film was ⁇ -Ga 2 O 3 . Further, the surface of the obtained crystal film was subjected to AFM measurement. The results are shown in FIG.
- the laminated structure of the present invention can be used in various fields such as semiconductors (for example, compound semiconductor electronic devices), electronic parts / electric equipment parts, optical / electrophotographic related apparatuses, industrial members, etc. Therefore, it is particularly useful for semiconductor devices.
- semiconductors for example, compound semiconductor electronic devices
- electronic parts / electric equipment parts for example, electronic parts / electric equipment parts
- optical / electrophotographic related apparatuses for example, optical / electrophotographic related apparatuses
- industrial members etc. Therefore, it is particularly useful for semiconductor devices.
- Mist CVD apparatus Crystal substrate 21 Susceptor 22 Carrier gas supply means 23 Flow control valve 24 Mist generation source 24a Raw material solution 25 Container 25a Water 26 Ultrasonic vibrator 27 Deposition chamber 28 Heater 51 Susceptor 52 Mist acceleration means 53 Substrate holding part 54 support portion 55 supply pipe 61 substrate / susceptor region 62 discharge region 101a n ⁇ type semiconductor layer 101b n + type semiconductor layer 102 p type semiconductor layer 103 metal layer 104 insulator layer 105a Schottky electrode 105b ohmic electrode 111a n ⁇ type semiconductor layer 111b n + type semiconductor layer 114 semi-insulator layer 115a gate electrode 115b source electrode 115c drain electrode 118 buffer layer 121a wide band gap n type semiconductor layer 121b narrow band gap n type semiconductor layer 121c n + Type semiconductor layer 123 p type semiconductor layer 124 semi-insulator layer 125a gate electrode 125b source electrode 125c drain electrode 128 buffer
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Abstract
Description
そのため、膜厚が1μm以上であり、結晶の品質も劣化していないα-Ga2O3薄膜が待ち望まれていた。
特許文献3~5には、コランダム型結晶構造を有する下地基板上に、コランダム型結晶構造を有する半導体層と、コランダム型結晶構造を有する絶縁膜とが積層された多層構造体が記載されている。
なお、特許文献2~5はいずれも本出願人による特許または特許出願に関する公報である。
また、本発明者らは、上記した各種知見を得た後、さらに検討を重ねて、本発明を完成させるに至った。
[1] コランダム構造を有する結晶基板上に、直接または別の層を介して、コランダム構造を有する結晶性酸化物を主成分として含む結晶膜が積層されている積層構造体であって、前記結晶基板が0.2°~12.0°のオフ角を有しており、前記結晶性酸化物が、インジウム、アルミニウムおよびガリウムから選ばれる1種または2種以上の金属を含むことを特徴とする積層構造体。
[2] 前記結晶基板のオフ角が1°~8°である前記[1]記載の積層構造体。
[3] 結晶基板がc面、m面、a面またはr面のサファイア基板である前記[1]または[2]に記載の積層構造体。
[4] 結晶膜の膜厚が1μm以上である前記[1]~[3]のいずれかに記載の積層構造体。
[5] 原子間力顕微鏡を用いて測定される結晶膜の膜表面の中心線平均粗さ(Ra)が10nm以下であり、最大高低差(P-V値)が100nm以下である前記[1]~[4]のいずれかに記載の積層構造体。
[6] 結晶性酸化物が半導体である前記[1]~[5]のいずれかに記載の積層構造体。
[7] 結晶膜が、さらにドーパントを含んでいる前記[6]記載の積層構造体。
[8] 原料溶液を霧化してミストを発生させ、ついで、キャリアガスを前記ミストに供給して、前記キャリアガスによって前記ミストを基板へ供給し、前記ミストを熱反応させて、前記基板表面の一部または全部に、結晶性酸化物からなる結晶膜を積層する積層構造体の製造方法であって、前記基板がコランダム構造を有する結晶基板であり、前記結晶基板が、0.2°~12.0°のオフ角を有しており、前記原料溶液が、インジウム、アルミニウムおよびガリウムから選ばれる1種または2種以上の金属を含んでいることを特徴とする製造方法。
[9] 熱反応を、400℃~700℃の温度で行う前記[8]記載の製造方法。
[10] 前記結晶基板のオフ角が2°~5°である前記[8]または[9]に記載の製造方法。
[11] 結晶基板がc面、m面、a面またはr面のサファイア基板である前記[8]~[10]のいずれかに記載の製造方法。
[12] 前記[6]または[7]に記載の積層構造体と電極とを少なくとも備えている半導体装置。
[13] コランダム構造を有する結晶性酸化物を主成分として含む結晶膜であって、前記結晶膜が0.2°~12.0°のオフ角を有しており、前記結晶性酸化物が、インジウム、アルミニウムおよびガリウムから選ばれる1種または2種以上の金属を含むことを特徴とする結晶膜。
[14] 前記結晶膜のオフ角が1°~8°である前記[13]記載の結晶膜。
[15] 結晶膜がc面、m面、a面またはr面の結晶膜である前記[13]または[14]に記載の結晶膜。
[16] 結晶膜の膜厚が1μm以上である前記[13]~[15]のいずれかに記載の結晶膜。
[17] 原子間力顕微鏡を用いて測定される結晶膜の膜表面の中心線平均粗さ(Ra)が10nm以下であり、最大高低差(P-V値)が100nm以下である前記[13]~[16]のいずれかに記載の結晶膜。
[18] 結晶性酸化物が半導体である前記[13]~[17]のいずれかに記載の結晶膜。
[19] 結晶膜が、さらにドーパントを含んでいる前記[18]記載の結晶膜。
[20] 前記[18]または[19]に記載の結晶膜と、電極とを少なくとも備えている半導体装置。
図1は、本発明に係るショットキーバリアダイオード(SBD)の一例を示している。図1のSBDは、n-型半導体層101a、n+型半導体層101b、ショットキー電極105aおよびオーミック電極105bを備えている。
図4は、本発明に係る金属半導体電界効果トランジスタ(MESFET)の一例を示している。図4のMESFETは、n-型半導体層111a、n+型半導体層111b、緩衝層(バッファ層)118、半絶縁体層114、ゲート電極115a、ソース電極115bおよびドレイン電極115cを備えている。
図5は、本発明に係る光電子移動度トランジスタ(HEMT)の一例を示している。図5のHEMTは、バンドギャップの広いn型半導体層121a、バンドギャップの狭いn型半導体層121b、n+型半導体層121c、半絶縁体層124、緩衝層128、ゲート電極125a、ソース電極125bおよびドレイン電極125cを備えている。
図5のHEMTでは、ゲート電極下に良好な空乏層が形成されるので、ドレイン電極からソース電極に流れる電流を効率よく制御することができる。また、本発明においては、さらにリセス構造とすることで、ノーマリーオフを発現することができる。
本発明の半導体装置がMOSFETである場合の一例を図6に示す。図6のMOSFETは、トレンチ型のMOSFETであり、n-型半導体層131a、n+型半導体層131b及び131c、ゲート絶縁膜134、ゲート電極135a、ソース電極135bおよびドレイン電極135cを備えている。
図9は、本発明の半導体装置がSITである場合の一例を示す。図9のSITは、n-型半導体層141a、n+型半導体層141b及び141c、ゲート電極145a、ソース電極145bおよびドレイン電極145cを備えている。
図9のSITのオン状態では、前記ソース電極145bと前記ドレイン電極145cとの間に電圧を印可し、前記ゲート電極145aに前記ソース電極145bに対して正の電圧を与えると、前記n-型半導体層141a内にチャネル層が形成され、電子が前記n-型半導体層141aに注入され、ターンオンする。オフ状態は、前記ゲート電極の電圧を0Vにすることにより、チャネル層ができなくなり、n-型半導体層141aが空乏層で満たされた状態になり、ターンオフとなる。
本発明の半導体装置が発光ダイオード(LED)である場合の一例を図16に示す。図16の半導体発光素子は、第2の電極165b上にn型半導体層161を備えており、n型半導体層161上には、発光層163が積層されている。そして、発光層163上には、p型半導体層162が積層されている。p型半導体層162上には、発光層163が発生する光を透過する透光性電極167を備えており、透光性電極167上には、第1の電極165aが積層されている。なお、図16の半導体発光素子は、電極部分を除いて保護層で覆われていてもよい。
1.成膜装置
図18を用いて、本実施例で用いたミストCVD装置19を説明する。ミストCVD装置19は、基板20を載置するサセプタ21と、キャリアガスを供給するキャリアガス供給手段22と、キャリアガス供給手段22から送り出されるキャリアガスの流量を調節するための流量調節弁23と、原料溶液24aが収容されるミスト発生源24と、水25aが入れられる容器25と、容器25の底面に取り付けられた超音波振動子26と、内径40mmの石英管からなる供給管27と、供給管27の周辺部に設置されたヒーター28を備えている。サセプタ21は、石英からなり、基板20を載置する面が水平面から傾斜している。供給管27とサセプタ21をどちらも石英で作製することにより、基板20上に形成される膜内に装置由来の不純物が混入することを抑制している。
なお、サセプタ21として、図19に示されるサセプタ51を用いた。なお、サセプタの傾斜角を45°とし、供給管内の基板・サセプタの総面積を、図19に示される通り、サセプタ領域を徐々に大きくなるようにし、排出領域を徐々に狭くなるようにし、図20に示される通り、サセプタ領域を排出領域よりも大きくなるように構成した。
臭化ガリウムと酸化ゲルマニウムをガリウムに対するゲルマニウムの原子比が1:0.05となるように水溶液を調整した。この際、48%臭化水素酸溶液を体積比で10%を含有させた。条件1では、酸化ゲルマニウムの濃度は、5.0×10-3mol/Lとした。この原料溶液24aをミスト発生源24内に収容した。また、結晶基板20として、0.2°のオフ角を有するc面サファイア基板(1辺が10mmの正方形で厚さ600μm)を用いた。
結晶基板20をサセプタ21上に設置させ、ヒーター28を作動させて供給管27内の温度を500℃にまで昇温させた。次に、流量調節弁23を開いてキャリアガス源22からキャリアガスを供給管27内に供給し、供給管27の雰囲気をキャリアガスで十分に置換した後、キャリアガスの流量を5L/minに調節した。キャリアガスとしては、酸素ガスを用いた。
次に、超音波振動子26を2.4MHzで振動させ、その振動を、水25aを通じて原料溶液24aに伝播させることによって、原料溶液24aを微粒子化させて、原料微粒子を生成した。
この原料微粒子が、キャリアガスによって供給管27内に導入され、供給管27内で反応して、結晶基板20の成膜面でのCVD反応によって結晶基板20上に膜を積層し、積層構造体を得た。
得られた結晶膜は、白濁もなく、きれいな結晶であった。また、得られた結晶膜の相の同定をした。同定は、XRD回折装置を用いて、15度から95度の角度で2θ/ωスキャンを行うことにより行った。測定は、CuKα線を用いて行った。その結果、得られた膜はα-Ga203であった。また、得られた結晶性半導体膜の膜厚は3.5μmであった。
結晶基板として、0.6°のオフ角を有するc面サファイア基板を用いたこと以外は、実施例1と同様にして、積層構造体を得た。
得られた結晶膜は、白濁もなく、きれいな結晶であった。また、実施例1と同様にして、得られた結晶膜の相の同定を実施したところ、得られた膜はα-Ga203であった。また、実施例1と同様にして、ホール効果測定を行ったところ、移動度は2(cm2/V・s)であった。
結晶基板として、1°のオフ角を有するc面サファイア基板を用いたこと、および成膜温度を600℃としたこと以外は、実施例1と同様にして、積層構造体を得た。
得られた結晶膜は、白濁もなく、きれいな結晶であった。また、実施例1と同様にして、得られた結晶膜の相の同定を実施したところ、得られた膜はα-Ga203であった。また、実施例1と同様にして、ホール効果測定を行ったところ、移動度は2(cm2/V・s)であった。
結晶基板として、2°のオフ角を有するc面サファイア基板を用いたこと、および成膜温度を600℃としたこと以外は、実施例1と同様にして、積層構造体を得た。
得られた結晶膜は、白濁もなく、きれいな結晶であった。また、実施例1と同様にして、得られた結晶膜の相の同定を実施したところ、得られた膜はα-Ga203であった。また、実施例1と同様にして、ホール効果測定を行ったところ、移動度は4(cm2/V・s)であった。
結晶基板として、4°のオフ角を有するc面サファイア基板を用いたこと、および成膜温度を600℃としたこと以外は、実施例1と同様にして、積層構造体を得た。
得られた結晶膜は、白濁もなく、きれいな結晶であった。また、実施例1と同様にして、得られた結晶膜の相の同定を実施したところ、得られた膜はα-Ga203であった。また、実施例1と同様にして、ホール効果測定を行ったところ、移動度は12(cm2/V・s)であった。
結晶基板として、5°のオフ角を有するc面サファイア基板を用いたこと、および成膜温度を600℃としたこと以外は、実施例1と同様にして、積層構造体を得た。
得られた結晶膜は、白濁もなく、きれいな結晶であった。また、実施例1と同様にして、得られた結晶膜の相の同定を実施したところ、得られた膜はα-Ga203であった。また、実施例1と同様にして、ホール効果測定を行ったところ、移動度は4(cm2/V・s)であった。
結晶基板として、6°のオフ角を有するc面サファイア基板を用いたこと以外は、実施例1と同様にして、積層構造体を得た。
得られた結晶膜は、白濁もなく、きれいな結晶であった。また、実施例1と同様にして、得られた結晶膜の相の同定を実施したところ、得られた膜はα-Ga203であった。また、実施例1と同様にして、ホール効果測定を行ったところ、移動度は4(cm2/V・s)であった。
結晶基板として、オフ角を有さないc面サファイア基板を用いたこと、および成膜温度を600℃としたこと以外は、実施例1と同様にして、積層構造体を得た。
得られた結晶膜は、一部白濁が見られた。しかし、実施例1と同様にして、得られた結晶膜の相の同定を実施したところ、得られた膜はα-Ga203であった。また、実施例1と同様にして、ホール効果測定を行ったところ、移動度は測定不可であった。
結晶基板として、16°のオフ角を有するc面サファイア基板を用いたこと、および成膜温度を600℃としたこと以外は、実施例1と同様にして、積層構造体を得た。
得られた結晶膜は白濁していた。しかし、実施例1と同様にして、得られた結晶膜の相の同定を実施したところ、得られた膜はα-Ga203であった。また、実施例1と同様にして、ホール効果測定を行ったところ、移動度は測定不可であった。
成膜温度を500℃としたこと以外は、比較例2と同様にして、積層構造体を得た。
得られた結晶膜は白濁していた。しかし、実施例1と同様にして、得られた結晶膜の相の同定を実施したところ、得られた膜はα-Ga203であった。また、実施例1と同様にして、ホール効果測定を行ったところ、移動度は測定不可であった。
結晶基板として、20°のオフ角を有するc面サファイア基板を用いたこと、および成膜温度を600℃としたこと以外は、実施例1と同様にして、積層構造体を得た。
得られた結晶膜は白濁していた。しかし、実施例1と同様にして、得られた結晶膜の相の同定を実施したところ、得られた膜はα-Ga203であった。また、実施例1と同様にして、ホール効果測定を行ったところ、移動度は測定不可であった。
成膜温度を500℃としたこと以外は、比較例4と同様にして、積層構造体を得た。
得られた結晶膜は白濁していた。しかし、実施例1と同様にして、得られた結晶膜の相の同定を実施したところ、得られた膜はα-Ga203であった。また、実施例1と同様にして、ホール効果測定を行ったところ、移動度は測定不可であった。
実施例5と同様にして、積層構造体を得た。得られた結晶膜につき、AFMを用いて、その表面を観察した。観察結果をAFM像として図21に示す。なお、中心線平均粗さは1.125×10-1nmであり、最大高低差(PV値)は8.118×10-1nmであった。また、前記と同様にして、再度、積層構造体を製作し、AFMを用いて、結晶膜表面のRaとPV値を測定した。その結果、中心線平均粗さは1.042×10-1nmであり、最大高低差(PV値)は1.050nmであった。これらの結果より、本発明の結晶膜は、表面平滑性に優れていることがわかる。
臭化ガリウムに代えてガリウムアセチルアセトナート(0.05mol/L)を用いたこと、および酸化ゲルマニウムに代えて塩化第一スズ二水和物をガリウムに対するスズの原子比が1:0.001となるようにして用いたこと、48%臭化水素酸溶液に代えて36%塩酸を体積比で1.5%用いたこと、キャリアガスとしての酸素に代えて、第1のキャリアガスとしての窒素ガス(1.0L/分)を、第2のキャリアガスとしての窒素ガス(0.5L/分)を用いたこと、および成膜温度を500℃とし、さらに成膜時間を3時間としたこと以外は、実施例5と同様にして、積層構造体を得た。得られた結晶膜の相の同定を実施したところ、得られた膜はα-Ga203であった。また、実施例1と同様にして、ホール効果測定を行ったところ、移動度は24(cm2/V・s)であった。
結晶基板として、0.4°のオフ角を有するm面サファイア基板を用いたこと以外は、実施例1と同様にして積層構造体を得た。得られた結晶膜は、白濁もなく、きれいな結晶であった。また、実施例1と同様にして、得られた結晶膜の相の同定を実施したところ、得られた膜はα-Ga203であった。
結晶基板として、オフ角を有さないm面サファイア基板を用いたこと以外は実施例10と同様にして積層構造体を得た。得られた結晶膜は白濁していた。しかし、実施例1と同様にして、得られた結晶膜の相の同定を実施したところ、得られた膜はα-Ga203であった。
結晶基板として、0.4°のオフ角を有するa面サファイア基板を用いたこと以外は、実施例1と同様にして積層構造体を得た。得られた結晶膜は、白濁もなく、きれいな結晶であった。また、実施例1と同様にして、得られた結晶膜の相の同定を実施したところ、得られた膜はα-Ga203であった。
結晶基板として、オフ角を有さないa面サファイア基板を用いたこと以外は実施例10と同様にして積層構造体を得た。得られた結晶膜は白濁していた。しかし、実施例1と同様にして、得られた結晶膜の相の同定を実施したところ、得られた膜はα-Ga203であった。
結晶基板として、0.4°のオフ角を有するr面サファイア基板を用いたこと以外は、実施例1と同様にして積層構造体を得た。得られた結晶膜は、白濁もなく、きれいな結晶であった。また、実施例1と同様にして、得られた結晶膜の相の同定を実施したところ、得られた膜はα-Ga203であった。
結晶基板として、オフ角を有さないr面サファイア基板を用いたこと以外は実施例10と同様にして積層構造体を得た。得られた結晶膜は白濁していた。しかし、実施例1と同様にして、得られた結晶膜の相の同定を実施したところ、得られた膜はα-Ga203であった。
結晶基板として、8°のオフ角を有するc面サファイア基板を用いたこと、成膜温度を580℃とし、成膜時間を130分としたこと以外は、実施例1と同様にして、積層構造体を得た。
得られた結晶膜は、白濁もなく、きれいな結晶であった。また、実施例1と同様にして、得られた結晶膜の相の同定を実施したところ、得られた膜はα-Ga203であった。また、得られた結晶膜の表面をAFM測定した。結果を図22に示す。
結晶基板として、12°のオフ角を有するc面サファイア基板を用いたこと、成膜温度を580℃とし、成膜時間を130分としたこと以外は、実施例1と同様にして、積層構造体を得た。
得られた結晶膜は、白濁もなく、きれいな結晶であった。また、実施例1と同様にして、得られた結晶膜の相の同定を実施したところ、得られた膜はα-Ga203であった。また、得られた結晶膜の表面をAFM測定した。結果を図23に示す。
20 結晶基板
21 サセプタ
22 キャリアガス供給手段
23 流量調節弁
24 ミスト発生源
24a 原料溶液
25 容器
25a 水
26 超音波振動子
27 成膜室
28 ヒーター
51 サセプタ
52 ミスト加速手段
53 基板保持部
54 支持部
55 供給管
61 基板・サセプタ領域
62 排出領域
101a n-型半導体層
101b n+型半導体層
102 p型半導体層
103 金属層
104 絶縁体層
105a ショットキー電極
105b オーミック電極
111a n-型半導体層
111b n+型半導体層
114 半絶縁体層
115a ゲート電極
115b ソース電極
115c ドレイン電極
118 緩衝層
121a バンドギャップの広いn型半導体層
121b バンドギャップの狭いn型半導体層
121c n+型半導体層
123 p型半導体層
124 半絶縁体層
125a ゲート電極
125b ソース電極
125c ドレイン電極
128 緩衝層
129 基板
131a n-型半導体層
131b 第1のn+型半導体層
131c 第2のn+型半導体層
132 p型半導体層
134 ゲート絶縁膜
135a ゲート電極
135b ソース電極
135c ドレイン電極
138 緩衝層
139 半絶縁体層
141a n-型半導体層
141b 第1のn+型半導体層
141c 第2のn+型半導体層
142 p型半導体層
145a ゲート電極
145b ソース電極
145c ドレイン電極
151 n型半導体層
151a n-型半導体層
151b n+型半導体層
152 p型半導体層
154 ゲート絶縁膜
155a ゲート電極
155b エミッタ電極
155c コレクタ電極
161 n型半導体層
162 p型半導体層
163 発光層
165a 第1の電極
165b 第2の電極
167 透光性電極
169 基板
Claims (20)
- コランダム構造を有する結晶基板上に、直接または別の層を介して、コランダム構造を有する結晶性酸化物を主成分として含む結晶膜が積層されている積層構造体であって、前記結晶基板が0.2°~12.0°のオフ角を有しており、前記結晶性酸化物が、インジウム、アルミニウムおよびガリウムから選ばれる1種または2種以上の金属を含むことを特徴とする積層構造体。
- 前記結晶基板のオフ角が1°~8°である請求項1記載の積層構造体。
- 結晶基板がc面、m面、a面またはr面のサファイア基板である請求項1または2に記載の積層構造体。
- 結晶膜の膜厚が1μm以上である請求項1~3のいずれかに記載の積層構造体。
- 原子間力顕微鏡を用いて測定される結晶膜の膜表面の中心線平均粗さ(Ra)が10nm以下であり、最大高低差(P-V値)が100nm以下である請求項1~4のいずれかに記載の積層構造体。
- 結晶性酸化物が半導体である請求項1~5のいずれかに記載の積層構造体。
- 結晶膜が、さらにドーパントを含んでいる請求項6記載の積層構造体。
- 原料溶液を霧化してミストを発生させ、ついで、キャリアガスを前記ミストに供給して、前記キャリアガスによって前記ミストを基板へ供給し、前記ミストを熱反応させて、前記基板表面の一部または全部に、結晶性酸化物からなる結晶膜を積層する積層構造体の製造方法であって、
前記基板がコランダム構造を有する結晶基板であり、前記結晶基板が、0.2°~12.0°のオフ角を有しており、前記原料溶液が、インジウム、アルミニウムおよびガリウムから選ばれる1種または2種以上の金属を含んでいることを特徴とする製造方法。 - 熱反応を、400℃~700℃の温度で行う請求項8記載の製造方法。
- 前記結晶基板のオフ角が2°~5°である請求項8または9に記載の製造方法。
- 結晶基板がc面、m面、a面またはr面のサファイア基板である請求項8~10のいずれかに記載の製造方法。
- 請求項6または7に記載の積層構造体と電極とを少なくとも備えている半導体装置。
- コランダム構造を有する結晶性酸化物を主成分として含む結晶膜であって、前記結晶膜が0.2°~12.0°のオフ角を有しており、前記結晶性酸化物が、インジウム、アルミニウムおよびガリウムから選ばれる1種または2種以上の金属を含むことを特徴とする結晶膜。
- 前記結晶膜のオフ角が1°~8°である請求項13記載の結晶膜。
- 結晶膜がc面、m面、a面またはr面の結晶膜である請求項13または14に記載の結晶膜。
- 結晶膜の膜厚が1μm以上である請求項13~15のいずれかに記載の結晶膜。
- 原子間力顕微鏡を用いて測定される結晶膜の膜表面の中心線平均粗さ(Ra)が10nm以下であり、最大高低差(P-V値)が100nm以下である請求項13~16のいずれかに記載の結晶膜。
- 結晶性酸化物が半導体である請求項13~17のいずれかに記載の結晶膜。
- 結晶膜が、さらにドーパントを含んでいる請求項18記載の結晶膜。
- 請求項18または19に記載の結晶膜と、電極とを少なくとも備えている半導体装置。
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US20170278706A1 (en) | 2017-09-28 |
EP3190608A4 (en) | 2017-07-26 |
JPWO2016035696A1 (ja) | 2017-10-19 |
CN106796891A (zh) | 2017-05-31 |
EP3190608B1 (en) | 2020-11-25 |
EP3190608A1 (en) | 2017-07-12 |
EP3783662A1 (en) | 2021-02-24 |
JP6916426B2 (ja) | 2021-08-11 |
CN106796891B (zh) | 2020-07-17 |
US10043664B2 (en) | 2018-08-07 |
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