WO2014103735A1 - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
WO2014103735A1
WO2014103735A1 PCT/JP2013/083310 JP2013083310W WO2014103735A1 WO 2014103735 A1 WO2014103735 A1 WO 2014103735A1 JP 2013083310 W JP2013083310 W JP 2013083310W WO 2014103735 A1 WO2014103735 A1 WO 2014103735A1
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WIPO (PCT)
Prior art keywords
wiring
circuit
resistor
semiconductor device
resistance value
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PCT/JP2013/083310
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French (fr)
Japanese (ja)
Inventor
謙治 浅木
研一 越後谷
鉄也 新井
Original Assignee
ピーエスフォー ルクスコ エスエイアールエル
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Publication of WO2014103735A1 publication Critical patent/WO2014103735A1/en

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1057—Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018557—Coupling arrangements; Impedance matching circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018585—Coupling arrangements; Interface arrangements using field effect transistors only programmable

Definitions

  • the present invention relates to a semiconductor device, and more particularly to a semiconductor device including an input / output circuit capable of adjusting the impedance of an output buffer.
  • a calibration circuit for adjusting the impedance of the output buffer may be provided in order to adjust the impedance of the output terminal (see Patent Document 1).
  • the output buffer has a pull-up output unit and a pull-down output unit, and these impedances are controlled based on the pull-up impedance code and the pull-down impedance code generated by the calibration circuit, respectively.
  • the calibration circuit has a replica buffer with substantially the same configuration as the output buffer of the input / output circuit.
  • the impedance of the replica buffer is adjusted by comparing the voltage of the calibration terminal with the reference voltage with an external resistor connected to the calibration terminal. Then, the adjustment contents of the replica buffer are reflected in the output buffer.
  • the impedance of the replica buffer and the output buffer is adjusted according to the external resistance connected to the calibration terminal.
  • the impedance of the adjusted output buffer may slightly deviate from the desired impedance due to this difference. They came up with the idea. It is more desirable to adjust the impedance of the output buffer after correcting such adjustment deviation based on the wiring structure.
  • a semiconductor device includes a data terminal, a calibration terminal, an output buffer, a first resistor connected to the output buffer at one end, the data terminal, and the first resistor.
  • a third wiring connecting the end and the comparison circuit, and a resistance value of the third resistance portion is larger than a resistance value of the first wiring and a resistance value of the second wiring. It is characterized by.
  • a semiconductor device includes an output buffer and a calibration circuit.
  • the calibration circuit includes a replica circuit and a comparator, adjusts the impedance of the replica circuit based on the output of the comparator, and reflects the adjustment result in the output buffer. Furthermore, the calibration circuit includes a second damping resistor and a correction resistor connected in series between the replica circuit and one input terminal of the comparator.
  • the impedance of the output buffer in the semiconductor device can be set more suitably.
  • FIG. 1 is a block diagram illustrating an overall configuration of a semiconductor device according to an embodiment of the present invention. It is a block diagram which shows the structure of an input / output circuit. It is a circuit diagram of a unit buffer. It is a circuit diagram of a calibration circuit. It is a circuit diagram of a pull-up circuit. It is a circuit diagram of a pull-down circuit. It is a circuit diagram which shows the connection relationship of a data terminal and an output circuit when the wiring resistance of the wiring which passes an electrostatic protection part is considered. It is a schematic diagram which shows the layout between a data terminal and an output circuit. It is the figure which showed typically the multilayer wiring structure which the semiconductor device by embodiment contains. It is a circuit diagram which shows the structure of the adjustment buffer in the conventional calibration circuit.
  • FIG. 3 is a circuit diagram (first configuration example) illustrating a connection relationship among a pull-up circuit, a correction resistor, an electrostatic protection unit, a comparator, and a calibration terminal in the calibration circuit of the present embodiment. It is a schematic diagram which shows the layout between the calibration terminal in the 1st structural example, a pull-up circuit, and a comparator.
  • FIG. 6 is a circuit diagram (second configuration example) showing a connection relationship among a pull-up circuit, a correction resistor, an electrostatic protection unit, a comparator, and a calibration terminal in the calibration circuit of the present embodiment. It is a schematic diagram which shows the layout between the data terminal and output circuit in a 2nd structural example.
  • FIG. 10 is a circuit diagram (third configuration example) illustrating a connection relationship among a pull-up circuit, a correction resistor, an electrostatic protection unit, a comparator, and a calibration terminal in the calibration circuit of the present embodiment.
  • FIG. 1 is a block diagram showing an overall configuration of a semiconductor device 10 according to a preferred embodiment of the present invention.
  • the semiconductor device 10 is a DRAM integrated on a single semiconductor chip, and is mounted on the external substrate 2.
  • the external substrate 2 is a wiring substrate such as a mother board and is provided with an external resistor Re.
  • One end of the external resistor Re is electrically connected to the calibration terminal ZQ of the semiconductor device 10. Details of the calibration circuit 100 will be described later.
  • the external resistor Re has a resistance value of 240 ⁇ , and the ground potential VSS is supplied to the other end of the external resistor Re.
  • the semiconductor device 10 has a memory cell array 11.
  • the memory cell array 11 includes a plurality of word lines WL and a plurality of bit lines BL, and memory cells MC are arranged at intersections thereof.
  • the word line WL is selected by the row decoder 12, and the bit line BL is selected by the column decoder 13.
  • a clock terminal 23 As external terminals of the semiconductor device 10, a clock terminal 23, a command address terminal 21, a chip select terminal 22, a data terminal 24, power supply terminals 25 and 26, and a calibration terminal ZQ are provided.
  • the clock terminal 23 is a terminal to which external clock signals CK and / CK are input.
  • a signal having “/” at the head of a signal name means an inverted signal of the corresponding signal or a low active signal. Therefore, external clock signal / CK is an inverted signal of external clock signal CK.
  • the external clock signals CK and / CK are both supplied to the clock input circuit 36.
  • the external clock signals CK and / CK supplied to the clock input circuit 36 are supplied to the clock generation circuit 54.
  • Clock generation circuit 54 generates internal clock signal ICLK based on external clock signals CK and / CK.
  • the internal clock signal ICLK is supplied to circuit blocks such as the address latch circuit 32, the command decode circuit 34, the calibration circuit 100, and the latch circuit 15, and defines the operation timing of these circuit blocks.
  • the command address signal CA is input to the command address terminal 21.
  • the command address signal constitutes a command signal CMD and an address signal ADD.
  • a chip select signal / CS is input to the chip select terminal 22.
  • These signals are supplied to a command address (CA) input circuit 31.
  • the address signal ADD is supplied to the address latch circuit 32, and the command signal CMD is supplied to the command decode circuit 34.
  • the address latch circuit 32 latches the address signal ADD in synchronization with the internal clock ICLK. Of the latched address signal ADD, the row address is supplied to the row decoder 12 and the column address is supplied to the column decoder 13. If the mode register set is entered, the address signal ADD is supplied to the mode register 14 as a mode setting signal.
  • the mode register 14 is set with a parameter indicating the operation mode of the semiconductor device 10.
  • FIG. 1 shows the drive capability setting signal DS among the parameters of the operation mode indicated by the mode register. Although details will be described later, the drive capability setting signal DS designates one or more unit buffers to be activated at the time of data output among the plurality of unit buffers in the input / output circuit 16.
  • the command decode circuit 34 generates various internal commands by holding, decoding and counting the command signal CMD in synchronization with the internal clock ICLK.
  • the internal commands include an active signal IACT, a column signal ICOL, a mode register set signal MRS, a calibration signal ZQCOM, and the like.
  • the active signal IACT is activated when the command signal CMD indicates row access (active command).
  • the address signal ADD latched by the address latch circuit 32 is supplied to the row decoder 12 as a row address. As a result, the word line WL specified by the row address is selected.
  • the column signal ICOL is activated when the command signal CMD indicates column access.
  • column access means read access when the command signal is a read command, and write access when the command signal is a write command.
  • the address signal ADD latched by the address latch circuit 32 is supplied to the column decoder 13 as a column address. As a result, the bit line BL specified by the column address is selected.
  • the mode register set signal MRS is activated when the command signal CMD indicates a mode register set command. Therefore, when the mode register set command is input, the semiconductor device 10 is entered into the mode register set. When the mode signal is input from the command address terminal 21 in synchronization therewith, the set value of the mode register 14 can be rewritten.
  • the calibration signal ZQCOM is activated when the command signal CMD indicates a calibration command.
  • the calibration command is issued not only when the semiconductor device 10 is initialized but also periodically during normal operation.
  • the calibration signal ZQCOM activates the calibration circuit 100.
  • the calibration circuit 100 performs a calibration operation in synchronization with the internal clock ICLK, and thereby adjusts the impedance of the output circuit 101 included in the input / output circuit 16. Details of the calibration circuit 100 and the output circuit 101 will be described later.
  • the power supply terminals 25 are supplied with power supply potentials VDD and VSS.
  • the power supply potentials VDD and VSS are supplied to the internal power supply generation circuit 39 via the power supply terminal 25.
  • the internal power supply generation circuit 39 generates various internal potentials VPP, VOD, VARY, and VPERI based on the power supply potentials VDD and VSS.
  • Internal potential VPP is mainly used in row decoder 12, internal potentials VOD and VARY are used in sense amplifiers in memory cell array 11, and internal potential VPERI is used in many other circuit blocks.
  • Power supply potentials VDDQ and VSSQ are supplied to the power supply terminal 26.
  • the power supply potentials VDDQ and VSSQ are supplied to the input / output circuit 16 and used as operation power for the output circuit 101 included in the input / output circuit 16.
  • the power supply potential VDDQ is the same as the power supply potential VDD
  • the power supply potential VSSQ is the same as the power supply potential VSS.
  • the power supply noise generated by the operation of the output circuit 101 is not propagated to other circuits. The route is separated. However, in the present invention, it is not essential to perform such power supply path separation.
  • FIG. 2 is a block diagram showing the configuration of the input / output circuit 16.
  • the input / output circuit 16 includes an output circuit 101, an input buffer 170, pre-stage circuits 141, 142, and 143, and an output control circuit 150.
  • the input / output circuit 16 further includes an electrostatic protection unit 160. Details of the electrostatic protection unit 160 will be described later.
  • the output circuit 101 includes three output units 110, 120, and 130. However, the number of output units of the present invention is not limited to three.
  • the output unit 110 includes four unit buffers (output buffers) 111 to 114 and damping resistors R11 and R12 connected in parallel with each other at 60 ⁇ , and the output unit 120 includes two unit buffers (output buffers) 121 and 122.
  • the output unit 130 includes one unit buffer (output buffer) 131 and a 120 ⁇ (r1) damping resistor R14 (first resistance unit, first damping resistor).
  • the damping resistors R11 to R14 for example, a high resistance wiring such as a diffusion layer, tungsten (W), or titanium nitride (TiN) can be used.
  • each of the unit buffers 111 to 114, 121, 122, and 131 can adjust the impedance (first impedance).
  • the impedance of each of the unit buffers 111 to 114, 121, 122, 131 is adjusted to 120 ⁇ .
  • the calibration operation can be simplified by collectively adjusting the impedances of a plurality of unit buffers with one calibration circuit.
  • each output unit 110 is adjusted to drive the data terminal 24 at 60 ⁇
  • the output unit 120 is adjusted to drive the data terminal 24 at 120 ⁇
  • the output unit 130 is adjusted to the data terminal 24. Is adjusted to drive at 240 ⁇ . That is, each output unit is designed to have an impedance substantially equal to a value obtained by dividing the resistance value of the external resistor Re by the number of unit buffers included in the output unit after adjusting the impedance of each unit buffer.
  • Each of the unit buffers 111 to 114, 121, 122, 131 is activated when the output unit 110, 120, 130 including the unit buffer is activated during the read operation, and the data terminal 24 is set to the high level. Drive to either low level.
  • Pre-stage circuits 141 to 143 are provided in front of the output units 110 to 130, respectively.
  • the pre-stage circuits 141 to 143 specify whether or not to activate the corresponding output unit, and adjust the impedance of the unit buffer included in the corresponding output unit.
  • activation signals 151P to 153P and activation signals 151N to 153N are supplied from the output control circuit 150 to the pre-stage circuits 141 to 143, and an impedance adjustment code DRZQ is supplied from the calibration circuit 100 in common. Is done.
  • the pre-stage circuits 141 to 143 indicate the corresponding output units according to the impedance adjustment code DRZQ. It designates which of a plurality of output transistors (described later) included in each of the unit buffers 111 to 114, 121, 122, 131 to be turned on. On / off of these output transistors is designated by activation signals 141P to 143P and activation signals 141N to 143N.
  • the output control circuit 150 designates the output units 110 to 130 to be activated among the plurality of output units 110 to 130, and designates the output logic level of the unit buffer to be activated.
  • the designation of the output unit to be activated is based on the drive capability setting signal DS supplied from the mode register 14.
  • the output control circuit 150 selects the output unit to be activated based on the drive capability setting signal DS, thereby changing the number of unit buffers for driving the data terminals.
  • the impedance (output impedance) of the output terminal changes.
  • the unit buffers 111 to 114, 121, 122, 131 are connected in parallel between the output control circuit 150 and the data terminal 24.
  • the output impedance decreases.
  • the output impedance increases.
  • FIG. 3 is a circuit diagram of the unit buffer 131.
  • the unit buffer 131 includes a plurality (five in this embodiment) of P-channel MOS transistors (output transistors, first transistors) connected in parallel between the power supply line (power supply potential VDDQ) and the node B.
  • the node B is connected to the data terminal 24 via the damping resistor R14 and the electrostatic protection unit 160.
  • a part composed of P channel MOS transistors 211 to 215 constitutes a pull-up circuit 18, and a part composed of N channel MOS transistors 221 to 225 constitutes a pull-down circuit 19.
  • Five activation signals 143P1 to 143P5 constituting the activation signal 143P are supplied to the gates of the output transistors 211 to 215, and five activation signals constituting the activation signal 143N are supplied to the gates of the output transistors 221 to 225.
  • Signals 143N1 to 143N5 are supplied.
  • the ten MOS transistors included in the unit buffer 131 are individually turned on / off by the ten activation signals 143P1 to 143P5 and the activation signals 143N1 to 143N5.
  • the pull-up circuit 18 and the pull-down circuit 19 are each designed to have a predetermined impedance (120 ⁇ in the embodiment) when conducting.
  • a predetermined impedance 120 ⁇ in the embodiment
  • the on-resistance of the output transistor varies depending on the manufacturing conditions and varies depending on the environmental temperature and the power supply voltage during operation. Therefore, a desired impedance is not always obtained. For this reason, in order to set the actual impedance to the target value, it is necessary to adjust the number of output transistors to be turned on. For this purpose, a parallel circuit including a plurality of output transistors is used.
  • the W / L ratio (gate width / gate length ratio) of the plurality of output transistors constituting the pull-up circuit 18 and the pull-down circuit 19 may be different from each other. It is particularly preferable to weight the power of 2. That is, when the W / L ratio of the output transistor 211 is “1WLp”, the W / L ratios of the output transistors 212 to 215 can be set to “2WLp”, “4WLp”, “8WLp”, and “16WLp”, respectively. Particularly preferred.
  • the W / L ratio of the output transistor 221 is “1WLn”
  • the W / L ratios of the output transistors 222 to 225 are set to “2WLn”, “4WLn”, “8WLn”, and “16WLn”, respectively. Is particularly preferred.
  • the other unit buffers 111 to 114, 121, and 122 are substantially the same as the unit buffer 131 shown in FIG. 3 except that the activation signals 141P and 142P and the operation signals 141N and 142N corresponding thereto are input. It has a circuit configuration.
  • FIG. 4 is a circuit diagram of the calibration circuit 100.
  • the calibration circuit 100 includes pull-up circuits (replica circuits) 310 and 320, a pull-down circuit 330, a counter 340 that controls operations of the pull-up circuits 310 and 320, and an operation of the pull-down circuit 330.
  • the calibration circuit 100 includes a damping resistor R21 (second resistor unit, second damping resistor) and a correction resistor 311 (third resistor) connected in series between the pull-up circuit 310 and the calibration terminal ZQ. Resistance portion, correction resistor) and electrostatic protection portion 312. Furthermore, the calibration circuit 100 includes a damping resistor R22 and a correction resistor 321 connected between the pull-up circuit 320 and the node A, and a damping resistor R23 and a correction connected between the pull-down circuit 330 and the node A. And a resistor 331. Node A is connected to one input terminal of comparator 370. Details of the correction resistor 311 and the electrostatic protection unit 312 will be described later.
  • FIG. 5 is a circuit diagram of the pull-up circuit 310.
  • the pull-up circuit 310 has substantially the same circuit configuration as the pull-up circuit 18 included in the unit buffers 111 to 114, 121, 122, 131. Specifically, the pull-up circuit 310 includes five P-channel MOS transistors 411 to 415 connected in parallel between the power supply line (power supply potential VDD) and the damping resistor R21.
  • adjustment buffer 50 second buffer
  • the transistors 411 to 415 included in the pull-up circuit 310 correspond to the output transistors 211 to 215 shown in FIG. 3, and have the same impedance. Therefore, similarly to the W / L ratios of the transistors 211 to 215, the W / L ratios of the transistors 411 to 415 are set to “1WLp”, “2WLp”, “4WLp”, “8WLp”, and “16WLp”, respectively. However, as long as the impedance is substantially the same, the transistors 411 to 415 included in the pull-up circuit 310 and the output transistors 211 to 215 shown in FIG. 3 do not have to have the same transistor size. You may use.
  • Impedance codes DRZQP1 to DRZQP5 are supplied from the counter 340 to the gates of the transistors 411 to 415, whereby the pull-up circuit 310 is controlled. Impedance codes DRZQP1 to DRZQP5 correspond to activation signals 141P1 to 141P5, respectively.
  • the pull-up circuit 320 also has the same circuit configuration as the pull-up circuit 310 shown in FIG. Impedance codes DRZQP1 to DRZQP5 are also supplied to the gates of the five transistors included in the pull-up circuit 320 side.
  • FIG. 6 is a circuit diagram of the pull-down circuit 330.
  • the pull-down circuit 330 has substantially the same circuit configuration as the pull-down circuit 19 included in the unit buffers 111 to 114, 121, 122, and 131.
  • the pull-down circuit 330 includes five N-channel MOS transistors 421 to 425 connected in parallel between the power supply line (power supply potential VSS) and the node A.
  • Transistors 421 to 425 included in the pull-down circuit 330 correspond to the transistors 221 to 225 shown in FIG. 3 and have the same impedance. This is the same as the pull-up circuit 310.
  • the damping resistor R21 corresponds to the damping resistor R14 of the output unit 130 shown in FIG. 2, and its resistance value is set to 120 ⁇ . This is because, in the present embodiment, the calibration circuit 100 is configured to correspond to the output unit composed of one unit buffer, that is, the output unit 130 of FIG.
  • the damping resistor R22 and the correction resistor 321 are resistors corresponding to the damping resistor R21 and the correction resistor 311, respectively.
  • the node C viewed from the pull-up circuit 310 and the node A viewed from the pull-up circuit 320 have substantially the same relationship.
  • the damping resistor R22 has substantially the same resistance value (120 ⁇ ) as the damping resistor R21
  • the correction resistor 321 has substantially the same resistance value (described later) as the correction resistor 311.
  • the damping resistor R23 and the correction resistor 331 are resistors corresponding to the damping resistor R22 and the correction resistor 321, respectively.
  • the pull-up circuit 320 viewed from the node A and the pull-down circuit 330 viewed from the node A have substantially the same relationship, and the pull-down circuit 330 can be adjusted more accurately.
  • the damping resistor R23 has substantially the same resistance value (120 ⁇ ) as the damping resistor R22
  • the correction resistor 331 has substantially the same resistance value as the correction resistor 321.
  • Impedance codes DRZQN1 to DRZQN5 are supplied from the counter 350 to the gates of the transistors 421 to 425, whereby the pull-down circuit 330 is controlled. Impedance codes DRZQN1 to DRZQN5 correspond to activation signals 161N1 to 161N5, respectively.
  • the pull-up circuits 310 and 320 all have substantially the same circuit configuration as the pull-up circuit 18 included in the unit buffers 111 to 114, 121, 122, and 131.
  • the pull-down circuit 19 included in the unit buffers 111 to 114, 121, 122, 131 has substantially the same circuit configuration.
  • the pull-up circuit 320 and the pull-down circuit 330 constitute a “replica buffer” having a circuit configuration substantially the same as that of the unit buffer 111.
  • “substantially the same” means that the transistors included in the replica buffer are regarded as the same even if they are shrunk.
  • the contact A that is the output terminal of the replica buffer is connected to the non-inverting input terminal (+) of the comparator 370.
  • the calibration control circuit 390 generates the operation signal ACT1 of the counter 340 and the operation signal ACT2 of the counter 350 in response to the calibration signal ZQCOM and the internal clock ICLK.
  • the comparator 360 compares the potential of the node C with the reference voltage ZQVREF, and outputs a comparison result signal COMP1 that takes either the high level or the low level based on the comparison result.
  • the comparator 370 compares the potential of the node A with the reference voltage ZQVREF, and outputs a comparison result signal COMP2 that takes either the high level or the low level based on the comparison result.
  • the counter 340 counts up or down its own count value according to the logic level of the output signal COMP1 of the comparator 360 in synchronization with the operation control signal ACT1.
  • the count value of the counter 340 is used as the impedance code DRZQP.
  • the counter 350 counts up or counts down its own count value in accordance with the logic level of the output signal COMP2 of the comparator 370 in synchronization with the operation control signal ACT2.
  • the count value of the counter 350 is used as the impedance code DRZQN.
  • the calibration circuit 100 sets the impedance of the pull-up circuit 310 and the impedance of the pull-down circuit 330 to 120 ⁇ so that the combined impedance of the pull-up circuit 310 and the damping resistor R21 matches the impedance of the external resistor Re. adjust. Then, using this adjustment result, the impedances of the pull-up circuit 18 and the pull-down circuit 19 of each unit buffer of the input / output circuit 16 are set to 120 ⁇ .
  • the conventional calibration circuit does not consider the influence of the wiring resistance of the wiring that passes through the electrostatic protection unit 160 of the input / output circuit 16 or the wiring that passes through the electrostatic protection unit 312 of the calibration circuit 100.
  • the impedance of each unit buffer after the calibration operation may be deviated from a desired value.
  • the correction resistor 311 is disposed between the damping resistor R21 and the node C of the calibration circuit 100.
  • FIG. 7 is a circuit diagram showing the connection relationship between the data terminal 24 and the output circuit 101 when the wiring resistance of the wiring passing through the electrostatic protection unit 160 is taken into consideration.
  • FIG. 7 is a diagram focusing on the connection between the output unit 130 and the data terminal 24.
  • An external terminal such as the data terminal 24 may be provided with an ESD (Electro-Static Discharge) element ESD1 (first ESD element) to protect the semiconductor circuit from electrostatic discharge.
  • ESD element is composed of, for example, a diode-connected MOS transistor. In order to protect the internal circuit from electrostatic discharge, it is necessary to quickly release the static electricity applied to the external terminal to the power line (VSS power line in FIG. 7). For this reason, a large MOS transistor is used for the ESD element.
  • FIG. 8 is a schematic diagram showing a layout between the data terminal 24 and the output circuit 101.
  • FIG. 9 is a diagram schematically showing a multilayer wiring structure included in the semiconductor device 10 of the present embodiment.
  • the diffusion layer DL and the gate wiring layer GL are formed on the surface of the substrate SS, and the first wiring layer L1 is sequentially disposed above the diffusion layer DL and the gate wiring layer GL.
  • the second wiring layer L2, the third wiring layer L3, and the fourth wiring layer L4 are stacked.
  • the first wiring layer is a wiring layer containing tungsten
  • the second to fourth wiring layers are wiring layers containing aluminum or copper, respectively.
  • Each layer is insulated from each other by interlayer insulating layers IL1 to IL4.
  • the upper surface of the uppermost fourth wiring layer L4 is covered with a protective interlayer insulating layer IL5.
  • a thin gate insulating film GI is formed between the gate wiring layer GL and the surface of the substrate SS.
  • the diffusion layer DL, the gate wiring layer GL, and the first wiring layer L1 are connected to each other only at a necessary place by a through-hole electrode TH0 that penetrates the interlayer insulating layer IL1.
  • the first wiring layer L1 and the second wiring layer L2 are connected to each other only where necessary by a through-hole electrode TH1 that penetrates the interlayer insulating layer IL2.
  • the second wiring layer L2 and the third wiring layer L3 are connected to each other only at a necessary place by a through-hole electrode TH2 penetrating the interlayer insulating layer IL3.
  • the third wiring layer L3 and the fourth wiring layer L4 are connected to each other only at a necessary place by a through-hole electrode TH3 penetrating the interlayer insulating layer IL4.
  • the ESD element ESD1 includes a diffusion layer DL formed as a source / drain in a substrate SS such as silicon and a gate electrode G formed on the substrate SS.
  • One of the source and drain of the ESD element 1 is connected to the data wiring DQL1 via the through-hole electrodes TH0 and TH1 and the first wiring layer L1 (not shown in FIG. 8).
  • the other of the source and drain of the ESD element ESD1 is connected to a power line (not shown) (VSS potential).
  • the data pad DQP is connected to the data wiring DQL1 through the through-hole electrodes TH3 and TH2 and the third wiring layer L3 (not shown in FIG. 8).
  • each of the data line DQL1 and the damping resistors R11 to R14 is connected to each other through the through-hole electrode TH1.
  • the other ends of the damping resistors R11 to R14 and the data wiring DQL2 are connected to each other through the corresponding through-hole electrode TH1.
  • the data line DQL1 includes a slit-like portion to be connected to the corresponding diffusion layer DL of the ESD element ESD1.
  • the data wiring DQL1 has a wiring resistance of about 1 ⁇ .
  • rm represents the impedance of the pull-up circuit 18
  • r1 represents the resistance value of the damping resistor R14.
  • rdESD indicates the resistance value of the data wiring DQL1, and specifically indicates the resistance value from the data terminal 24 to one end of the damping resistor R14. That is, in FIG. 8, rdESD indicates the resistance value from the data pad DQP to the through-hole electrode TH1 that connects one end of the damping resistor R14 and the data wiring DQL1.
  • FIG. 10 is a circuit diagram showing the configuration of the adjustment buffer 50 ′ in the conventional calibration circuit (no correction resistor).
  • the adjustment buffer 50 ′ corresponds to the adjustment buffer 50 shown in FIG.
  • the ESD element ESD2 second ESD element
  • the calibration wiring ZQL1 resistance value rzESD
  • re indicates the resistance value of the external resistor Re.
  • R1 represents the resistance value of the damping resistor R21, and this value is set to be equal to the damping resistor R14 of the output unit 130.
  • the impedance at which the unit buffer of the output unit 130 drives the data terminal 24 becomes re + rdEDS + rzEDS. That is, there is a possibility that the impedance at which the unit buffer of the output unit 130 drives the data terminal 24 deviates from the impedance of the external resistor Re. Similar problems occur in other unit buffers.
  • FIG. 11 is a circuit diagram (first configuration example) showing a connection relationship between the pull-up circuit 310 to which the correction resistor 311 is added and the calibration terminal ZQ in the present embodiment.
  • a correction resistor 311 is added between the damping resistor R21 and the connection point C. The correction resistor 311 cancels the influence of the wiring resistance of the data wiring DQL1 shown in FIGS. 7 and 8 and the wiring resistance of the calibration wiring ZQL1 shown in FIGS.
  • FIG. 12 is a schematic diagram showing a layout between the calibration terminal ZQ, the pull-up circuit 310, and the comparator 360 in the circuit diagram shown in FIG.
  • an ESD element formed with a MOS transistor structure.
  • ESD2 calibration wiring ZQL1 (second wiring), ZQL2 (third wiring) formed as the second wiring layer L2, correction resistor 311 and damping resistance R21 formed as the first wiring layer L1 And including.
  • the ESD element ESD2 includes a diffusion layer DL formed as a source / drain in a substrate SS such as silicon and a gate electrode G formed on the substrate SS.
  • One of the source and drain of the ESD element ESD2 is connected to the calibration wiring ZQL1 via the through-hole electrodes TH0 and TH1 and the first wiring layer L1 (not shown in FIG. 12).
  • the other of the source and drain of the ESD element ESD1 is connected to a power line (not shown) (VSS potential).
  • the calibration pad ZQP is connected to the calibration wiring ZQL1 through the through-hole electrodes TH3 and TH2 and the third wiring layer L3 (not shown in FIG. 12).
  • the calibration wiring ZQL1 includes a slit-like portion to be connected to the corresponding diffusion layer DL of the ESD element ESD2. For this reason, in the present embodiment, the calibration wiring ZQL1 has a wiring resistance of about 1 ⁇ .
  • a branch point where the calibration wiring ZQL1 branches to the calibration wiring ZQL2 toward the comparator 360 and the correction resistor 311 toward the pull-up circuit 310 corresponds to the node C in FIG.
  • the correction resistor 311 is connected to one end of the damping resistor R21 through the through-hole electrode TH1 at one end.
  • the resistance value rzESD of the wiring resistance of the calibration wiring ZQL1 shown in FIG. 11 corresponds to the resistance value from the calibration pad ZQP to the node C.
  • the resistance value rc of the correction resistor 311 is calculated by the following method.
  • rc rzESD + rdESD, but even if rc is a value in the vicinity thereof, a certain correction effect is obtained, and it is desirable that rc is less than 1.5 times rzESD + rdESD.
  • FIG. 13 is a circuit diagram (second configuration example) of the pull-up circuit 310 (adjustment buffer 50) to which a correction resistor is added in the present embodiment.
  • the data wiring DQL1 and the calibration wiring ZQL1 are both formed as the second wiring layer L2.
  • the data wiring DQL1 ′ and the calibration wiring ZQL1 are formed in different wiring layers.
  • FIG. 14 is a schematic diagram showing a layout between the data terminal 24 and the output circuit 101 in the second configuration example
  • FIG. 15 shows a calibration terminal ZQ, a pull-up circuit 310, and the like in the second configuration example.
  • 3 is a schematic diagram showing a layout with a comparator 360.
  • FIG. In FIGS. 14 and 15, the same components as those in FIGS. 8 and 12 are denoted by the same reference numerals, and redundant description is omitted.
  • the data wiring DQL1 ′ is formed as the third wiring layer L3.
  • the calibration wiring ZQL1 is formed as the second wiring layer L2 as in the first configuration example.
  • the correction resistor 311 ′ is formed as a series resistance of the two correction resistors 3111 and 3112.
  • the correction resistor 3112 first resistance component
  • the correction resistor 3111 second resistance component
  • the correction resistor 3111 is formed as the same wiring layer as the calibration wiring ZQL1, ie, the second wiring layer L2, and has the same resistance value (rc′2) as the calibration wiring ZQL1.
  • FIG. 16 is a circuit diagram showing a connection relationship between the data terminal 24 and the output circuit 101 when the power source parasitic resistance and the bonding resistance are taken into consideration.
  • the source of the MOS transistor is a power source parasitic resistance (resistance value rsd) of the power source line PSDL
  • the outside of the external terminal is a bonding resistance (resistance value of the package bonding wire BWD). rud) exists.
  • FIG. 17 is a circuit diagram (third configuration example) showing a connection relationship between the pull-up circuit 310 to which the correction resistor is added and the calibration terminal ZQ in the present embodiment.
  • the correction resistor 3113 of the third configuration example takes into account the power supply parasitic resistance of the power supply line PSDL and the bonding resistance of the bonding wire BWZ.
  • the power supply line PSZL of the pull-up circuit 310 also has a power supply parasitic resistance (resistance value rsr) and a bonding resistance (resistance value ur) due to the connection of the external resistance Re.
  • the resistance value rc2 of the correction resistor 3113 considering not only the resistances of the wirings DQL1 and ZQL1 but also the power source parasitic resistance and bonding resistance is calculated by the following method.
  • rsr + rm + r1 + rc2 rzESD + rur + (rsd + rm + r1 + rdESD + rud).
  • the semiconductor device 10 has been described above based on the embodiment.
  • a correction resistor into the adjustment buffer 50, the influence of the wiring resistance of the data wiring and the calibration wiring, the power source parasitic resistance, and the bonding resistance can be offset, and more accurate calibration can be performed.
  • Which of the wiring resistance, power supply parasitic resistance, and bonding resistance of the data wiring and calibration wiring is taken into consideration is arbitrary. For example, when the bonding resistance is sufficiently smaller than the wiring resistance and power supply parasitic resistance of the data wiring and calibration wiring, only the influence of the wiring resistance of the data wiring and calibration wiring and the power supply parasitic resistance may be considered.
  • the linearity in the IV characteristic of the adjustment buffer 50 increases.
  • the influence of the IV characteristics (non-linearity) of the transistor group included in the pull-up circuit 310 on the adjustment buffer 50 is reduced.
  • the correction resistance is about 1 ⁇ , and at most about 5 ⁇ . If the correction resistance is 5 ⁇ or less, it has been confirmed that the influence of the correction resistance on the IV characteristics of the adjustment buffer 50 hardly occurs.

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Abstract

[Problem] To more precisely adjust impedance of an output terminal. [Solution] Impedance of an output buffer (unit buffer) included in an I/O circuit is adjusted on the basis of impedance of a pull-up circuit (replica circuit) included in a calibration circuit. In the calibration circuit, a pull-up circuit (310), a damping resistor (R21), a correction resistor (311), an electrostatic protection unit (312), and an external resistor (Re) are connected in series. The potential at the connection of the correction resistor (311) with the electrostatic protection unit (312) is compared with a reference potential by a comparator (360). The resistance value of the correction resistor (311) is determined on the basis of line resistances of lines which are respectively connected to a data terminal and a calibration terminal (ZQ).

Description

半導体装置Semiconductor device
　本発明は半導体装置に関し、特に、出力バッファのインピーダンスを調整可能な入出力回路を備えた半導体装置に関する。 The present invention relates to a semiconductor device, and more particularly to a semiconductor device including an input / output circuit capable of adjusting the impedance of an output buffer.
　ＤＲＡＭ（Dynamic Random Access Memory）などの半導体装置においては、出力端子のインピーダンスを調整するために、出力バッファのインピーダンスを調整するキャリブレーション回路が設けられていることがある（特許文献１参照）。出力バッファはプルアップ出力部とプルダウン出力部を有しており、これらのインピーダンスは、キャリブレーション回路によって生成されるプルアップインピーダンスコードおよびプルダウンインピーダンスコードに基づいてそれぞれ制御される。 In a semiconductor device such as a DRAM (Dynamic Random Access Memory), a calibration circuit for adjusting the impedance of the output buffer may be provided in order to adjust the impedance of the output terminal (see Patent Document 1). The output buffer has a pull-up output unit and a pull-down output unit, and these impedances are controlled based on the pull-up impedance code and the pull-down impedance code generated by the calibration circuit, respectively.
特開２０００－１８３７１７号公報JP 2000-183717 A
　キャリブレーション回路は、入出力回路の出力バッファと実質同一構成のレプリカバッファを有する。まず、キャリブレーション端子に外部抵抗を接続した状態でキャリブレーション端子の電圧と基準電圧を比較し、レプリカバッファのインピーダンスを調整する。そして、レプリカバッファの調整内容を出力バッファに反映させる。 The calibration circuit has a replica buffer with substantially the same configuration as the output buffer of the input / output circuit. First, the impedance of the replica buffer is adjusted by comparing the voltage of the calibration terminal with the reference voltage with an external resistor connected to the calibration terminal. Then, the adjustment contents of the replica buffer are reflected in the output buffer.
　このようなキャリブレーション回路では、キャリブレーション端子に接続された外部抵抗に応じてレプリカバッファと出力バッファのインピーダンスを調整する。 In such a calibration circuit, the impedance of the replica buffer and the output buffer is adjusted according to the external resistance connected to the calibration terminal.
　しかし、キャリブレーション回路と入出力回路は、一部の配線構造が異なるため、この相違に起因して、調整後の出力バッファのインピーダンスが所望のインピーダンスから若干ずれてしまう恐れがあることに本発明者らは想到した。このような配線構造に基づく調整ずれを補正した上で出力バッファのインピーダンスを調整することがより望ましい。 However, since the calibration circuit and the input / output circuit are partially different in wiring structure, the impedance of the adjusted output buffer may slightly deviate from the desired impedance due to this difference. They came up with the idea. It is more desirable to adjust the impedance of the output buffer after correcting such adjustment deviation based on the wiring structure.
　本発明の一側面による半導体装置は、データ端子及びキャリブレーション端子と、出力バッファと、前記出力バッファに一端で接続された第１の抵抗部と、前記データ端子と前記第１の抵抗部の他端とを接続する第１の配線と、前記出力バッファと実質的に等しいインピーダンスを有するレプリカ回路と、比較回路と、前記レプリカ回路に一端で接続された第２の抵抗部と、前記第２の抵抗部の他端に一端で接続された第３の抵抗部と、前記第３の抵抗部の他端と前記キャリブレーション端子とを接続する第２の配線と、前記第３の抵抗部の他端と前記比較回路とを接続する第３の配線と、を備え、前記第３の抵抗部の抵抗値は、前記第１の配線の抵抗値及び前記第２の配線の抵抗値よりも大きいことを特徴とする。 A semiconductor device according to an aspect of the present invention includes a data terminal, a calibration terminal, an output buffer, a first resistor connected to the output buffer at one end, the data terminal, and the first resistor. A first wiring connecting the ends, a replica circuit having substantially the same impedance as the output buffer, a comparison circuit, a second resistor connected to the replica circuit at one end, and the second A third resistor connected at one end to the other end of the resistor, a second wiring connecting the other end of the third resistor and the calibration terminal, and the other of the third resistor A third wiring connecting the end and the comparison circuit, and a resistance value of the third resistance portion is larger than a resistance value of the first wiring and a resistance value of the second wiring. It is characterized by.
　本発明の他の一側面による半導体装置は、出力バッファと、キャリブレーション回路とを備える。前記キャリブレーション回路は、レプリカ回路とコンパレータを含み、前記コンパレータの出力に基づいて前記レプリカ回路のインピーダンスを調整してその調整結果を前記出力バッファに反映させる。更に、前記キャリブレーション回路が、前記レプリカ回路と前記コンパレータの一方の入力端子との間に直列に接続された第２ダンピング抵抗および補正抵抗を含むことを特徴とする。 A semiconductor device according to another aspect of the present invention includes an output buffer and a calibration circuit. The calibration circuit includes a replica circuit and a comparator, adjusts the impedance of the replica circuit based on the output of the comparator, and reflects the adjustment result in the output buffer. Furthermore, the calibration circuit includes a second damping resistor and a correction resistor connected in series between the replica circuit and one input terminal of the comparator.
　本発明によれば、半導体装置における出力バッファのインピーダンスをより好適に設定できる。 According to the present invention, the impedance of the output buffer in the semiconductor device can be set more suitably.
本発明の実施形態による半導体装置の全体構成を示すブロック図である。1 is a block diagram illustrating an overall configuration of a semiconductor device according to an embodiment of the present invention. 入出力回路の構成を示すブロック図である。It is a block diagram which shows the structure of an input / output circuit. 単位バッファの回路図である。It is a circuit diagram of a unit buffer. キャリブレーション回路の回路図である。It is a circuit diagram of a calibration circuit. プルアップ回路の回路図である。It is a circuit diagram of a pull-up circuit. プルダウン回路の回路図である。It is a circuit diagram of a pull-down circuit. 静電気保護部を通過する配線の配線抵抗を考慮したときのデータ端子と出力回路との接続関係を示す回路図である。It is a circuit diagram which shows the connection relationship of a data terminal and an output circuit when the wiring resistance of the wiring which passes an electrostatic protection part is considered. データ端子と出力回路との間のレイアウトを示す模式図である。It is a schematic diagram which shows the layout between a data terminal and an output circuit. 実施形態による半導体装置が含む多層配線構造を模式的に示した図である。It is the figure which showed typically the multilayer wiring structure which the semiconductor device by embodiment contains. 従来のキャリブレーション回路における調整バッファの構成を示す回路図である。It is a circuit diagram which shows the structure of the adjustment buffer in the conventional calibration circuit. 本実施形態のキャリブレーション回路における、プルアップ回路、補正抵抗、静電気保護部、コンパレータおよびキャリブレーション端子の接続関係を示す回路図（第１構成例）である。FIG. 3 is a circuit diagram (first configuration example) illustrating a connection relationship among a pull-up circuit, a correction resistor, an electrostatic protection unit, a comparator, and a calibration terminal in the calibration circuit of the present embodiment. 第１構成例におけるキャリブレーション端子とプルアップ回路及びコンパレータ間のレイアウトを示す模式図である。It is a schematic diagram which shows the layout between the calibration terminal in the 1st structural example, a pull-up circuit, and a comparator. 本実施形態のキャリブレーション回路における、プルアップ回路、補正抵抗、静電気保護部、コンパレータおよびキャリブレーション端子の接続関係を示す回路図（第２構成例）である。FIG. 6 is a circuit diagram (second configuration example) showing a connection relationship among a pull-up circuit, a correction resistor, an electrostatic protection unit, a comparator, and a calibration terminal in the calibration circuit of the present embodiment. 第２構成例におけるデータ端子と出力回路との間のレイアウトを示す模式図である。It is a schematic diagram which shows the layout between the data terminal and output circuit in a 2nd structural example. 第２構成例におけるキャリブレーション端子とプルアップ回路及びコンパレータ間のレイアウトを示す模式図である。It is a schematic diagram which shows the layout between the calibration terminal in the 2nd structural example, a pull-up circuit, and a comparator. 電源寄生抵抗およびボンディング抵抗を考慮したときのデータ端子と出力回路との接続関係を示す回路図である。It is a circuit diagram which shows the connection relation of the data terminal and output circuit when power supply parasitic resistance and bonding resistance are considered. 本実施形態のキャリブレーション回路における、プルアップ回路、補正抵抗、静電気保護部、コンパレータおよびキャリブレーション端子の接続関係を示す回路図（第３構成例）である。FIG. 10 is a circuit diagram (third configuration example) illustrating a connection relationship among a pull-up circuit, a correction resistor, an electrostatic protection unit, a comparator, and a calibration terminal in the calibration circuit of the present embodiment.
　以下、添付図面を参照しながら、本発明の好ましい実施の形態について詳細に説明する。 Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.
　図１は、本発明の好ましい実施形態による半導体装置１０の全体構成を示すブロック図である。 FIG. 1 is a block diagram showing an overall configuration of a semiconductor device 10 according to a preferred embodiment of the present invention.
　本実施形態による半導体装置１０は単一の半導体チップに集積されたＤＲＡＭであり、外部基板２に実装されている。外部基板２は、マザーボード等の配線基板であり、外部抵抗Ｒｅが設けられている。外部抵抗Ｒｅの一端は半導体装置１０のキャリブレーション端子ＺＱに電気的に接続される。キャリブレーション回路１００の詳細については後述する。本実施形態においては、外部抵抗Ｒｅは２４０Ωの抵抗値を有し、また、外部抵抗Ｒｅの他端には接地電位ＶＳＳが供給される。 The semiconductor device 10 according to the present embodiment is a DRAM integrated on a single semiconductor chip, and is mounted on the external substrate 2. The external substrate 2 is a wiring substrate such as a mother board and is provided with an external resistor Re. One end of the external resistor Re is electrically connected to the calibration terminal ZQ of the semiconductor device 10. Details of the calibration circuit 100 will be described later. In the present embodiment, the external resistor Re has a resistance value of 240Ω, and the ground potential VSS is supplied to the other end of the external resistor Re.
　半導体装置１０はメモリセルアレイ１１を有する。メモリセルアレイ１１は、複数のワード線ＷＬと複数のビット線ＢＬを備え、これらの交点にメモリセルＭＣが配置される。ワード線ＷＬはロウデコーダ１２により選択され、ビット線ＢＬはカラムデコーダ１３により選択される。また、半導体装置１０の外部端子としてクロック端子２３、コマンドアドレス端子２１、チップセレクト端子２２、データ端子２４、電源端子２５，２６およびキャリブレーション端子ＺＱが設けられる。 The semiconductor device 10 has a memory cell array 11. The memory cell array 11 includes a plurality of word lines WL and a plurality of bit lines BL, and memory cells MC are arranged at intersections thereof. The word line WL is selected by the row decoder 12, and the bit line BL is selected by the column decoder 13. As external terminals of the semiconductor device 10, a clock terminal 23, a command address terminal 21, a chip select terminal 22, a data terminal 24, power supply terminals 25 and 26, and a calibration terminal ZQ are provided.
　クロック端子２３は、外部クロック信号ＣＫ，／ＣＫが入力される端子である。本明細書において、信号名の先頭に「／」が付されている信号は、対応する信号の反転信号又はローアクティブな信号であることを意味する。したがって、外部クロック信号／ＣＫは、外部クロック信号ＣＫの反転信号である。外部クロック信号ＣＫ，／ＣＫは、いずれもクロック入力回路３６に供給される。クロック入力回路３６に供給された外部クロック信号ＣＫ，／ＣＫは、クロック発生回路５４に供給される。クロック発生回路５４は、外部クロック信号ＣＫ，／ＣＫに基づいて内部クロック信号ＩＣＬＫを生成する。内部クロック信号ＩＣＬＫは、アドレスラッチ回路３２、コマンドデコード回路３４、キャリブレーション回路１００及びラッチ回路１５などの回路ブロックに供給され、これら回路ブロックの動作タイミングを規定する。 The clock terminal 23 is a terminal to which external clock signals CK and / CK are input. In this specification, a signal having “/” at the head of a signal name means an inverted signal of the corresponding signal or a low active signal. Therefore, external clock signal / CK is an inverted signal of external clock signal CK. The external clock signals CK and / CK are both supplied to the clock input circuit 36. The external clock signals CK and / CK supplied to the clock input circuit 36 are supplied to the clock generation circuit 54. Clock generation circuit 54 generates internal clock signal ICLK based on external clock signals CK and / CK. The internal clock signal ICLK is supplied to circuit blocks such as the address latch circuit 32, the command decode circuit 34, the calibration circuit 100, and the latch circuit 15, and defines the operation timing of these circuit blocks.
　コマンドアドレス端子２１には、コマンドアドレス信号ＣＡが入力される。コマンドアドレス信号は、コマンド信号ＣＭＤ及びアドレス信号ＡＤＤを構成する。チップセレクト端子２２には、チップセレクト信号／ＣＳが入力される。これらの信号はコマンドアドレス（ＣＡ）入力回路３１に供給される。コマンドアドレス入力回路に供給されたこれらの信号のうち、アドレス信号ＡＤＤはアドレスラッチ回路３２に供給され、コマンド信号ＣＭＤは、コマンドデコード回路３４に供給される。 The command address signal CA is input to the command address terminal 21. The command address signal constitutes a command signal CMD and an address signal ADD. A chip select signal / CS is input to the chip select terminal 22. These signals are supplied to a command address (CA) input circuit 31. Of these signals supplied to the command address input circuit, the address signal ADD is supplied to the address latch circuit 32, and the command signal CMD is supplied to the command decode circuit 34.
　アドレスラッチ回路３２は、内部クロックＩＣＬＫに同期してアドレス信号ＡＤＤをラッチする。ラッチされたアドレス信号ＡＤＤのうち、ロウアドレスはロウデコーダ１２に供給され、カラムアドレスはカラムデコーダ１３に供給される。また、モードレジスタセットにエントリしている場合には、アドレス信号ＡＤＤはモード設定信号としてモードレジスタ１４に供給される。モードレジスタ１４は、半導体装置１０の動作モードを示すパラメータを設定される。図１には、モードレジスタが示す動作モードのパラメータのうち、駆動能力設定信号ＤＳが示されている。詳細は後述するが、駆動能力設定信号ＤＳは、入出力回路１６内の複数の単位バッファのうち、データ出力時に活性化させる１以上の単位バッファを指定する。 The address latch circuit 32 latches the address signal ADD in synchronization with the internal clock ICLK. Of the latched address signal ADD, the row address is supplied to the row decoder 12 and the column address is supplied to the column decoder 13. If the mode register set is entered, the address signal ADD is supplied to the mode register 14 as a mode setting signal. The mode register 14 is set with a parameter indicating the operation mode of the semiconductor device 10. FIG. 1 shows the drive capability setting signal DS among the parameters of the operation mode indicated by the mode register. Although details will be described later, the drive capability setting signal DS designates one or more unit buffers to be activated at the time of data output among the plurality of unit buffers in the input / output circuit 16.
　コマンドデコード回路３４は、内部クロックＩＣＬＫに同期して、コマンド信号ＣＭＤの保持、デコード及びカウントなどを行うことによって、各種内部コマンドを生成する。内部コマンドとしては、アクティブ信号ＩＡＣＴ、カラム信号ＩＣＯＬ、モードレジスタセット信号ＭＲＳ、キャリブレーション信号ＺＱＣＯＭなどがある。 The command decode circuit 34 generates various internal commands by holding, decoding and counting the command signal CMD in synchronization with the internal clock ICLK. The internal commands include an active signal IACT, a column signal ICOL, a mode register set signal MRS, a calibration signal ZQCOM, and the like.
　アクティブ信号ＩＡＣＴは、コマンド信号ＣＭＤがロウアクセス（アクティブコマンド）を示している場合に活性化される。アクティブ信号ＩＡＣＴが活性化すると、アドレスラッチ回路３２にラッチされたアドレス信号ＡＤＤがロウアドレスとしてロウデコーダ１２に供給される。これにより、ロウアドレスにより指定されるワード線ＷＬが選択される。 The active signal IACT is activated when the command signal CMD indicates row access (active command). When the active signal IACT is activated, the address signal ADD latched by the address latch circuit 32 is supplied to the row decoder 12 as a row address. As a result, the word line WL specified by the row address is selected.
　カラム信号ＩＣＯＬは、コマンド信号ＣＭＤがカラムアクセスを示している場合に活性化される。ここで、カラムアクセスとは、コマンド信号がリードコマンドの場合リードアクセスを、コマンド信号がライトコマンドの場合ライトアクセスをそれぞれ意味する。内部カラム信号ＩＣＯＬが活性化すると、アドレスラッチ回路３２にラッチされたアドレス信号ＡＤＤがカラムアドレスとしてカラムデコーダ１３に供給される。これにより、カラムアドレスにより指定されるビット線ＢＬが選択される。 The column signal ICOL is activated when the command signal CMD indicates column access. Here, column access means read access when the command signal is a read command, and write access when the command signal is a write command. When the internal column signal ICOL is activated, the address signal ADD latched by the address latch circuit 32 is supplied to the column decoder 13 as a column address. As a result, the bit line BL specified by the column address is selected.
　したがって、アクティブコマンド及びリードコマンドをこの順に入力するとともに、これらに同期してロウアドレス及びカラムアドレスを入力すれば、これらロウアドレス及びカラムアドレスによって指定されるメモリセルＭＣからリードデータが読み出される。リードデータＤＱは、ラッチ回路１５及び入出力回路１６を介して、データ端子２４から出力される。一方、アクティブコマンドおよびライトコマンドをこの順に入力するとともに、これらに同期してロウアドレスおよびカラムアドレスを入力し、その後、データ端子２４にライトデータＤＱを入力すれば、ライトデータＤＱは入出力回路１６とラッチ回路１５を介してメモリセルアレイ１１に供給され、ロウアドレス及びカラムアドレスによって指定されるメモリセルＭＣに書き込まれる。ラッチ回路１５は、内部クロック信号ＩＣＬＫに同期してメモリセルアレイ１１と入出力回路１６との間のデータ転送を実行する。 Therefore, when an active command and a read command are input in this order, and a row address and a column address are input in synchronization therewith, read data is read from the memory cell MC specified by the row address and the column address. The read data DQ is output from the data terminal 24 via the latch circuit 15 and the input / output circuit 16. On the other hand, when an active command and a write command are input in this order, a row address and a column address are input in synchronization therewith, and then write data DQ is input to the data terminal 24, the write data DQ is input to the input / output circuit 16 Are supplied to the memory cell array 11 via the latch circuit 15 and written in the memory cells MC specified by the row address and the column address. The latch circuit 15 executes data transfer between the memory cell array 11 and the input / output circuit 16 in synchronization with the internal clock signal ICLK.
　モードレジスタセット信号ＭＲＳは、コマンド信号ＣＭＤがモードレジスタセットコマンドを示している場合に活性化される。したがって、モードレジスタセットコマンドを入力すると半導体装置１０はモードレジスタセットにエントリされ、これに同期してコマンドアドレス端子２１からモード信号を入力すれば、モードレジスタ１４の設定値を書き換えることができる。 The mode register set signal MRS is activated when the command signal CMD indicates a mode register set command. Therefore, when the mode register set command is input, the semiconductor device 10 is entered into the mode register set. When the mode signal is input from the command address terminal 21 in synchronization therewith, the set value of the mode register 14 can be rewritten.
　キャリブレーション信号ＺＱＣＯＭは、コマンド信号ＣＭＤがキャリブレーションコマンドを示している場合に活性化される。キャリブレーションコマンドは、半導体装置１０の初期化時に発行される他、通常動作時においても定期的に発行される。キャリブレーション信号ＺＱＣＯＭは、キャリブレーション回路１００を活性化させる。キャリブレーション回路１００は、キャリブレーション信号ＺＱＣＯＭに応答し、内部クロックＩＣＬＫに同期してキャリブレーション動作を実行し、これにより入出力回路１６に含まれる出力回路１０１のインピーダンスを調整する。キャリブレーション回路１００及び出力回路１０１の詳細については後述する。 The calibration signal ZQCOM is activated when the command signal CMD indicates a calibration command. The calibration command is issued not only when the semiconductor device 10 is initialized but also periodically during normal operation. The calibration signal ZQCOM activates the calibration circuit 100. In response to the calibration signal ZQCOM, the calibration circuit 100 performs a calibration operation in synchronization with the internal clock ICLK, and thereby adjusts the impedance of the output circuit 101 included in the input / output circuit 16. Details of the calibration circuit 100 and the output circuit 101 will be described later.
　電源端子２５には、電源電位ＶＤＤ，ＶＳＳが供給される。電源電位ＶＤＤ，ＶＳＳは電源端子２５を介して内部電源発生回路３９に供給される。内部電源発生回路３９は、電源電位ＶＤＤ，ＶＳＳに基づいて各種の内部電位ＶＰＰ，ＶＯＤ，ＶＡＲＹ，ＶＰＥＲＩを発生させる。内部電位ＶＰＰは主にロウデコーダ１２において使用され、内部電位ＶＯＤ，ＶＡＲＹはメモリセルアレイ１１内のセンスアンプにおいて使用され、内部電位ＶＰＥＲＩは他の多くの回路ブロックにおいて使用される。 The power supply terminals 25 are supplied with power supply potentials VDD and VSS. The power supply potentials VDD and VSS are supplied to the internal power supply generation circuit 39 via the power supply terminal 25. The internal power supply generation circuit 39 generates various internal potentials VPP, VOD, VARY, and VPERI based on the power supply potentials VDD and VSS. Internal potential VPP is mainly used in row decoder 12, internal potentials VOD and VARY are used in sense amplifiers in memory cell array 11, and internal potential VPERI is used in many other circuit blocks.
　電源端子２６には、電源電位ＶＤＤＱ，ＶＳＳＱが供給される。電源電位ＶＤＤＱ，ＶＳＳＱは入出力回路１６に供給され、入出力回路１６に含まれる出力回路１０１の動作電源として使用される。電源電位ＶＤＤＱの電位は電源電位ＶＤＤと同じであり、電源電位ＶＳＳＱの電位は電源電位ＶＳＳと同じであるが、出力回路１０１の動作にともなって発生する電源ノイズが他の回路に伝搬しないよう電源経路が分離されている。ただし、本発明においてこのような電源経路の分離を行うことは必須でない。 Power supply potentials VDDQ and VSSQ are supplied to the power supply terminal 26. The power supply potentials VDDQ and VSSQ are supplied to the input / output circuit 16 and used as operation power for the output circuit 101 included in the input / output circuit 16. The power supply potential VDDQ is the same as the power supply potential VDD, and the power supply potential VSSQ is the same as the power supply potential VSS. However, the power supply noise generated by the operation of the output circuit 101 is not propagated to other circuits. The route is separated. However, in the present invention, it is not essential to perform such power supply path separation.
　図２は、入出力回路１６の構成を示すブロック図である。 FIG. 2 is a block diagram showing the configuration of the input / output circuit 16.
　図２に示すように、入出力回路１６は、出力回路１０１、入力バッファ１７０、前段回路１４１，１４２，１４３、出力制御回路１５０を備える。入出力回路１６は、更に、静電気保護部１６０を備える。静電気保護部１６０についての詳細は後述する。 As shown in FIG. 2, the input / output circuit 16 includes an output circuit 101, an input buffer 170, pre-stage circuits 141, 142, and 143, and an output control circuit 150. The input / output circuit 16 further includes an electrostatic protection unit 160. Details of the electrostatic protection unit 160 will be described later.
　出力回路１０１は、出力ユニット１１０、１２０、１３０の３つの出力ユニットを含む。ただし、本発明の出力ユニットの個数は、３つに限定されるものではない。 The output circuit 101 includes three output units 110, 120, and 130. However, the number of output units of the present invention is not limited to three.
　出力ユニット１１０は、４つの単位バッファ（出力バッファ）１１１～１１４とそれぞれ６０Ωで互いに並列に接続されたダンピング抵抗Ｒ１１、Ｒ１２とを、出力ユニット１２０は、２つの単位バッファ（出力バッファ）１２１，１２２と６０Ωのダンピング抵抗Ｒ１３とを、出力ユニット１３０は、１つの単位バッファ（出力バッファ）１３１と１２０Ω（ｒ１）のダンピング抵抗Ｒ１４（第１の抵抗部、第１ダンピング抵抗）とを、それぞれ含む。ここで、ダンピング抵抗Ｒ１１～Ｒ１４としては、例えば拡散層、タングステン（Ｗ）、窒化チタン（ＴｉＮ）などの高抵抗配線を用いることができる。ただし、本発明の出力ユニット中の単位バッファの個数及びダンピング抵抗の個数並びに抵抗値は、図２に示す構成に限定されるものではない。単位バッファ１１１～１１４、１２１、１２２、１３１のそれぞれは、インピーダンス（第１のインピーダンス）を調整可能である。本実施形態においては、単位バッファ１１１～１１４、１２１、１２２、１３１それぞれのインピーダンスが１２０Ωに調整される。このような構成とすることで、１つのキャリブレーション回路で複数の単位バッファのインピーダンスを一括して調整し、キャリブレーション動作を簡略化できる。 The output unit 110 includes four unit buffers (output buffers) 111 to 114 and damping resistors R11 and R12 connected in parallel with each other at 60Ω, and the output unit 120 includes two unit buffers (output buffers) 121 and 122. The output unit 130 includes one unit buffer (output buffer) 131 and a 120Ω (r1) damping resistor R14 (first resistance unit, first damping resistor). Here, as the damping resistors R11 to R14, for example, a high resistance wiring such as a diffusion layer, tungsten (W), or titanium nitride (TiN) can be used. However, the number of unit buffers, the number of damping resistors, and the resistance value in the output unit of the present invention are not limited to the configuration shown in FIG. Each of the unit buffers 111 to 114, 121, 122, and 131 can adjust the impedance (first impedance). In the present embodiment, the impedance of each of the unit buffers 111 to 114, 121, 122, 131 is adjusted to 120Ω. With such a configuration, the calibration operation can be simplified by collectively adjusting the impedances of a plurality of unit buffers with one calibration circuit.
　また、出力ユニット毎に見ると、出力ユニット１１０はデータ端子２４を６０Ωで駆動するように調整され、出力ユニット１２０はデータ端子２４を１２０Ωで駆動するように調整され、出力ユニット１３０はデータ端子２４を２４０Ωで駆動するように調整される。即ち、各出力ユニットは、各単位バッファのインピーダンスの調整後に、外部抵抗Ｒｅの抵抗値を自身が含む単位バッファの数で除した値に実質的に等しいインピーダンスとなるように設計されている。 Further, when viewed for each output unit, the output unit 110 is adjusted to drive the data terminal 24 at 60Ω, the output unit 120 is adjusted to drive the data terminal 24 at 120Ω, and the output unit 130 is adjusted to the data terminal 24. Is adjusted to drive at 240Ω. That is, each output unit is designed to have an impedance substantially equal to a value obtained by dividing the resistance value of the external resistor Re by the number of unit buffers included in the output unit after adjusting the impedance of each unit buffer.
　また、各単位バッファ１１１～１１４、１２１、１２２、１３１は、リード動作時において、自身が含まれる出力ユニット１１０，１２０，１３０が活性化されるときに活性化され、データ端子２４をハイレベルまたはローレベルのいずれかに駆動する。 Each of the unit buffers 111 to 114, 121, 122, 131 is activated when the output unit 110, 120, 130 including the unit buffer is activated during the read operation, and the data terminal 24 is set to the high level. Drive to either low level.
　出力ユニット１１０～１３０の前段には、それぞれ前段回路１４１～１４３が設けられている。前段回路１４１～１４３は、対応する出力ユニットを活性化させるか否かを指定し、対応する出力ユニットに含まれる単位バッファのインピーダンスを調整する。図２に示すように、前段回路１４１～１４３には、出力制御回路１５０から活性化信号１５１Ｐ～１５３Ｐと活性化信号１５１Ｎ～１５３Ｎが供給され、キャリブレーション回路１００からインピーダンス調整コードＤＲＺＱが共通に供給される。つまり、前段回路１４１～１４３は、活性化信号１５１Ｐ～１５３Ｐまたは活性化信号１５１Ｎ～１５３Ｎによって、対応する出力ユニットの活性化を指示されると、インピーダンス調整コードＤＲＺＱに応じて、対応する出力ユニットの中の単位バッファ１１１～１１４、１２１、１２２、１３１のそれぞれに含まれる複数の出力トランジスタ（後述）のいずれをオンさせるかを指定する。これら出力トランジスタのオン／オフは、活性化信号１４１Ｐ～１４３Ｐ及び活性化信号１４１Ｎ～１４３Ｎによって指定される。 Pre-stage circuits 141 to 143 are provided in front of the output units 110 to 130, respectively. The pre-stage circuits 141 to 143 specify whether or not to activate the corresponding output unit, and adjust the impedance of the unit buffer included in the corresponding output unit. As shown in FIG. 2, activation signals 151P to 153P and activation signals 151N to 153N are supplied from the output control circuit 150 to the pre-stage circuits 141 to 143, and an impedance adjustment code DRZQ is supplied from the calibration circuit 100 in common. Is done. That is, when the activation circuits 151P to 153P or the activation signals 151N to 153N are instructed to activate the corresponding output units, the pre-stage circuits 141 to 143 indicate the corresponding output units according to the impedance adjustment code DRZQ. It designates which of a plurality of output transistors (described later) included in each of the unit buffers 111 to 114, 121, 122, 131 to be turned on. On / off of these output transistors is designated by activation signals 141P to 143P and activation signals 141N to 143N.
　出力制御回路１５０は、複数の出力ユニット１１０～１３０のうち活性化させる出力ユニット１１０～１３０を指定するとともに、活性化させる単位バッファの出力論理レベルを指定する。活性化させる出力ユニットの指定は、モードレジスタ１４から供給される駆動能力設定信号ＤＳに基づく。 The output control circuit 150 designates the output units 110 to 130 to be activated among the plurality of output units 110 to 130, and designates the output logic level of the unit buffer to be activated. The designation of the output unit to be activated is based on the drive capability setting signal DS supplied from the mode register 14.
　このように、出力制御回路１５０が、駆動能力設定信号ＤＳに基づいて、活性化対象の出力ユニットを選択することで、データ端子を駆動する単位バッファの数を変化させる。活性化される単位バッファの数が変化すると、出力端子のインピーダンス（出力インピーダンス）が変化する。図２に示すように、本実施形態では、単位バッファ１１１～１１４、１２１、１２２、１３１が出力制御回路１５０とデータ端子２４との間に並列接続されているため、活性化される単位バッファの数が増えると出力インピーダンスは減少し、逆に、活性化される単位バッファの数が減ると出力インピーダンスは増加する。 As described above, the output control circuit 150 selects the output unit to be activated based on the drive capability setting signal DS, thereby changing the number of unit buffers for driving the data terminals. When the number of unit buffers to be activated changes, the impedance (output impedance) of the output terminal changes. As shown in FIG. 2, in this embodiment, the unit buffers 111 to 114, 121, 122, 131 are connected in parallel between the output control circuit 150 and the data terminal 24. When the number increases, the output impedance decreases. Conversely, when the number of activated unit buffers decreases, the output impedance increases.
　図３は、単位バッファ１３１の回路図である。 FIG. 3 is a circuit diagram of the unit buffer 131.
　図３に示すように、単位バッファ１３１は、電源線（電源電位ＶＤＤＱ）とノードＢとの間に並列接続された複数（本実施形態では５つ）のＰチャンネルＭＯＳトランジスタ（出力トランジスタ、第１のトランジスタ）２１１～２１５と、電源線（電源電位ＶＳＳＱ）とノードＢとの間に並列接続された複数（本実施形態では５つ）のＮチャンネルＭＯＳトランジスタ（出力トランジスタ、第２のトランジスタ）２２１～２２５とを備える。また、ノードＢはダンピング抵抗Ｒ１４、及び、静電気保護部１６０を介してデータ端子２４に接続される。単位バッファ１３１のうち、ＰチャンネルＭＯＳトランジスタ２１１～２１５からなる部分はプルアップ回路１８を構成しており、ＮチャンネルＭＯＳトランジスタ２２１～２２５からなる部分はプルダウン回路１９を構成している。 As shown in FIG. 3, the unit buffer 131 includes a plurality (five in this embodiment) of P-channel MOS transistors (output transistors, first transistors) connected in parallel between the power supply line (power supply potential VDDQ) and the node B. Transistors) 211 to 215, and a plurality (five in this embodiment) of N-channel MOS transistors (output transistors, second transistors) 221 connected in parallel between the power supply line (power supply potential VSSQ) and the node B. To 225. The node B is connected to the data terminal 24 via the damping resistor R14 and the electrostatic protection unit 160. In the unit buffer 131, a part composed of P channel MOS transistors 211 to 215 constitutes a pull-up circuit 18, and a part composed of N channel MOS transistors 221 to 225 constitutes a pull-down circuit 19.
　出力トランジスタ２１１～２１５のゲートには、活性化信号１４３Ｐを構成する５つの活性化信号１４３Ｐ１～１４３Ｐ５が供給され、出力トランジスタ２２１～２２５のゲートには、活性化信号１４３Ｎを構成する５つの活性化信号１４３Ｎ１～１４３Ｎ５が供給される。これにより、単位バッファ１３１に含まれる１０個のＭＯＳトランジスタは、１０本の活性化信号１４３Ｐ１～１４３Ｐ５と活性化信号１４３Ｎ１～１４３Ｎ５によって、個別にオン／オフ制御される。 Five activation signals 143P1 to 143P5 constituting the activation signal 143P are supplied to the gates of the output transistors 211 to 215, and five activation signals constituting the activation signal 143N are supplied to the gates of the output transistors 221 to 225. Signals 143N1 to 143N5 are supplied. As a result, the ten MOS transistors included in the unit buffer 131 are individually turned on / off by the ten activation signals 143P1 to 143P5 and the activation signals 143N1 to 143N5.
　プルアップ回路１８とプルダウン回路１９は、それぞれ、導通時に所定のインピーダンス（実施例においては、１２０Ω）となるように設計されている。しかしながら、出力トランジスタのオン抵抗は製造条件によってばらつくとともに、動作時における環境温度や電源電圧によって変動することから、必ずしも所望のインピーダンスが得られるとは限らない。このため、実際のインピーダンスを目標値とするためには、オンさせるべき出力トランジスタの数を調整する必要があり、かかる目的のために、複数の出力トランジスタからなる並列回路が用いられている。 The pull-up circuit 18 and the pull-down circuit 19 are each designed to have a predetermined impedance (120Ω in the embodiment) when conducting. However, the on-resistance of the output transistor varies depending on the manufacturing conditions and varies depending on the environmental temperature and the power supply voltage during operation. Therefore, a desired impedance is not always obtained. For this reason, in order to set the actual impedance to the target value, it is necessary to adjust the number of output transistors to be turned on. For this purpose, a parallel circuit including a plurality of output transistors is used.
　単位バッファ１３１のインピーダンスを微細且つ広範囲に調整するためには、プルアップ回路１８及びプルダウン回路１９を構成する複数の出力トランジスタのＷ／Ｌ比（ゲート幅／ゲート長比）を互いに異ならせることが好ましく、２のべき乗の重み付けをすることが特に好ましい。すなわち、出力トランジスタ２１１のＷ／Ｌ比を「１ＷＬｐ」とした場合、出力トランジスタ２１２～２１５のＷ／Ｌ比をそれぞれ「２ＷＬｐ」、「４ＷＬｐ」、「８ＷＬｐ」、「１６ＷＬｐ」に設定することが特に好ましい。同様に、出力トランジスタ２２１のＷ／Ｌ比を「１ＷＬｎ」とした場合、出力トランジスタ２２２～２２５のＷ／Ｌ比をそれぞれ「２ＷＬｎ」、「４ＷＬｎ」、「８ＷＬｎ」、「１６ＷＬｎ」に設定することが特に好ましい。 In order to finely adjust the impedance of the unit buffer 131 over a wide range, the W / L ratio (gate width / gate length ratio) of the plurality of output transistors constituting the pull-up circuit 18 and the pull-down circuit 19 may be different from each other. It is particularly preferable to weight the power of 2. That is, when the W / L ratio of the output transistor 211 is “1WLp”, the W / L ratios of the output transistors 212 to 215 can be set to “2WLp”, “4WLp”, “8WLp”, and “16WLp”, respectively. Particularly preferred. Similarly, when the W / L ratio of the output transistor 221 is “1WLn”, the W / L ratios of the output transistors 222 to 225 are set to “2WLn”, “4WLn”, “8WLn”, and “16WLn”, respectively. Is particularly preferred.
　他の単位バッファ１１１～１１４、１２１、１２２についても、それらに対応する活性化信号１４１Ｐ、１４２Ｐ及び動作信号１４１Ｎ、１４２Ｎが入力される他は、図３に示した単位バッファ１３１と実質的に同じ回路構成を有している。 The other unit buffers 111 to 114, 121, and 122 are substantially the same as the unit buffer 131 shown in FIG. 3 except that the activation signals 141P and 142P and the operation signals 141N and 142N corresponding thereto are input. It has a circuit configuration.
　図４は、キャリブレーション回路１００の回路図である。 FIG. 4 is a circuit diagram of the calibration circuit 100.
　図４に示すように、キャリブレーション回路１００は、プルアップ回路（レプリカ回路）３１０，３２０と、プルダウン回路３３０と、プルアップ回路３１０，３２０の動作を制御するカウンタ３４０と、プルダウン回路３３０の動作を制御するカウンタ３５０と、カウンタ３４０を制御するコンパレータ３６０と、カウンタ３５０を制御するコンパレータ３７０と、コンパレータ３６０、３７０に基準電圧ＺＱＶＲＥＦ（＝１／２ＶＤＤ）を供給する電圧発生回路３８０と、カウンタの動作信号ＡＣＴ１，ＡＣＴ２を発生するキャリブレーション制御回路３９０と、を備えている。また、キャリブレーション回路１００は、プルアップ回路３１０とキャリブレーション端子ＺＱとの間に直列に接続されたダンピング抵抗Ｒ２１（第２の抵抗部、第２ダンピング抵抗）と、補正抵抗３１１（第３の抵抗部、補正抵抗）と、静電気保護部３１２とを含む。さらにまた、キャリブレーション回路１００は、プルアップ回路３２０とノードＡとの間に接続されたダンピング抵抗Ｒ２２及び補正抵抗３２１と、プルダウン回路３３０とノードＡとの間に接続されたダンピング抵抗Ｒ２３及び補正抵抗３３１とを含む。ノードＡは、コンパレータ３７０の一方の入力端子に接続される。補正抵抗３１１と静電気保護部３１２の詳細については、後述する。 As shown in FIG. 4, the calibration circuit 100 includes pull-up circuits (replica circuits) 310 and 320, a pull-down circuit 330, a counter 340 that controls operations of the pull-up circuits 310 and 320, and an operation of the pull-down circuit 330. A counter 350 for controlling the counter 350, a comparator 360 for controlling the counter 340, a comparator 370 for controlling the counter 350, a voltage generation circuit 380 for supplying the reference voltage ZQVREF (= 1 / 2VDD) to the comparators 360 and 370, And a calibration control circuit 390 for generating operation signals ACT1 and ACT2. The calibration circuit 100 includes a damping resistor R21 (second resistor unit, second damping resistor) and a correction resistor 311 (third resistor) connected in series between the pull-up circuit 310 and the calibration terminal ZQ. Resistance portion, correction resistor) and electrostatic protection portion 312. Furthermore, the calibration circuit 100 includes a damping resistor R22 and a correction resistor 321 connected between the pull-up circuit 320 and the node A, and a damping resistor R23 and a correction connected between the pull-down circuit 330 and the node A. And a resistor 331. Node A is connected to one input terminal of comparator 370. Details of the correction resistor 311 and the electrostatic protection unit 312 will be described later.
　図５は、プルアップ回路３１０の回路図である。 FIG. 5 is a circuit diagram of the pull-up circuit 310.
　図５に示すように、プルアップ回路３１０は、単位バッファ１１１～１１４、１２１、１２２、１３１に含まれるプルアップ回路１８と実質的に同じ回路構成を有する。具体的には、プルアップ回路３１０は、電源線（電源電位ＶＤＤ）とダンピング抵抗Ｒ２１との間に並列接続された５つのＰチャンネルＭＯＳトランジスタ４１１～４１５とを備える。 As shown in FIG. 5, the pull-up circuit 310 has substantially the same circuit configuration as the pull-up circuit 18 included in the unit buffers 111 to 114, 121, 122, 131. Specifically, the pull-up circuit 310 includes five P-channel MOS transistors 411 to 415 connected in parallel between the power supply line (power supply potential VDD) and the damping resistor R21.
　以下、プルアップ回路３１０、補正抵抗３１１、静電気保護部３１２、キャリブレーション端子ＺＱおよび外部抵抗Ｒｅをまとめて「調整バッファ５０（第２バッファ）」とよぶこともある。 Hereinafter, the pull-up circuit 310, the correction resistor 311, the electrostatic protection unit 312, the calibration terminal ZQ, and the external resistor Re may be collectively referred to as “adjustment buffer 50 (second buffer)”.
　プルアップ回路３１０に含まれるトランジスタ４１１～４１５は、図３に示した出力トランジスタ２１１～２１５に対応しており、それぞれ同一のインピーダンスを有している。したがって、トランジスタ２１１～２１５のＷ／Ｌ比と同様、トランジスタ４１１～４１５のＷ／Ｌ比もそれぞれ「１ＷＬｐ」、「２ＷＬｐ」、「４ＷＬｐ」、「８ＷＬｐ」、「１６ＷＬｐ」に設定されている。但し、インピーダンスが実質的に同じである限り、プルアップ回路３１０に含まれるトランジスタ４１１～４１５と、図３に示す出力トランジスタ２１１～２１５とが全く同じトランジスタサイズである必要はなく、シュリンクしたトランジスタを用いても構わない。 The transistors 411 to 415 included in the pull-up circuit 310 correspond to the output transistors 211 to 215 shown in FIG. 3, and have the same impedance. Therefore, similarly to the W / L ratios of the transistors 211 to 215, the W / L ratios of the transistors 411 to 415 are set to “1WLp”, “2WLp”, “4WLp”, “8WLp”, and “16WLp”, respectively. However, as long as the impedance is substantially the same, the transistors 411 to 415 included in the pull-up circuit 310 and the output transistors 211 to 215 shown in FIG. 3 do not have to have the same transistor size. You may use.
　トランジスタ４１１～４１５のゲートには、カウンタ３４０よりインピーダンスコードＤＲＺＱＰ１～ＤＲＺＱＰ５が供給され、これによってプルアップ回路３１０が制御される。インピーダンスコードＤＲＺＱＰ１～ＤＲＺＱＰ５は、それぞれ活性化信号１４１Ｐ１～１４１Ｐ５に対応する。 Impedance codes DRZQP1 to DRZQP5 are supplied from the counter 340 to the gates of the transistors 411 to 415, whereby the pull-up circuit 310 is controlled. Impedance codes DRZQP1 to DRZQP5 correspond to activation signals 141P1 to 141P5, respectively.
　プルアップ回路３２０についても、図５に示したプルアップ回路３１０と同一の回路構成を有している。プルアップ回路３２０側に含まれる５つのトランジスタのゲートにも、インピーダンスコードＤＲＺＱＰ１～ＤＲＺＱＰ５が供給される。 The pull-up circuit 320 also has the same circuit configuration as the pull-up circuit 310 shown in FIG. Impedance codes DRZQP1 to DRZQP5 are also supplied to the gates of the five transistors included in the pull-up circuit 320 side.
　図６は、プルダウン回路３３０の回路図である。 FIG. 6 is a circuit diagram of the pull-down circuit 330.
　図６に示すように、プルダウン回路３３０は、単位バッファ１１１～１１４、１２１、１２２、１３１に含まれるプルダウン回路１９と実質的に同じ回路構成を有している。具体的には、プルダウン回路３３０は、電源線（電源電位ＶＳＳ）とノードＡとの間に並列接続された５つのＮチャンネルＭＯＳトランジスタ４２１～４２５とを備える。プルダウン回路３３０に含まれるトランジスタ４２１～４２５は、図３に示したトランジスタ２２１～２２５に対応しており、それぞれ同一のインピーダンスを有している。この点は、プルアップ回路３１０と同様である。 As shown in FIG. 6, the pull-down circuit 330 has substantially the same circuit configuration as the pull-down circuit 19 included in the unit buffers 111 to 114, 121, 122, and 131. Specifically, the pull-down circuit 330 includes five N-channel MOS transistors 421 to 425 connected in parallel between the power supply line (power supply potential VSS) and the node A. Transistors 421 to 425 included in the pull-down circuit 330 correspond to the transistors 221 to 225 shown in FIG. 3 and have the same impedance. This is the same as the pull-up circuit 310.
　ダンピング抵抗Ｒ２１は、図２に示した出力ユニット１３０のダンピング抵抗Ｒ１４に対応しており、その抵抗値は１２０Ωに設定される。この理由は、本実施形態において、キャリブレーション回路１００が１つの単位バッファからなる出力ユニット、即ち、図２の出力ユニット１３０に対応するように構成されるからである。 The damping resistor R21 corresponds to the damping resistor R14 of the output unit 130 shown in FIG. 2, and its resistance value is set to 120Ω. This is because, in the present embodiment, the calibration circuit 100 is configured to correspond to the output unit composed of one unit buffer, that is, the output unit 130 of FIG.
　また、ダンピング抵抗Ｒ２２及び補正抵抗３２１は、それぞれ、ダンピング抵抗Ｒ２１及び補正抵抗３１１に対応する抵抗である。このような構成とすることで、プルアップ回路３１０からみたノードＣとプルアップ回路３２０からみたノードＡとが実質的に同一の関係となる。ここで、ダンピング抵抗Ｒ２２は、ダンピング抵抗Ｒ２１と実質的に同一の抵抗値（１２０Ω）を有し、また、補正抵抗３２１は、補正抵抗３１１と実質的に同一の抵抗値（後述）を有する。 Further, the damping resistor R22 and the correction resistor 321 are resistors corresponding to the damping resistor R21 and the correction resistor 311, respectively. With such a configuration, the node C viewed from the pull-up circuit 310 and the node A viewed from the pull-up circuit 320 have substantially the same relationship. Here, the damping resistor R22 has substantially the same resistance value (120Ω) as the damping resistor R21, and the correction resistor 321 has substantially the same resistance value (described later) as the correction resistor 311.
　また、ダンピング抵抗Ｒ２３及び補正抵抗３３１は、それぞれ、ダンピング抵抗Ｒ２２及び補正抵抗３２１に対応する抵抗である。このような構成とすることで、ノードＡから見たプルアップ回路３２０とノードＡから見たプルダウン回路３３０とが実質的に同一の関係となり、プルダウン回路３３０の調整をより精確に行うことができる。ここで、ダンピング抵抗Ｒ２３は、ダンピング抵抗Ｒ２２と実質的に同一の抵抗値（１２０Ω）を有し、また、補正抵抗３３１は、補正抵抗３２１と実質的に同一の抵抗値を有する。 Further, the damping resistor R23 and the correction resistor 331 are resistors corresponding to the damping resistor R22 and the correction resistor 321, respectively. With such a configuration, the pull-up circuit 320 viewed from the node A and the pull-down circuit 330 viewed from the node A have substantially the same relationship, and the pull-down circuit 330 can be adjusted more accurately. . Here, the damping resistor R23 has substantially the same resistance value (120Ω) as the damping resistor R22, and the correction resistor 331 has substantially the same resistance value as the correction resistor 321.
　トランジスタ４２１～４２５のゲートには、カウンタ３５０よりインピーダンスコードＤＲＺＱＮ１～ＤＲＺＱＮ５が供給され、これによってプルダウン回路３３０が制御される。インピーダンスコードＤＲＺＱＮ１～ＤＲＺＱＮ５は、それぞれ活性化信号１６１Ｎ１～１６１Ｎ５に対応する。 Impedance codes DRZQN1 to DRZQN5 are supplied from the counter 350 to the gates of the transistors 421 to 425, whereby the pull-down circuit 330 is controlled. Impedance codes DRZQN1 to DRZQN5 correspond to activation signals 161N1 to 161N5, respectively.
　このように、プルアップ回路３１０，３２０は、いずれも単位バッファ１１１～１１４、１２１、１２２、１３１に含まれるプルアップ回路１８と実質的に同じ回路構成を有しており、プルダウン回路３３０は、単位バッファ１１１～１１４、１２１、１２２、１３１に含まれるプルダウン回路１９と実質的に同じ回路構成を有している。 As described above, the pull-up circuits 310 and 320 all have substantially the same circuit configuration as the pull-up circuit 18 included in the unit buffers 111 to 114, 121, 122, and 131. The pull-down circuit 19 included in the unit buffers 111 to 114, 121, 122, 131 has substantially the same circuit configuration.
　図４に示すように、プルアップ回路３２０とプルダウン回路３３０は、単位バッファ１１１と実質的に同じ回路構成をもった「レプリカバッファ」を構成する。ここでいう「実質的に同じ」とは、レプリカバッファに含まれるトランジスタがシュリンクされている場合であっても同じとみなす意である。レプリカバッファの出力端である接点Ａは、図４に示すように、コンパレータ３７０の非反転入力端子（＋）に接続されている。 As shown in FIG. 4, the pull-up circuit 320 and the pull-down circuit 330 constitute a “replica buffer” having a circuit configuration substantially the same as that of the unit buffer 111. Here, “substantially the same” means that the transistors included in the replica buffer are regarded as the same even if they are shrunk. As shown in FIG. 4, the contact A that is the output terminal of the replica buffer is connected to the non-inverting input terminal (+) of the comparator 370.
　キャリブレーション制御回路３９０は、キャリブレーション信号ＺＱＣＯＭと内部クロックＩＣＬＫに応じて、カウンタ３４０の動作信号ＡＣＴ１とカウンタ３５０の動作信号ＡＣＴ２とをそれぞれ発生する。 The calibration control circuit 390 generates the operation signal ACT1 of the counter 340 and the operation signal ACT2 of the counter 350 in response to the calibration signal ZQCOM and the internal clock ICLK.
　コンパレータ３６０は、ノードＣの電位と基準電圧ＺＱＶＲＥＦとを比較し、比較結果に基づいてハイレベル又はローレベルのいずれか一方の論理レベルをとる比較結果信号ＣＯＭＰ１を出力する。 The comparator 360 compares the potential of the node C with the reference voltage ZQVREF, and outputs a comparison result signal COMP1 that takes either the high level or the low level based on the comparison result.
　コンパレータ３７０は、ノードＡの電位と基準電圧ＺＱＶＲＥＦとを比較し、比較結果に基づいてハイレベル又はローレベルのいずれか一方の論理レベルをとる比較結果信号ＣＯＭＰ２を出力する。 The comparator 370 compares the potential of the node A with the reference voltage ZQVREF, and outputs a comparison result signal COMP2 that takes either the high level or the low level based on the comparison result.
　カウンタ３４０は、動作制御信号ＡＣＴ１に同期して、コンパレータ３６０の出力信号ＣＯＭＰ１の論理レベルに応じて自身のカウント値をカウントアップ又カウントダウンする。カウンタ３４０のカウント値はインピーダンスコードＤＲＺＱＰとして用いられる。 The counter 340 counts up or down its own count value according to the logic level of the output signal COMP1 of the comparator 360 in synchronization with the operation control signal ACT1. The count value of the counter 340 is used as the impedance code DRZQP.
　一方、カウンタ３５０は、動作制御信号ＡＣＴ２に同期して、コンパレータ３７０の出力信号ＣＯＭＰ２の論理レベルに応じて自身のカウント値をカウントアップ又カウントダウンする。カウンタ３５０のカウント値はインピーダンスコードＤＲＺＱＮとして用いられる。 On the other hand, the counter 350 counts up or counts down its own count value in accordance with the logic level of the output signal COMP2 of the comparator 370 in synchronization with the operation control signal ACT2. The count value of the counter 350 is used as the impedance code DRZQN.
　以上が、入出力回路１６及びキャリブレーション回路１００の構成である。キャリブレーション動作においては、キャリブレーション回路１００が、プルアップ回路３１０及びダンピング抵抗Ｒ２１の合成インピーダンスを外部抵抗Ｒｅのインピーダンスと一致させるようにプルアップ回路３１０のインピーダンス及びプルダウン回路３３０のインピーダンスをそれぞれ１２０Ωに調整する。そして、この調整結果を利用して入出力回路１６の各単位バッファのプルアップ回路１８及びプルダウン回路１９のそれぞれのインピーダンスを１２０Ωに設定する。しかしながら、従来のキャリブレーション回路は、入出力回路１６の静電気保護部１６０を通過する配線やキャリブレーション回路１００の静電気保護部３１２を通過する配線の配線抵抗の影響を考慮しておらず、このため、キャリブレーション動作後の各単位バッファのインピーダンスが、所望の値からずれてしまう恐れがあった。本実施形態では、このずれを解消するために、キャリブレーション回路１００のダンピング抵抗Ｒ２１とノードＣとの間に補正抵抗３１１を配置する。以下、静電気保護部３１２を通過する配線がキャリブレーション動作に与える影響、及び、補正抵抗３１１の配置について、詳細に説明する。 The above is the configuration of the input / output circuit 16 and the calibration circuit 100. In the calibration operation, the calibration circuit 100 sets the impedance of the pull-up circuit 310 and the impedance of the pull-down circuit 330 to 120Ω so that the combined impedance of the pull-up circuit 310 and the damping resistor R21 matches the impedance of the external resistor Re. adjust. Then, using this adjustment result, the impedances of the pull-up circuit 18 and the pull-down circuit 19 of each unit buffer of the input / output circuit 16 are set to 120Ω. However, the conventional calibration circuit does not consider the influence of the wiring resistance of the wiring that passes through the electrostatic protection unit 160 of the input / output circuit 16 or the wiring that passes through the electrostatic protection unit 312 of the calibration circuit 100. The impedance of each unit buffer after the calibration operation may be deviated from a desired value. In the present embodiment, in order to eliminate this shift, the correction resistor 311 is disposed between the damping resistor R21 and the node C of the calibration circuit 100. Hereinafter, the influence of the wiring passing through the electrostatic protection unit 312 on the calibration operation and the arrangement of the correction resistor 311 will be described in detail.
　図７は、静電気保護部１６０を通過する配線の配線抵抗を考慮したときのデータ端子２４と出力回路１０１との接続関係を示す回路図である。特に、図７は、出力ユニット１３０とデータ端子２４との接続に着目した図である。データ端子２４などの外部端子には、静電気放電から半導体回路を守るためにＥＳＤ（Electro-Static Discharge）素子ＥＳＤ１（第１ＥＳＤ素子）が設置されることがある。このＥＳＤ素子は、例えば、ダイオード接続されたＭＯＳトランジスタ等から構成される。静電気放電から内部回路を保護するためには、外部端子に印加された静電気を速やかに電源線（図７では、ＶＳＳ電源線）に逃がす必要がある。このため、ＥＳＤ素子には、サイズの大きなＭＯＳトランジスタが使用される。 FIG. 7 is a circuit diagram showing the connection relationship between the data terminal 24 and the output circuit 101 when the wiring resistance of the wiring passing through the electrostatic protection unit 160 is taken into consideration. In particular, FIG. 7 is a diagram focusing on the connection between the output unit 130 and the data terminal 24. An external terminal such as the data terminal 24 may be provided with an ESD (Electro-Static Discharge) element ESD1 (first ESD element) to protect the semiconductor circuit from electrostatic discharge. The ESD element is composed of, for example, a diode-connected MOS transistor. In order to protect the internal circuit from electrostatic discharge, it is necessary to quickly release the static electricity applied to the external terminal to the power line (VSS power line in FIG. 7). For this reason, a large MOS transistor is used for the ESD element.
　図８は、データ端子２４と出力回路１０１との間のレイアウトを示す模式図である。また、図９は、本実施形態の半導体装置１０が含む多層配線構造を模式的に示した図である。 FIG. 8 is a schematic diagram showing a layout between the data terminal 24 and the output circuit 101. FIG. 9 is a diagram schematically showing a multilayer wiring structure included in the semiconductor device 10 of the present embodiment.
　図９に示すとおり、本実施形態の半導体装置１０は、基板ＳＳの表面に拡散層ＤＬ及びゲート配線層ＧＬが形成され、その上方に、基板ＳＳの表面に近い側から順に第１配線層Ｌ１、第２配線層Ｌ２、第３配線層Ｌ３、第４配線層Ｌ４が積層された構造を有している。第１配線層は、例えば、タングステンを含む配線層、第２乃至第４配線層は、それぞれアルミニウムや銅を含む配線層である。各層は、層間絶縁層ＩＬ１～ＩＬ４によって相互に絶縁される。また、最上層の第４配線層Ｌ４の上面は、保護用の層間絶縁層ＩＬ５によって覆われる。ゲート配線層ＧＬと基板ＳＳの表面の間には、薄いゲート絶縁膜ＧＩが形成される。拡散層ＤＬ及びゲート配線層ＧＬと第１配線層Ｌ１とは、層間絶縁層ＩＬ１を貫通するスルーホール電極ＴＨ０によって、必要な場所でのみ相互に接続される。同様に、第１配線層Ｌ１と第２配線層Ｌ２とは、層間絶縁層ＩＬ２を貫通するスルーホール電極ＴＨ１によって、必要な場所でのみ相互に接続される。また、第２配線層Ｌ２と第３配線層Ｌ３とは、層間絶縁層ＩＬ３を貫通するスルーホール電極ＴＨ２によって、必要な場所でのみ相互に接続される。さらに、第３配線層Ｌ３と第４配線層Ｌ４とは、層間絶縁層ＩＬ４を貫通するスルーホール電極ＴＨ３によって、必要な場所でのみ相互に接続される。 As shown in FIG. 9, in the semiconductor device 10 according to the present embodiment, the diffusion layer DL and the gate wiring layer GL are formed on the surface of the substrate SS, and the first wiring layer L1 is sequentially disposed above the diffusion layer DL and the gate wiring layer GL. The second wiring layer L2, the third wiring layer L3, and the fourth wiring layer L4 are stacked. For example, the first wiring layer is a wiring layer containing tungsten, and the second to fourth wiring layers are wiring layers containing aluminum or copper, respectively. Each layer is insulated from each other by interlayer insulating layers IL1 to IL4. The upper surface of the uppermost fourth wiring layer L4 is covered with a protective interlayer insulating layer IL5. A thin gate insulating film GI is formed between the gate wiring layer GL and the surface of the substrate SS. The diffusion layer DL, the gate wiring layer GL, and the first wiring layer L1 are connected to each other only at a necessary place by a through-hole electrode TH0 that penetrates the interlayer insulating layer IL1. Similarly, the first wiring layer L1 and the second wiring layer L2 are connected to each other only where necessary by a through-hole electrode TH1 that penetrates the interlayer insulating layer IL2. Further, the second wiring layer L2 and the third wiring layer L3 are connected to each other only at a necessary place by a through-hole electrode TH2 penetrating the interlayer insulating layer IL3. Further, the third wiring layer L3 and the fourth wiring layer L4 are connected to each other only at a necessary place by a through-hole electrode TH3 penetrating the interlayer insulating layer IL4.
　図８に示すとおり、第４配線層Ｌ４として形成されたデータパッドＤＱＰ（データ端子２４に対応）と出力回路１０１との間には、ＭＯＳトランジスタ構造で形成されたＥＳＤ素子ＥＳＤ１と、それぞれ第１配線層Ｌ１として形成されたダンピング抵抗Ｒ１１～Ｒ１４と、第２配線層Ｌ２として形成されＥＳＤ素子ＥＳＤ１の上方を通過してデータパッドＤＱＰとダンピング抵抗Ｒ１１～Ｒ１４のそれぞれの一端とを接続するデータ配線ＤＱＬ１（第１の配線）と、それぞれダンピング抵抗Ｒ１１～Ｒ１４のうちの対応する１つの他端と単位バッファ１１１～１１４、１２１、１２２、１３１のうちの対応する１又は複数個とを接続するデータ配線ＤＱＬ２とを含む。ＥＳＤ素子ＥＳＤ１は、シリコン等の基板ＳＳ中にソース・ドレインとして形成された拡散層ＤＬと基板ＳＳ上に形成されたゲート電極Ｇとを含む。ＥＳＤ素子１のソース・ドレインの一方は、スルーホール電極ＴＨ０、ＴＨ１及び第１配線層Ｌ１（図８には図示せず）を介してデータ配線ＤＱＬ１に接続される。ＥＳＤ素子ＥＳＤ１のソース・ドレインの他方は、不図示の電源線（ＶＳＳ電位）に接続される。データパッドＤＱＰは、スルーホール電極ＴＨ３、ＴＨ２及び第３配線層Ｌ３（図８には図示せず）を介してデータ配線ＤＱＬ１と接続される。データ配線ＤＱＬ１とダンピング抵抗Ｒ１１～Ｒ１４のそれぞれの一端は、スルーホール電極ＴＨ１を介して互いに接続される。同様に、ダンピング抵抗Ｒ１１～Ｒ１４の他端とデータ配線ＤＱＬ２とは、対応するスルーホール電極ＴＨ１を介して、互いに接続される。図８に示すように、データ配線ＤＱＬ１は、ＥＳＤ素子ＥＳＤ１の対応する拡散層ＤＬに接続されるためにスリット状の部分を含む。このため、本実施形態では、データ配線ＤＱＬ１は１Ω程度の配線抵抗を有する。 As shown in FIG. 8, between the data pad DQP (corresponding to the data terminal 24) formed as the fourth wiring layer L4 and the output circuit 101, the ESD element ESD1 formed in the MOS transistor structure, and the first A data wiring that connects the damping pads R11 to R14 formed as the wiring layer L1 and the data pad DQP and one end of each of the damping resistors R11 to R14 through the ESD element ESD1 formed as the second wiring layer L2. Data connecting DQL1 (first wiring), one corresponding other end of each of the damping resistors R11 to R14, and one or more corresponding ones of the unit buffers 111 to 114, 121, 122, 131 Wiring DQL2. The ESD element ESD1 includes a diffusion layer DL formed as a source / drain in a substrate SS such as silicon and a gate electrode G formed on the substrate SS. One of the source and drain of the ESD element 1 is connected to the data wiring DQL1 via the through-hole electrodes TH0 and TH1 and the first wiring layer L1 (not shown in FIG. 8). The other of the source and drain of the ESD element ESD1 is connected to a power line (not shown) (VSS potential). The data pad DQP is connected to the data wiring DQL1 through the through-hole electrodes TH3 and TH2 and the third wiring layer L3 (not shown in FIG. 8). One end of each of the data line DQL1 and the damping resistors R11 to R14 is connected to each other through the through-hole electrode TH1. Similarly, the other ends of the damping resistors R11 to R14 and the data wiring DQL2 are connected to each other through the corresponding through-hole electrode TH1. As shown in FIG. 8, the data line DQL1 includes a slit-like portion to be connected to the corresponding diffusion layer DL of the ESD element ESD1. For this reason, in this embodiment, the data wiring DQL1 has a wiring resistance of about 1Ω.
　再び図７に戻って、上述のデータ配線ＤＱＬ１の配線抵抗を考慮して、出力ユニット１３０がデータ端子２４を駆動するインピーダンスを計算すると、ｒｍ＋ｒ１＋ｒｄＥＳＤとなる。ｒｍはプルアップ回路１８のインピーダンスを示し、ｒ１はダンピング抵抗Ｒ１４の抵抗値を示す。また、ｒｄＥＳＤは、データ配線ＤＱＬ１の抵抗値を示し、具体的には、データ端子２４からダンピング抵抗Ｒ１４の一端までの抵抗値を示す。即ち、ｒｄＥＳＤは、図８において、データパッドＤＱＰからダンピング抵抗Ｒ１４の一端とデータ配線ＤＱＬ１とを接続するスルーホール電極ＴＨ１までの抵抗値を示す。 Returning to FIG. 7 again, when the impedance at which the output unit 130 drives the data terminal 24 is calculated in consideration of the wiring resistance of the data wiring DQL1, the result is rm + r1 + rdESD. rm represents the impedance of the pull-up circuit 18, and r1 represents the resistance value of the damping resistor R14. Further, rdESD indicates the resistance value of the data wiring DQL1, and specifically indicates the resistance value from the data terminal 24 to one end of the damping resistor R14. That is, in FIG. 8, rdESD indicates the resistance value from the data pad DQP to the through-hole electrode TH1 that connects one end of the damping resistor R14 and the data wiring DQL1.
　図１０は、従来のキャリブレーション回路における調整バッファ５０'の構成を示す回路図である（補正抵抗なし）。この調整バッファ５０'は、図４に示した調整バッファ５０に対応する。上述のとおり、データ端子２４と同様、キャリブレーション端子ＺＱにもＥＳＤ素子ＥＳＤ２（第２ＥＳＤ素子）が設置される。このため、ノードＣからキャリブレーション端子ＺＱの間には、キャリブレーション配線ＺＱＬ１（抵抗値ｒｚＥＳＤ）が存在する。 FIG. 10 is a circuit diagram showing the configuration of the adjustment buffer 50 ′ in the conventional calibration circuit (no correction resistor). The adjustment buffer 50 ′ corresponds to the adjustment buffer 50 shown in FIG. As described above, like the data terminal 24, the ESD element ESD2 (second ESD element) is also installed in the calibration terminal ZQ. Therefore, the calibration wiring ZQL1 (resistance value rzESD) exists between the node C and the calibration terminal ZQ.
　プルアップ回路３１０のインピーダンスをｒｍとすると、コンパレータ３６０はｒｍ＋ｒ１＝ｒｅではなく、より厳密には、ｒｍ＋ｒ１＝ｒｚＥＳＤ＋ｒｅとなるｒｍを探ることになる。ここでｒｅは外部抵抗Ｒｅの抵抗値を示す。また、ｒ１はダンピング抵抗Ｒ２１の抵抗値を示し、この値は、出力ユニット１３０のダンピング抵抗Ｒ１４と等しくなるように設定されている。この結果を用いて出力ユニット１３０の単位バッファ１３１のインピーダンスを調整した場合、即ち、出力ユニット１３０の単位バッファ１３１のインピーダンスｒｍがプルアップ回路３１０のインピーダンスｒｍ＝ｒｚＥＳＤ＋ｒｅ－ｒ１と等しくなるように単位バッファ１３１のインピーダンスを調整した場合、出力ユニット１３０の単位バッファがデータ端子２４を駆動するインピーダンスがｒｅ＋ｒｄＥＤＳ＋ｒｚＥＤＳとなる。つまり、出力ユニット１３０の単位バッファがデータ端子２４を駆動するインピーダンスが外部抵抗Ｒｅのインピーダンスからずれてしまう恐れがある。他の単位バッファにおいても同様の問題が生じる。したがって、プルアップ回路３１０の調整内容をレプリカバッファに反映させ、レプリカバッファの調整内容を出力バッファのプルアップ回路１８に反映させるときには、図７、８に示したデータ配線ＤＱＬ１と図１０に示したキャリブレーション配線ＺＱＬ１の配線抵抗も考慮することが望ましい。 Suppose that the impedance of the pull-up circuit 310 is rm, the comparator 360 is not rm + r1 = re, but more strictly, it searches for rm that satisfies rm + r1 = rzESD + re. Here, re indicates the resistance value of the external resistor Re. R1 represents the resistance value of the damping resistor R21, and this value is set to be equal to the damping resistor R14 of the output unit 130. When the impedance of the unit buffer 131 of the output unit 130 is adjusted using this result, that is, the unit buffer 131 so that the impedance rm of the unit buffer 131 of the output unit 130 becomes equal to the impedance rm = rzESD + re−r1 of the pull-up circuit 310. When the impedance of 131 is adjusted, the impedance at which the unit buffer of the output unit 130 drives the data terminal 24 becomes re + rdEDS + rzEDS. That is, there is a possibility that the impedance at which the unit buffer of the output unit 130 drives the data terminal 24 deviates from the impedance of the external resistor Re. Similar problems occur in other unit buffers. Therefore, when the adjustment contents of the pull-up circuit 310 are reflected in the replica buffer and the adjustment contents of the replica buffer are reflected in the pull-up circuit 18 of the output buffer, the data wiring DQL1 shown in FIGS. It is desirable to consider the wiring resistance of the calibration wiring ZQL1.
　図１１は、本実施形態において補正抵抗３１１を追加したプルアップ回路３１０とキャリブレーション端子ＺＱの接続関係を示す回路図（第１構成例）である。本実施形態においては、ダンピング抵抗Ｒ２１と接続点Ｃの間に補正抵抗３１１を追加している。この補正抵抗３１１により、図７、８に示したデータ配線ＤＱＬ１の配線抵抗と図１０、１１に示したキャリブレーション配線ＺＱＬ１の配線抵抗の影響を相殺する。 FIG. 11 is a circuit diagram (first configuration example) showing a connection relationship between the pull-up circuit 310 to which the correction resistor 311 is added and the calibration terminal ZQ in the present embodiment. In the present embodiment, a correction resistor 311 is added between the damping resistor R21 and the connection point C. The correction resistor 311 cancels the influence of the wiring resistance of the data wiring DQL1 shown in FIGS. 7 and 8 and the wiring resistance of the calibration wiring ZQL1 shown in FIGS.
　図１１に示す回路図のキャリブレーション端子ＺＱとプルアップ回路３１０及びコンパレータ３６０間のレイアウトを示す模式図を図１２に示す。 FIG. 12 is a schematic diagram showing a layout between the calibration terminal ZQ, the pull-up circuit 310, and the comparator 360 in the circuit diagram shown in FIG.
　図１２に示すとおり、第４配線層Ｌ４として形成されたキャリブレーションパッドＺＱＰ（キャリブレーション端子ＺＱに対応）とプルアップ回路３１０及びコンパレータ３６０との間には、ＭＯＳトランジスタ構造で形成されたＥＳＤ素子ＥＳＤ２と、第２配線層Ｌ２として形成されたキャリブレーション配線ＺＱＬ１（第２の配線）、ＺＱＬ２（第３の配線）、及び、補正抵抗３１１と、第１配線層Ｌ１として形成されたダンピング抵抗Ｒ２１と、を含む。ＥＳＤ素子ＥＳＤ２は、図８に示したＥＳＤ素子ＥＳＤ１と同様に、シリコン等の基板ＳＳ中にソース・ドレインとして形成された拡散層ＤＬと基板ＳＳ上に形成されたゲート電極Ｇとを含む。ＥＳＤ素子ＥＳＤ２のソース・ドレインの一方は、スルーホール電極ＴＨ０、ＴＨ１及び第１配線層Ｌ１（図１２には図示せず）を介してキャリブレーション配線ＺＱＬ１に接続される。ＥＳＤ素子ＥＳＤ１のソース・ドレインの他方は、不図示の電源線（ＶＳＳ電位）に接続される。キャリブレーションパッドＺＱＰは、スルーホール電極ＴＨ３、ＴＨ２及び第３配線層Ｌ３（図１２には図示せず）を介してキャリブレーション配線ＺＱＬ１と接続される。図１２に示すように、キャリブレーション配線ＺＱＬ１は、ＥＳＤ素子ＥＳＤ２の対応する拡散層ＤＬに接続されるためにスリット状の部分を含む。このため、本実施形態では、キャリブレーション配線ＺＱＬ１は１Ω程度の配線抵抗を有する。 As shown in FIG. 12, between the calibration pad ZQP (corresponding to the calibration terminal ZQ) formed as the fourth wiring layer L4 and the pull-up circuit 310 and the comparator 360, an ESD element formed with a MOS transistor structure. ESD2, calibration wiring ZQL1 (second wiring), ZQL2 (third wiring) formed as the second wiring layer L2, correction resistor 311 and damping resistance R21 formed as the first wiring layer L1 And including. Similarly to the ESD element ESD1 shown in FIG. 8, the ESD element ESD2 includes a diffusion layer DL formed as a source / drain in a substrate SS such as silicon and a gate electrode G formed on the substrate SS. One of the source and drain of the ESD element ESD2 is connected to the calibration wiring ZQL1 via the through-hole electrodes TH0 and TH1 and the first wiring layer L1 (not shown in FIG. 12). The other of the source and drain of the ESD element ESD1 is connected to a power line (not shown) (VSS potential). The calibration pad ZQP is connected to the calibration wiring ZQL1 through the through-hole electrodes TH3 and TH2 and the third wiring layer L3 (not shown in FIG. 12). As shown in FIG. 12, the calibration wiring ZQL1 includes a slit-like portion to be connected to the corresponding diffusion layer DL of the ESD element ESD2. For this reason, in the present embodiment, the calibration wiring ZQL1 has a wiring resistance of about 1Ω.
　また、キャリブレーション配線ＺＱＬ１が、コンパレータ３６０に向かうキャリブレーション配線ＺＱＬ２とプルアップ回路３１０に向かう補正抵抗３１１とに分岐する分岐点が、図１１のノードＣに対応する。補正抵抗３１１は、一端でスルーホール電極ＴＨ１を介してダンピング抵抗Ｒ２１の一端と接続される。 Further, a branch point where the calibration wiring ZQL1 branches to the calibration wiring ZQL2 toward the comparator 360 and the correction resistor 311 toward the pull-up circuit 310 corresponds to the node C in FIG. The correction resistor 311 is connected to one end of the damping resistor R21 through the through-hole electrode TH1 at one end.
　図１２において、図１１に示したキャリブレーション配線ＺＱＬ１の配線抵抗の抵抗値ｒｚＥＳＤは、キャリブレーションパッドＺＱＰからノードＣまでの抵抗値に対応する。 12, the resistance value rzESD of the wiring resistance of the calibration wiring ZQL1 shown in FIG. 11 corresponds to the resistance value from the calibration pad ZQP to the node C.
　次に、補正抵抗３１１の抵抗値の決め方について説明する。補正抵抗３１１の抵抗値ｒｃは、下記の方法により算出される。プルアップ回路３１０の抵抗値ｒｍは、ｒｍ＋ｒ１＋ｒｃ＝ｒｚＥＳＤ＋ｒｅが成立するように調整される。この抵抗値ｒｍを出力バッファに反映させたあと、出力バッファにおいては、ｒｍ＋ｒ１＋ｒｄＥＳＤ＝ｒｅが成立しなければならない（図７参照）。以上の２式からｒｅを消去すると、ｒｍ＋ｒ１＋ｒｃ＝ｒｚＥＳＤ＋（ｒｍ＋ｒ１＋ｒｄＥＳＤ）となり、ｒｃ＝ｒｚＥＳＤ＋ｒｄＥＳＤとなる。すなわち、ｒｃ＝（ｒｚＥＳＤ＋ｒｄＥＳＤ）の補正抵抗３１１を追加することにより、図７、８に示したデータ配線ＤＱＬ１の配線抵抗と図１１、１２に示したキャリブレーション配線ＺＱＬ１の配線抵抗の影響を相殺できる。その結果、出力回路１０１の各単位バッファのインピーダンスｒｍ＝ｒｅ－ｒ１となり、出力回路１０１の出力ユニット１１０、１２０、１３０のそれぞれがデータ端子２４を駆動するインピーダンスの精度が改善される。ここで、ｒｃ＝ｒｚＥＳＤ＋ｒｄＥＳＤであることが望ましいが、ｒｃはその近辺の値であっても一定の補正効果は得られ、ｒｃはｒｚＥＳＤ＋ｒｄＥＳＤの１．５倍未満とすることが望ましい。 Next, how to determine the resistance value of the correction resistor 311 will be described. The resistance value rc of the correction resistor 311 is calculated by the following method. The resistance value rm of the pull-up circuit 310 is adjusted so that rm + r1 + rc = rzESD + re is established. After reflecting the resistance value rm in the output buffer, rm + r1 + rdESD = re must be established in the output buffer (see FIG. 7). If re is deleted from the above two formulas, rm + r1 + rc = rzESD + (rm + r1 + rdESD) and rc = rzESD + rdESD. That is, by adding the correction resistor 311 of rc = (rzESD + rdESD), the influence of the wiring resistance of the data wiring DQL1 shown in FIGS. 7 and 8 and the wiring resistance of the calibration wiring ZQL1 shown in FIGS. . As a result, the impedance rm = re−r1 of each unit buffer of the output circuit 101 is obtained, and the accuracy of the impedance at which each of the output units 110, 120, and 130 of the output circuit 101 drives the data terminal 24 is improved. Here, it is desirable that rc = rzESD + rdESD, but even if rc is a value in the vicinity thereof, a certain correction effect is obtained, and it is desirable that rc is less than 1.5 times rzESD + rdESD.
　図１３は、本実施形態において補正抵抗を追加したプルアップ回路３１０（調整バッファ５０）の回路図（第２構成例）である。図８、図１２に示したとおり、第１実施形態では、データ配線ＤＱＬ１とキャリブレーション配線ＺＱＬ１とが共に第２配線層Ｌ２として形成される例を示した。これに対し、第２構成例は、図１４及び図１５に示すとおり、データ配線ＤＱＬ１'とキャリブレーション配線ＺＱＬ１とが互いに異なる配線層に形成されている。ここで、図１４は、第２構成例におけるデータ端子２４と出力回路１０１との間のレイアウトを示す模式図であり、図１５は、第２構成例におけるキャリブレーション端子ＺＱとプルアップ回路３１０及びコンパレータ３６０との間のレイアウトを示す模式図である。尚、図１４、図１５では、それぞれ図８，図１２と重複する構成には同一の符号を付し、重複する説明を省略する。 FIG. 13 is a circuit diagram (second configuration example) of the pull-up circuit 310 (adjustment buffer 50) to which a correction resistor is added in the present embodiment. As shown in FIGS. 8 and 12, in the first embodiment, the data wiring DQL1 and the calibration wiring ZQL1 are both formed as the second wiring layer L2. On the other hand, in the second configuration example, as shown in FIGS. 14 and 15, the data wiring DQL1 ′ and the calibration wiring ZQL1 are formed in different wiring layers. Here, FIG. 14 is a schematic diagram showing a layout between the data terminal 24 and the output circuit 101 in the second configuration example, and FIG. 15 shows a calibration terminal ZQ, a pull-up circuit 310, and the like in the second configuration example. 3 is a schematic diagram showing a layout with a comparator 360. FIG. In FIGS. 14 and 15, the same components as those in FIGS. 8 and 12 are denoted by the same reference numerals, and redundant description is omitted.
　図１４に示すとおり、第２構成例では、データ配線ＤＱＬ１'が第３配線層Ｌ３として形成されている。一方、図１５に示すとおり、キャリブレーション配線ＺＱＬ１は、第１構成例と同様に第２配線層Ｌ２として形成されている。 As shown in FIG. 14, in the second configuration example, the data wiring DQL1 ′ is formed as the third wiring layer L3. On the other hand, as shown in FIG. 15, the calibration wiring ZQL1 is formed as the second wiring layer L2 as in the first configuration example.
　そこで、図１３、図１５に示すとおり、第２構成例では、補正抵抗３１１'を２つの補正抵抗３１１１，３１１２の直列抵抗として形成している。具体的には、補正抵抗３１１２（第１抵抗成分）は、データ配線ＤＱＬ１'と同一の配線層、即ち、第３配線層Ｌ３として形成さるとともに、データ配線ＤＱＬ１'と実質的に等しい抵抗値（ｒｃ'１）を有する。一方、補正抵抗３１１１（第２抵抗成分）は、キャリブレーション配線ＺＱＬ１と同一の配線層、即ち、第２配線層Ｌ２として形成されるとともに、キャリブレーション配線ＺＱＬ１と同一の抵抗値（ｒｃ'２）を有する。このように２種類の抵抗により補正抵抗を構成することにより、２つの配線ＤＱＬ１'、ＺＱＬ１の温度特性と補正抵抗の温度特性を近づけることができる。 Therefore, as shown in FIGS. 13 and 15, in the second configuration example, the correction resistor 311 ′ is formed as a series resistance of the two correction resistors 3111 and 3112. Specifically, the correction resistor 3112 (first resistance component) is formed as the same wiring layer as the data wiring DQL1 ′, that is, the third wiring layer L3, and has a resistance value substantially equal to the data wiring DQL1 ′ ( rc′1). On the other hand, the correction resistor 3111 (second resistance component) is formed as the same wiring layer as the calibration wiring ZQL1, ie, the second wiring layer L2, and has the same resistance value (rc′2) as the calibration wiring ZQL1. Have By configuring the correction resistor with two types of resistors in this way, the temperature characteristics of the two wirings DQL1 ′ and ZQL1 and the temperature characteristics of the correction resistor can be brought close to each other.
　図１６は、電源寄生抵抗およびボンディング抵抗を考慮したときのデータ端子２４と出力回路１０１との接続関係を示す回路図である。データ配線ＤＱＬ１やキャリブレーション配線ＺＱＬ１の抵抗以外にも、ＭＯＳトランジスタのソースには電源線ＰＳＤＬの電源寄生抵抗（抵抗値ｒｓｄ）、外部端子の外側にはパッケージのボンディングワイヤＢＷＤのボンディング抵抗（抵抗値ｒｕｄ）が存在する。 FIG. 16 is a circuit diagram showing a connection relationship between the data terminal 24 and the output circuit 101 when the power source parasitic resistance and the bonding resistance are taken into consideration. In addition to the resistance of the data wiring DQL1 and the calibration wiring ZQL1, the source of the MOS transistor is a power source parasitic resistance (resistance value rsd) of the power source line PSDL, and the outside of the external terminal is a bonding resistance (resistance value of the package bonding wire BWD). rud) exists.
　図１７は、本実施形態において補正抵抗を追加したプルアップ回路３１０とキャリブレーション端子ＺＱの接続関係を示す回路図（第３構成例）である。第３構成例の補正抵抗３１１３は、上述の電源線ＰＳＤＬの電源寄生抵抗やボンディングワイヤＢＷＺのボンディング抵抗も考慮される。プルアップ回路３１０の電源線ＰＳＺＬにも電源寄生抵抗（抵抗値ｒｓｒ）や外部抵抗Ｒｅの接続に起因するボンディング抵抗（抵抗値ｒｕｒ）が存在する。 FIG. 17 is a circuit diagram (third configuration example) showing a connection relationship between the pull-up circuit 310 to which the correction resistor is added and the calibration terminal ZQ in the present embodiment. The correction resistor 3113 of the third configuration example takes into account the power supply parasitic resistance of the power supply line PSDL and the bonding resistance of the bonding wire BWZ. The power supply line PSZL of the pull-up circuit 310 also has a power supply parasitic resistance (resistance value rsr) and a bonding resistance (resistance value ur) due to the connection of the external resistance Re.
　配線ＤＱＬ１、ＺＱＬ１の抵抗だけでなく、電源寄生抵抗やボンディング抵抗を考慮した補正抵抗３１１３の抵抗値ｒｃ２は、下記の方法により算出される。調整バッファ５０においては、ｒｓｒ＋ｒｍ＋ｒ１＋ｒｃ２＝ｒｚＥＳＤ＋ｒｕｒ＋ｒｅが成立するようにプルアップ回路３１０の抵抗値ｒｍが調整される。このときの抵抗値ｒｍを出力バッファに反映させたあと、出力バッファにおいては、ｒｓｄ＋ｒｍ＋ｒ１＋ｒｄＥＳＤ＝ｒｅ－ｒｕｄが成立しなければならない（図１６参照）。以上の２式からｒｅを消去すると、ｒｓｒ＋ｒｍ＋ｒ１＋ｒｃ２＝ｒｚＥＳＤ＋ｒｕｒ＋（ｒｓｄ＋ｒｍ＋ｒ１＋ｒｄＥＳＤ＋ｒｕｄ）となる。ｒｃ２＝ｒｚＥＳＤ＋ｒｄＥＳＤ＋（ｒｓｄ－ｒｓｒ）＋（ｒｕｄ＋ｒｕｒ）となる。となる。すなわち、抵抗値ｒｃ２がｒｚＥＳＤ＋ｒｄＥＳＤ＋（ｒｓｄ－ｒｓｒ）＋（ｒｕｄ＋ｒｕｒ）の補正抵抗３１１３を追加することにより、配線ＤＱＬ１、ＺＱＬ１に加え、電源寄生抵抗やボンディング抵抗よる相違までを補正できる。ｒｃ２＝ｒｚＥＳＤ＋ｒｄＥＳＤ＋（ｒｓｄ－ｒｓｒ）＋（ｒｕｄ＋ｒｕｒ）であることが望ましいが、ｒｃ２はその近辺の値であっても一定の補正効果は得られる。 The resistance value rc2 of the correction resistor 3113 considering not only the resistances of the wirings DQL1 and ZQL1 but also the power source parasitic resistance and bonding resistance is calculated by the following method. In the adjustment buffer 50, the resistance value rm of the pull-up circuit 310 is adjusted so that rsr + rm + r1 + rc2 = rzESD + rur + re is established. After reflecting the resistance value rm at this time in the output buffer, rsd + rm + r1 + rdESD = re−rud must be satisfied in the output buffer (see FIG. 16). If re is deleted from the above two equations, rsr + rm + r1 + rc2 = rzESD + rur + (rsd + rm + r1 + rdESD + rud). rc2 = rzESD + rdESD + (rsd−rsr) + (rud + rur) It becomes. That is, by adding the correction resistor 3113 whose resistance value rc2 is rzESD + rdESD + (rsd−rsr) + (rud + rur), it is possible to correct even the difference due to the power source parasitic resistance and the bonding resistance in addition to the wirings DQL1 and ZQL1. Although it is desirable that rc2 = rzESD + rdESD + (rsd−rsr) + (rud + rur), a constant correction effect can be obtained even if rc2 is a value in the vicinity thereof.
　以上、実施形態に基づいて、半導体装置１０について説明した。調整バッファ５０に補正抵抗を導入することにより、データ配線やキャリブレーション配線の配線抵抗、電源寄生抵抗、ボンディング抵抗の影響を相殺し、より精確なキャリブレーションが可能となる。データ配線やキャリブレーション配線の配線抵抗、電源寄生抵抗およびボンディング抵抗のうちいずれを考慮するかについては任意である。たとえば、ボンディング抵抗がデータ配線やキャリブレーション配線の配線抵抗や電源寄生抵抗に比べて充分に小さいときには、データ配線やキャリブレーション配線の配線抵抗と電源寄生抵抗の影響のみを考慮してもよい。 The semiconductor device 10 has been described above based on the embodiment. By introducing a correction resistor into the adjustment buffer 50, the influence of the wiring resistance of the data wiring and the calibration wiring, the power source parasitic resistance, and the bonding resistance can be offset, and more accurate calibration can be performed. Which of the wiring resistance, power supply parasitic resistance, and bonding resistance of the data wiring and calibration wiring is taken into consideration is arbitrary. For example, when the bonding resistance is sufficiently smaller than the wiring resistance and power supply parasitic resistance of the data wiring and calibration wiring, only the influence of the wiring resistance of the data wiring and calibration wiring and the power supply parasitic resistance may be considered.
　補正抵抗の抵抗値が大きくなると、調整バッファ５０のＩＶ特性における線形性が強くなる。いいかえれば、プルアップ回路３１０に含まれるトランジスタ群のＩＶ特性（非線形）の調整バッファ５０における影響が小さくなる。しかし、本発明者らの調査によれば、ｒｍ＋ｒ１＝２４０Ωに対して、補正抵抗は１Ω程度、大きくとも５Ω程度である。そして、補正抵抗が５Ω以下であるならば、調整バッファ５０のＩＶ特性に対する補正抵抗の影響はほとんど生じていないことが確認されている。 When the resistance value of the correction resistor increases, the linearity in the IV characteristic of the adjustment buffer 50 increases. In other words, the influence of the IV characteristics (non-linearity) of the transistor group included in the pull-up circuit 310 on the adjustment buffer 50 is reduced. However, according to the investigation by the present inventors, for rm + r1 = 240Ω, the correction resistance is about 1Ω, and at most about 5Ω. If the correction resistance is 5Ω or less, it has been confirmed that the influence of the correction resistance on the IV characteristics of the adjustment buffer 50 hardly occurs.
　以上、本発明の好ましい実施形態について説明したが、本発明は、上記の実施形態に限定されることなく、本発明の主旨を逸脱しない範囲で種々の変更が可能であり、それらも本発明の範囲内に包含されるものであることはいうまでもない。例えば、本発明は、特開２００８－２２８３３２号公報及び特開２０１１－６１５８０号公報に記載の半導体装置にも適用可能である。これらの公開公報の開示内容を引用してここに取り込むものとする。 The preferred embodiments of the present invention have been described above, but the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the spirit of the present invention. Needless to say, it is included in the range. For example, the present invention can be applied to the semiconductor devices described in Japanese Patent Application Laid-Open Nos. 2008-228332 and 2011-61580. The disclosure contents of these publications are incorporated herein by reference.
２　　　　外部基板
１０　　　半導体装置
１１　　　メモリセルアレイ
１２　　　ロウデコーダ
１３　　　カラムデコーダ
１４　　　モードレジスタ
１５　　　ラッチ回路
１６　　　入出力回路
１８　　　プルアップ回路
１９　　　プルダウン回路
２１　　　コマンドアドレス端子
２２　　　チップセレクト端子
２３　　　クロック端子
２４　　　データ端子
２５，２６　　電源端子
３１　　　ＣＡ入力回路
３２　　　アドレスラッチ回路
３４　　　コマンドデコード回路
３６　　　クロック入力回路
３９　　　内部電源発生回路
５０　　　調整バッファ
５４　　　クロック発生回路
１００　　キャリブレーション回路
１０１　　出力回路
１１０，１２０，１３０　　出力ユニット
１１１～１１４，１２１，１２２，１３１　　単位バッファ
１４１～１４３　　前段回路
１５０　　出力制御回路
１６０　　静電気保護部
１７０　　入力バッファ
３１０，３２０　　プルアップ回路
３１１，３２１，３３１，３１１１～３１１３　　補正抵抗
３１２　　静電気保護部
３３０　　プルダウン回路
３４０，３５０　　カウンタ
３６０，３７０　　コンパレータ
３８０　　電圧発生回路
３９０　　キャリブレーション制御回路
ＢＷＤ，ＢＷＺ　　ボンディングワイヤ
ＤＬ　　　拡散層
ＤＱＰ　　データパッド
ＥＳＤ１，ＥＳＤ２　　ＥＳＤ素子
Ｇ　　　　ゲート電極
ＧＩ　　　ゲート絶縁膜
ＧＬ　　　ゲート配線層
ＩＬ１～ＩＬ４　　層間絶縁層
Ｌ１～Ｌ４　　配線層
ＰＳＤＬ，ＰＳＺＬ　　電源線
Ｒ１１～Ｒ１４，Ｒ２１～Ｒ２３　　ダンピング抵抗
Ｒｅ　　　外部抵抗
ＳＳ　　　基板
ＴＨ０～ＴＨ３　　スルーホール電極
ＴＬ　　　タングステン層
ＺＱＬ１，ＺＱＬ２　　キャリブレーション配線
ＺＱＰ　　キャリブレーションパッド 2 External substrate 10 Semiconductor device 11 Memory cell array 12 Row decoder 13 Column decoder 14 Mode register 15 Latch circuit 16 Input / output circuit 18 Pull-up circuit 19 Pull-down circuit 21 Command address terminal 22 Chip select terminal 23 Clock terminal 24 Data terminal 25, 26 Power supply Terminal 31 CA input circuit 32 Address latch circuit 34 Command decode circuit 36 Clock input circuit 39 Internal power generation circuit 50 Adjustment buffer 54 Clock generation circuit 100 Calibration circuit 101 Output circuits 110, 120, 130 Output units 111-114, 121, 122 131 Unit buffers 141 to 143 Pre-stage circuit 150 Output control circuit 160 Static electricity protection unit 170 Input buffers 310 and 320 Up circuit 311, 321, 331, 3111 to 3113 Correction resistor 312 Static electricity protection unit 330 Pull down circuit 340, 350 Counter 360, 370 Comparator 380 Voltage generation circuit 390 Calibration control circuit BWD, BWZ Bonding wire DL Diffusion layer DQP Data pad ESD 1 ESD2 ESD element G Gate electrode GI Gate insulating film GL Gate wiring layers IL1 to IL4 Interlayer insulating layers L1 to L4 Wiring layers PSDL, PSZL Power supply lines R11 to R14, R21 to R23 Damping resistance Re External resistance SS Substrate TH0 to TH3 Through-hole electrode TL Tungsten layer ZQL1, ZQL2 Calibration wiring ZQP Calibration pad

Claims (18)

  1. 　データ端子及びキャリブレーション端子と、
    　出力バッファと、
    　前記出力バッファに一端で接続された第１の抵抗部と、
    　前記データ端子と前記第１の抵抗部の他端とを接続する第１の配線と、
    　前記出力バッファと実質的に等しいインピーダンスを有するレプリカ回路と、
    　比較回路と、
    　前記レプリカ回路に一端で接続された第２の抵抗部と、
    　前記第２の抵抗部の他端に一端で接続された第３の抵抗部と、
    　前記第３の抵抗部の他端と前記キャリブレーション端子とを接続する第２の配線と、
    　前記第３の抵抗部の他端と前記比較回路とを接続する第３の配線と、を備え、
    　前記第３の抵抗部の抵抗値は、前記第１の配線の抵抗値及び前記第２の配線の抵抗値よりも大きいことを特徴とする半導体装置。     A data terminal and a calibration terminal;
    An output buffer;
    A first resistor connected at one end to the output buffer;
    A first wiring connecting the data terminal and the other end of the first resistance unit;
    A replica circuit having an impedance substantially equal to the output buffer;
    A comparison circuit;
    A second resistor connected at one end to the replica circuit;
    A third resistor connected at one end to the other end of the second resistor;
    A second wiring for connecting the other end of the third resistance unit and the calibration terminal;
    A third wiring for connecting the other end of the third resistance portion and the comparison circuit;
    The semiconductor device, wherein a resistance value of the third resistance portion is larger than a resistance value of the first wiring and a resistance value of the second wiring.
  2. 　前記第３の抵抗部の抵抗値は、前記第１の配線の抵抗値と前記第２の配線の抵抗値の和に実質的に等しいことを特徴とする請求項１に記載の半導体装置。 2. The semiconductor device according to claim 1, wherein a resistance value of the third resistance portion is substantially equal to a sum of a resistance value of the first wiring and a resistance value of the second wiring.
  3. 　前記第３の抵抗部は、前記第１の配線と同じ温度特性を有する第１の部分と、前記第２の配線と同じ温度特性を有する第２の部分とを含むことを特徴とする請求項１に記載の半導体装置。 The third resistance portion includes a first portion having the same temperature characteristic as that of the first wiring, and a second portion having the same temperature characteristic as that of the second wiring. 2. The semiconductor device according to 1.
  4. 　前記第１の配線に接続された第１の保護素子と、前記第２の配線に接続された第２の保護素子と、をさらに備えることを特徴とする請求項１に記載の半導体装置。 2. The semiconductor device according to claim 1, further comprising: a first protection element connected to the first wiring; and a second protection element connected to the second wiring.
  5. 　前記第１および第２の保護素子は、ＥＳＤ保護素子であることを特徴とする請求項４に記載の半導体装置。 The semiconductor device according to claim 4, wherein the first and second protection elements are ESD protection elements.
  6. 　第１の配線層と前記第１の配線層の上方に形成された第２の配線層とを含む多層配線構造を更に含み、前記第１及び第２の配線並びに前記第３の抵抗部の各々は前記第２の配線層として形成されることを特徴とする請求項１に記載の半導体装置。 A multilayer wiring structure including a first wiring layer and a second wiring layer formed above the first wiring layer; and each of the first and second wirings and the third resistance portion. The semiconductor device according to claim 1, wherein the semiconductor device is formed as the second wiring layer.
  7. 　前記第１及び第２の抵抗部の各々が前記第１の配線層として形成されることを特徴とする請求項６に記載の半導体装置。 The semiconductor device according to claim 6, wherein each of the first and second resistance portions is formed as the first wiring layer.
  8. 　出力バッファと、
    　レプリカ回路及びコンパレータを含み、前記コンパレータの出力に基づいて前記レプリカ回路のインピーダンスを調整してその調整結果を前記出力バッファに反映させるキャリブレーション回路を備え、
    　前記キャリブレーション回路が、前記レプリカ回路と前記コンパレータの一方の入力端子との間に直列に接続された第２ダンピング抵抗および補正抵抗を、更に含むことを特徴とする半導体装置。     An output buffer;
    A calibration circuit that includes a replica circuit and a comparator, adjusts the impedance of the replica circuit based on the output of the comparator, and reflects the adjustment result in the output buffer;
    The semiconductor device, wherein the calibration circuit further includes a second damping resistor and a correction resistor connected in series between the replica circuit and one input terminal of the comparator.
  9. 　キャリブレーション端子を更に備え、
    　前記補正抵抗は一端で前記第２ダンピング抵抗と接続され、他端で前記キャリブレーション端子とも接続されることを特徴とする請求項８に記載の半導体装置。     A calibration terminal,
    9. The semiconductor device according to claim 8, wherein the correction resistor is connected to the second damping resistor at one end and to the calibration terminal at the other end.
  10. 　データ端子を更に備え、
    　前記出力バッファは、プルアップ回路と、一端で前記プルアップ回路に接続され、他端で前記データ端子に接続される第１ダンピング抵抗とを更に含むことを特徴とする請求項９に記載の半導体装置。     A data terminal;
    The semiconductor device according to claim 9, wherein the output buffer further includes a pull-up circuit, and a first damping resistor connected to the pull-up circuit at one end and connected to the data terminal at the other end. apparatus.
  11. 　前記第１ダンピング抵抗の他端と前記データ端子を接続する第１の配線と、前記補正抵抗の他端と前記キャリブレーション端子を接続する第２の配線と、を更に備えることを特徴とする請求項１０に記載の半導体装置。 The apparatus further comprises: a first wiring that connects the other end of the first damping resistor and the data terminal; and a second wiring that connects the other end of the correction resistor and the calibration terminal. Item 11. The semiconductor device according to Item 10.
  12. 　前記補正抵抗の抵抗値は、前記第１の配線の抵抗値および前記第２の配線の抵抗値に基づいて設定されることを特徴とする請求項１１に記載の半導体装置。 12. The semiconductor device according to claim 11, wherein the resistance value of the correction resistor is set based on a resistance value of the first wiring and a resistance value of the second wiring.
  13. 　前記補正抵抗の抵抗値は、前記第１の配線の抵抗値と前記第２の配線の抵抗値の合計値と実質的に等しいことを特徴とする請求項１２に記載の半導体装置。 13. The semiconductor device according to claim 12, wherein a resistance value of the correction resistor is substantially equal to a total value of a resistance value of the first wiring and a resistance value of the second wiring.
  14. 　前記第１の配線に接続された第１の保護素子と前記第２の配線に接続された第２の保護素子と、を更に含むことを特徴とする請求項１１に記載の半導体装置。 12. The semiconductor device according to claim 11, further comprising a first protection element connected to the first wiring and a second protection element connected to the second wiring.
  15. 　第１の配線層と当該第１の配線層の上方に形成された第２の配線層とを含む多層配線構造を更に備え、
    　前記第１及び第２ダンピング抵抗のそれぞれは前記第１の配線層として形成され、前記第１及び第２の配線並びに前記補正抵抗のそれぞれは前記第２の配線層として形成されることを特徴とする請求項１１に記載の半導体装置。     A multilayer wiring structure including a first wiring layer and a second wiring layer formed above the first wiring layer;
    Each of the first and second damping resistors is formed as the first wiring layer, and each of the first and second wirings and the correction resistor is formed as the second wiring layer. The semiconductor device according to claim 11.
  16. 　第１の配線層と当該第１の配線層の上方に形成された第２の配線層と当該第２の配線層の上方に形成された第３の配線層とを含む多層配線構造を更に備え、
    　前記第１及び第２ダンピング抵抗のそれぞれは前記第１の配線層として形成され、前記第１の配線は前記第２の配線層として形成され、前記第２の配線は前記第３の配線層として形成され、前記補正抵抗は前記第２の配線層として形成された第１の部分と前記第３の配線層として形成された第３の部分とを含むことを特徴とする請求項１１に記載の半導体装置。     A multilayer wiring structure including a first wiring layer, a second wiring layer formed above the first wiring layer, and a third wiring layer formed above the second wiring layer; ,
    Each of the first and second damping resistors is formed as the first wiring layer, the first wiring is formed as the second wiring layer, and the second wiring is formed as the third wiring layer. The formed correction resistor includes a first portion formed as the second wiring layer and a third portion formed as the third wiring layer. Semiconductor device.
  17. 　前記補正抵抗の抵抗値は、前記データ端子のボンディング抵抗の抵抗値と前記キャリブレーション端子のボンディング抵抗の抵抗値に基づいて設定されることを特徴とする請求項１０に記載の半導体装置。 11. The semiconductor device according to claim 10, wherein the resistance value of the correction resistor is set based on a resistance value of the bonding resistor of the data terminal and a resistance value of the bonding resistor of the calibration terminal.
  18. 　前記補正抵抗の抵抗値は、前記出力バッファにおける電源寄生抵抗の抵抗値と前記レプリカ回路における電源寄生抵抗の抵抗値に基づいて設定されることを特徴とする請求項８に記載の半導体装置。 9. The semiconductor device according to claim 8, wherein the resistance value of the correction resistor is set based on a resistance value of a power supply parasitic resistance in the output buffer and a resistance value of a power supply parasitic resistance in the replica circuit.
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