WO2013137222A1 - Satellite communication reception device and reception method - Google Patents

Satellite communication reception device and reception method Download PDF

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Publication number
WO2013137222A1
WO2013137222A1 PCT/JP2013/056726 JP2013056726W WO2013137222A1 WO 2013137222 A1 WO2013137222 A1 WO 2013137222A1 JP 2013056726 W JP2013056726 W JP 2013056726W WO 2013137222 A1 WO2013137222 A1 WO 2013137222A1
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Prior art keywords
frequency
frequency shift
signal
unit
synchronization
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PCT/JP2013/056726
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French (fr)
Japanese (ja)
Inventor
康浩 井戸
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三菱電機株式会社
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Publication of WO2013137222A1 publication Critical patent/WO2013137222A1/en

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B7/00—Radio transmission systems, i.e. using radiation field
    • H04B7/14—Relay systems
    • H04B7/15—Active relay systems
    • H04B7/185—Space-based or airborne stations; Stations for satellite systems
    • H04B7/1851—Systems using a satellite or space-based relay
    • H04B7/18515—Transmission equipment in satellites or space-based relays

Definitions

  • the present invention relates to a satellite communication receiving apparatus and a receiving method.
  • a satellite communication system that transmits signals between earth stations via a communication satellite is known.
  • a certain earth station transmits a signal to another earth station (receiving station)
  • a frequency deviation caused by a transmitting station, a local transmitter of a communication satellite, etc. occurs.
  • the frequency deviation exceeds the allowable deviation, the receiving station cannot receive the received signal.
  • Patent Document 1 detects a phase difference from a signal delayed by a certain time with respect to the received signal, and averages the phase difference. Is an automatic frequency control circuit that corrects a frequency deviation of a received signal based on the received signal, and determines a received signal detection area based on a synchronization word (UW) included in the received signal, and receives based on the determined detected area An automatic frequency control circuit that corrects a frequency deviation when a signal is not correctly captured is disclosed.
  • UW synchronization word
  • the technique according to Patent Document 1 is premised on a demodulation operation by a delay detection method, and there is a problem that an effect cannot be obtained by a synchronous detection method widely used in fixed satellite communication. Further, since the technique according to Patent Document 1 corrects the frequency deviation of the received signal based on the synchronization word included in the received signal, it is applied when the received signal is a burst wave having no synchronization word. In the case where the received signal is a continuous wave, there is a problem that it is difficult to shorten the time until the establishment of reception synchronization due to the time for controlling the correction amount of the frequency deviation.
  • the present invention has been made in view of the above circumstances, and is not limited to a specific detection method and reception wave, and can be used to expand a reception frequency range and shorten a time until establishment of reception synchronization and a satellite communication reception apparatus and reception. It aims to provide a method.
  • a satellite communication receiver includes a receiving unit that receives a signal transmitted via a communication satellite, and a plurality of frequency shift circuits that shift the frequency of the signal received by the receiving unit with different frequency shift amounts.
  • Each of the signals output from the plurality of frequency shift circuits includes synchronization processing means for performing synchronization processing, and selection means for selecting, as a reception signal, an output signal of the frequency shift circuit for which synchronization has been established by the synchronization processing means.
  • the reception frequency range can be expanded and the time until establishment of reception synchronization can be shortened without being limited to a specific detection method and reception wave.
  • FIG. 1 is a block diagram of a satellite communication system according to an embodiment of the present invention. It is a block diagram which shows schematic structure of the earth station shown in FIG.
  • FIG. 3 is a block diagram of a receiving circuit of the modem device shown in FIG. 2.
  • FIG. 4 is a block diagram of the IF sampling circuit shown in FIG. 3. It is a figure for demonstrating operation
  • FIG. 4 is a block diagram of a carrier processing unit shown in FIG. 3.
  • the satellite communication system 1000 includes a communication satellite 100 that is a space station and a plurality of earth stations 200, as shown in FIG.
  • the earth station 200 includes a master station 210 and a plurality of slave stations (VSAT: Very Small Aperture Terminal) 221 to 22m (m is an integer of 2 or more).
  • VSAT Very Small Aperture Terminal
  • Each of the plurality of slave stations 221 to 22m and the master station 210 transmits and receives signals through the lines 30 and 40.
  • the lines 30 and 40 connecting each of the plurality of slave stations 221 to 22m and the master station 210 are relayed via the communication satellite 100.
  • the master station 210 is also called a HUB station, and performs setting / cancellation, monitoring, and control of the lines of the slave stations 221 to 22m.
  • Each of the plurality of slave stations 221 to 22m is configured as a fixed station, a portable station, an in-vehicle station, and the like, and a line frequency is assigned to each of them by the control of the master station 210.
  • a signal is transmitted from the master station 210 to each of the slave stations 221 to 22m by a TDM (Time Division Multiplexing) system via the line 30.
  • a continuous wave is transmitted from the master station 210 to each of the slave stations 221 to 22m through the line 30.
  • the line 30 is a communication line, a supervisory control line, a tracking line in the case where the slave station has an automatic acquisition function in the satellite direction, etc., and its application is not limited.
  • the signals from each of the slave stations 221 to 22m to the master station 210 are transmitted by the TDMA (Time Division Multiple Access) system via the line 40.
  • a burst wave is transmitted from each of the slave stations 221 to 22m to the master station 210 via the line 40.
  • the line 40 may be used for a communication line, a monitoring line, or the like.
  • the satellite communication system 1000 is configured as a TDM / TDMA system.
  • the receiving circuit of the modem device included in the earth station 200 has a configuration unique to the present embodiment.
  • This unique configuration can be applied to any earth station of the master station 210 and the plurality of slave stations 221 to 22m. Therefore, hereinafter, the configuration of a predetermined earth station among the master station 210 and the plurality of slave stations 221 to 22m will be described as the configuration of the earth station 200.
  • the earth station 200 is configured as an earth station having a receiving circuit of a modem that can capture the direction of the communication satellite 100.
  • the earth station 200 communicates with the master station 210 or the slave stations 221 to 22m via the communication satellite 100.
  • the earth station 200 includes a directional antenna 20, an antenna control / drive unit 21, a high frequency transmission / reception unit 22, a modem device 23, and a terminal device 24.
  • the antenna 20 tracks the communication satellite 100 and transmits / receives radio waves to / from the communication satellite 100 under the control of the antenna control / drive unit 21.
  • the antenna control / drive unit 21 drives the antenna 20 in order to adjust the direction, polarization plane, and the like of the antenna 20.
  • the antenna control / drive unit 21 directs the antenna 20 in the satellite direction based on the reception level and the reception synchronization information acquired from the modem 23.
  • the high frequency transmission / reception unit 22 is a device that transmits and receives a high frequency (RF) signal, and is configured integrally with the antenna control / drive unit 21 or installed in the vicinity of the antenna control / drive unit 21.
  • RF high frequency
  • the modem 23 is connected to the high frequency transmitter / receiver 22 and supplies the reception level and the reception synchronization information to the antenna control / drive unit 21. Also, the modem 23 exchanges predetermined communication data with the terminal device 24.
  • the transmission circuit of the modem device 23 is based on a known design.
  • the receiving circuit 230 of the modem 23 includes a frequency conversion unit 1, an analog-digital conversion circuit (ADC) 2, an IF sampling circuit 3, a frequency shift unit 4, a carrier processing unit 5, and the like.
  • the frequency shift unit 4, the carrier processing unit 5, the symbol memory unit 6, and the demodulation unit 7 operate under the control of the control unit 10.
  • the frequency converter 1 converts the RF signal sent from the high-frequency transmitter / receiver 22 into an intermediate frequency (IF) signal, and includes a synthesizer 1a, a mixer 1b, and a low-pass filter 1c.
  • the synthesizer 1a is for selecting a reception frequency band, and supplies a sine wave signal used for frequency conversion to the mixer 1b.
  • the mixer 1b converts the RF signal from the high frequency transmitter / receiver 22 into an IF signal in the operating frequency band of the ADC 2 based on the sine wave signal from the synthesizer 1a. This IF signal is sent to the ADC 2.
  • the synthesizer 1a is a sine wave signal having a local oscillation frequency fo corresponding to the difference between the frequency fr (t) of the signal in the high frequency band to be received and the operating frequency band (frequency in the sampling frequency band) fi of the ADC 2.
  • (Local oscillation signal) So (t) is generated and supplied to the mixer 1b.
  • the mixer 1b mixes the reception signal Sr (t) and the local oscillation signal So (t), and outputs signals having frequencies of (fr ⁇ fo) and (fr + fo).
  • the low-pass filter 1c extracts an intermediate frequency (IF) band signal having a frequency of (fr-fo) and outputs an analog IF (intermediate frequency) signal Sr (t).
  • the ADC 2 samples the analog IF signal Sr (t) sent from the frequency converter 1 at a predetermined sampling rate, converts it to a digital signal DSr (t), and sends it to the IF sampling circuit 3.
  • the IF sampling circuit 3 frequency-converts the digital IF signal DSr (t) sent from the ADC 2 to generate a baseband signal. This baseband signal is sent to the frequency shift unit 4.
  • the IF sampling circuit 3 includes, for example, a numerically controlled oscillator (NCO) 31, first and second mixers 32 and 33, and low-pass filters 34 and 35 as shown in FIG. Composed.
  • NCO numerically controlled oscillator
  • the NCO 31 generates orthogonal local oscillation signals sin ( ⁇ n) and cos ( ⁇ n).
  • the first mixer 32 multiplies the digital IF signal DSr (t) by the local oscillation signal sin ( ⁇ n) and converts it into an I component baseband signal.
  • the second mixer 33 multiplies the digital IF signal DSr (t) by the local oscillation signal cos ( ⁇ n) and converts it into a Q component baseband signal.
  • the low-pass filter 34 removes the double frequency component contained in the I component baseband signal by limiting the high frequency band.
  • the low pass filter 35 removes the double frequency component contained in the baseband signal of the Q component by limiting the high frequency band.
  • the frequency shift unit 4 is a device that shifts the frequency of the signal received by the receiving means from the high frequency transmitting / receiving unit 22 to the IF sampling circuit 3.
  • the frequency shift unit 4 includes a plurality of frequency shift circuits 41 to 4n (n is an integer of 2 or more). Each of the frequency shift circuits 41 to 4n shifts the frequency of the signal received by the receiving unit by a frequency shift amount different from that of other frequency shift circuits.
  • the frequency shift amounts of the frequency shift circuits 41 to 4n are expressed as f1 to fn, respectively.
  • the frequency shift amounts f1 to fn of the frequency shift circuits 41 to 4n are bands in which an assumed range of reception frequency deviation included in the baseband signal (a wider range than the pullable range determined by the modulation band of the received signal) is determined by the symbol rate.
  • the frequency corresponds to each section when divided into n pieces for each width (withdrawable range). That is, in the frequency shift circuits 41 to 4n, the frequency shift amount is determined so that the shift interval becomes equal to the pullable range.
  • the shift interval may be smaller than the pullable range.
  • Each of the frequency shift circuits 41 to 4n includes an NCO 401, mixers 402 and 403, and low-pass filters 404 and 405, as illustrated in FIG.
  • the mixer 402 multiplies the I component baseband signal and the local oscillation signal, and outputs an I component baseband signal shifted in frequency by fi.
  • the mixer 403 multiplies the Q component baseband signal and the local oscillation signal, and outputs a Q component baseband signal whose frequency is shifted by fi.
  • the low-pass filter 404 outputs only the low frequency side of the signal output from the mixer 402 to the carrier processing unit 5.
  • the low-pass filter 405 outputs only the low frequency side of the signal output from the mixer 403 to the carrier processing unit 5.
  • the baseband signal can be waited at n (plural) frequencies. For this reason, the allowable deviation of the reception frequency can be expanded.
  • each frequency shift circuit 41 to 4n can perform processing in parallel, and the received signal of the received signal can be processed at a higher speed than the method of expanding the pullable frequency range by sweeping on the frequency axis by one frequency shift circuit. Pull-in is possible.
  • the carrier processing unit 5 oversamples a plurality of baseband signals from each of the frequency shift circuits 41 to 4n in accordance with the symbol rate, adjusts the waveform shaping processing for limiting the channel band, and the signal power level to be constant.
  • AGC Automatic-Gain-Control
  • BTR Bit-Timing-Recovery
  • the generated signal is stored in the symbol memory unit 6.
  • the carrier processing unit 5 includes an input unit 51, an oversampling unit 52, a waveform shaping circuit 53, an AGC circuit 54, and a BTR unit 55, as shown in FIG.
  • the input unit 51 takes in and outputs the output signals of the frequency shift circuits 41 to 4n and supplies them to the subsequent stage in a time division manner.
  • the oversampling unit 52 oversamples the signal at a sampling frequency corresponding to the symbol rate of the transmission signal, in this example, the symbol rate of the transmission data of the center station and the symbol rate of the transmission wave of the satellite. .
  • the waveform shaping circuit 53 shapes the waveform of the output signal of the oversampling unit 52 so as to remove the frequency component of the unnecessary reception band based on the band limitation of the channel of the received signal.
  • the AGC circuit 54 adjusts the amplitude so that the power level of the signal becomes constant.
  • the BTR unit 55 generates a clock serving as a bit timing reference from a signal whose power level is adjusted to be constant.
  • the symbol memory unit 6 stores symbol data from the carrier processing unit 5 and is composed of n symbol memories 61 to 6n.
  • the time-multiplexed baseband signal from the carrier processing unit 5 is stored in the symbol memories 61 to 6n for each channel whose frequency is shifted by each of the frequency shift circuits 41 to 4n constituting the frequency shift unit 4.
  • the carrier processing unit 5 processes the output signal of the frequency shift circuit 4i and outputs the baseband signal and the clock timing generation signal (BTR).
  • the demodulator 7 acquires time-multiplexed data from the symbol memory unit 6 and demodulates the acquired data.
  • the demodulator 7 includes a continuous wave (CW) detector 71, a synchronization word (UW) detector 72, and a phase estimator 73. And a soft decision unit 74 and an AFC (Automatic Frequency Control) unit 75.
  • CW continuous wave
  • UW synchronization word
  • AFC Automatic Frequency Control
  • the phase estimation unit 73 estimates the carrier phase based on the UW pattern detected by the UW detection unit 72, the baseband signal stored in the symbol memory 6i, and the BTR.
  • Soft decision unit 74 outputs a soft decision value of the demodulated data. That is, the soft decision unit 74 calculates a soft decision value for each bit of the baseband signal based on the carrier phase estimated by the phase estimation unit 73, the baseband signal stored in the symbol memory 6i, and the BTR. Ask.
  • the AFC unit 75 obtains a phase rotation amount per symbol from a phase difference over a plurality of symbols of the received signal, and detects a frequency deviation.
  • the demodulator 7 performs the above operation on the symbol memories 61 to 6n while switching i.
  • the demodulator 7 performs demodulation operation in a time division manner and returns frequency deviation data indicating the frequency deviation detected by the AFC unit 75 to the frequency shift circuits 41 to 4n.
  • the demodulator 7 determines whether synchronization is established from the soft decision value generated by the soft decision unit 74, the demodulation result of the CW detection unit, etc., and the synchronization establishment information indicating the discrimination result and the soft decision unit 74
  • the generated soft decision value is output for each symbol memory 6i.
  • the carrier processing unit 5, the symbol memory 6, and the demodulation unit 7 perform synchronization processing on each of the output signals of the frequency shift circuits 41 to 4n.
  • the synchronization shift line determination unit 8 determines a shift line for which reception synchronization has been established based on the synchronization establishment information supplied from the demodulation unit 7 and notifies the line selection unit 9 of line selection information indicating the determination result. For example, assume that it is determined that synchronization is established for the baseband signal stored in the symbol memory 6i. At this time, the synchronous shift line determination unit 8 determines that the shift line processed by the frequency shift circuit 4 i is a shift line for which synchronization has been established, and outputs line selection information indicating i to the line selection unit 9.
  • the line selection unit 9 extracts the received data of the shift line for which reception synchronization has been established from the time multiplexed data, transmits it to the decoding unit 11 as a soft decision signal, and notifies the control unit 10 of the number of the selected shift line. That is, the line selection unit 9 extracts only the received data of the normally received shift line based on the line selection information from the synchronous shift line determination unit 8 and sends only the received data to the decoding unit 11.
  • the line selection information indicating the shift line number i is provided from the synchronous shift line determination unit 8 to the line selection unit 9.
  • the line selection unit 9 outputs the soft signal generated based on the baseband signal stored in the symbol memory 6 i to the decoding unit 11.
  • the line selector 9 discards the soft signals generated from the other symbol memories 61 to 6 (i ⁇ 1) and 6 (i + 1) to 6n. Further, the line selection unit 9 notifies the control unit 10 of the shift line number i.
  • the synchronization shift line determination unit 8 and the line selection unit 9 select the output signal of any frequency shift circuit in which synchronization is established by the carrier processing unit 5 to the synchronization shift line determination unit 8. And output to the decoding unit 11.
  • the control unit 10 is composed of a CPU (Central Processing Unit) ROM (Read Only Memory) or the like, and controls the operation of each unit by the CPU operating based on data and programs stored in the ROM or the like.
  • CPU Central Processing Unit
  • ROM Read Only Memory
  • the control unit 10 instructs the frequency shift unit 4 to stop the function blocks related to the lines other than the shift line for which reception synchronization has been established, based on the shift line number notified from the line selection unit 9. Thereby, the operation of the circuit is unnecessarily suppressed and the power consumption of the circuit is suppressed.
  • the control unit 10 causes the frequency shift unit 4 to operate only the frequency shift circuit 4i, so that other frequency shift circuits, that is, frequency
  • the shift circuits 41 to 4 (i ⁇ 1) and 4 (i + 1) to 4n are instructed to be stopped.
  • the control unit 10 instructs the carrier processing unit 5 to process only the output of the frequency shift circuit 4i.
  • control unit 10 causes the symbol memory unit 6 to store only the symbol memory 6i, and stops the storage operation of other symbol memories, that is, the symbol memories 61 to 6 (i-1) and 6 (i + 1) to 6n. Instruct them to do so. Further, the control unit 10 instructs the demodulation unit 7 to process only the data in the symbol memory 6i.
  • the frequency shift unit 4 operates the frequency shift circuit 4i in response to an instruction from the control unit 10, and pauses the other frequency shift circuits 41 to 4 (i-1) and 4 (i + 1) to 4n. Further, in response to an instruction from the control unit 10, the carrier processing unit 5 switches the internal state to a state where only the output of the frequency shift circuit 4i can be processed. In response to an instruction from the control unit 10, the symbol memory unit 6 stops the operation of symbol memories other than the symbol memory 6i. The symbol memory 6i stores a baseband signal generated from the output signal of the frequency shift circuit 4i by the carrier processing unit 5. Further, in response to an instruction from the control unit 10, the demodulation unit 7 processes only the data in the symbol memory 6i.
  • the decoding unit 11 is based on the soft decision value generated from the baseband signal obtained from the normally received shift line sent from the line selection unit 9 and the error correction method used for the line 30 or 40. Decrypt.
  • the signal decoded by the decoding unit 11 is sent to the data processing unit 12 as decoded data.
  • the data processing unit 12 transmits the received data to the terminal device 24 shown in FIG. 2 in a form corresponding to the conversion to the terminal data format and the communication protocol.
  • the frequency shift unit 4 can wait for a baseband signal at a plurality of frequencies. For this reason, as a result, the allowable deviation of the reception frequency can be increased. Further, since the frequency shift unit 4 can perform processing in parallel by each of the frequency shift circuits 41 to 4n, the frequency shift unit 4 is a method of expanding the pullable frequency range by sweeping on the frequency axis by one frequency shift circuit. In comparison, it is possible to pull in the received signal at high speed.
  • the reception frequency deviation in the communication line is the sum of the transmission frequency deviation from the transmission earth station and the frequency deviation of the local oscillation circuit of the communication satellite.
  • a voice band signal For example, in a satellite communication system, a voice band signal, a small amount of control signal
  • the communication line is a narrow-band line and the reception frequency deviation is larger than that, the receiving earth station 200 cannot pull in the signal.
  • the receiving circuit 230 according to the present embodiment it is possible to widen the pullable frequency range, and thus it is possible to maintain good reception accuracy.
  • the main factor of the reception frequency deviation is the transmission frequency deviation of the transmitting station, it is not necessary to keep the transmission deviation of the transmitting station with higher precision than necessary. There is no need to provide a highly accurate reference signal source in the earth station. Therefore, the price of the earth station can be reduced.
  • the receiving circuit 230 since the time until the establishment of reception synchronization can be shortened, a high-speed acquisition is possible in a system that performs acquisition in the satellite direction with determination of establishment of reception synchronization. Therefore, as a result, the time required to start the satellite line and the time required for re-acquisition can be shortened, and the satellite line can be quickly connected.
  • the portions other than the frequency shift circuits 41 to 4n constituting the frequency shift unit 4 are realized by the time-division operation of the same circuit, so that the FPGA (Field-Programmable) is mainly used. It is possible to minimize the amount of increase in circuit capacity of digital elements such as Gate Array.
  • the circuit configuration itself of the modem device 23 illustrated in FIG. 3 can be changed as needed.
  • the circuit shown in FIG. 3 may be configured by a discrete circuit or a DSP (Digital Signal Processor) or the like.
  • the line selection by the line selection unit 9 can be performed based on, for example, synchronization establishment information instead of the output of the synchronization shift line determination unit 8. That is, the soft decision value of the shift line determined to have established synchronization may be output to the decoding unit 11 and the control unit 10 may be notified of information about the shift line. In this case, the synchronous shift line determination unit 8 may be removed.
  • the earth station 200 is not provided with the antenna control / drive unit 21, and the earth station 200 may not have an automatic satellite capturing function. Moreover, the earth station 200 may not have a transmission function but may have only a reception function. In these cases, as in the above embodiment, the reception frequency deviation can be increased and the satellite line can be quickly connected.
  • 1000 satellite communication system 100 communication satellite, 200 earth station, 210 master station, 221-22m slave station, 30, 40 lines, 20 antennas, 21 antenna control / drive unit, 22 high frequency transmission / reception unit, 23 modulation / demodulation device, 24 terminal device , 230 receiver circuit, 1 frequency converter, 1a synthesizer, 1b mixer, 1c low pass filter, 2 ADC, 3 IF sampling circuit, 31 NCO, 32, 33 mixer, 34, 35 low pass filter, 4 frequency shift unit, 41 to 4n Frequency shift circuit, 401 NCO, 402, 403 mixer, 404, 405 low pass filter, 5 carrier processing unit, 51 input unit, 52 oversampling unit, 53 waveform shaping circuit, 54 AGC circuit, 55 BTR unit, 6 symbol Memory section, 61-6n symbol memory, 7 demodulator section, 71 CW detection section, 72 UW detection section, 73 phase estimation section, 74 soft decision section, 75 AFC section, 8 synchronous shift line determination section, 9 line selection section, 10 Control unit, 11 decoding unit, 12 data

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Abstract

Provided is a satellite communication reception device comprising the following: a reception means for receiving signals transmitted through a communication satellite; a plurality of frequency shift circuits (41-4n) for shifting the frequency of signals received by the reception means by different frequency shift amounts for each; a synchronization processing means for performing synchronization processing on the respective signals output by the frequency shift circuits (41-4n); and a line selection unit (9) for selecting, as the reception signals, the frequency shift circuit (41-4n) output signals for which synchronization was established by the synchronization means.

Description

衛星通信受信装置及び受信方法Satellite communication receiving apparatus and receiving method
　本発明は、衛星通信受信装置及び受信方法に関する。 The present invention relates to a satellite communication receiving apparatus and a receiving method.
　地球局間で通信衛星を介して信号を伝送する衛星通信システムが知られている。このシステムにおいて、ある地球局（送信局）が他の地球局（受信局）に信号を送信する際に、送信局、通信衛星の局部発信器等に起因する周波数偏差が生じ、この周波数偏差が周波数の許容偏差を超えた場合は、受信局は、受信信号の引き込みができなくなる。 A satellite communication system that transmits signals between earth stations via a communication satellite is known. In this system, when a certain earth station (transmitting station) transmits a signal to another earth station (receiving station), a frequency deviation caused by a transmitting station, a local transmitter of a communication satellite, etc. occurs. When the frequency deviation exceeds the allowable deviation, the receiving station cannot receive the received signal.
　周波数の許容偏差を超える受信信号を引き込み可能とする技術として、特許文献１には、受信信号に対して一定時間だけ遅延させた信号との位相差を検出し、その位相差を平均化した信号に基づいて受信信号の周波数偏差を補正する自動周波数制御回路であって、受信信号に含まれる同期語（ＵＷ）に基づいて受信信号の検出領域を判断し、判断された検出領域に基づいて受信信号が正しく捕捉できでいない場合に、周波数偏差を補正する自動周波数制御回路が開示されている。 As a technique for enabling reception of a received signal that exceeds a frequency tolerance, Patent Document 1 detects a phase difference from a signal delayed by a certain time with respect to the received signal, and averages the phase difference. Is an automatic frequency control circuit that corrects a frequency deviation of a received signal based on the received signal, and determines a received signal detection area based on a synchronization word (UW) included in the received signal, and receives based on the determined detected area An automatic frequency control circuit that corrects a frequency deviation when a signal is not correctly captured is disclosed.
特許第３３２７１５２号公報Japanese Patent No. 3327152
　特許文献１に係る技術は、遅延検波方式による復調動作を前提としており、固定衛星通信で広く用いられている同期検波方式では効果が得られないという問題があった。また、特許文献１に係る技術は、受信信号に含まれる同期語に基づいて、受信信号の周波数偏差を補正するものであるため、受信信号が同期語を持たないバースト波である場合には適用できず、受信信号が連続波である場合には、周波偏差の補正量を制御する時間により、受信同期確立までの時間を短縮することが困難であるという問題もあった。 The technique according to Patent Document 1 is premised on a demodulation operation by a delay detection method, and there is a problem that an effect cannot be obtained by a synchronous detection method widely used in fixed satellite communication. Further, since the technique according to Patent Document 1 corrects the frequency deviation of the received signal based on the synchronization word included in the received signal, it is applied when the received signal is a burst wave having no synchronization word. In the case where the received signal is a continuous wave, there is a problem that it is difficult to shorten the time until the establishment of reception synchronization due to the time for controlling the correction amount of the frequency deviation.
　本発明は、上記実状に鑑みてなされたものであり、特定の検波方法及び受信波に限られずに、受信周波数範囲の拡大と受信同期確立までの時間の短縮が可能な衛星通信受信装置及び受信方法を提供することを目的とする。 The present invention has been made in view of the above circumstances, and is not limited to a specific detection method and reception wave, and can be used to expand a reception frequency range and shorten a time until establishment of reception synchronization and a satellite communication reception apparatus and reception. It aims to provide a method.
　本発明に係る衛星通信受信装置は、通信衛星を介して送信されてくる信号を受信する受信手段と、受信手段で受信した信号を、それぞれ異なる周波数シフト量で周波数シフトする複数の周波数シフト回路と、複数の周波数シフト回路が出力する信号のそれぞれについて、同期処理を行う同期処理手段と、同期処理手段により同期が確立した周波数シフト回路の出力信号を受信信号として選択する選択手段と、を備える。 A satellite communication receiver according to the present invention includes a receiving unit that receives a signal transmitted via a communication satellite, and a plurality of frequency shift circuits that shift the frequency of the signal received by the receiving unit with different frequency shift amounts. Each of the signals output from the plurality of frequency shift circuits includes synchronization processing means for performing synchronization processing, and selection means for selecting, as a reception signal, an output signal of the frequency shift circuit for which synchronization has been established by the synchronization processing means.
　本発明によれば、特定の検波方法及び受信波に限られずに、受信周波数範囲の拡大と受信同期確立までの時間の短縮が可能である。 According to the present invention, the reception frequency range can be expanded and the time until establishment of reception synchronization can be shortened without being limited to a specific detection method and reception wave.
本発明の一実施形態に係る衛星通信システムのブロック図である。1 is a block diagram of a satellite communication system according to an embodiment of the present invention. 図１に示す地球局の概略構成を示すブロック図である。It is a block diagram which shows schematic structure of the earth station shown in FIG. 図２に示す変復調装置の受信回路のブロック図である。FIG. 3 is a block diagram of a receiving circuit of the modem device shown in FIG. 2. 図３に示すＩＦサンプリング回路のブロック図である。FIG. 4 is a block diagram of the IF sampling circuit shown in FIG. 3. 周波数シフト回路の動作を説明するための図である。It is a figure for demonstrating operation | movement of a frequency shift circuit. 図３に示す周波数シフト部を構成する周波数シフト回路のブロック図である。It is a block diagram of the frequency shift circuit which comprises the frequency shift part shown in FIG. 図３に示すキャリア処理部のブロック図である。FIG. 4 is a block diagram of a carrier processing unit shown in FIG. 3.
　本発明の実施の形態に係る衛星通信システムについて図面を参照して説明する。 A satellite communication system according to an embodiment of the present invention will be described with reference to the drawings.
　本実施の形態に係る衛星通信システム１０００は、図１に示すように、宇宙局である通信衛星１００と、複数の地球局２００と、を備える。 The satellite communication system 1000 according to the present embodiment includes a communication satellite 100 that is a space station and a plurality of earth stations 200, as shown in FIG.
　地球局２００は、親局２１０と、複数の子局（ＶＳＡＴ：Very Small Aperture Terminal）２２１～２２ｍ（ｍは、２以上の整数）と、から構成される。複数の子局２２１～２２ｍ各々と親局２１０とは、回線３０、４０により信号を送受信する。複数の子局２２１～２２ｍ各々と親局２１０とを結ぶ回線３０、４０は、通信衛星１００を介して中継される。 The earth station 200 includes a master station 210 and a plurality of slave stations (VSAT: Very Small Aperture Terminal) 221 to 22m (m is an integer of 2 or more). Each of the plurality of slave stations 221 to 22m and the master station 210 transmits and receives signals through the lines 30 and 40. The lines 30 and 40 connecting each of the plurality of slave stations 221 to 22m and the master station 210 are relayed via the communication satellite 100.
　親局２１０は、ＨＵＢ局とも呼ばれるものであり、各子局２２１～２２ｍの回線の設定／解除、監視、制御を行う。複数の子局２２１～２２ｍ各々は、固定局、可搬局、車載局等として構成され、これら各々には親局２１０の制御によって回線の周波数が割り当てられる。 The master station 210 is also called a HUB station, and performs setting / cancellation, monitoring, and control of the lines of the slave stations 221 to 22m. Each of the plurality of slave stations 221 to 22m is configured as a fixed station, a portable station, an in-vehicle station, and the like, and a line frequency is assigned to each of them by the control of the master station 210.
　親局２１０から各子局２２１～２２ｍへは、回線３０によりＴＤＭ（Time Division Multiplexing）方式で信号が伝送される。親局２１０から各子局２２１～２２ｍには、回線３０により連続波が送信される。回線３０は、通信回線、監視制御回線、子局が衛星方向の自動捕捉機能を有する場合の追尾回線等であり用途が限定されるものではない。 A signal is transmitted from the master station 210 to each of the slave stations 221 to 22m by a TDM (Time Division Multiplexing) system via the line 30. A continuous wave is transmitted from the master station 210 to each of the slave stations 221 to 22m through the line 30. The line 30 is a communication line, a supervisory control line, a tracking line in the case where the slave station has an automatic acquisition function in the satellite direction, etc., and its application is not limited.
　各子局２２１～２２ｍから親局２１０への信号は、回線４０によりＴＤＭＡ（Time Division Multiple Access）方式で伝送される。各子局２２１～２２ｍから親局２１０には、回線４０によりバースト波が送信される。回線４０も通信回線、監視回線等の用途は問わない。 The signals from each of the slave stations 221 to 22m to the master station 210 are transmitted by the TDMA (Time Division Multiple Access) system via the line 40. A burst wave is transmitted from each of the slave stations 221 to 22m to the master station 210 via the line 40. The line 40 may be used for a communication line, a monitoring line, or the like.
　つまり、本実施形態に係る衛星通信システム１０００は、ＴＤＭ／ＴＤＭＡ方式のシステムとして構成されている。 That is, the satellite communication system 1000 according to the present embodiment is configured as a TDM / TDMA system.
　衛星通信システム１０００では、地球局２００が備える変復調装置の受信回路が本実施形態に特有の構成を有する。この特有の構成は、親局２１０、複数の子局２２１～２２ｍのいずれの地球局にも適用可能である。従って、以下では、親局２１０、複数の子局２２１～２２ｍのうち所定の地球局の構成を地球局２００の構成として説明する。 In the satellite communication system 1000, the receiving circuit of the modem device included in the earth station 200 has a configuration unique to the present embodiment. This unique configuration can be applied to any earth station of the master station 210 and the plurality of slave stations 221 to 22m. Therefore, hereinafter, the configuration of a predetermined earth station among the master station 210 and the plurality of slave stations 221 to 22m will be described as the configuration of the earth station 200.
　地球局２００は、図２に示すように、通信衛星１００の方向を捕捉可能な変復調装置の受信回路を有する地球局として構成されている。地球局２００は、通信衛星１００を介して親局２１０又は子局２２１～２２ｍと通信を行う。 As shown in FIG. 2, the earth station 200 is configured as an earth station having a receiving circuit of a modem that can capture the direction of the communication satellite 100. The earth station 200 communicates with the master station 210 or the slave stations 221 to 22m via the communication satellite 100.
　地球局２００は、指向性のあるアンテナ２０と、アンテナ制御／駆動部２１と、高周波送受信部２２と、変復調装置２３と、端末装置２４と、を備える。 The earth station 200 includes a directional antenna 20, an antenna control / drive unit 21, a high frequency transmission / reception unit 22, a modem device 23, and a terminal device 24.
　アンテナ２０は、アンテナ制御／駆動部２１の制御の下、通信衛星１００を追尾し、通信衛星１００と電波を送受信する。 The antenna 20 tracks the communication satellite 100 and transmits / receives radio waves to / from the communication satellite 100 under the control of the antenna control / drive unit 21.
　アンテナ制御／駆動部２１は、アンテナ２０の方向、偏波面等を調整するためにアンテナ２０を駆動する。アンテナ制御／駆動部２１は、変復調装置２３から取得した受信レベルと受信同期情報とに基づいて、アンテナ２０を衛星方向に向ける。 The antenna control / drive unit 21 drives the antenna 20 in order to adjust the direction, polarization plane, and the like of the antenna 20. The antenna control / drive unit 21 directs the antenna 20 in the satellite direction based on the reception level and the reception synchronization information acquired from the modem 23.
　高周波送受信部２２は、高周波（ＲＦ）信号を送受信する装置であり、アンテナ制御／駆動部２１と一体に構成されるか、アンテナ制御／駆動部２１の近傍に設置される。 The high frequency transmission / reception unit 22 is a device that transmits and receives a high frequency (RF) signal, and is configured integrally with the antenna control / drive unit 21 or installed in the vicinity of the antenna control / drive unit 21.
　変復調装置２３は、高周波送受信部２２と接続され、アンテナ制御／駆動部２１に受信レベルと受信同期情報を供給する。また、変復調装置２３は、端末装置２４と所定の通信データのやり取りを行う。 The modem 23 is connected to the high frequency transmitter / receiver 22 and supplies the reception level and the reception synchronization information to the antenna control / drive unit 21. Also, the modem 23 exchanges predetermined communication data with the terminal device 24.
　次に、変復調装置２３が備える受信回路２３０について、図３を参照して説明する。なお、変復調装置２３の送信回路は周知の設計による。 Next, the receiving circuit 230 provided in the modem device 23 will be described with reference to FIG. The transmission circuit of the modem device 23 is based on a known design.
　変復調装置２３の受信回路２３０は、図３に示すように、周波数変換部１と、アナログ－デジタル変換回路（ＡＤＣ）２と、ＩＦサンプリング回路３と、周波数シフト部４と、キャリア処理部５と、シンボルメモリ部６と、復調部７と、同期シフト回線判定部８と、回線選択部９と、制御部１０と、復号部１１と、データ処理部１２と、を備える。なお、周波数シフト部４、キャリア処理部５、シンボルメモリ部６、復調部７各部は、制御部１０の制御の下、動作する。 As shown in FIG. 3, the receiving circuit 230 of the modem 23 includes a frequency conversion unit 1, an analog-digital conversion circuit (ADC) 2, an IF sampling circuit 3, a frequency shift unit 4, a carrier processing unit 5, and the like. A symbol memory unit 6, a demodulation unit 7, a synchronous shift channel determination unit 8, a channel selection unit 9, a control unit 10, a decoding unit 11, and a data processing unit 12. The frequency shift unit 4, the carrier processing unit 5, the symbol memory unit 6, and the demodulation unit 7 operate under the control of the control unit 10.
　周波数変換部１は、高周波送受信部２２から送られたＲＦ信号を中間周波数（ＩＦ）信号に変換するものであり、シンセサイザ１ａと、ミキサ１ｂと、ローパスフィルタ１ｃとから構成される。シンセサイザ１ａは、受信周波数帯を選択するためのものであり、周波数変換に用いられる正弦波信号をミキサ１ｂに供給する。ミキサ１ｂは、シンセサイザ１ａからの正弦波信号に基づき、高周波送受信部２２からのＲＦ信号をＡＤＣ２の動作周波数帯のＩＦ信号に変換する。このＩＦ信号は、ＡＤＣ２に送られる。 The frequency converter 1 converts the RF signal sent from the high-frequency transmitter / receiver 22 into an intermediate frequency (IF) signal, and includes a synthesizer 1a, a mixer 1b, and a low-pass filter 1c. The synthesizer 1a is for selecting a reception frequency band, and supplies a sine wave signal used for frequency conversion to the mixer 1b. The mixer 1b converts the RF signal from the high frequency transmitter / receiver 22 into an IF signal in the operating frequency band of the ADC 2 based on the sine wave signal from the synthesizer 1a. This IF signal is sent to the ADC 2.
　具体的には、シンセサイザ１ａは、受信対象の高周波帯域の信号の周波数ｆｒ（ｔ）とＡＤＣ２の動作周波数帯（サンプリング周波数帯域の周波数）ｆｉとの差に相当する局部発振周波数ｆｏの正弦波信号（局部発振信号）Ｓｏ（ｔ）を生成し、ミキサ１ｂに供給する。ミキサ１ｂは、受信信号Ｓｒ（ｔ）と局部発振信号Ｓｏ（ｔ）を混合し、周波数が（ｆｒ－ｆｏ）と（ｆｒ＋ｆｏ）の信号を出力する。ローパスフィルタ１ｃは、周波数が（ｆｒ－ｆｏ）の中間周波数（ＩＦ）帯域の信号を抽出し、アナログのＩＦ（中間周波数）信号Ｓｒ（ｔ）を出力する。 Specifically, the synthesizer 1a is a sine wave signal having a local oscillation frequency fo corresponding to the difference between the frequency fr (t) of the signal in the high frequency band to be received and the operating frequency band (frequency in the sampling frequency band) fi of the ADC 2. (Local oscillation signal) So (t) is generated and supplied to the mixer 1b. The mixer 1b mixes the reception signal Sr (t) and the local oscillation signal So (t), and outputs signals having frequencies of (fr−fo) and (fr + fo). The low-pass filter 1c extracts an intermediate frequency (IF) band signal having a frequency of (fr-fo) and outputs an analog IF (intermediate frequency) signal Sr (t).
　ＡＤＣ２は、周波数変換部１から送られたアナログのＩＦ信号Ｓｒ（ｔ）を所定のサンプリングレートでサンプリングしてデジタル信号ＤＳｒ（ｔ）に変換し、ＩＦサンプリング回路３に送る。 The ADC 2 samples the analog IF signal Sr (t) sent from the frequency converter 1 at a predetermined sampling rate, converts it to a digital signal DSr (t), and sends it to the IF sampling circuit 3.
　ＩＦサンプリング回路３は、ＡＤＣ２から送られたデジタルＩＦ信号ＤＳｒ（ｔ）を周波数変換してベースバンド信号を生成する。このベースバンド信号は、周波数シフト部４に送られる。 The IF sampling circuit 3 frequency-converts the digital IF signal DSr (t) sent from the ADC 2 to generate a baseband signal. This baseband signal is sent to the frequency shift unit 4.
　具体的には、ＩＦサンプリング回路３は、例えば、図４に示すように、数値制御発振器（ＮＣＯ：Numerical Controlled Oscillator）３１と、第１と第２のミキサ３２，３３、ローパスフィルタ３４，３５から構成される。 Specifically, the IF sampling circuit 3 includes, for example, a numerically controlled oscillator (NCO) 31, first and second mixers 32 and 33, and low- pass filters 34 and 35 as shown in FIG. Composed.
　ＮＣＯ３１は、直交する局部発振信号sin（ωｎ）とcos（ωｎ）を生成する。 The NCO 31 generates orthogonal local oscillation signals sin (ωn) and cos (ωn).
　第１のミキサ３２は、デジタルＩＦ信号ＤＳｒ（ｔ）と局部発振信号sin（ωｎ）とを乗算し、Ｉ成分のベースバンド信号に変換する。第２のミキサ３３は、デジタルＩＦ信号ＤＳｒ（ｔ）と局部発振信号cos（ωｎ）とを乗算し、Ｑ成分のベースバンド信号に変換する。 The first mixer 32 multiplies the digital IF signal DSr (t) by the local oscillation signal sin (ωn) and converts it into an I component baseband signal. The second mixer 33 multiplies the digital IF signal DSr (t) by the local oscillation signal cos (ωn) and converts it into a Q component baseband signal.
　ローパスフィルタ３４は、高周波帯域を制限することにより、Ｉ成分のベースバンド信号に含まれている倍周波成分を除去する。 The low-pass filter 34 removes the double frequency component contained in the I component baseband signal by limiting the high frequency band.
　ローパスフィルタ３５は、高周波帯域を制限することにより、Ｑ成分のベースバンド信号に含まれている倍周波成分を除去する。 The low pass filter 35 removes the double frequency component contained in the baseband signal of the Q component by limiting the high frequency band.
　こうして、Ｉ成分のベースバンド信号とＱ成分のベースバンド信号とから構成される複素ベースバンド信号が出力される。 Thus, a complex baseband signal composed of an I component baseband signal and a Q component baseband signal is output.
　周波数シフト部４は、高周波送受信部２２～ＩＦサンプリング回路３までの受信手段で受信した信号の周波数をシフトする装置である。周波数シフト部４は、複数の周波数シフト回路４１～４ｎ（ｎは、２以上の整数）を有している。周波数シフト回路４１～４ｎは、それぞれ、受信手段で受信した信号の周波数を、他の周波数シフト回路とは異なった周波数シフト量で周波数シフトする。なお、以下の説明では、理解を容易にするため、周波数シフト回路４１～４ｎの周波数シフト量を、それぞれ、ｆ１～ｆｎと表現する。 The frequency shift unit 4 is a device that shifts the frequency of the signal received by the receiving means from the high frequency transmitting / receiving unit 22 to the IF sampling circuit 3. The frequency shift unit 4 includes a plurality of frequency shift circuits 41 to 4n (n is an integer of 2 or more). Each of the frequency shift circuits 41 to 4n shifts the frequency of the signal received by the receiving unit by a frequency shift amount different from that of other frequency shift circuits. In the following description, for easy understanding, the frequency shift amounts of the frequency shift circuits 41 to 4n are expressed as f1 to fn, respectively.
　周波数シフト回路４１～４ｎの周波数シフト量ｆ１～ｆｎは、ベースバンド信号に含まれる受信周波数偏差の想定範囲（受信信号の変調帯域により定まる引き込み可能範囲よりも広い範囲）を、シンボルレートで定まる帯域幅（引き込み可能範囲）毎にｎ個に区切った場合の、各区分に相当する周波数となっている。つまり、周波数シフト回路４１～４ｎは、シフト間隔が引き込み可能範囲と等しくなるように、周波数シフト量が定められている。 The frequency shift amounts f1 to fn of the frequency shift circuits 41 to 4n are bands in which an assumed range of reception frequency deviation included in the baseband signal (a wider range than the pullable range determined by the modulation band of the received signal) is determined by the symbol rate. The frequency corresponds to each section when divided into n pieces for each width (withdrawable range). That is, in the frequency shift circuits 41 to 4n, the frequency shift amount is determined so that the shift interval becomes equal to the pullable range.
　例えば、受信周波数偏差の想定範囲がｆａであり、シンボルレートで定まる帯域幅（引き込み可能範囲）がｆａ／４であるとする。このとき、ｎ＝４となり、周波数シフト回路４１～４４が配置される。この場合、周波数シフト回路４１は、図５に示すように、ベースバンド信号の周波数を周波数シフト量ｆ１＝ｆａ／８だけシフトしてキャリア処理部５に送出する。また、周波数シフト回路４２は、ベースバンド信号の周波数を周波数シフト量ｆ２＝－ｆａ／８だけシフトしてキャリア処理部５に送出する。また、周波数シフト回路４３は、ベースバンド信号の周波数を周波数シフト量ｆ３＝３×ｆａ／８だけシフトしてキャリア処理部５に送出する。また、周波数シフト回路４４は、ベースバンド信号の周波数を周波数シフト量ｆ４＝－３×ｆａ／８だけシフトしてキャリア処理部５に送出する。このようにして、周波数シフト部４は、同一回線を複数の周波数帯で受信することを可能とする。なお、シフト間隔は、引き込み可能範囲よりも小さくてもよい。 For example, assume that the assumed range of the reception frequency deviation is fa, and the bandwidth determined by the symbol rate (withdrawable range) is fa / 4. At this time, n = 4, and the frequency shift circuits 41 to 44 are arranged. In this case, as shown in FIG. 5, the frequency shift circuit 41 shifts the frequency of the baseband signal by the frequency shift amount f1 = fa / 8 and sends it to the carrier processing unit 5. Further, the frequency shift circuit 42 shifts the frequency of the baseband signal by the frequency shift amount f2 = −fa / 8 and sends it to the carrier processing unit 5. Further, the frequency shift circuit 43 shifts the frequency of the baseband signal by the frequency shift amount f3 = 3 × fa / 8 and sends it to the carrier processing unit 5. Further, the frequency shift circuit 44 shifts the frequency of the baseband signal by the frequency shift amount f4 = −3 × fa / 8 and sends it to the carrier processing unit 5. In this way, the frequency shift unit 4 can receive the same line in a plurality of frequency bands. The shift interval may be smaller than the pullable range.
　周波数シフト回路４１～４ｎは、それぞれ、図６に例示するように、ＮＣＯ４０１と、ミキサ４０２、４０３と、ローパスフィルタ４０４、４０５とから構成される。 Each of the frequency shift circuits 41 to 4n includes an NCO 401, mixers 402 and 403, and low- pass filters 404 and 405, as illustrated in FIG.
　周波数シフト回路４ｉ（ｉ＝１～ｎ）のＮＣＯ４０１は、周波数シフト量ｆｉ（ｉ＝１～ｎ）に相当する周波数の局部発振信号を生成する。ミキサ４０２は、Ｉ成分のベースバンド信号と局部発振信号とを乗算して、周波数がｆｉだけシフトしたＩ成分のベースバンド信号を出力する。ミキサ４０３は、Ｑ成分のベースバンド信号と局部発振信号とを乗算して、周波数がｆｉだけシフトしたＱ成分のベースバンド信号を出力する。ローパスフィルタ４０４は、ミキサ４０２から出力された信号のうちの低周波側のみをキャリア処理部５に出力する。ローパスフィルタ４０５は、ミキサ４０３から出力された信号のうちの低周波側のみをキャリア処理部５に出力する。 The NCO 401 of the frequency shift circuit 4i (i = 1 to n) generates a local oscillation signal having a frequency corresponding to the frequency shift amount fi (i = 1 to n). The mixer 402 multiplies the I component baseband signal and the local oscillation signal, and outputs an I component baseband signal shifted in frequency by fi. The mixer 403 multiplies the Q component baseband signal and the local oscillation signal, and outputs a Q component baseband signal whose frequency is shifted by fi. The low-pass filter 404 outputs only the low frequency side of the signal output from the mixer 402 to the carrier processing unit 5. The low-pass filter 405 outputs only the low frequency side of the signal output from the mixer 403 to the carrier processing unit 5.
　なお、周波数シフト回路４ｉ（ｉ＝１～ｎ）のＮＣＯ４０１は、後述する復調部７のＡＦＣ部７５から周波数偏差ｆｂｉを受信した時には、周波数変位ｆｂｉを０にするように、例えば、局部信号の周波数ｆｉをｆｉ－ｆｂｉに修正する。この点は、後述する。 The NCO 401 of the frequency shift circuit 4i (i = 1 to n) receives the frequency deviation fbi from the AFC unit 75 of the demodulator 7 described later, so that the frequency displacement fbi is set to 0, for example, the local signal The frequency fi is corrected to fi-fbi. This point will be described later.
　周波数シフト部４によれば、ベースバンド信号をｎ個（複数）の周波数で待ち受け可能となる。このため、受信周波数の許容偏差を拡大することができる。また、各周波数シフト回路４１～４ｎは、同時並行的に処理が可能であり、一つの周波数シフト回路によって周波数軸上をスイープさせることで引き込み可能周波数範囲を広げる手法に比べ、高速に受信信号の引き込みが可能となる。 According to the frequency shift unit 4, the baseband signal can be waited at n (plural) frequencies. For this reason, the allowable deviation of the reception frequency can be expanded. In addition, each frequency shift circuit 41 to 4n can perform processing in parallel, and the received signal of the received signal can be processed at a higher speed than the method of expanding the pullable frequency range by sweeping on the frequency axis by one frequency shift circuit. Pull-in is possible.
　キャリア処理部５では、周波数シフト回路４１～４ｎ各々からの複数のベースバンド信号をシンボルレートに応じてオーバーサンプリングすると共に、チャネル帯域制限の波形整形処理、信号の電力レベルが一定となるように調整するＡＧＣ（Automatic Gain Control）処理、ビット同期を取るためのＢＴＲ（Bit Timing Recovery）処理等が実行され、ビットタイミング誤差を補正した後に、時間多重されたベースバンド信号が生成される。生成された信号は、シンボルメモリ部６に格納される。 The carrier processing unit 5 oversamples a plurality of baseband signals from each of the frequency shift circuits 41 to 4n in accordance with the symbol rate, adjusts the waveform shaping processing for limiting the channel band, and the signal power level to be constant. AGC (Automatic-Gain-Control) processing, BTR (Bit-Timing-Recovery) processing for obtaining bit synchronization, and the like are executed, and after correcting the bit timing error, a time-multiplexed baseband signal is generated. The generated signal is stored in the symbol memory unit 6.
　具体的には、キャリア処理部５は、図７に示すように、入力部５１、オーバーサンプリング部５２、波形整形回路５３、ＡＧＣ回路５４、ＢＴＲ部５５、を備える。 Specifically, the carrier processing unit 5 includes an input unit 51, an oversampling unit 52, a waveform shaping circuit 53, an AGC circuit 54, and a BTR unit 55, as shown in FIG.
　入力部５１は、周波数シフト回路４１～４ｎの出力信号を取り込みいったん蓄積し、時分割的に後段に供給する。 The input unit 51 takes in and outputs the output signals of the frequency shift circuits 41 to 4n and supplies them to the subsequent stage in a time division manner.
　オーバーサンプリング部５２は、送信信号のシンボルレート、この例では、センタ局の送信データのシンボルレートと衛星の送信波のシンボルレートとに応じて、それぞれに応じたサンプリング周波数で、信号をオーバーサンプリングする。 The oversampling unit 52 oversamples the signal at a sampling frequency corresponding to the symbol rate of the transmission signal, in this example, the symbol rate of the transmission data of the center station and the symbol rate of the transmission wave of the satellite. .
　波形整形回路５３は、受信信号のチャネルの帯域制限に基づいて、受信不要帯域の周波数成分を除去するように、オーバーサンプリング部５２の出力信号の波形を整形する。 The waveform shaping circuit 53 shapes the waveform of the output signal of the oversampling unit 52 so as to remove the frequency component of the unnecessary reception band based on the band limitation of the channel of the received signal.
　ＡＧＣ回路５４は、信号の電力レベルが一定となるように、その振幅を調整する。 The AGC circuit 54 adjusts the amplitude so that the power level of the signal becomes constant.
　ＢＴＲ部５５は、電力レベルが一定に調整された信号から、ビットタイミング基準となるクロックを生成する。 The BTR unit 55 generates a clock serving as a bit timing reference from a signal whose power level is adjusted to be constant.
　シンボルメモリ部６は、キャリア処理部５からのシンボルデータを蓄えるものであり、ｎ個のシンボルメモリ６１～６ｎから構成される。キャリア処理部５からの時間多重されたベースバンド信号は、周波数シフト部４を構成する周波数シフト回路４１～４ｎ各々によって周波数がシフトされたチャネル毎に、シンボルメモリ６１～６ｎに格納される。具体的には、シンボルメモリ６ｉ（ｉ＝１～ｎ）は、キャリア処理部５が、周波数シフト回路４ｉの出力信号を処理して出力したベースバンド信号とクロックタイミング生成用信号（ＢＴＲ）とを記憶する。 The symbol memory unit 6 stores symbol data from the carrier processing unit 5 and is composed of n symbol memories 61 to 6n. The time-multiplexed baseband signal from the carrier processing unit 5 is stored in the symbol memories 61 to 6n for each channel whose frequency is shifted by each of the frequency shift circuits 41 to 4n constituting the frequency shift unit 4. Specifically, in the symbol memory 6i (i = 1 to n), the carrier processing unit 5 processes the output signal of the frequency shift circuit 4i and outputs the baseband signal and the clock timing generation signal (BTR). Remember.
　復調部７は、シンボルメモリ部６から時間多重データを取得し、取得したデータを復調するものであり、連続波（ＣＷ）検出部７１、同期語（ＵＷ）検出部７２と、位相推定部７３と、軟判定部７４と、ＡＦＣ（Automatic Frequency Control）部７５と、を有する。 The demodulator 7 acquires time-multiplexed data from the symbol memory unit 6 and demodulates the acquired data. The demodulator 7 includes a continuous wave (CW) detector 71, a synchronization word (UW) detector 72, and a phase estimator 73. And a soft decision unit 74 and an AFC (Automatic Frequency Control) unit 75.
　ＣＷ（Continuous Wave）検出部７１は、シンボルメモリ部６の各シンボルメモリ６ｉ（ｉ＝１～ｎ）に蓄積されている一連のベースバンド信号とＢＴＲとから、受信波が連続波であるか否かを検出する。即ち、ＣＷ検出部７１は、シンボルメモリ６ｉに格納されているベースバンド信号が、連続的に出力されている信号であるか、一時的に出力されている信号であるかを判別する。さらに、ＣＷ検出部７１は、連続波であると判別した場合は、ＢＴＲに基づいて、１フレーム内の復調処理を行い、そうでない場合（つまり、受信波がバースト波の場合）は、ＢＴＲに基づいて、１バースト内の復調処理を行う。ＣＷ検出部７１は、シンボルメモリ６ｉ（ｉ＝１～ｎ）を切り替えながら、順次この動作を行う。 A CW (Continuous Wave) detection unit 71 determines whether or not the received wave is a continuous wave from a series of baseband signals and BTR stored in each symbol memory 6 i (i = 1 to n) of the symbol memory unit 6. To detect. That is, the CW detection unit 71 determines whether the baseband signal stored in the symbol memory 6i is a signal that is continuously output or a signal that is temporarily output. Further, if the CW detection unit 71 determines that the wave is a continuous wave, the CW detection unit 71 performs demodulation processing within one frame based on the BTR. If not (that is, if the received wave is a burst wave), Based on this, demodulation processing within one burst is performed. The CW detection unit 71 sequentially performs this operation while switching the symbol memory 6i (i = 1 to n).
　ＵＷ検出部７２は、シンボルメモリ部６のシンボルメモリ６ｉ（ｉ＝１～ｎ）に蓄積されている一連のベースバンド信号中に配置されているユニークワード（ＵＷ）パターンを検出する。 The UW detection unit 72 detects a unique word (UW) pattern arranged in a series of baseband signals stored in the symbol memory 6i (i = 1 to n) of the symbol memory unit 6.
　位相推定部７３は、ＵＷ検出部７２が検出したＵＷパターンと、シンボルメモリ６ｉに蓄積されているベースバンド信号とＢＴＲとに基づいて、キャリア位相を推定する。 The phase estimation unit 73 estimates the carrier phase based on the UW pattern detected by the UW detection unit 72, the baseband signal stored in the symbol memory 6i, and the BTR.
　軟判定部７４は、復調データの軟判定値を出力する。即ち、軟判定部７４は、位相推定部７３で推定されたキャリア位相と、シンボルメモリ６ｉに蓄積されているベースバンド信号とＢＴＲとに基づいて、ベースバンド信号の各ビットについて、軟判定値を求める。 Soft decision unit 74 outputs a soft decision value of the demodulated data. That is, the soft decision unit 74 calculates a soft decision value for each bit of the baseband signal based on the carrier phase estimated by the phase estimation unit 73, the baseband signal stored in the symbol memory 6i, and the BTR. Ask.
　ＡＦＣ部７５は、受信信号の複数シンボルに渡る位相差から１シンボル当たりの位相回転量を求め、周波数偏差を検出する。 The AFC unit 75 obtains a phase rotation amount per symbol from a phase difference over a plurality of symbols of the received signal, and detects a frequency deviation.
　復調部７は、ｉを切り替えながら、上述の動作を、シンボルメモリ６１～６ｎについて行う。復調部７は、復調動作を時分割で行う他、ＡＦＣ部７５で検出した周波数偏差を示す周波数偏差データを、各周波数シフト回路４１～４ｎに返す。周波数シフト部４の各周波数シフト回路４ｉ（ｉ＝１～ｎ）は、ＡＦＣ部７５から通知された周波数偏差データに基づいて、周波数偏差が０になるように、ＮＣＯ４０１の局部信号の周波数を調整（補正）する。例えば、周波数偏差がｆｂの場合には、局部発振信号ｆｉの周波数を－ｆｂする。但し、ここでの周波数偏差データは、各周波数シフト回路４１～４ｎで区切られた引き込み可能範囲内に制限されることになる。復調部７は、軟判定部７４が生成した軟判定値、ＣＷ検出部の復調結果、等から同期が確立しているか否かを判別し、判別結果を示す同期確立情報と軟判定部７４が生成した軟判定値とを、各シンボルメモリ６ｉについて出力する。 The demodulator 7 performs the above operation on the symbol memories 61 to 6n while switching i. The demodulator 7 performs demodulation operation in a time division manner and returns frequency deviation data indicating the frequency deviation detected by the AFC unit 75 to the frequency shift circuits 41 to 4n. Each frequency shift circuit 4i (i = 1 to n) of the frequency shift unit 4 adjusts the frequency of the local signal of the NCO 401 based on the frequency deviation data notified from the AFC unit 75 so that the frequency deviation becomes zero. (to correct. For example, when the frequency deviation is fb, the frequency of the local oscillation signal fi is -fb. However, the frequency deviation data here is limited within the pullable range delimited by the frequency shift circuits 41 to 4n. The demodulator 7 determines whether synchronization is established from the soft decision value generated by the soft decision unit 74, the demodulation result of the CW detection unit, etc., and the synchronization establishment information indicating the discrimination result and the soft decision unit 74 The generated soft decision value is output for each symbol memory 6i.
　こうして、キャリア処理部５、シンボルメモリ６、及び復調部７は、周波数シフト回路４１～４ｎの出力信号のそれぞれについて、同期処理を行う。 Thus, the carrier processing unit 5, the symbol memory 6, and the demodulation unit 7 perform synchronization processing on each of the output signals of the frequency shift circuits 41 to 4n.
　同期シフト回線判定部８は、復調部７から供給された同期確立情報に基づいて、受信同期の確立したシフト回線を判定し、その判定結果を示す回線選択情報を、回線選択部９へ通知する。例えば、シンボルメモリ６ｉに格納されているベースバンド信号について、同期が確立していると判別されたとする。このとき、同期シフト回線判定部８は、周波数シフト回路４ｉが処理したシフト回線が、同期が確立したシフト回線であると判別し、ｉを示す回線選択情報を回線選択部９に出力する。 The synchronization shift line determination unit 8 determines a shift line for which reception synchronization has been established based on the synchronization establishment information supplied from the demodulation unit 7 and notifies the line selection unit 9 of line selection information indicating the determination result. . For example, assume that it is determined that synchronization is established for the baseband signal stored in the symbol memory 6i. At this time, the synchronous shift line determination unit 8 determines that the shift line processed by the frequency shift circuit 4 i is a shift line for which synchronization has been established, and outputs line selection information indicating i to the line selection unit 9.
　回線選択部９は、時間多重データから受信同期が確立したシフト回線の受信データを抜き出し、復号部１１に軟判定信号として伝達すると共に、選択したシフト回線の番号を制御部１０に通知する。即ち、回線選択部９は、同期シフト回線判定部８からの回線選択情報に基づいて、正常に受信したシフト回線の受信データのみを抽出し、復号部１１にその受信データのみを送る。 The line selection unit 9 extracts the received data of the shift line for which reception synchronization has been established from the time multiplexed data, transmits it to the decoding unit 11 as a soft decision signal, and notifies the control unit 10 of the number of the selected shift line. That is, the line selection unit 9 extracts only the received data of the normally received shift line based on the line selection information from the synchronous shift line determination unit 8 and sends only the received data to the decoding unit 11.
　例えば、同期シフト回線判定部８から、回線選択部９に対し、シフト回線番号ｉを示す回線選択情報が提供されたとする。このとき、回線選択部９は、シンボルメモリ６ｉに格納されているベースバンド信号に基づいて生成した軟信号を復号部１１に出力する。そして、回線選択部９は、他のシンボルメモリ６１～６（ｉ－１）、６（ｉ＋１）～６ｎから生成された軟信号を破棄する。さらに、回線選択部９は、シフト回線番号ｉを制御部１０に通知する。 For example, it is assumed that the line selection information indicating the shift line number i is provided from the synchronous shift line determination unit 8 to the line selection unit 9. At this time, the line selection unit 9 outputs the soft signal generated based on the baseband signal stored in the symbol memory 6 i to the decoding unit 11. Then, the line selector 9 discards the soft signals generated from the other symbol memories 61 to 6 (i−1) and 6 (i + 1) to 6n. Further, the line selection unit 9 notifies the control unit 10 of the shift line number i.
　このように、同期シフト回線判定部８と回線選択部９とは、キャリア処理部５～同期シフト回線判定部８は、同期処理部より同期が確立したいずれかの周波数シフト回路の出力信号を選択して復号部１１に出力する。 As described above, the synchronization shift line determination unit 8 and the line selection unit 9 select the output signal of any frequency shift circuit in which synchronization is established by the carrier processing unit 5 to the synchronization shift line determination unit 8. And output to the decoding unit 11.
　制御部１０は、ＣＰＵ（Central Processing Unit）ＲＯＭ（Read Only Memory）等から構成され、ＲＯＭ等に格納されたデータ、プログラムに基づいてＣＰＵが動作することで、前記各部の動作を制御する。 The control unit 10 is composed of a CPU (Central Processing Unit) ROM (Read Only Memory) or the like, and controls the operation of each unit by the CPU operating based on data and programs stored in the ROM or the like.
　制御部１０は、回線選択部９から通知されたシフト回線の番号に基づいて、受信同期の確立したシフト回線以外の回線に係る機能ブロックの停止を周波数シフト部４に指示する。これにより、不必要に回路の動作を抑制し、回路の消費電力を抑えている。具体的には、制御部１０は、回線選択部９から通知されたシフト回線番号がｉの場合、周波数シフト部４に、周波数シフト回路４ｉのみを動作させ、他の周波数シフト回路、すなわち、周波数シフト回路４１～４（ｉ－１）、４（ｉ＋１）～４ｎの動作を停止させるよう指示する。また、制御部１０は、キャリア処理部５に、周波数シフト回路４ｉの出力のみを処理するよう指示する。また、制御部１０は、シンボルメモリ部６に、シンボルメモリ６ｉのみ記憶動作させ、他のシンボルメモリ、すなわち、シンボルメモリ６１～６（ｉ－１）、６（ｉ＋１）～６ｎの記憶動作を停止させるよう指示する。また、制御部１０は、復調部７に、シンボルメモリ６ｉのデータのみを処理するよう指示する。 The control unit 10 instructs the frequency shift unit 4 to stop the function blocks related to the lines other than the shift line for which reception synchronization has been established, based on the shift line number notified from the line selection unit 9. Thereby, the operation of the circuit is unnecessarily suppressed and the power consumption of the circuit is suppressed. Specifically, when the shift line number notified from the line selection unit 9 is i, the control unit 10 causes the frequency shift unit 4 to operate only the frequency shift circuit 4i, so that other frequency shift circuits, that is, frequency The shift circuits 41 to 4 (i−1) and 4 (i + 1) to 4n are instructed to be stopped. In addition, the control unit 10 instructs the carrier processing unit 5 to process only the output of the frequency shift circuit 4i. Further, the control unit 10 causes the symbol memory unit 6 to store only the symbol memory 6i, and stops the storage operation of other symbol memories, that is, the symbol memories 61 to 6 (i-1) and 6 (i + 1) to 6n. Instruct them to do so. Further, the control unit 10 instructs the demodulation unit 7 to process only the data in the symbol memory 6i.
　周波数シフト部４は、制御部１０からの指示に応答して、周波数シフト回路４ｉを動作させるともに、他の周波数シフト回路４１～４（ｉ－１）、４（ｉ＋１）～４ｎを休止させる。また、キャリア処理部５は、制御部１０からの指示に応答して、内部の状態を、周波数シフト回路４ｉの出力のみを処理可能な状態に切り替える。シンボルメモリ部６は、制御部１０からの指示に応答して、シンボルメモリ６ｉ以外のシンボルメモリの動作を停止させる。シンボルメモリ６ｉは、キャリア処理部５が周波数シフト回路４ｉの出力信号から生成したベースバンド信号を記憶する。また、復調部７は、制御部１０からの指示に応答して、シンボルメモリ６ｉのデータのみを処理する。 The frequency shift unit 4 operates the frequency shift circuit 4i in response to an instruction from the control unit 10, and pauses the other frequency shift circuits 41 to 4 (i-1) and 4 (i + 1) to 4n. Further, in response to an instruction from the control unit 10, the carrier processing unit 5 switches the internal state to a state where only the output of the frequency shift circuit 4i can be processed. In response to an instruction from the control unit 10, the symbol memory unit 6 stops the operation of symbol memories other than the symbol memory 6i. The symbol memory 6i stores a baseband signal generated from the output signal of the frequency shift circuit 4i by the carrier processing unit 5. Further, in response to an instruction from the control unit 10, the demodulation unit 7 processes only the data in the symbol memory 6i.
　復号部１１は、回線選択部９から送られた正常に受信したシフト回線で得られたベースバンド信号から生成された軟判定値と、回線３０又は４０に使用されている誤り訂正方式に基づいて復号する。この復号部１１で復号された信号は復号データとしてデータ処理部１２に送られる。 The decoding unit 11 is based on the soft decision value generated from the baseband signal obtained from the normally received shift line sent from the line selection unit 9 and the error correction method used for the line 30 or 40. Decrypt. The signal decoded by the decoding unit 11 is sent to the data processing unit 12 as decoded data.
　データ処理部１２は、図２に示す端末装置２４等に、端末データ形式への変換、通信プロトコルに対応した形態で、受信データを伝達する。 The data processing unit 12 transmits the received data to the terminal device 24 shown in FIG. 2 in a form corresponding to the conversion to the terminal data format and the communication protocol.
　以上の構成からなる変復調装置２３の受信回路２３０では、周波数シフト部４によって、ベースバンド信号を複数の周波数で待ち受け可能となる。このため、結果的に受信周波数の許容偏差の拡大を図ることができる。また、周波数シフト部４では、各周波数シフト回路４１～４ｎにより、同時並行的に処理が可能であるため、一つの周波数シフト回路によって周波数軸上をスイープさせることで引き込み可能周波数範囲を広げる手法に比べ、高速に受信信号の引き込みが可能となる。 In the receiving circuit 230 of the modulation / demodulation device 23 configured as described above, the frequency shift unit 4 can wait for a baseband signal at a plurality of frequencies. For this reason, as a result, the allowable deviation of the reception frequency can be increased. Further, since the frequency shift unit 4 can perform processing in parallel by each of the frequency shift circuits 41 to 4n, the frequency shift unit 4 is a method of expanding the pullable frequency range by sweeping on the frequency axis by one frequency shift circuit. In comparison, it is possible to pull in the received signal at high speed.
　通信回線での受信周波数偏差は、送信地球局からの送信周波数偏差と、通信衛星の局所発振回路の周波数偏差の合計となるが、例えば、衛星通信システムで、音声帯域の信号、少量の制御信号等を伝送する場合、通信回線が狭帯域回線となり、それに比較して、受信周波数偏差が大きい場合は、受信側の地球局２００で信号の引き込みができなくなる。このような場合であっても、本実施形態に係る受信回路２３０によれば、引き込み可能周波数範囲を広げることができるため、受信精度を良好に保つことができる。 The reception frequency deviation in the communication line is the sum of the transmission frequency deviation from the transmission earth station and the frequency deviation of the local oscillation circuit of the communication satellite. For example, in a satellite communication system, a voice band signal, a small amount of control signal When the communication line is a narrow-band line and the reception frequency deviation is larger than that, the receiving earth station 200 cannot pull in the signal. Even in such a case, according to the receiving circuit 230 according to the present embodiment, it is possible to widen the pullable frequency range, and thus it is possible to maintain good reception accuracy.
　また、受信周波数偏差の主要因が送信局の送信周波数偏差である場合は、送信局の送信偏差を必要以上に高精度に保つ必要はなくなるため、あえて、高精度な周波数偏差を実現するための高精度な基準信号源を地球局に設ける必要はなくなる。したがって、地球局の低価格化が実現できる。 In addition, when the main factor of the reception frequency deviation is the transmission frequency deviation of the transmitting station, it is not necessary to keep the transmission deviation of the transmitting station with higher precision than necessary. There is no need to provide a highly accurate reference signal source in the earth station. Therefore, the price of the earth station can be reduced.
　また、受信回路２３０によれば受信同期確立までの時間を短縮できるため、受信同期確立の判定を持って衛星方向の捕捉を行うようなシステムにおいては、高速捕捉が可能となる。したがって、結果的に衛星回線の開始までの時間、再捕捉時に要する時間を短縮でき、迅速な衛星回線の導通が可能となる。 Further, according to the receiving circuit 230, since the time until the establishment of reception synchronization can be shortened, a high-speed acquisition is possible in a system that performs acquisition in the satellite direction with determination of establishment of reception synchronization. Therefore, as a result, the time required to start the satellite line and the time required for re-acquisition can be shortened, and the satellite line can be quickly connected.
　また、本実施形態の受信回路２３０の構成では、周波数シフト部４を構成する周波数シフト回路４１～４ｎ以外の部分については、同一回路の時分割動作により実現するため、主にＦＰＧＡ（Field-Programmable Gate Array）等のデジタル素子の回路容量の増加量を必要最低限に抑えることが可能である。 Further, in the configuration of the receiving circuit 230 of the present embodiment, the portions other than the frequency shift circuits 41 to 4n constituting the frequency shift unit 4 are realized by the time-division operation of the same circuit, so that the FPGA (Field-Programmable) is mainly used. It is possible to minimize the amount of increase in circuit capacity of digital elements such as Gate Array.
　なお、本発明は上記の実施形態及び図面によって限定されるものではない。適宜変更（構成要素の削除も含む）を加えることができる。 In addition, this invention is not limited by said embodiment and drawing. Changes can be made as appropriate (including deletion of components).
　例えば、図３に例示する変復調装置２３の回路構成自体は、必要に応じて、適宜変更可能である。また、図３に示す回路をディスクリート回路で構成しても、ＤＳＰ（Digital Signal Processor）等で構成してもよい。また、回線選択部９による回線選択を、同期シフト回線判定部８の出力ではなく、例えば、同期確立情報に基づいて行うことも可能である。即ち、同期を確立したと判別されたシフト回線の軟判定値を復号部１１に出力し、制御部１０にそのシフト回線の情報を通知するようにしてもよい。この場合、同期シフト回線判定部８を除去してもよい。 For example, the circuit configuration itself of the modem device 23 illustrated in FIG. 3 can be changed as needed. Also, the circuit shown in FIG. 3 may be configured by a discrete circuit or a DSP (Digital Signal Processor) or the like. In addition, the line selection by the line selection unit 9 can be performed based on, for example, synchronization establishment information instead of the output of the synchronization shift line determination unit 8. That is, the soft decision value of the shift line determined to have established synchronization may be output to the decoding unit 11 and the control unit 10 may be notified of information about the shift line. In this case, the synchronous shift line determination unit 8 may be removed.
　地球局２００にアンテナ制御／駆動部２１が設けられず、地球局２００が自動衛星捕捉機能を有していなくてもよい。また、地球局２００は、送信機能を有さず、受信機能のみを有していてもよい。これらの場合においても、上記実施形態と同様、受信周波数偏差の拡大と、迅速に衛星回線の導通が可能である。 The earth station 200 is not provided with the antenna control / drive unit 21, and the earth station 200 may not have an automatic satellite capturing function. Moreover, the earth station 200 may not have a transmission function but may have only a reception function. In these cases, as in the above embodiment, the reception frequency deviation can be increased and the satellite line can be quickly connected.
　上記実施の形態は、いずれも本発明の趣旨の範囲内で各種の変形が可能である。上記実施の形態は本発明を説明するためのものであり、本発明の範囲を限定することを意図したものではない。本発明の範囲は実施形態よりも添付した請求項によって示される。請求項の範囲内、および発明の請求項と均等の範囲でなされた各種変形は本発明の範囲に含まれる。 Any of the above embodiments can be variously modified within the scope of the gist of the present invention. The above embodiments are for explaining the present invention, and are not intended to limit the scope of the present invention. The scope of the invention is indicated by the appended claims rather than the embodiments. Various modifications made within the scope of the claims and within the scope equivalent to the claims of the invention are included in the scope of the present invention.
　本出願は、２０１２年３月１４日に出願された、明細書、特許請求の範囲、図、および要約書を含む日本国特許出願２０１２－０５７４７９号に基づく優先権を主張するものである。この元となる特許出願の開示内容は参照により全体として本出願に含まれる。 This application claims priority based on Japanese Patent Application No. 2012-057479 filed on March 14, 2012, including the specification, claims, figures, and abstract. The disclosure of this original patent application is hereby incorporated by reference in its entirety.
　１０００　衛星通信システム、１００　通信衛星、２００　地球局、２１０　親局、２２１～２２ｍ　子局、３０、４０　回線、２０　アンテナ、２１　アンテナ制御／駆動部、２２　高周波送受信部、２３　変復調装置、２４　端末装置、２３０　受信回路、１　周波数変換部、１ａ　シンセサイザ、１ｂ　ミキサ、１ｃ　ローパスフィルタ、２　ＡＤＣ、３　ＩＦサンプリング回路、３１　ＮＣＯ、３２、３３　ミキサ、３４、３５　ローパスフィルタ、４　周波数シフト部、４１～４ｎ　周波数シフト回路、４０１　ＮＣＯ、４０２、４０３　ミキサ、４０４、４０５　ローパスフィルタ、５　キャリア処理部、５１　入力部、５２　オーバーサンプリング部、５３　波形整形回路、５４　ＡＧＣ回路、５５　ＢＴＲ部、６　シンボルメモリ部、６１～６ｎ　シンボルメモリ、７　復調部、７１　ＣＷ検出部、７２　ＵＷ検出部、７３　位相推定部、７４　軟判定部、７５　ＡＦＣ部、８　同期シフト回線判定部、９　回線選択部、１０　制御部、１１　復号部、１２　データ処理部。 1000 satellite communication system, 100 communication satellite, 200 earth station, 210 master station, 221-22m slave station, 30, 40 lines, 20 antennas, 21 antenna control / drive unit, 22 high frequency transmission / reception unit, 23 modulation / demodulation device, 24 terminal device , 230 receiver circuit, 1 frequency converter, 1a synthesizer, 1b mixer, 1c low pass filter, 2 ADC, 3 IF sampling circuit, 31 NCO, 32, 33 mixer, 34, 35 low pass filter, 4 frequency shift unit, 41 to 4n Frequency shift circuit, 401 NCO, 402, 403 mixer, 404, 405 low pass filter, 5 carrier processing unit, 51 input unit, 52 oversampling unit, 53 waveform shaping circuit, 54 AGC circuit, 55 BTR unit, 6 symbol Memory section, 61-6n symbol memory, 7 demodulator section, 71 CW detection section, 72 UW detection section, 73 phase estimation section, 74 soft decision section, 75 AFC section, 8 synchronous shift line determination section, 9 line selection section, 10 Control unit, 11 decoding unit, 12 data processing unit.

Claims (8)

  1. 　通信衛星を介して送信されてくる信号を受信する受信手段と、
    　前記受信手段で受信した信号を、それぞれ異なる周波数シフト量で周波数シフトする複数の周波数シフト回路と、
    　前記複数の周波数シフト回路が出力する信号のそれぞれについて、同期処理を行う同期処理手段と、
    　前記同期処理手段により同期が確立した周波数シフト回路の出力信号を受信信号として選択する選択手段と、を備える、
    　衛星通信受信装置。     Receiving means for receiving a signal transmitted via a communication satellite;
    A plurality of frequency shift circuits for frequency-shifting the signals received by the receiving means by different frequency shift amounts;
    Synchronization processing means for performing synchronization processing for each of the signals output from the plurality of frequency shift circuits;
    Selecting means for selecting, as a received signal, an output signal of the frequency shift circuit whose synchronization is established by the synchronization processing means,
    Satellite communication receiver.
  2. 　前記選択手段は、同期が確立した出力信号を生成した周波数シフト回路以外の周波数シフト回路の動作を停止させる手段を備える、
    　請求項１に記載の衛星通信受信装置。     The selection means includes means for stopping the operation of a frequency shift circuit other than the frequency shift circuit that generated the output signal with which synchronization is established,
    The satellite communication receiver according to claim 1.
  3. 　前記選択手段は、前記同期処理手段に、同期が確立した出力信号を生成した周波数シフト回路以外の周波数シフト回路の出力信号についての同期処理を停止させる手段を備える、
    　請求項１又は２に記載の衛星通信受信装置。     The selection unit includes a unit that causes the synchronization processing unit to stop synchronization processing for an output signal of a frequency shift circuit other than the frequency shift circuit that generates the output signal with which synchronization is established.
    The satellite communication receiver according to claim 1 or 2.
  4. 　前記同期処理手段は、前記複数の周波数シフト回路の出力からそれぞれベースバンド信号を生成する処理と生成したベースバンド信号を復調する復調処理とを時分割で実行し、各周波数シフト回路の出力について同期が確立したか否かを判別する、
    　請求項１乃至３のいずれか１項に記載の衛星通信受信装置。     The synchronization processing means executes processing for generating a baseband signal from outputs of the plurality of frequency shift circuits and demodulation processing for demodulating the generated baseband signal in a time division manner, and synchronizes the outputs of the frequency shift circuits. Determine whether or not
    The satellite communication receiving device according to any one of claims 1 to 3.
  5. 　前記同期処理手段は、各周波数シフト回路の信号について、周波数偏差を求め、求めた周波数偏差を、対応する周波数シフト回路にフィードバックし、
    　各周波数シフト回路は、フィードバックされた周波数偏差に基づいて、周波数シフト量を調整する、
    　請求項１乃至４のいずれか１項に記載の衛星通信受信装置。     The synchronization processing means obtains a frequency deviation for the signal of each frequency shift circuit, and feeds back the obtained frequency deviation to the corresponding frequency shift circuit.
    Each frequency shift circuit adjusts the amount of frequency shift based on the fed back frequency deviation.
    The satellite communication receiver according to any one of claims 1 to 4.
  6. 　前記複数の周波数シフト回路のシフト間隔は、変調帯域により定まる引き込み可能範囲以下である、
    　請求項１乃至５のいずれか１項に記載の衛星通信受信装置。     The shift interval of the plurality of frequency shift circuits is less than or equal to the pullable range determined by the modulation band,
    The satellite communication receiver according to any one of claims 1 to 5.
  7. 　前記受信手段は、受信高周波信号から中間周波数帯のベースバンド信号を生成する手段を備える、
    　請求項１乃至６のいずれか１項に記載の衛星通信受信装置。     The receiving means includes means for generating a baseband signal of an intermediate frequency band from the received high-frequency signal.
    The satellite communication receiver according to any one of claims 1 to 6.
  8. 　信号を受信し、
    　受信した信号を複数の信号に分けるとともに、前記複数の信号をそれぞれ異なる周波数シフト量で周波数シフトし、
    　周波数シフトした前記複数の信号それぞれについて同期処理を行うとともに、同期処理を行った前記複数の信号それぞれについて受信同期が確立しているか否かを判別し、
    　前記複数の信号のうちの受信同期が確立していると判別された信号を選択して出力する、
    　受信方法。     Receive the signal,
    The received signal is divided into a plurality of signals, and the plurality of signals are frequency shifted by different frequency shift amounts,
    Performing synchronization processing for each of the plurality of signals shifted in frequency and determining whether reception synchronization has been established for each of the plurality of signals subjected to synchronization processing;
    Selecting and outputting a signal determined to have established reception synchronization among the plurality of signals;
    Receiving method.
PCT/JP2013/056726 2012-03-14 2013-03-12 Satellite communication reception device and reception method WO2013137222A1 (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009182837A (en) * 2008-01-31 2009-08-13 Mitsubishi Electric Corp Demodulator
WO2010021041A1 (en) * 2008-08-21 2010-02-25 富士通株式会社 Receiver and receiving method
JP2010219935A (en) * 2009-03-17 2010-09-30 Mitsubishi Electric Corp Receiver

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009182837A (en) * 2008-01-31 2009-08-13 Mitsubishi Electric Corp Demodulator
WO2010021041A1 (en) * 2008-08-21 2010-02-25 富士通株式会社 Receiver and receiving method
JP2010219935A (en) * 2009-03-17 2010-09-30 Mitsubishi Electric Corp Receiver

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