WO2011137701A1 - 一种静电保护器件及其制备方法 - Google Patents

一种静电保护器件及其制备方法 Download PDF

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WO2011137701A1
WO2011137701A1 PCT/CN2011/072409 CN2011072409W WO2011137701A1 WO 2011137701 A1 WO2011137701 A1 WO 2011137701A1 CN 2011072409 W CN2011072409 W CN 2011072409W WO 2011137701 A1 WO2011137701 A1 WO 2011137701A1
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well
type
resistor
implantation
doping
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PCT/CN2011/072409
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English (en)
French (fr)
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黄如
张丽杰
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北京大学
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Priority to US13/201,370 priority Critical patent/US8476672B2/en
Publication of WO2011137701A1 publication Critical patent/WO2011137701A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/87—Thyristor diodes, e.g. Shockley diodes, break-over diodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H01L27/0262—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements including a PNP transistor and a NPN transistor, wherein each of said transistors has its base coupled to the collector of the other transistor, e.g. silicon controlled rectifier [SCR] devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to CMOS Very Large Scale Integrated Circuit (ULSI) technology, and more particularly to an ESD protection device structure and a method of fabricating the same.
  • ULSI Very Large Scale Integrated Circuit
  • Electrostatic discharge (ESD) is very harmful to the circuit.
  • the integrated circuit designes an electrostatic protection device at the input and output ports of the circuit to discharge the current generated by the static electricity to prevent the static electricity from harming the circuit.
  • the thyristor rectification (SCR) structure has a snapback feature and is commonly used as an ESD protection device.
  • the SCR has a high discharge capacity and a good cut-off feature, but the turn-on voltage of the SCR structure is high, and many research efforts are devoted to how to reduce the turn-on voltage of the SCR structure.
  • the trigger circuit is generally used to reduce the voltage of the SCR device.
  • the trigger circuit is often implemented by a series diode or MOSFET, such as DTSCR, LVSCR, and the like. These devices are complex in structure and generally have a high trigger voltage, which is difficult to meet the requirements of low supply voltages after the CMOS device size continues to shrink. Moreover, due to the introduction of the trigger circuit, the protection circuit occupies a large area. In order to continue to shrink the size of CMOS devices, ESD protection devices must have low trigger voltage, simple structure, and small area. Summary of the invention
  • An ESD protection device comprising an SCR structure, a P-type implant and an N-type implanted lateral PNPN structure in an N-well and a P-well on a silicon substrate, wherein the P-type doping in the N-well acts as a device
  • the anode, the N-type doping in the P-well is used as the cathode of the device, characterized in that N-type doping is implanted as a resistance terminal in the N-well, and P-type doping is implanted as a resistance in the P-well.
  • the above two terminals are connected by a resistor.
  • the resistor is a polysilicon resistor or an active region resistor.
  • the N well and P well on the silicon substrate are isolated by STI.
  • a method for preparing an ESD protection device comprising:
  • the P-type implantation and the N-type implantation concentration are 10 17 to 10 18 /cm 3 .
  • step 3) and step 4 the implantation concentration of P-type heavily doped or N-type heavily doped is 10 19 ⁇ 10 21 /cm 3
  • step 1) the N well and the P well on the silicon substrate are isolated by STI.
  • the present invention connects the N-well terminal of the SCR structure to the P-well terminal through a resistor to realize a low-trigger voltage SCR structure.
  • the SCR structure has a small area and a high degree of integration. For silicon-based processes, the trigger voltage is lower, about 1.4V.
  • the present invention is fully compatible with existing CMOS processes, has a simple process preparation, and is prepared for any standard process, minimizing cost.
  • FIG. 1 is a top plan view of a layout of an ESD protection device according to the present invention.
  • Figure 3 is a cross-sectional view of the A of Figure 1;
  • Figure 4 is a cross-sectional view of the B of Figure 1;
  • an N-well and a P-well are prepared by N-type doping and P-type doping, and deep trench isolation (STI) is simultaneously performed to prevent P-doped region and N-type implanted extraction in the N-well.
  • STI deep trench isolation
  • the mutual expansion between the regions, the two regions are separated by STI, which can prevent mutual expansion between the N-doped region and the P-type implanted lead-out region in the P-well.
  • P-type implantation and N-type implantation are respectively performed in the N well (Nwell) and the P well (Pwell) on the silicon substrate to form a lateral PNPN structure.
  • an N-type implant is used as a lead-out of the N-well in a region away from the P-type implant in the N-well
  • a P-type implant is used as a lead-out of the P-well in a region away from the N-type implant in the P well.
  • the terminal of the N-well and the terminal of the P-well are connected by a resistor, thereby realizing an SCR structure with a low trigger voltage.
  • the resistor can be a polysilicon resistor or an active region resistor.
  • the N-well terminal is located in the N-well and cannot be implanted in close proximity to the P-type.
  • the P-well is located in the P-well. It is not possible to be in close proximity to the N-type implant. It is ensured that there is no doping mutual expansion between the P-type implant and the N-type implant at the lead-out end of the P-well; the two lead-out terminals can be appropriately adjusted according to the actual required polysilicon resistance.
  • FIG. 1 is a schematic diagram of a layout of an ESD protection device of the present invention, and does not include all versions in the actual design, for example, a source area plate, a metal layer layout of each layer, and the like.
  • Figure 3 and Figure 4 are cross-sectional views of the ESD protection device (RTSCR) structure.
  • the present invention can be implemented by a layout method using a standard CMOS process.
  • the shape of the polycrystalline silicon is not limited to the shape shown in Fig. 1, and can be formed into various shapes.
  • the polycrystalline silicon can be formed into a multi-strand-shaped thin strip shape.
  • the polysilicon resistor region should be covered by a silicided version to protect it from subsequent source and drain silicidation processes.
  • the terminals of the N-well and the P-well are not limited to the position shown in FIG. 1, and may be placed anywhere in the N-well and the P-well as needed.
  • the N-well terminal and the P-well terminal are preferably placed at Close to the edge of Nwell and Pwell, that is, the farther apart the two terminals are.
  • the N-type and P-type low-doping implants are respectively performed using the layout of the N-well and the P-well in Fig. 1, and the implantation concentration is 10 17 to 10 18 /cm 3 .
  • a polysilicon resistor is prepared in the preparation of the polysilicon gate structure.
  • polycrystalline silicon is deposited, and the polysilicon resistive strip of Fig. 1 is used for photolithography and etching to prepare a polysilicon resistive strip.
  • an N-type doping implant is performed in the N well, and an implantation concentration is 10 19 to 10 21 /cm 3 to form a lead terminal of the polysilicon resistor, and N is performed in the P well.
  • Type doping implantation to form the cathode of the device This step can be performed by doping the source and drain regions of the NMOS in a standard process.
  • P is performed in the N well.
  • Type doping implantation forms the anode of the device, and P-type doping implantation in the P-well forms another terminal of the polysilicon resistor. This process can be performed by doping implantation of the source and drain regions of the PMOS in a standard process.
  • the ESD protection device RTSCR structure is exactly the same as the conventional MOS structure, and successively: depositing the isolation layer, lithography lead hole; depositing metal, lithography lead; Chemical.
  • the length and width of the polysilicon resistor can be realized by the layout, and the thickness of the polysilicon resistor is determined by the implemented process.
  • the terminals of the N-well and P-well of the present invention can also be connected to both ends of the active region resistor.
  • the layout size used as the active area resistance can be determined according to actual needs.
  • the terminals of the N-well and P-well are anywhere in the N-well and P-well as needed.
  • the same substrate material as the conventional MOS is used (for example, a P-type material);
  • the N-type and P-type low-doping implants are respectively performed using the layout of the N-well and the P-well in FIG. 1, and the implantation concentration is about 10 17 . ⁇ 10 18 /cm 3 :
  • an N-type doping implant is performed in the N well to form a lead terminal of the active region resistance, and an N-type doping implant is performed in the P well to form a cathode of the device.
  • This step can be implemented in the standard process for doping implantation of the source and drain regions of the NMOS;
  • a P-type doping implant is performed in the N well to form an anode of the device, and a P-type doping implant is performed in the P well to form another lead end of the active region resistance, and at the same time Two separate places in the source region are subjected to P-type doping implantation to form two terminals of the active region resistance.
  • This step can be realized when the source and drain regions of the PMOS are implanted in a complicated process in a standard process.
  • the length and width of the active area resistor can be realized by the layout.
  • the present specification describes in detail the structure of the RTSCR device of the present invention and the process of manufacturing using the CMOS process through specific embodiments, those skilled in the art should understand that the implementation of the present invention is not limited to the scope of the description of the embodiment, for example, based on SOI. Design and fabrication of circuit ESD protection devices for processes. Various modifications and alterations of the present invention are possible without departing from the spirit and scope of the invention.

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  • Microelectronics & Electronic Packaging (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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Description

一种静电保护器件及其制备方法 技术领域
本发明涉及 CMOS超大规模集成电路 （ULSI) 技术， 具体是一种 ESD保护器件结构及 其制备方法。 背景技术
静电放电 （ESD) 对电路的危害很大， 通常集成电路在电路的输入输出口设计静电保护 器件， 泄放静电所产生的电流， 以防止静电对电路的危害。 可控硅整流 （SCR ) 结构具有 snapback特性， 常用来做 ESD保护器件。 SCR具有较高的泄流能力和良好的截止特型， 但是 SCR结构的开启电压较高， 很多研究工作都致力于如何降低 SCR结构的开启电压。 目前， 一 般采用触发电路降低 SCR器件的电压， 触发电路常常由串联二极管或者 MOSFET实现， 如 DTSCR, LVSCR等。 这些器件的结构复杂， 其触发电压一般也较高， 很难满足 CMOS器件 尺寸继续缩小之后低电源电压的要求。 而且由于引入的触发电路， 使得保护电路所占面积较 大。 为适应 CMOS器件尺寸继续缩小趋势， ESD保护器件必须具备低触发电压、 结构简单、 面积小等特点。 发明内容
本发明的目的在于提供一种低触发电压的 ESD保护器件及其制备方法。
本发明的上述目的是通过如下的技术方案予以实现的：
一种 ESD保护器件，包括一 SCR结构， 为硅衬底上的 N阱和 P阱中分别进行 P型注入 和 N型注入的横向 PNPN结构， 其中， 在 N阱中的 P型掺杂作为器件的阳极， P阱中的 N型 掺杂作为器件的阴极， 其特征在于， 在上述 N阱中注入 N型掺杂作为一电阻引出端， 在 P阱 中注入 P型掺杂作为电阻的另一引出端， 上述两引出端通过电阻相连。
所述电阻为多晶硅电阻或有源区电阻。
所述硅衬底上的 N阱和 P阱用 STI隔离。
一种 ESD保护器件的制备方法， 其步骤包括：
1)硅衬底上分别进行 P型注入和 N型注入， 形成 N阱和 P阱；
2)在制备多晶硅栅结构时，刻蚀多晶硅形成电阻；
3)在上述 N阱中的部分区域进行 N型重掺杂注入， 形成 N+区， 作为上述电阻的一引出 端， 同时上述 P阱中的部分区域进行 N型重掺杂注入， 形成器件的阴极； 4)在 P阱中的部分区域进行 P型重掺杂注入， 形成 P+区， 作为上述电阻的另一引出端， 同时上述 N阱中的部分区域 P型重糁杂注入， 形成器件的阳极；
5)采用 COMS标准工艺完成 ESD保护器件的后续制备。
步骤 1)中， P型注入和 N型的注入浓度为 1017~1018/cm3。
步骤 3)和步骤 4)中， P型重掺杂或 N型重掺杂的注入浓度为 1019~1021/cm3
步骤 1)中， 硅衬底上的 N阱和 P阱用 STI隔离。
本发明的技术优点和效果：
参考图 2， 本发明通过电阻将 SCR结构的 N阱引出端和 P阱引出端相连， 实现低触发电 压的 SCR结构。 该 SCR结构面积小， 集成度高。 对于硅基工艺来说， 其触发电压较低， 约 为 1.4V。
本发明和现有 CMOS工艺完全兼容， 工艺制备简单， 且制备办法对于任何标准工艺均有 效， 最大程度降低了成本。 附图说明
下面结合附图对本发明进一步详细地说明：
图 1为本发明 ESD保护器件版图俯视示意图；
图 2为本发明 ESD保护器件的等效电路图；
图 3为图 1的 A剖面示意图；
图 4为图 1的 B剖面示意图；
其中 1 器件的阴极； 2 器件的阳极； 3— N阱； 4 P阱； 5— N阱中的电阻引出端； 6 P阱中的电阻引出端； 7—电阻； 8—引出孔。 具体实施方式
下面参照本发明的附图， 更详细的描述出本发明的最佳实施例。
在硅衬底上， 通过 N型掺杂和 P型掺杂制备出 N阱和 P阱， 同时进行深沟槽隔离（STI) 制备， 为了防止 N阱中 P型掺杂区和 N型注入引出区之间的互扩， 两区中间用 STI隔离， 可 以防止 P阱中 N型掺杂区和 P型注入引出区之间的互扩。 在硅衬底上的 N阱 （Nwell) 和 P 阱 （Pwell) 中分别进行 P型注入和 N型注入形成横向的 PNPN结构。 本发明提出， 在 N阱 中远离 P型注入的区域有 N型注入作为 N阱的引出端， P阱中远离 N型注入的区域有 P型注 入作为 P阱的引出端。 N阱的引出端和 P阱中的引出端通过电阻相连， 从而实现低触发电压 的 SCR结构。 电阻可以是多晶硅电阻， 也可以是有源区电阻。 N阱引出端位于 N阱中， 不能紧邻 P型注入， 得保证 N阱引出端的 N型注入和 P型注 入之间不能有所掺杂质的互扩； P阱的引出端位于 P阱中， 不能紧邻 N型注入， 得保证 P阱 引出端的 P型注入和 N型注入之间不能有所掺杂质的互扩； 两个引出端可以根据实际需要的 多晶硅电阻大小适当调整。
下面结合实施例来进一歩说明本发明，但本发明的用途并不仅限于下面的具体实施例子。 实施例一
图 1是本发明 ESD保护器件的版图示意图， 并没有包括实际设计中所有的版， 比如， 有 源区版、 各层金属线版图等。 图 3、 图 4所示 ESD保护器件 （RTSCR) 结构的剖视图。
本发明通过版图设计的方法， 利用标准的 CMOS工艺就能实现。 上述版图设计， 多晶硅 的形状不限于示图 1所示的形状， 可以做成各种形状， 为了增大多晶硅电阻值， 多晶硅可以 做成多折线型细条状。 多晶硅电阻区应该被硅化保护版覆盖， 使不受后续的源漏区硅化工艺 的影响。 N阱和 P阱的引出端不限于图 1所示位置， 可以根据需要在 N阱和 P阱中的任意位 置， 为了增大多晶硅电阻值， N阱引出端和 P阱引出端最好放置在靠近 Nwell和 Pwell边缘 处， 即两个引出端相隔越远越好。
上述器件的具体制备过程如下：
制备开始时， 采用和常规 MOS相同的衬底材料；
首先， 采用标准工艺流程的阱注入工艺时， 利用图 1中 N阱和 P阱的版图， 分别进行 N 型和 P型低掺杂注入， 注入浓度为 1017~1018/cm3。
接下来在 CMOS工艺中在制备多晶硅栅结构时，制备多晶硅电阻。 首先淀积多晶硅， 利 用图 1中的多晶硅电阻版进行光刻、 刻蚀， 制备出多晶硅电阻条。
接下来， 根据图 1 所示的 N+注入版图， 在 N 阱中进行 N型掺杂注入， 注入浓度为 1019~1021/cm3, 形成多晶硅电阻的一个引出端， 在 P阱中进行 N型掺杂注入， 形成器件的阴 极， 此步骤可以在标准工艺中对 NMOS的源漏区进行掺杂注入时实现； 接下来， 根据图 1所 示的 P+注入版图， 在 N阱中进行 P型掺杂注入， 形成器件的阳极， 在 P阱中进行 P型掺杂注 入形成多晶硅电阻的另一个引出端， 此工艺可以在标准工艺中对 PMOS的源漏区进行掺杂注 入时实现。 然后是阳极阴极引出端硅化工艺， 后面的工艺流程中， ESD保护器件 RTSCR结 构和常规的 MOS 结构完全一样， 先后进行： 淀积隔离层， 光刻引线孔； 淀积金属， 光刻引 线； 钝化。
其中， 多晶硅电阻的长度、 宽度可以通过版图实现， 多晶硅电阻的厚度由所实现的工艺 决定。 实施例二
本发明 N阱和 P阱的引出端也可以接有源区电阻的两端。用作有源区电阻的版图大小可 以根据实际需要确定出。 N阱和 P阱的引出端根据需要在 N阱和 P阱中的任意位置。
器件的具体制备过程如下：
制备开始时， 采用和常规 MOS相同的衬底材料 （以 P型材料为例）；
首先， 进行有源区的注入， 然后采用标准工艺流程的阱注入工艺时， 利用图 1中 N阱和 P阱的版图， 分别进行 N型和 P型低掺杂注入， 注入浓度约为 1017~1018/cm3 :
接下来， 根据图 1所示的 N+注入版图， 在 N阱中进行 N型掺杂注入， 形成有源区电阻 的一个引出端， 在 P阱中进行 N型掺杂注入， 形成器件的阴极， 此步骤可以在标准工艺中对 NMOS的源漏区进行掺杂注入时实现；
根据图 1所示的 P+注入版图， 在 N阱中进行 P型掺杂注入， 形成器件的阳极， 在 P阱中 进行 P型掺杂注入形成有源区电阻的另一个引出端， 同时在有源区两个分离的地方进行 P型 掺杂注入形成有源区电阻的两个引出端， 此步骤可以在标准工艺中对 PMOS的源漏区进行惨 杂注入时实现。
后面的工艺流程中， 先后进行： 所有引出端的硅化， 淀积隔离层， 光刻引线孔； 淀积金 属， 光刻引线； 钝化。 有源区电阻两端通过多晶硅连线或者金属连线分别和有源区电阻的两 端相连。
其中， 有源区电阻的长度、 宽度可以通过版图实现。 虽然本说明书通过具体的实施例详细描述了本发明的 RTSCR器件结构以及利用 CMOS 工艺制备的过程， 但是本领域的技术人员应该理解， 本发明的实现方式不限于实施例的描述 范围，例如基于 SOI工艺的电路 ESD保护器件的设计和制备等。在不脱离本发明实质和精神 范围内， 可以对本发明进行各种修改和替换，

Claims

权 利 要 求 书
1、一种 ESD保护器件， 包括一 SCR结构， 为硅衬底上的 N阱和 P阱中分别进行 P型注 入和 N型注入的横向 PNPN结构， 其中， 在 N阱中的 P型掺杂作为器件的阳极， P阱中的 N 型惨杂作为器件的阴极， 其特征在于， 在上述 N阱中注入 N型惨杂作为一电阻引出端， 在 P 阱中注入 P型掺杂作为电阻的另一引出端， 上述两引出端通过电阻相连。
2、 如权利要求 1所述的器件， 其特征在于， 所述电阻为多晶硅电阻或有源区电阻。
3、 如权利要求 1或 2所述的器件， 其特征在于， 所述硅衬底上的 N阱和 P阱用 STI隔 离。
4、 一种 ESD保护器件的制备方法， 其步骤包括：
1)硅衬底上分别进行 P型注入和 N型注入， 形成 N阱和 P阱；
2)在制备多晶硅栅结构时， 刻蚀多晶硅形成电阻；
3)在上述 N阱中的部分区域进行 N型重掺杂注入， 形成 N+区， 作为上述电阻的一引 出端， 同时上述 P阱中的部分区域进行 N型重掺杂注入， 形成器件的阴极；
4)在 P阱中的部分区域进行 P型重掺杂注入，形成 P+区，作为上述电阻的另一引出端， 同时上述 N阱中的部分区域 P型重掺杂注入， 形成器件的阳极；
5)采用 COMS标准工艺完成 ESD保护器件的后续制备。
5、 如权利要求 4所述的方法， 其特征在于， 步骤 1)中， P型注入和 N型的注入浓度为 1017~1018/cm3。
6、 如权利要求 4或 5所述的方法， 其特征在于， 步骤 3)和步骤 4)中， P型重掺杂或 N 型重掺杂的注入浓度为 1019~1021/cm3。
7、 如权利要求 4所述的方法， 其特征在于， 步骤 1)中， 硅衬底上的 N阱和 P阱用 STI 隔离。
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