WO2010020015A1 - Synchronisation and timing method and apparatus - Google Patents
Synchronisation and timing method and apparatus Download PDFInfo
- Publication number
- WO2010020015A1 WO2010020015A1 PCT/AU2009/001081 AU2009001081W WO2010020015A1 WO 2010020015 A1 WO2010020015 A1 WO 2010020015A1 AU 2009001081 W AU2009001081 W AU 2009001081W WO 2010020015 A1 WO2010020015 A1 WO 2010020015A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- usb
- time
- local
- clock
- counter
- Prior art date
Links
- 238000000034 method Methods 0.000 title claims abstract description 265
- 230000001360 synchronised effect Effects 0.000 claims abstract description 81
- 238000004891 communication Methods 0.000 claims abstract description 78
- 238000005259 measurement Methods 0.000 claims description 67
- 230000000737 periodic effect Effects 0.000 claims description 65
- 230000007704 transition Effects 0.000 claims description 18
- 239000013078 crystal Substances 0.000 claims description 16
- 238000013507 mapping Methods 0.000 claims description 13
- 238000013213 extrapolation Methods 0.000 claims description 12
- 230000007246 mechanism Effects 0.000 claims description 8
- 238000007619 statistical method Methods 0.000 claims description 7
- 238000001914 filtration Methods 0.000 claims description 6
- 238000012544 monitoring process Methods 0.000 claims description 6
- 230000002093 peripheral effect Effects 0.000 claims description 4
- 239000004065 semiconductor Substances 0.000 claims description 4
- 230000003252 repetitive effect Effects 0.000 claims description 3
- 150000001875 compounds Chemical class 0.000 claims description 2
- 230000006870 function Effects 0.000 description 33
- 238000013459 approach Methods 0.000 description 9
- 238000012545 processing Methods 0.000 description 8
- 238000012546 transfer Methods 0.000 description 8
- 238000001514 detection method Methods 0.000 description 7
- 241000238876 Acari Species 0.000 description 5
- 238000004364 calculation method Methods 0.000 description 5
- 230000001934 delay Effects 0.000 description 5
- 230000008859 change Effects 0.000 description 4
- 230000003287 optical effect Effects 0.000 description 4
- 238000012360 testing method Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000000691 measurement method Methods 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 238000004422 calculation algorithm Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000037361 pathway Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000011664 signaling Effects 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 238000001228 spectrum Methods 0.000 description 2
- 230000001960 triggered effect Effects 0.000 description 2
- 241000218691 Cupressaceae Species 0.000 description 1
- 238000004458 analytical method Methods 0.000 description 1
- 238000003491 array Methods 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 238000012512 characterization method Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 239000000835 fiber Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000004886 process control Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 230000005236 sound signal Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/14—Time supervision arrangements, e.g. real time clock
-
- A—HUMAN NECESSITIES
- A61—MEDICAL OR VETERINARY SCIENCE; HYGIENE
- A61K—PREPARATIONS FOR MEDICAL, DENTAL OR TOILETRY PURPOSES
- A61K31/00—Medicinal preparations containing organic active ingredients
- A61K31/33—Heterocyclic compounds
- A61K31/395—Heterocyclic compounds having nitrogen as a ring hetero atom, e.g. guanethidine or rifamycins
- A61K31/495—Heterocyclic compounds having nitrogen as a ring hetero atom, e.g. guanethidine or rifamycins having six-membered rings with two or more nitrogen atoms as the only ring heteroatoms, e.g. piperazine or tetrazines
- A61K31/496—Non-condensed piperazines containing further heterocyclic rings, e.g. rifampin, thiothixene or sparfloxacin
Definitions
- the present invention relates to a method and apparatus for providing a microcontroller based synchronization and timing system, of particular but by no means exclusive use in providing syntonised clocks, data acquisition and automation and control of test and measurement equipment, instrumentation interfaces and process control equipment, and synchronization of such clocks to an essentially arbitrary degree in either a local or distributed environment.
- USB specification is intended to facilitate the interoperation of devices from different vendors in an open architecture.
- USB data is encoded using differential signalling, that is, in the form of the difference between the signal levels of two wires that transfer the information.
- the USB specification is intended as an enhancement to the PC architecture, spanning portable, desktop and home environments.
- USB specification assumes that devices differ. This is true for the intended environments in which devices from a multiplicity of manufacturers are connected, but there exist other environments (such as certain common industrial or laboratory environments) that require a specification for operating multiple devices of a similar nature in a synchronized manner. The specification does not sufficiently address this issue. Such environments are typically those where testing, measuring or monitoring is performed, and which require the devices to be synchronized to a more accurate degree than is specified.
- the USB specification allows limited inter-device synchronization by providing a 1 kHz clock signal to all devices- However, many laboratory and industrial environments require synchronization at megahertz frequencies and higher.
- USB employs a tiered star topology, where hubs provide attachment points for USB devices.
- the USB host controller which is located on the user's personal computer (PC), laptop or personal digital assistant (PDA) contains the root hub, which is the origin of all USB ports in the system.
- the root hub provides a number of USB ports to which USB functional devices or additional hubs may be attached.
- USB allows a maximum of 127 devices (including hubs) to be connected, with the restriction that any device may be at most five levels deep.
- the root hub in the host transmits a Start of Frame (SOF) signal packet every 1 ms to every device, the time between two SOF packets being termed a frame.
- SOF Start of Frame
- Each module receives this SOF packet at a different time, owing to electrical delays inherent in the USB topology, which means that there may be a significant time delay (specified as ⁇ 380 ns) between the receipt of a signal at a device connected directly to the host controller and at a device that is five levels down. This is a severe restriction when it is desired to synchronize devices at megahertz levels and above.
- the USB specification allows the host controller to fail to transmit up to five consecutive SOF tokens.
- Interrupt transfers allow guaranteed polling frequencies of devices with minimum periods of 125 ⁇ s
- isochronous transfers guarantee a constant transfer rate.
- Both methods require there to be traffic between the device and host for synchronization to take place and therefore reserve more bandwidth for higher degrees of synchronization. This unfortunately means that the available USB bandwidth can be used up before the maximum number of devices has been connected.
- This approach also places on the host the great computational burden of keeping 127 devices synchronized to the host by means of software, yet still fails to address maintaining synchrony between the devices as to the host the individual devices represent separate processes.
- a device such as a laser diode with a modulated light output at .1 MHz may use a clock signal to perform transducer functions at regular intervals or at a constant frequency.
- a trigger signal is usually used to start or end an operation at a set time. In the laser diode example, a trigger signal could be used to turn the modulated light output on or off.
- clock and trigger signals can be used to synchronize a multiplicity of devices to each other (and hence constitute what is referred to below as "synchronization information"), provided that the signals are common and simultaneous to all devices.
- synchronization information e.g., a multiplicity of devices to each other
- 'Common' and 'simultaneous' here mean that the variation in time of these signals between the devices is less than a specified quantity, ⁇ t. Jn the laser diode example, this would enable a multiplicity of laser diodes to modulate their light output at one frequency.
- the modulation frequency of all devices would be the same, and their waveforms would be in- phase.
- the current USB specification (viz. 2.0) allows for a ⁇ t of up to 0.35 ⁇ s. For a signal with a frequency of 1 MHz and a period of 1.0 ⁇ s, this delay represents almost half of the period. It is thus unusable as synchronization information for routine use.
- USB devices such as hubs and USB controller chips commonly use some amount of endpoint phase locking in order to decode the USB protocol. It is the purpose of the SYNC pattern in the USB protocol to provide a synchronization pattern for another electronic circuit to lock to. However, this is intended to synchronize the device endpoint to the USB bit streams to an accuracy sufficient to interpret data streams. It is not intended to synchronize the functionality of two separate devices to each other. In particular it is not intended to synchronise device functionality to the level required by many test and measurement instruments.
- the USB specification to the extent that it deals with inter-device synchronization — is mainly concerned with synchronizing the data packets of a USB-CD audio stream sufficiently for output on a USB-speaker pair.
- USB specification allows implementation of an isochronous pipe in which data loss is tolerated.
- the specification does not address the potential problems of synchronizing, for example, 100 USB-speaker pairs as the present means merely synchronises pairs of endpoints rather than the functionality of the device. Nor does it address issues related to data loss which are unacceptable in the vast majority of applications.
- USB communication transfers data during regular 1 ms frames (or, in the case of the High-Speed USB specification, in eight micro- frames per 1 ms frame).
- a Start of Frame (SOF) packet is transmitted to all but Low-Speed devices at the beginning of each frame and to all High-Speed devices at the beginning of each micro-frame.
- the SOF packet therefore represents a periodic low resolution signal broadcast to all but Low-Speed devices connected to a given Host Controller.
- This SOF packet broadcast occurs at a nominal frequency of 1 kHz (or, in the case of the High-Speed USB specification, 8 kHz).
- the USB specification allows a very large frequency tolerance (by instrumentation standards) of 500 parts per million.
- the background art utilises this low resolution frequency signal that is broadcast to each of the devices to provide clock synchronization, but only to the somewhat ambiguous frequency provided by the USB Host Controller.
- US Patent No. 6,343,364 discloses an example of frequency locking to USB traffic, which is directed toward a smart card reader.
- This document teaches a local, free-running clock that is compared to USB SYNC and packet ID streams; its period is updated to match this frequency, resulting in a local clock with a nominal frequency of 1.5 MHz.
- This provides a degree of synchronization sufficient to read smart card information into a host PC but, as this approach is directed to a smart card reader, inter-device synchronization is . not addressed.
- US Patent No. 6,092,210 discloses a method for connecting two USB hosts for the purpose of data transfer, by employing a USB-to-USB connecting device for synchronizing local device clocks to the data streams of both USB hosts. Phase locked loops are used to synchronize local clocks and over-sampling is used to ensure that data loss does not occur.
- This document relates to the synchronization of the data streams of two USB hosts with each other (and with limited accuracy) such that transfer of information is then possible between said Hosts; no method for synchronizing a plurality of USB devices to a single USB Host or to a plurality of USB hosts is provided.
- US Patent Application No. 10/620,769 discloses a synchronized version of the USB, in which the local clock of each, device is synchronized on a given USB to an arbitrary degree. This document also discloses a method and apparatus for providing a trigger signal to each device within the USB such that an event may be synchronously initiated on multiple devices by the trigger signal.
- This architecture for synchronization of the local clock on each of a plurality of USB devices employs periodic data structures already present in the USB traffic.
- An embodiment disclosed in US Application No. 10/620,769 essentially locks the local clock in frequency and phase to the detection of a SOF packet token at the USB device.
- Circuitry is employed to observe traffic through the USB and decode a clock carrier signal from bus traffic (in one embodiment, SOF packets), which results in a nominal carrier signal frequency of 1kHz (or 8kHz for USB High Speed).
- the local clock. signal from a controlled oscillator clock is locked to the reception of the USB SOF packet in both phase and frequency. This ensures that all devices attached to the root hub are locked in frequency to the point at which they receive the SOF packet token.
- this approach is limited in its ability to provide a precisely known clock frequency to each device.
- the carrier signal once decoded from the USB traffic, is combined with a scaling factor to generate synchronization information and hence to synthesize a local clock signal with precise control of the clock frequency.
- the frequency of the local clock signal can be more accurate than the somewhat ambiguous frequency of the carrier signal.
- US Application No. 10/620,769 also teaches a method and apparatus to further synchronize multiple local clocks in phase by measurement of signal propagation time from the host to each device and provision of clock phase compensation on each of the USB devices.
- USB systems can perform accurate clock synchronisation between USB devices with accurate clock frequency generation, they require special hardware components to decode data present on the USB and precision determination of the moment in time of carrier signal reception. These components are required in addition to the normal USB bus interface circuitry and microcontroller so these approaches are not compatible with a generic implementation of USB using off the shelf USB interface microcontrollers.
- USB specification constraints the level of capacitance that the USB device can present to the bus.
- the effective capacitance of USB each data line to ground in the presence of the parallel effective resistance to ground is very tightly controlled. There is generally only a small capacitance margin with compliant USB devices. Addition of a parallel data pathway circuit to a conventional USB device would typically exceed the capacitance limits.
- the invention provides a method of synchronising a first device and at least one second device (which may be one or a plurality of such second devices), each having a local oscillator (such as a free-running oscillator) and a microcontroller, and the second device being in data communication with the first device via a communication bus, the method comprising: said first device transmitting a plurality of signals to said second device; said second device using said plurality of signals to measure the frequency of its local oscillator; said first device transmitting a signal to said second device indicative of a required frequency to be synchronised to; and said second device employing its microcontroller to configure itself to generate a local clock signal with said required frequency using the frequency of its local oscillator.
- a local oscillator such as a free-running oscillator
- the devices may be USB devices. • .
- the method includes the second device configuring itself to generate said local clock signal with said required frequency to an arbitrary degree.
- microcontroller-based multi-device synchronisation whereby the (at least one) second device, each with their own oscillator, are attached to a common bus and synchronised using signals from that bus.
- each device receives a common signal from the bus which is used as a reference carrier signal.
- the local clock of each device can be characterised by the common carrier signal using resources normally available in a microcontroller and thereby synchronised.
- a system controller such as a personal computer containing a USB host controller, receives information from each attached device about the frequency of its free running local clock. The system then provides each of the devices with information to synthesise their own synchronised clocks from the carrier signal and the local free running clock.
- Statistical means may be used to process the information to provide greater synchronisation accuracy. Additional hardware support may be used by each of the devices to increase the resolution and accuracy of their clock synthesis.
- the present invention is not limited in application to the USB or external busses, but may also find application in any general communication bus, such as PCi 1 PCI-e, Ethernet, Firewire. Similarly the present invention can be applied, for example, to wireless or fibre optic communication systems or busses between components on a printed wiring board or integrated silicon chip.
- the plurality of signals comprise a plurality of periodic signals.
- the method includes the first device transmitting the plurality of signals at predefined times (such as at the one second boundary in local universal time).
- the first device may be a master or controller device, wherein the second device is a slave device.
- the method. may also comprise a peer to peer network of devices, such that the first device does not control the second device, but rather merely acts as the synchronisation signal source.
- the method includes the first device transmitting the plurality of signals to the second device in a non-periodic manner, with a time- stamp.
- the time-stamp may be from a time domain of a host system or a master time device.
- the microcontroller may comprise a clock generator, such as a timer/counter.
- the microcontroller is configured to execute an interrupt service routine upon detection of the plurality of signals.
- the microcontroller may be provided in the form of a field programmable gate array logic device or other logic element.
- the microcontroller comprises circuitry to measure the interval between receptions of synchronisation reference signals, such as in the form of a counter/timer (whether hardware, software or otherwise) clocked from said local oscillator.
- the microcontroller comprises circuitry to generate a local clock signal comprising a counter/timer or other clock generation circuitry clocked from the same local oscillator.
- the counter/timer or other clock generation functionality may be contained within a field programmable gate array logic device or other logic element.
- the communication bus may be a serial bus, a parallel bus or other form of communication bus, the first and second devices being of respective types attached to their respective bus.
- the communication bus may be a serial bus in the form of a Universal Serial Bus (USB), a PCI-Express bus, Ethernet, Firewire bus, RS232 or other serial interface bus.
- the communication bus may be a parallel bus in the form of a PCI bus, a. PXI bus, a VME bus, a VXI bus, or a GPIB or other parallel interface bus.
- the communication bus may be located between devices on a wired, optical or wireless bus, a backplane bus for a rack-based instrument, a bus on a printed circuit board or an intra-chip bus.
- the communication bus may comprise a single bus or a plurality of interconnected busses, such as a hybrid interconnected bus comprising a plurality of different but connected busses (such as used in some electronic test equipment).
- the first and (at least one) second devices may be attached to a plurality of different busses and all synchronised.
- USB devices, Ethernet devices and PCI devices may all be synchronised according to this aspect of the invention.
- the second device is one of a plurality of second devices in data communication with the first device via the communication bus, wherein the method comprises: said first device transmitting the plurality of signals to the plurality of other devices; each of the second devices using said plurality of signals to measure the frequency of its respective local oscillator; said first device transmitting a signal to said second devices indicative of a required frequency to be synchronised to; and . said second devices employing their respective microcontrollers to configure themselves to generate respective local clock signals with said required frequency using the frequency of their respective local oscillators.
- the present invention provides an apparatus, comprising: a USB device with a local clock, a microcontroller with counter/timer functionality and an oscillator (such as a free-running local oscillator), wherein the microcontroller is configured to respond to a predefined software interrupt (such as with an interrupt service routine provided therein) by generating an output signal adapted to be used as a synchronization reference signal for substantially all of a plurality of clock carrier signals, said USB device being attachable to a USB host controller; circuitry configured to observe USB traffic, decode from a USB data stream a periodic signal transmitted by said host controller and comprising a clock carrier signal containing information about a distributed clock frequency and phase, and to output a decoded carrier signal; circuitry configured to receive said decoded carrier signal, to generate said predefined software interrupt upon receipt of a predefined data packet (such as a SOF packet) and to pass the software ' interrupt to the microcontroller; circuitry to measure the interval between receptions of said synchonisation reference signals (and
- a method for generating a synchronised local clock on a device attached to a communication bus is provided that is suitable for using an inexpensive free running oscillator and the features available to a standard microcontroller.
- the circuitry to measure the interval between receptions of said synchonisation reference signals is a first counter/timer function clocked from the local oscillator.
- a second counter/timer circuitry is used to generate the synchronised clock signal.
- the frequency of the local oscillator is continually measured with respect to said clock carrier signal and modifications to the configuration of said second counter/timer circuitry are continually made in order to maintain synchronisation of said local clock signal while the local oscillator drifts in frequency.
- the interval used to measure the local oscillator's frequency is the interval between receptions of successive carrier signals.
- the accuracy of measurement of the local oscillator's frequency is increased by measurement over multiple successive intervals and using statistical means.
- the microcontroller is a device containing timer/counter functionality. It will be understood by those skilled in the art that such counter/timers can be replicated externally to a microcontroller in logic devices, for example but not limited to Field Programmable Gate Arrays (FPGA) or Complex Programmable Logic Devices (CPLD).
- FPGA Field Programmable Gate Arrays
- CPLD Complex Programmable Logic Devices
- the microcontroller comprises an interrupt service routine whereby said interrupt service routines can be called or triggered by detection of said carrier signals.
- said interrupt is a hardware interrupt wherein there is minimal late ⁇ cy in generating the required output from Interrupt Service Routine (ISR).
- ISR Interrupt Service Routine
- said second counter/timer circuitry is operable to generate a hardware output signal upon reaching terminal count or timeout wherein there is minimal latency in generating the required output signal.
- calculation of setting for said counter/timer circuitry is made in said USB device.
- calculation of setting for said counter/timer circuitry is alternatively made in said USB host controller.
- the local oscillator may be free-running for economy, but may alternatively be in the form of- ⁇ For example — a Voltage Controlled Crystal Oscillator (VCXO) (especially in phase locked loop (PLL) architectures), a Temperature Compensated Crystal Oscillator (TCXO), a Oven Controlled Crystal Oscillator (OCXO) or a multi-tap clock for increased accuracy.
- VXO Voltage Controlled Crystal Oscillator
- TCXO Temperature Compensated Crystal Oscillator
- OXO Oven Controlled Crystal Oscillator
- multi-tap clock for increased accuracy.
- said counter/timer circuitry may not be clocked directly from the local oscillator but from a clock source divided or multiplied in frequency from the local oscillator.
- the present invention provides a method of synchronising the local clock of a USB device having a microcontroller and a local oscillator (such as a free-running local oscillator) attached to a USB host controller, said microcontroller containing counter/timer functionality, the method comprising: said host controller transmitting a periodic signal to said USB device, wherein said periodic signal constitutes a clock carrier signal; observing USB traffic and decoding from a USB data stream said periodic signal containing information about a distributed clock frequency arid phase and outputHng a decoded carrier signal; receiving said decoded carrier signal, generating a software interrupt upon receipt of a predefined data packet (such as a SOF packet) and passing the software interrupt to the USB microcontroller; said USB microcontroller responding to the software interrupt
- a plurality of USB devices may be synchronised to an arbitrary degree, wherein said method is applied to synchronise a plurality of USB devices attached to a common USB host controller.
- the invention provides a system for synchronising the local clock of a device to a bus derived timebase, comprising: a measurement stage; a prediction stage; and a control stage.
- said measurement stage comprises: a first device having a microcontroller and local oscillator attached to a communication bus, said microcontroller containing a counter/timer clocked by a oscillator; circuitry for monitoring said bus traffic, and circuitry for decoding from said bus a dock carrier signal generated by at least one of at least one second device attached to said bus wherein said carrier signal is a known frequency; and wherein said measurement stage is configured to perform a plurality of measurements of the local time of said counter/timer circuitry upon receipt of a plurality of said carrier signals from said communication bus, each of said measurements corresponding to receipt of each of said plurality of carrier signals.
- the counter/timer circuitry of a typical microcontroller generally has fewer than .16-bits of resolution, and often fewer than 12. This means that the counter/timer will rollover frequently when clocked by a high frequency oscillator.
- the measurement stage is adapted to track the rollover events and convert the plurality of low bit-count timer measurements to a high resolution 64-bit or other representation of time.
- the measurement stage provides an array of measurements of the time of the plurality of carrier signals in the time domains of one or more second devices and 64-bit timer values corresponding to time in the time domain of the first device.
- the carrier signals are periodic but need not be as the result of said measurement method is a map of carrier signal time versus local oscillator time.
- the at least one second device may be a bus controller or host controller device or master bus device.
- the second device may also be a standard device in a peer-to-peer bus architecture.
- the plurality of timing reference signals are periodic signals wherein the period and absolute time of said signals is known in the time domain of the second device.
- the plurality of timing reference signals may also be non- periodic but are each time-stamped in the time domain of the second device.
- the measurement stage is adapted to operate continuously, wherein each of the measurements provides a new measure of the frequency of the oscillator in the second device over the most recent measurement period.
- each of the measurements provides a new measure of the frequency of the oscillator in the second device over the most recent measurement period.
- the communication bus may be a serial bus, parallel bus or other form of communication bus, with the devices being of the type attached to their respective. bus.
- the communication bus may be a Universal Serial Bus (USB), a PCI-Express bus, an Ethernet, a F ⁇ rawire bus, or an RS232 or other serial interface bus.
- USB Universal Serial Bus
- the communication bus may be a PCI bus, a PXI bus, a VME bus, a VXI bus, or a GPIB or other parallel interface bus.
- the communication bus may be between devices on a wired, optical or wireless bus, a backplane bus for a rack-based instrument, a bus on a printed circuit board or even an intra-chip bus.
- the communication bus may be a single bus or a plurality of interconnected busses. It is within the scope of this aspect that a plurality of devices attached to a plurality of different busses may all be synchronised. By way of example (but not limited to) USB devices, Ethernet devices and PCI devices may all be synchronised using this aspect of the invention.
- the measurement stage may be applied to each interconnection of said busses and said devices attached thereto. In this way a map (array of interrelated measurements) of the relative clock rates of each of said attached bus and device would be built up over time.
- the bus is a USB and the first device is a USB host controller
- the carrier signals may comprise any of the USB packet signal structures defined in the USB specification, command sequences sent to said USB device, data sequences sent to the USB device, OUT tokens, IN tokens, ACK tokens, NAK tokens, STALL tokens, PRE tokens, SOF tokens, SETUP tokens, DATAO tokens, DATA1 tokens, or predefined bit pattern sequences in the USB data packets.
- the oscillator is characterised over a period of time with respect to the plurality of timing reference signals.
- the drift iri frequency of said oscillator can be precisely known over extended periods of time with respect to the time domain of said first device.
- the tir ⁇ ebase of said second device is know, then the frequency of said oscillator and hence timebase of said first device can be characterised absolutely.
- a useful disciplining algorithm is known as Kalman filtering in which the state of a generic system can be estimated from a series of measurements which contain random error (such as the discretisation errors in determination of said oscillator frequency). Using this approach the oscillator can be characterised over very long periods and with a high degree of accuracy, leading to accurate predictions of future frequency drift.
- Preferably said prediction stage reads a data set corresponding to a plurality of time-stamped measurements in a plurality of time domains; determines a relationship between the plurality of time domains; and extrapolates said relationship forward in time.
- the data set comprises the measurements.
- the prediction stage employs statistical calculation to Improve the accuracy of determining the relationship.
- the extrapolation comprises linear, polynomial or exponential extrapolation or a predictive approach based on Kalman filtering or similar statistical techniques.
- Calculations performed by the prediction stage may be performed by the first device, in one of the at least one second devices or in another device in communication with first and second devices.
- the output of the prediction stage is a map of the plurality of time domains. This provides an estimate of the local time in each time domain at all times.
- the data set may correspond to a plurality of interconnected busses. It is within the scope of this aspect that a plurality of devices attached to a plurality of different busses may all be synchronised. By way of example (but not limited to) USB devices, Ethernet devices and PCI devices may all be synchronised using this aspect of the invention.
- mapping and prediction of time applies to each of said plurality of busses and devices - across the breadth of said hybrid interconnected bus.
- control stage is adapted to: receive data indicative of a current time (t1) of said counter/timer of said first device from said measurement or prediction stage; select a point in time (t2) at which a future event is to be generated; control an output signal with a second counter/timer resource such that the output signal is generated at said time (t2) of said future event; calculate the number of ticks ⁇ or "tick count") of said second counter/timer required to generate said output signal at time t2 upon reaching a terminal count event in the case of a counter function or a timeout event in the case of a timer function; configure said second counter/timer circuitry with said tick count to generate an output signal upon reaching said terminal count event in the case of a counter function or said timeout event in the case of a timer function; wherein said second counter/timer is clocked by said oscillator
- the control stage may be adapted to generate a local clock signal. According to this embodiment, the control stage is adapted to: generate an output signal at time t1 ; generate an output signal at time t2 by loading said second count ⁇ r/timer with a new tick count; and reset said second counter/timer with said tick count configuration SUGh that a next timeout or terminal count occurs at time t2 + ( t2 - 11 ).
- the measurement and prediction stages are also continuously employed so that drift in the frequency of the oscillator is measured and the predictive stage provides updated values of the tick count to maintain synchranicity of the local clock signal with reference clock of the second device.
- control stage is able to synthesise the local clock signal up to arbitrarily high frequencies given a sufficiently high operating frequency of the oscillator.
- the frequency of the oscillator is substantially higher than the frequency of the periodic carrier signals. This allows high resolution in determination of said interval between said periodic carrier signals. Similarly, in the case of a non periodic but time-stamped carrier signal the period (inverse of frequency) of said oscillator is substantially smaller than said interval between receptions of carrier signals.
- the frequency of the local clock signal is substantially lower than the frequency of the oscillator to allow a high resolution in controlling the local clock frequency. Additionally it is unlikely that the local clock period (i.e. the inverse of frequency) will be an exact multiple of the period of the oscillator, particularly as the local clock is controlled to some external frequency reference and said oscillator is expected to drift in frequency. In this case there will be some jitter in the period of the local clock of at least one oscillator period. ' •
- various methods may be employed in order to provide finer control of the final synchronised clock signal.
- said method of controlling the final output frequency of said local clock may involve adjustments to the rate at which said timer/counter is clocked.
- judicious choice of said 'tick count' during consecutive cycles of said local clock signal may be used to reduce the effects of clock frequency noise as frequency tuning occurs. For example, if an adjustment is required to be made to the local clock signal to account for drift in said local oscillator (which may be free- running) it is preferable, to slowly adjust the local clock rate over a period of several cycles rather than use a step change.
- Such a method can significantly influence the frequency spectrum of the clock noise and potentially spread such control-loop noise over a wide frequency band (at low amplitude) rather that generate a large amplitude narrow frequency component into the noise spectrum.
- Other similar methods and applications of such methods will be readily apparent to those skilled in the art.
- control stage can then adjust how it manages the digital adjustment of phase (configuration of subsequent counter/timer periods) over the next interval while said system it is waiting for a updated synchronisation information.
- the local oscillator is preferably a free-running local oscillator, but it will be understood by those skilled in the art that Voltage Controlled Crystal Oscillators (VCXO) (especially in a phase locked loop (PLL) architectures), Temperature Compensated Crystal Oscillators (TCXO), Oven Controlled Crystal Oscillators (OCXO) multi-tap clocks or other more accurate clock sources could also be used instead of a free-running local oscillator for increased accuracy.
- VXO Voltage Controlled Crystal Oscillators
- TCXO Temperature Compensated Crystal Oscillators
- OXO Oven Controlled Crystal Oscillators
- the counter/timer circuitry may be clocked, not directly from the local oscillator, but from a clock source either divided down or multiplied up frequency from the local oscillator.
- a phase adjustment may be made to the local oscillator signal before being used to clock the counter/timer circuitry in order to increase the resolution of event generation.
- the synchronised local clock signal can then be used to generate a plurality of output signals and/or accurately timestamp external events or signals.
- the communication bus can be a single bus or a plurality of inter-connected busses. It is within the scope of this aspect that a plurality of devices attached to a plurality of different busses may all be synchronised. By way of example (but not limited to) USB devices, Ethernet devices and PCI devices may all be synchronised using this aspect of the invention.
- control stage is preferably applied to each interconnection of busses and devices attached thereto.
- the present invention provides a method of synchronising data acquired by a plurality of devices attached to a communication bus, the method comprising: determining a mapping between the unsynchronised time domains of said plurality of devices using any of the methods taught in this disclosure; time stamping data acquired in the time domain of each respective device; transmitting said time stamped data to a central location; and time aligning said data from said plurality of devices.
- a plurality of USB devices attached to a USB each contain a free-running local oscillator, said respective free running local oscillators being used to control the acquisition of data at each of said respective USB devices.
- Said plurality of USB devices have their time domains mapped to the time domain of a USB host controller via the methods disclosed here. Data acquired by each of said USB devices is then, time aligned in the host PC by the time stamps associated with each acquisition point.
- the present invention provides a method for improving the accuracy of local clock phase synchronisation, the method comprising: syntonising a local clock of a device attached to a communication bus; decoding bus traffic of said communication bus for a predefined periodic carrier signal; determining a phase of a local clock signal of said local clock at the instant of reception of each of said periodic carrier signals; determining with statistical methods a true phase of said local clock signal with respect to said periodic carrier signals; and adjusting the phase of said local clock such that said local clock is synchronised.
- syntonising the local clock adapts the frequency of the local clock to be locked to the periodic clock carrier signal. In this way there is an integral number of clock cycles between reception of successive periodic carrier signals, simplifying the method of statistically determining local clock phase.
- the communication bus may be a serial bus, a parallel bus or any other form of communication bus, the devices being of the type attached to their respective bus.
- the communication bus may be a Universal Serial Bus (USB), a PCI-E ⁇ xpress bus, an Ethernet, a Firewire bus, or an RS232 or other serial interface bus.
- USB Universal Serial Bus
- the communication bus may be a PCI bus, a PXI bus, a VME bus, a VXI bus, or a GPIB or other parallel interface bus.
- the communication bus may be between devices on a wired, optical or wireless bus, a backplane bus for a rack-based instrument, a bus on a printed circuit board or even an intra-chip bus.
- the communication bus may be a single bus or a plurality of inter-connected busses. It is within the scope of this aspect that a plurality of devices attached to a plurality of different busses may all be synchronised. By way of example (but not limited to) USB devices, Ethernet devices and PCI devices may all be synchronised using this aspect of the invention.
- the communication bus is a USB and the carrier signals comprise any of the USB packet signal structures defined in the USB specification, command sequences sent to said USB device, data sequences sent to the USB device, OUT tokens, IN tokens, ACK tokens, NAK tokens, STALL tokens, PRE tokens, SOF tokens, SETUP tokens, DATAO tokens, DATA1 tokens, or predefined bit pattern sequences in the USB data packets.
- a method for improving the accuracy of synchronising the local clock of a plurality of devices attached to a communication bus comprising: the method of the fourth aspect described above applied to a plurality of devices attached to a communication bus.
- the communication bus may be a serial bus, parallel bus or other form of communication bus and the devices being of the type attached to their respective bus.
- the invention provides a method for synchronisation of a plurality of devices attached to a bus with respect to an externally provided reference signal.
- the local clocks of each of said plurality of devices are characterised over a period of time with respect to a periodic signal (carrier signal) of either the host controller or one of the devices on the bus by any of the methods taught in this disclosure.
- An external reference signal provided to at least one of said attached devices is also characterised with respect to said periodic signal structure. Information about said external reference signal is sent to each of said devices. The devices are then able to synthesise their local synchronous clocks in frequency and phase with said external signal.
- a method of synchronising a plurality of devices attached to a communication bus to an external signal provided to at least one of said devices comprising: using the measurement and prediction methods of the third aspect of the present invention to characterise the free-running oscillators of said plurality of devices; using the measurement and prediction methods of the third aspect of the present invention to characterise an external signal provided to at least one of said plurality of devices; and using the control method of the third aspect of the present invention to generate a synchronised local clock for each of said plurality of devices ; wherein said local clocks are each synchronised to the timebase of said external signal.
- a reference clock signal can be provided to one of a plurality of devices attached to the described bus and each of said attached devices can synthesise their local clocks to said external reference signal.
- the external reference signal can be a clock signal derived from (but not limited to) atomic reference clocks, the Global Positioning System (GPS), synchronised Ethernet protocols such as IEEE-1588, instrumentation chassis such as PXI, PXI-e, cPCI, VXI, VME or any other clock source.
- GPS Global Positioning System
- instrumentation chassis such as PXI, PXI-e, cPCI, VXI, VME or any other clock source.
- the USB host controller transmits a plurality of clock carrier signals to said first USB device.
- the carrier signals may be the periodic Start of Frame (SOF) signals.
- the carrier signals may alternatively be non-periodic signals that have been time stamped in the time domain of the USB host controller.
- the GPS clock is therefore characterised with respect to the carrier signals.
- An alternative way to view this scenario is that the carrier signals and hence the time domain of the USB host controller is characterised according to the GPS clock.
- a local oscillator of a second USB device attached to the USB can be characterised with respect to the carrier signals.
- Both the first and second USB devices may be characterised using the same carrier signals, as would be the case with a broadcast carrier signal.
- the first and second USB devices may be characterised using different sets of carrier signals, as long as both sets of carrier signals originate from the same time domain, namely the USB host controller.
- the time domain of the second USB device can therefore be mapped and synchronised to the GPS time domain as follows: i) the GPS time domain is mapped to the USB host controller time domain via the carrier signals; and ii) the time domain of the second USB device is mapped to the USB host controller time domain via the carrier signals.
- the time domain of the second USB device may be mapped to a third device by a similar exchange of carrier signals in their respective time domains.
- the third device need not be a USB device: it may be any device capable of communicating carrier and possibly time stamp information with the second device.
- the third device may be a PCI bus, a PCI-Express bus, an Ethernet, a Fir ⁇ wire bus, a PCI-Express bus, an RS232 bus, a VME bus, a VXI bus, a GPIB or other serial or parallel interface bus.
- the communication busses may be located between devices on a wired, optical or wireless bus, a backplane bus for a rack-based instrument, a bus on a printed circuit board or an intra-chip bus.
- This method of time domain mapping does not rely on an extremely accurate clock source for the carrier signal. Since it employs a mapping between time domains (which may even be non-periodic in nature provided they contain timestampsj, devices may be synchronised to one another and, if desired, to an absolute time to a high degree regardless of the quality of the carrier signal information.
- the present invention provides a method of synchronising a plurality of devices attached to a plurality of inter-connected busses wherein the busses contain a variety of different types (including but not limited to USB, Ethernet and PCI), the method comprising: the method of the first aspect applied between each of said plurality of devices (and bus controllers as appropriate) attached to said plurality of busses; the prediction method of said third aspect applied to each of said plurality of devices (and bus controllers as appropriate) attached to said plurality of busses; wherein said mapping comprises the interrelationship between timebases for each of said devices attached to each of said plurality of busses; and a control stage (such as that of the third aspect) to generate a synchronised local clock for each of said plurality of devices attached to each of said plurality of busses.
- the plurality of busses contain different bus types and/or the same bus types.
- this aspect applies equally well to a network comprising a USB, a PCI and two Ethernet busses or comprising a plurality of
- control system comprises the control method of the third aspect of the present invention. It should be understood however that any means for generating a local clock signal synchronised to said mapping generated by said prediction system is equally applicable. . •
- the busses may be simply connected, that is with only one connection path between any two nodes, or multiply-connected wherein a plurality of connection paths exists between any two nodes.
- This broad aspect comprises a network of busses and devices where multiple cross measurements between timebases are made in order to build said interrelationships.
- a local oscillator's notion of time is referred to a carrier signal on a communication bus.
- Said carrier signal does . not necessarily correspond to an absolute notion of time, but it is understood by those skilled in the art that any appropriate time reference may be chosen from a system comprising several independent notions of time.
- said carrier signal may be tied to some traceable frequency standard.
- a given local oscillator may be chosen as the absolute time reference for a system (with said carrier signal calibrated against said reference) and choice of time frame ultimately comes down to the specific system.
- any of the aspects of the present invention may be combined with measurement and compensation of signal propagation delays in the interconnections. This can be achieved using the methods of Foster et. al. (US Patent Application No. 10/620,769) or any other compensation scheme including for example the methods of IEEE-1588.
- apparatuses and systems according to the invention can be embodied in various ways.
- such devices could be constructed in the form of multiple components on a printed circuit or printed wiring board, on a ceramic substrate or at the semiconductor level, that is, as a single silicon (or other semiconductor material) chip.
- systems according to the present invention may be embodied as a plurality of components that function as a coordinated system or as a single functional unit, as would be readily appreciated by those skilled in the art.
- the present invention provides a method of synchronising a first device and at least one second device, the first device having a local oscillator and the second device being in data communication with the first device via a communication bus, the method comprising: the first device transmitting a plurality of carrier signals to the second device indicative of the time domain of the first device; the second device using the plurality of carrier signals to measure the frequency of its local oscillator; the first device transmitting a signal to the second device indicative of a required frequency to be synchronised to; and the second device generating a local clock signal that is syntonised to the time domain of the first device.
- the first and second devices are USB devices and the communication bus is a USB.
- one of the first and second devices is a USB device and another of the first and second devices is a USB Host Controller.
- the plurality of carrier signals may be periodic.
- the plurality of carrier signals may be non-periodic, and transmitted at known times.
- the method may include transmitting the respective known times to the second device.
- the method may include transmitting the respective known times to the second device in the same data packet as the carrier signals.
- the method may include transmitting the plurality of carrier signals near USB Start of Frame boundaries.
- the method may include transmitting the plurality of carrier signals near one second boundaries of Coordinated Universal Time (UTC).
- UTC Coordinated Universal Time
- the method may include transmitting the plurality of carrier signals near one second boundaries of the Global Positioning System (GPS) time.
- GPS Global Positioning System
- the method may include generating the local clock signal by a phase locked loop (PLL) architecture.
- PLL phase locked loop
- the local oscillator may be free running.
- the method may include generating the local clock signal with a programmable counter/timer comprising a programmable prescaler and a programmable counter function, wherein the counter/timer is clocked from the local oscillator.
- the method may include generating the local clock signal with a programmable counter/timer.
- the programmable counter/timer may comprises a programmable prescaler, a programmable counter function and a mechanism for shifting the phase of the input local oscillator, the counter/timer being clocked from the local oscillator.
- the counter/timer may be, for example, part of a microcontroller, part of a field programmable gate array device, part of a programmable logic device or part of a compound semiconductor device.
- the communication bus may be, for example, a Peripheral Component Interconnect (PCI) bus, a PCI-Express bus, an Ethernet bus, a Firewire bus, or a wireless bus.
- PCI Peripheral Component Interconnect
- PCI-Express Peripheral Component Interconnect
- Ethernet Ethernet
- Firewire Firewire
- wireless bus wireless bus
- the plurality of carrier signals may be periodic, and the method include generating the local clock signal by a voltage controlled crystal oscillator (VCXO) or phase locked loop (PLL) architecture.
- VXO voltage controlled crystal oscillator
- PLL phase locked loop
- the invention provides an apparatus, comprising: a USB device with a local oscillator, a microcontroller and a counter/timer (such as in the form of counter/timer circuitry), wherein the USB device is configured to respond to substantially all of a plurality of bus derived time-stamped clock carrier signals; circuitry configured to observe USB traffic, decode from a USB data stream a signal transmitted by a USB host controller and comprising a clock carrier signal containing information about a distributed clock frequency and phase, and to output a decoded carrier signal; a first counter/timer (such as in the form of counter/timer circuitry) configured to measure the interval between receptions of the clock carrier signals in the time domain of the local oscillator, the measurement providing information about the frequency of the local oscillator with respect to the known carrier signal frequency; wherein the apparatus is adapted to respond to a message from the USB host controller containing information about a required synchronisation frequency by calculating a setting for a second cou ⁇ iter/t ⁇ mer (
- the invention provides a method of synchronising the local clock of a USB device attached to a USB host controller comprising: the host controller transmitting a plurality of signals to the USB device, wherein the plurality of signals constitute a clock carrier signal of known time in the time domain of the USB host controller; observing USB traffic by the USB device and decoding from the traffic the plurality of signals containing information about a distributed clock frequency and phase and outputting a decoded carrier signal; measuring the interval between receptions of the decoded carrier signals in the time domain of the local clock, to provide information about the time domain of the USB host controller; determining the phase of the local clock with respect to the plurality of decoded carrier signals; the USB host controller transmitting the respective known times of substantially all ⁇ f the clock carrier signals to the USB device; the USB host controller transmitting a message to the USB device indicative of the required synchronisation frequency and phase; and controlling the frequency and phase of the local clock so that the local clock is syntonised and in phase with the notion of time of the USB
- the plurality of signals may be periodic.
- the periodic signals may be USB Start of Frame (SOF) signals.
- SOF USB Start of Frame
- the method may include transmitting the respective known times to the USB device in the same data packet as the plurality of signals.
- the method may include transmitting the plurality of carrier signals near one second boundaries of Coordinated Universal Time (UTC) or near one second boundaries of the Global Positioning System (GPS) time.
- UTC Coordinated Universal Time
- GPS Global Positioning System
- the local clock may comprise a phase locked loop (PLL) architecture or voltage controller crystal oscillator (VCXO).
- PLL phase locked loop
- VCXO voltage controller crystal oscillator
- the method may include generating the local clock by, for example, a field programmable gate array device or a programmable logic device.
- the counter/timer may comprise, for example, a programmable prescaler and a programmable counter function, the counter/timer being clocked from the local oscillator.
- the programmable counter/timer may further comprise a mechanism for shifting the phase of the input local oscillator.
- the counter/timer may be part of a microcontroller.
- the invention provides a method of synchronising a local clock of a USB device with the time domain of a USB Host controller attached thereto, the USB device having a local oscillator and containing counter/timer functionality, the method comprising: the host controller transmitting a plurality of signals to the USB device, wherein the plurality of signals constitutes a clock carrier signal of known frequency in the time domain of the USB host controller; observing USB traffic with the USB device and decoding from the
- USB traffic the plurality of signals containing information about a distributed clock frequency and phase and generating a decoded carrier signal therefrom; measuring the interval between receptions of the decoded carrier signals with a first counter/timer function in the time domain of the local oscillator, and determining from the interval the frequency of the local oscillator with respect to the known carrier signal interval; determining the phase of the local oscillator with respect to the plurality of decoded carrier signals; the USB host controller transmitting a message to the USB device, the message containing information about the required local clock frequency; calculating a setting for a second counter/timer function using the required local clock frequency and phase, and the frequency and phase of the local oscillator; configuring the second counter/timer function to generate a local clock transition signal at a predetermined time in the time domain of the USB device; wherein the second counter/timer function is clocked by the local oscillator; and the local clock transition signal toggles the local clock output.
- the local oscillator may be free-running.
- the method may include transmitting the known times of the respective plurality of signals to the USB device in the same data packet as the plurality signals.
- a time series of readings from the first timer/counter contains information about the phase of the local oscillator at the time of receipt of each of the decoded carrier signals-
- Configuring the second timer/counter may comprise setting a starting value that represents a number of the local oscillator cycles before the next required local clock transition.
- the method may include generating the local clock transition signal upon the second timer/counter reaching terminal count in the case of a counter function.
- the method may include generating the local clock transition signal upon the second timer/counter reaching a timeout condition in the case of a timer function.
- the method may include repetitively making the measurement of local oscillator frequency and phase.
- the method may include statistically analyzing the repetitive measurements of local oscillator frequency and phase and increasing the accuracy of the measurements thereby.
- the method may include continually updating the configuration of the second . counter/timer to maintain synchronisation of the local clock signal.
- the first counter/timer function may be contained within, for example, a microcontroller, a field programmable gate array device or a programmable logic device.
- the method may include reading the first counter/timer then resetting the first counter/timer on receipt of the decoded carrier signals.
- the plurality of signals may be periodic.
- the plurality of signals may be USB Start of Frame (SOF) signals.
- SOF USB Start of Frame
- the plurality of signals may be non-periodic, and the method include generating the signals at known times in the time domain of the USB Host controller.
- the method may include transmitting the plurality of signals near USB Start of Frame (SOF) signals.
- SOF Start of Frame
- the method may include transmitting the plurality of carrier signals near one second boundaries of Coordinated Universal Time (UTC) or near one second boundaries of the Global Positioning System (GPS) time.
- UTC Coordinated Universal Time
- GPS Global Positioning System
- the invention provides a method of determining the frequency and phase of a local oscillator of a device having a local oscillator and attached to a communication bus, the method comprising: the device monitoring bus traffic of the communication bus and decoding from the bus traffic a plurality of time carrier signal generated by at least one of a plurality of other devices attached to the bus; the device measuring the interval between receptions of the decoded carrier signals in the time domain of the local oscillator, to provide information about the frequency of the local oscillator with respect to the known carrier signal interval; and determining the phase of the local oscillator with respect to the plurality of decoded carrier signals;
- the plurality of carrier signals may be time-stamped in the time domain of the respective second device.
- the plurality of carrier signals may be not periodic.
- the plurality of intervals between reception of the time-stamped carrier signals may provide a plurality of measurements of the local oscillator frequency in the time domain of the respective other devices.
- a time series of the intervals is indicative the phase of the local oscillator at the time of receipt of each of the decoded carrier signals.
- a time series of the intervals is indicative of the evolution of time according to the local oscillator in the time domain of the respective other devices.
- the method may further comprise statistically analyzing the plurality of the measurements in the time domain of the respective other devices to improve the accuracy of the determination of the local oscillator frequency.
- Measuring the interval between receptions of the decoded carrier signals in the time domain of the local oscillator may comprise counting the number of transitions of the local oscillator within a window gated by receptions of the time-stamped carrier signals.
- one of the other devices is a bus master device.
- the other devices may be peer devices.
- the invention provides a method of predicting the time of a first free-running clock at some future time in the time domain of at least one of a plurality of second clocks, comprising: reading a data set containing a plurality of measurements of the local time of the first clock in the time domain of at least one of the plurality of second clocks; computing a relationship between the time domain of the first clock and each of the plurality of second time domains; extrapolating a relationship forward in time between the time domain of the first clock and at least one of the plurality of the second time domains; and determining a local time of the first clock based at some future time, based on the relationship between the plurality of time domains.
- the method may include improving the determining of the local time of the first clock with statistical analysis of the plurality of relationships between the plurality of time domains.
- the extrapolation may comprise, for example, a linear, polynomial, exponential extrapolation technique or combinations thereof, or a Kalman or G-H filtering technique.
- the invention provides a method of predicting the time of a plurality of free-running clocks at some future time in the time domain of at least one of a plurality of reference clocks, comprising: reading a data set containing a plurality of measurements of the local time of the plurality of free-running clocks in the time domain of at least one of the plurality of reference clocks; computing a relationship between the time domain of each of the free-running clocks and each of the plurality of reference time domains; extrapolating a relationship forward in time between the time domain of each of the free-running clocks and at least one of the plurality of the reference time domains; and determining a local time of each of the free-running clocks at some future time, based on the plurality of the relationships between the plurality of time domains.
- the method may include improving the determining of the local time of the free- running clocks by statistical analysis of the plurality of relationships between the plurality of time domains.
- the extrapolation may comprise, for example, a linear, polynomial, exponential extrapolation technique or combinations thereof, or a Kalman or G-H filtering technique.
- the invention provides a method of controlling an event timed from a local oscillator, comprising: receiving data indicative of a first time at which the event is to be generated in the time domain of the local oscillator; generating a clock signal from the local oscillator; resetting and configuring a counter/timer function with data indicative of the interval between the present time and the first time; generating the event upon reaching a terminal count in the case of a counter function or a timeout in the case of a timer function; clocking the counter/timer by the local oscillator.
- the clock signal may be at the same frequency as and in phase with the local oscillator.
- the clock signal may be a multiple of the frequency of and in phase with the local oscillator, wherein the clock signal provides greater clocking resolution than the local oscillator.
- the local oscillator is free-running.
- the local oscillator is a voltage controlled crystal oscillator (VCXO) or phase locked loop (PLL) and is locked to a required frequency.
- VXO voltage controlled crystal oscillator
- PLL phase locked loop
- the invention provides a method of generating a local clock signal from a local oscillator, comprising: i) receiving data indicative of a first time at which a transition of the local clock is to be generated in the time domain of the local oscillator; ii) generating a clock signal from the local oscillator; iii) resetting and configuring a counter/timer function with data indicative of the interval between the present time and the first time; iv) generating the transition of the local clock upon reaching a terminal count event in the case of a counter function or a timeout event in the case of a timer function; v) clocking the counter/timer by the local clock; and vi) repeating steps i) to v) upon generation of the transition of the local clock one or more times.
- the clock signal may be at the same frequency as and in phase with the local oscillator.
- the clock signal may be a multiple of the frequency of and in phase with the local oscillator, wherein the clock signal provides greater clocking resolution than the local oscillator.
- the local oscillator may be free-running.
- the local oscillator is a voltage controlled crystal oscillator (VCXO) or phase locked loop (PLL) and is locked to a required frequency.
- VXO voltage controlled crystal oscillator
- PLL phase locked loop
- the method may include adjusting or dithering the configuration of the counter timer between several settings in order to provide finer control of the frequency and phase of the local clock signal.
- the invention provides a method of synchronising data acquired by a plurality of unsynchronised devices attached to a common communication bus, comprising: determining a mapping between unsynchronised time domains of the plurality of devices, comprising: determining the frequency and phase of a local oscillator of each of the devices according to the method described above; and predicting the time of the local oscillator at some future time in.the time domain of at least one of a plurality of second local oscillators according to the method described above; time stamping the data acquired in the time domain of each respective device; transmitting the time stamped data to a central location; and time aligning the data from, the plurality of devices in a common time domain.
- the invention provides a method of synchronising data acquired by a plurality of unsynchronised USB devices attached to a USB, each having a free-running local oscillator, the method comprising: the plurality of USB devices monitoring the USB traffic and decoding from the USB a plurality of time carrier signals generated by a USB host controller; the plurality of USB devices measuring the interval between receptions of the decoded carrier signals in the time domain of the local oscillator, to provide information about the frequency of the local oscillator with respect to the known carrier signal interval; and determining the phase of the local oscillator of each of the respective USB devices with respect to the plurality of decoded carrier signals; the plurality of USB devices acquiring data wherein data acquisition is clocked by the respective free-running local oscillators; time stamping the data acquired in the time domain of each respective USB device; transmitting the time stamped data to a central location; and time aligning the data from the plurality of devices in a common time domain.
- the invention provides a system for synchronising the local oscillator of one or more devices to a bus derived timebase, comprising: a measurement stage adapted to characterise the local oscillators with respect to the bus derived timebase; a prediction stage adapted to determine the evolution of time in each of the local oscillators; and a control stage adapted to generate a synchronous clock signal local to each of the respective devices from the respective local oscillators.
- the measurement stage is adapted to perform the method of determining the frequency and phase of a local oscillator of a device described above;
- the prediction stage is adapted to perform the method of predicting the time of a first free-running clock at some future time described above;
- the control stage is adapted to perform the method of controlling an event timed from a local oscillator described above.
- the prediction stage may comprise a centrally located computing mechanism and the system adapted to transmit data indicative of the first time to each of the devices.
- a plurality of the computing mechanisms are located within each of the respective devices, with data indicative of the first time being calculated locally to each of the devices.
- the invention provides a method of synchro ⁇ ising a plurality of devices, each having a local oscillator, connected via a communication bus comprising: designating a first or master timing device chosen from the plurality of devices; the master timing device transmitting a plurality of clock carrier signals to each of a plurality of second devices; each of the plurality of second devices determining the frequency and phase of their respective local oscillators with respect to the time domain of the master timing device according to the method of determining the frequency and phase of a local oscillator of a device described above; predicting the evolution of time in each of the plurality of other devices in the time domain of the master timing device according to the method of predicting the time of a first free-running clock at some future time described above; and synchronising a local clock of each of the plurality of devices with the notion of time of the master timing device according to the method of controlling an event timed from a local oscillator described above.
- the method may include centrally calculating data indicative of the first time and transmitted the data to each of the devices.
- the method includes calculating data indicative of the first time locally to each of the devices.
- the clock carrier signals may be periodic.
- the clock carrier signals are non periodic, and are time- stamped or transmitted at known times in the time domain of the master timing device.
- the invention provides a method of synchronising a plurality of devices, each having a local oscillator, connected via a plurality of interconnected communication busses comprising: designating a master timing device for each bus interconnection, chosen from the plurality of devices; the plurality of master timing devices transmitting a plurality of clock carrier signals to each of the plurality of other devices; each of the plurality of other devices determining the frequency and phase of their respective local oscillators with respect to the time domain of the master timing device according to the method of determining the frequency and phase of a local oscillator of a device described above; and predicting the evolution of time in each of the plurality of other devices in the time domain of the master timing device according to the method of predicting the time of a first free-running clock at some future time described above; and synchronising the local clock of each of the plurality of devices with the notion of time of the master timing device according to the method of controlling an event timed from a local oscillator described above.
- the evolution of time in each of the plurality of devices across a plurality of interconnected communication busses may be known to arbitrary precision, and the accuracy of dock carrier signal frequency known to a lesser degree. ' .
- Figure 1 is a schematic diagram of a synchronised USB device according to a first broad aspect of the present invention
- Figure 2 is a schematic representation of a microcontroller as used in a first broad aspect of the present invention
- Figure 3 is a schematic representation of the internal resources and architecture of the microcontroller of figure 2;
- Figure 4 is a schematic representation of a synchronised USB according to a second embodiment of the present invention.
- FIG. 5 is a schematic representation of a USB synchronised to a GPS time server according to a third embodiment of the present invention.
- Figure 6 ts a schematic representation of a network of synchronised devices synchronised across a PCI bus according to a fourth embodiment of the present invention
- Figure 7 is a schematic representation of a hybrid network of synchronised interconnected busses according to a fifth embodiment of the present invention.
- Figure 8 is a schematic representation of carrier and synchronisation signals for a syntonised system.
- USB device 10 includes a bus connector 14, for connection to USB 12, a USB interface/microcontroller 16, digital input/output circuitry 18 (in the form, for example, of a digital transducer such as an analogue to digital converter, pressure transducer or strain gauge) and a free-running oscillator 20.
- Oscillator 20 provides a clock signal 22 for USB interface/microcontroller 16.
- USB interface/microcontroller 16 has a data bus 26 which controls digital input/output circuitry 18.
- USB interface/microcontroller 16 is configured to compare clock signal 22 with a clock carrier signal decoded internally from USB traffic 24.
- the frequency of an oscillator is measured in cycles per second. Oscillators are often used as clocks and each cycle of an oscillator can be considered a single "tick" of the clock. Time may therefore be measured in terms of the number of ticks of an oscillator. This provides a local notion of time, so the oscillator may also be referenced to some absolute (or more authoritative) notion of time, if available. In this way, the carrier signal decoded from USB traffic 24 provides another tim ⁇ base for comparison. If this carrier signal contains a more accurate notion of absolute time (or even a chosen appropriate timebase for the given system) then local oscillator 20 may be calibrated against that carrier signal.
- USB 1 clock signal 22 of local free-running oscillator 20 is referred to the Start of Frame (SOF) packet carrier signal.
- SOF Start of Frame
- SOF packets are numbered with a 12-bit number that rolls over at 2048.
- the operating system of the host controller it is possible for the operating system of the host controller to maintain a larger bit-count number as its time reference. This is desirable for maintaining a significant USB host controller timebase that can then be compared to other interconnected busses if required.
- USB interface/microcontroller 16 includes a USB Physical Layer Transceiver (Phy) 32 and conventional microcontroller 34.
- Phy 32 receives USB traffic through USB interface port 36.
- Microcontroller 34 has a plurality of output ports (represented collectively at 38), a clock source input port 40 and a dedicated synchronised clock generation output 42; synchronised clock generation output 42 may in fact be a dedicated one of the plurality of output ports 38.
- USB Phy 32 is connected to microcontroller 34 via a data bus 44 and via an additional hardware interrupt signal connection 46.
- Hardware interrupt signal connection 46 allows USB Phy 32 to inform microcontroller 34 of the receipt of a nominated carrier signal from the USB traffic.
- FIG. 3 is a schematic representation of microcontroller 34 of USB interface/microcontroller 16.
- Microcontroller 34 has an input 52 for data bus 44 of figure 2, SOF interrupt input port 54, a plurality of output ports (represented collectively at 56, and connected to or integral with output ports 38 of USB interface/microcontroller 16), a clock source input port 58 and a dedicated synchronised clock generation output 60 (connected to or integral with clock source input port 40 and a dedicated synchronised clock generation output 42 of USB interface/microcontroller 16).
- Microcontroller 34 also contains a processing core 62 (which typically contains memory and'other functionality) and first and second counter/timers 64a and 64b.
- First counter/timer 64a is adapted to measure the local oscillator time (or frequency) with respect to the SOF carrier signal 66.
- Second counter/timer 64b is clocked by local clock signal 22 from clock source input port 58.
- SOF carrier signal 66 is used to gate first counter/timer 64a so that second counter/timer 64b counts ticks (or times the period) of local clock signal 22 in the period between receptions of successive SOF carrier signals 66.
- a measurement result 68 of first counter/timer 64a comprising a digital representation of time (counts) in the period defined by successive SOF receptions, is transmitted by first counter/timer 64a to processing core 62, and processing core 62 determines time in the time domain of USB device 10 from this measurement result 68.
- USB microcontrollers can be configured to execute a software interrupt on reception of the Start of Frame (SOF) packet in the USB data stream.
- SOF Start of Frame
- an interrupt service routine provided in microcontroller 34 is executed in response to receipt of the SOF packet, and is configured to generate a reference timing signal (at either 1 kHz for USB Full Speed or 8 kHz for USB High Speed), which is used to gate first counter/timer 64a.
- a plurality of such measurement results 68 of local clock time (or frequency/period) are conducted, and processing core 62 applies statistical techniques to these results 68 to determine a final result of increased accuracy.
- This periodic determination of the local clock time is described in the third broad aspect of the present invention as the measurement method.
- USB device 10 determines how second counter/timer 64b should be configured to maintain time synchronisation with the time domain of the USB 12.
- the values that are loaded to counter/timer 64b are based on the notions of time of each time domain - in this case, the SOF time domain (Host Controller) and that of local oscillator 20 (of USB device 10).
- Second counter/timer 64b is operated according to the control method of the third broad aspect of the present invention described above.
- second counter/timer 64b is clocked from local clock signal 22, so is in the time domain of local oscillator 20.
- Microcontroller processing core 62 periodically pre- configures counter/timer 64b with a value 70.
- Second counter/timer 64b may either be operating in timer mode or counter mode with appropriate control signals sent from processing core 62.
- a hardware signal 72 is generated on synchronised clock generation port 60. This hardware signal 72 can be used to toggle a clock pin or other function of microcontroller 34.
- Synchronised USB 80 comprises a USB host controller 82 and a plurality of USB devices 84, 86 and 88 (each with the features of USB device 10 of figure 1).
- USB devices 84, 86, 88 each has a free-running oscillator or clock 90, 92, 94, respectively.
- USB host controller 82 has, and is driven by > a local clock 96, and generates periodic SOF packets which it broadcasts to USB devices 84, 86, 88.
- USB devices 84, 86, 88 each generates a synchronised local clock according to the method described above in the first embodiment.
- USB device 84 measures the rate of its internal oscillator 90 versus the timebase of clock 96 of USB host controller 82 (timed by periodic SOF packet reception) across USB connection 98.
- USB devices 86 and 88 measure their local clock rates using the same broadcast SOF packets from USB host controller 82.
- the measurement method of the third broad aspect of the present invention therefore provides an array of data comprising the local time (of respective oscillators 90, 92, 94) at each USB device 84, 86, 88 corresponding to the receipt of this periodic SOF carrier signal (i.e. the timebase of the USB host controller 82).
- each of USB devices 84, 86, 88 is configured such that a counter/timer function on each of USB devices 84, 86, 88 synchronously outputs a clock signal when clocked from its respective free-running oscillator 90, 92, 94.
- the frequency stability of local oscillators 90, 92, 94 determines how often the measurement, prediction and control loop should be performed. If local oscillators 90, 92, 94 are provided in the form of standard crystal oscillator chips operating at 48 MHz with a frequency tolerance of 100 parts per million (ppm), and if it is assumed that the periodic carrier signal corresponds to USB SOF packet tokens occurring at exactly the ideal 125 ⁇ s intervals, then in each 125 ⁇ s interval there will be 6000 ticks of the 48 MHz clock. If the clock is at the end of its tolerance band then the frequency would be 48.00048 MHz. This results in 6000.06 ticks in the 125 ⁇ s interval. The local oscillator would be in error by one cycle of the 48 MHz clock (approximately 20 ns) every 17 microframe periods (roughly every 2 ms).
- control loop only needs to operate at about once every 2 ms or 500 Hz.
- a high specification local clock source such as an Oven Controlled Crystal Oscillator (OCXO) the stability of the clock allows a very infrequent control loop.
- OXO Oven Controlled Crystal Oscillator
- FIG. 5 is a schematic diagram of a USB 100 synchronised to a GPS clock according to a third embodiment of the present invention.
- synchronised USB 100 comprises a USB host controller 102 and a plurality of USB devices 104 and 106 in data communication therewith.
- USB device 106 is additionally connected to a GPS time server 108.
- GPS time server 108 receives time codes from the GPS (or equivalent) satellite system via aerial 110 and maintains a local clock 112 accurate to universal time with high precision.
- GPS time server 108 transmits one pulse per second on the Universal Time second boundary (1 PPS signal) via data connection 114 to USB device 106.
- Other time or clock signals may be used, such as the 10 MHz clock signal.
- These 1 PPS signals can be considered a periodic clock carrier signal transmitted across data connection 114.
- USB device 106 is functionally equivalent to USB device 10 of figure 1 and is therefore adapted to implement the methods of the third aspect of the present invention to measure and map the relative times of local clock 112 of GPS time server 108 and clock 116 of USB device 106.
- USB device 106 is adapted such that these 1 PPS signals generate interrupt rather than receptions of SOF packets as in the embodiments described above.
- USB host controller 102 is transmitting periodic SOF packets to USB device 106, so USB device 106 can use the methods of the third aspect of the present invention to measure and map the time of its local clock 116 relative to the time of the local clock 118 of USB host controller 102.
- USB device 106 can use the methods of the third aspect of the present invention to measure and map the time of its local clock 116 relative to the time of the local clock 118 of USB host controller 102.
- USB device 104 is able to characterise its local clock 122 by direct measurement against the timebase provided by local clock 118 of USB host controller 102, as described above for USB device 10 of figure 1.
- USB 100 After measurement of the relative times of each clock in the system (i.e. local clock 112 of GPS time server 108, local clock 116 of USB device 106, local clock 118 of USB host controller 102 and local clock 112 of USB device 104), USB 100 generates a predicted map of the relative time of these four clocks, a procedure equivalent to the prediction method of the third aspect of the invention described above.
- the control method of the third aspect of the invention is then applied to generate a synchronised clock for each of USB devices 104,.106.
- the synchronised docks are synchronous with local clock 112 of GPS time server 108, but need not be.
- the absolute accuracy of clocks 116 and 1.18 do not affect the ability to synchronise clock 122 of USB device 104 with clock 112 of GPS time server 108 to a high degree of accuracy.
- the relative mapping between all time domains is such that, provided drift in each clock is not significant, clocks can be widely separated and connected through inaccurate clocks but still be synchronised to a high degree of accuracy.
- the methodology is also thus relatively insensitive to stochastic jitter owing to the statistical processing of measurements.
- Controller 134 hosts a plurality of USB host controllers 136, 138.
- Each of USB host controllers 136, 138 hosts a plurality of USB devices 140, 142 and 144, 146 respectively.
- USB Host Controller 136 compares its local oscillator with a clock signal present on PCI bus 132 (generated by PCI Controller 134). Using techniques in line with those taught above, the dock signal from PCI bus 132 is compared to a local clock signal present inside the plurality of USB host controllers 136, 138. Similarly USB host controller 138 compares its local oscillator to a clock signal present on PCI bus 132. The measurement, prediction and control of these three clocks allows the plurality of USB host controllers 136, 138 to be ⁇ synchronised according to the method of the third aspect of the present invention described above.
- USB devices 140, 142 hosted by USB host controller 136 are synchronised to USB host controller 136, and USB devices 144, 146 hosted by USB host controller 138 are synchronised to USB host controller 138.
- USB devices 140, 142, 144 and 146 are synchronised across PCI bus 132.
- a hybrid network of interconnected busses according to a fifth embodiment of the present invention is shown schematically at 150 in figure 7, connected to a GPS time server.
- network 150 comprises a PCI bus 152 controlled by a PCI Controller 154 and, connected thereto by an Ethernet bus 156, a PCI bus 158 controlled by a PCI Controller 160.
- Network 150 also includes a PGI-Ethemet controller 162 connected to PCI bus 152 and a PCI-Ethemet controller 164 connected to PCI bus 158 to host Ethernet link 156.
- PCI bus 152 contains a USB host controller 166 supporting a USB device 168 which is in turn connected to the GPS time server 170.
- PCI bus 158 contains a USB host controller 172 supporting USB device 174.
- each interconnected node PCI controllers 154, 160, USB host controllers 166, 172, Ethernet controllersi 62, 164, USB device 16 and GPS time server 170
- each interconnected node is able to compare its local clock signal (time) to that of its neighbouring node. In this way a map of the relative timebases of the interconnections is developed thereby allowing each node to be synchronised.
- the local clock 176 of USB device 174 can be synchronised to GPS time 178 through the chain of interconnected hybrid communication busses.
- the absolute accuracy of the intermediate clocks does not affect the ability to synchronise clock 176 of USB device 174 with GPS time 178 to a high degree of accuracy.
- the relative mapping between all time domains is such that, provided drift in each clock is not significant, clocks can be widely separated across multiple hybrid bus connections with inaccurate clocks but still be synchronised to a high degree of accuracy.
- the methodology is also quite insensitive to stochastic jitter due to the statistical processing of measurements.
- a plurality of PCI busses are synchronised with various other busses. It will be evident to those skilled in the art that a PXI bus may also be synchronised.
- PXI is an industrial instrumentation standard that combines a standard PCI bus with a dedicated timing and triggering bus. The previous embodiments can therefore equally employ PXI busses, wherein the inaccurate PCI clock source is replaced with a precision and phase aligned clock source on the PXI timing bus.
- synchronisation predominantly refers to synchronisation of clocks in frequency and phase to the reception of a carrier signal, without reference to compensation for propagation delays of the carrier signals across the busses.
- differences in propagation time of the bus clock carrier signal from device to device are very small owing to the physically limited nature of the bus.
- the physical extent of the bus results in significant propagation delays from point to point USB is between these extremes, with device to device propagation discrepancies limited to only a few hundred nanoseconds.
- PCI busses requires special termination conditions. As such it is possible to locate a given device's signal propagation time from a PCI bus controller by means of multi-level signalling. Similarly techniques exist with Ethernet to measure and compensate for signal propagation delays from simple techniques to methods taught by the IEEE-1588 standard.
- FIG. 8 is a schematic representation 180 of the time sequence of signals in two cases to illustrate this method for the case of a USB.
- Case A 182 represents a carrier signal (SOF) in time.
- SOF carrier signal
- a singular SOF synchronisation event is detected and output by software Interrupt service routine at 184. This represents the ideal case where the singular event is at the average of the delay between detection of any singular SOF packet and generating a resulting control signal.
- One carrier period later (at 186) the next SOF signal is detected, but the uncertainty in generating a local control signal 188 results in the control signal being either "early" at 190 or "late” at 192 with respect to the carrier period 186.
- the distribution of carrier signal reception within uncertainty window 188 will be centred on the expected carrier signal location 194 because the singular event was synchronised with the carrier signal.
- Case B 196 also represents a carrier signal (SOF) in time.
- SOF carrier signal
- a singular synchronisation event can be statistically compared to the average carrier signal time.
- the device's local notion of time can therefore be adjusted to compensate for the error in singular event and increasing the synchronisation accuracy.
- USB Host Controller refers to a standard USB Host controller, a USB-on-the-go Host Controller, a wireless USB Host Controller or any other form of USB Host
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Information Transfer Systems (AREA)
Abstract
Description
Claims
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CA2755750A CA2755750A1 (en) | 2008-08-21 | 2009-08-21 | Synchronisation and timing method and apparatus |
CN2009801413704A CN102265237A (en) | 2008-08-21 | 2009-08-21 | Synchronisation and timing method and apparatus |
JP2011523269A JP2012500430A (en) | 2008-08-21 | 2009-08-21 | Synchronization and timing method and apparatus |
AU2009284710A AU2009284710A1 (en) | 2008-08-21 | 2009-08-21 | Synchronisation and timing method and apparatus |
US13/060,181 US20120005517A1 (en) | 2008-08-21 | 2009-08-21 | Synchronisation and timing method and apparatus |
EP09807766.2A EP2329333A4 (en) | 2008-08-21 | 2009-08-21 | Synchronisation and timing method and apparatus |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US9063808P | 2008-08-21 | 2008-08-21 | |
US61/090,638 | 2008-08-21 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2010020015A1 true WO2010020015A1 (en) | 2010-02-25 |
Family
ID=41706776
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/AU2009/001081 WO2010020015A1 (en) | 2008-08-21 | 2009-08-21 | Synchronisation and timing method and apparatus |
Country Status (7)
Country | Link |
---|---|
US (1) | US20120005517A1 (en) |
EP (1) | EP2329333A4 (en) |
JP (1) | JP2012500430A (en) |
CN (1) | CN102265237A (en) |
AU (1) | AU2009284710A1 (en) |
CA (1) | CA2755750A1 (en) |
WO (1) | WO2010020015A1 (en) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2015048986A1 (en) * | 2013-10-01 | 2015-04-09 | Telefonaktiebolaget L M Ericsson (Publ) | Synchronization module and method |
CN105342640A (en) * | 2015-11-26 | 2016-02-24 | 深圳市理邦精密仪器股份有限公司 | Synchronous calibration method and device of wireless probe ultrasonic signal transmission and monitoring apparatus |
CN103684728B (en) * | 2012-09-04 | 2016-11-02 | 中国航空工业集团公司第六三一研究所 | FC network clocking synchronous error compensation method |
CN112565554A (en) * | 2020-12-09 | 2021-03-26 | 威创集团股份有限公司 | Clock synchronization system based on FPGA |
Families Citing this family (39)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101281512A (en) * | 2002-07-17 | 2008-10-08 | 菲博比特有限公司 | Synchronized multichannel universal serial bus |
US8842790B2 (en) * | 2009-12-22 | 2014-09-23 | Intel Corporation | Methods and systems to synchronize network nodes |
GB201116521D0 (en) * | 2011-09-23 | 2011-11-09 | Imagination Tech Ltd | Method and apparatus for time synchronisation in wireless networks |
ES2485377T3 (en) * | 2012-05-15 | 2014-08-13 | Omicron Electronics Gmbh | Test device, test system and test procedure of an electrical engineering test object |
TWI522772B (en) * | 2012-10-17 | 2016-02-21 | Automatic transmission interface device and method for correcting transmission frequency | |
KR101571338B1 (en) * | 2013-03-13 | 2015-11-24 | 삼성전자주식회사 | Method and apparatus for allowing plural media players to perform synchronized play of streaming content |
US10142044B2 (en) * | 2013-03-20 | 2018-11-27 | Qulsar, Inc. | Managed timing engine |
CN103309397B (en) * | 2013-06-17 | 2015-11-18 | 杭州锐达数字技术有限公司 | Based on the synchronous sampling method of the data acquisition equipment of USB |
US20150033294A1 (en) * | 2013-07-26 | 2015-01-29 | Xtera Communications, Inc. | Network management system architecture of a telecommunications network |
US9395795B2 (en) * | 2013-09-20 | 2016-07-19 | Apple Inc. | System power management using communication bus protocols |
CN104597964A (en) * | 2013-10-30 | 2015-05-06 | 中国航空工业集团公司第六三一研究所 | Time server |
US9784601B2 (en) * | 2014-11-20 | 2017-10-10 | Computational Systems, Inc. | Apparatus and method for signal synchronization |
US10129839B2 (en) * | 2014-12-05 | 2018-11-13 | Qualcomm Incorporated | Techniques for synchronizing timing of wireless streaming transmissions to multiple sink devices |
CN106301644B (en) * | 2015-05-18 | 2018-03-30 | 深圳市中兴微电子技术有限公司 | A kind of synchronous method and apparatus of voice |
US10338201B2 (en) | 2015-09-17 | 2019-07-02 | Qualcomm Incorporated | Timing synchronization of LIDAR system to reduce interference |
EP3156904A1 (en) * | 2015-10-13 | 2017-04-19 | Autoliv Development AB | A vehicle safety electronic control system |
US9864399B2 (en) * | 2015-12-10 | 2018-01-09 | Apple Inc. | Timebase synchronization |
US10096450B2 (en) | 2015-12-28 | 2018-10-09 | Mapper Lithography Ip B.V. | Control system and method for lithography apparatus |
NL2018196B1 (en) * | 2017-01-19 | 2018-08-01 | Mapper Lithography Ip Bv | Control system and method for lithography apparatus |
CN106814789B (en) * | 2017-01-25 | 2020-07-03 | 腾讯科技(深圳)有限公司 | Timing method and device |
CN106656397B (en) * | 2017-03-01 | 2019-04-05 | 广州广哈通信股份有限公司 | Clock synchronizing method and device |
CN108319762B (en) * | 2018-01-08 | 2021-07-06 | 无锡中微亿芯有限公司 | Clock area support-based sectional programmable clock network structure |
CN108573544B (en) * | 2018-05-31 | 2024-06-28 | 山东中泳电子股份有限公司 | Multi-clock dual-core synchronous timer |
EP3591435B1 (en) * | 2018-07-02 | 2022-08-10 | NXP USA, Inc. | Communication unit, integrated circuit and method for clock distribution and synchronization |
EP3591431B1 (en) * | 2018-07-02 | 2021-05-05 | NXP USA, Inc. | Communication unit and method for clock distribution and synchronization |
JP2020013087A (en) * | 2018-07-20 | 2020-01-23 | 株式会社ニコン | adapter |
JP7218512B2 (en) * | 2018-07-30 | 2023-02-07 | セイコーエプソン株式会社 | Sensor modules, electronic devices and mobile objects |
CN109819108B (en) * | 2019-01-04 | 2021-03-02 | Oppo广东移动通信有限公司 | Method and device for adjusting driving parameters, electronic equipment and storage medium |
DE102019200437A1 (en) * | 2019-01-16 | 2020-07-16 | Robert Bosch Gmbh | Synchronization of components by a control unit |
US11002764B2 (en) * | 2019-02-12 | 2021-05-11 | Tektronix, Inc. | Systems and methods for synchronizing multiple test and measurement instruments |
CN110174120B (en) * | 2019-04-16 | 2021-10-08 | 百度在线网络技术(北京)有限公司 | Time synchronization method and device for AR navigation simulation |
GB201912169D0 (en) * | 2019-08-23 | 2019-10-09 | Nordic Semiconductor Asa | Radio apparatus for communicating digital audio streams |
AU2021325826B2 (en) * | 2020-08-13 | 2023-11-23 | Fermat International, Inc. | System and method for global synchronization of time in a distributed processing environment |
CN112578413A (en) * | 2020-11-13 | 2021-03-30 | 中国电子技术标准化研究院 | Timing synchronous timing method, device and remote synchronous timing system |
CN112578847A (en) * | 2020-12-21 | 2021-03-30 | 青岛鼎信通讯股份有限公司 | Linux system-based multi-MCU clock synchronization scheme |
CN112947034B (en) * | 2021-05-13 | 2021-08-03 | 北京炬玄智能科技有限公司 | High-precision clock chip compensation production system and method |
CN113608574B (en) * | 2021-08-09 | 2024-06-11 | 贵州省计量测试院 | Microsecond time output method, microsecond time output system and microsecond time output calibration system for computer |
TWI779921B (en) * | 2021-11-08 | 2022-10-01 | 優達科技股份有限公司 | Method for correcting 1 pulse per second signal and timing receiver |
WO2023215940A1 (en) * | 2022-05-09 | 2023-11-16 | Freqport Pty Ltd | Method and apparatus for control and transfer of audio between analog and computer in digital audio processing |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2004008330A1 (en) * | 2002-07-17 | 2004-01-22 | Fiberbyte Pty Ltd | Synchronized multichannel universal serial bus |
US20060146968A1 (en) * | 2005-01-05 | 2006-07-06 | Axalto Sa | Data communication device |
WO2007092997A1 (en) * | 2006-02-15 | 2007-08-23 | Fiberbyte Pty Ltd | Distributed synchronization and timing system |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE10041772C2 (en) * | 2000-08-25 | 2002-07-11 | Infineon Technologies Ag | Clock generator, especially for USB devices |
JP2002232408A (en) * | 2001-01-30 | 2002-08-16 | Matsushita Electric Ind Co Ltd | Clock synchronizing circuit |
US7120813B2 (en) * | 2003-01-28 | 2006-10-10 | Robert Antoine Leydier | Method and apparatus for clock synthesis using universal serial bus downstream received signals |
JP4266358B2 (en) * | 2004-04-12 | 2009-05-20 | 三菱電機株式会社 | In-vehicle electronic control unit |
-
2009
- 2009-08-21 JP JP2011523269A patent/JP2012500430A/en active Pending
- 2009-08-21 CN CN2009801413704A patent/CN102265237A/en active Pending
- 2009-08-21 WO PCT/AU2009/001081 patent/WO2010020015A1/en active Application Filing
- 2009-08-21 AU AU2009284710A patent/AU2009284710A1/en not_active Abandoned
- 2009-08-21 CA CA2755750A patent/CA2755750A1/en not_active Abandoned
- 2009-08-21 EP EP09807766.2A patent/EP2329333A4/en not_active Withdrawn
- 2009-08-21 US US13/060,181 patent/US20120005517A1/en not_active Abandoned
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2004008330A1 (en) * | 2002-07-17 | 2004-01-22 | Fiberbyte Pty Ltd | Synchronized multichannel universal serial bus |
US20060146968A1 (en) * | 2005-01-05 | 2006-07-06 | Axalto Sa | Data communication device |
WO2007092997A1 (en) * | 2006-02-15 | 2007-08-23 | Fiberbyte Pty Ltd | Distributed synchronization and timing system |
Non-Patent Citations (3)
Title |
---|
"Schedule Timeout - Schedule timeout event for each entity", 18 January 2008 (2008-01-18), XP008155049, Retrieved from the Internet <URL:http:/lweb.archive.org/web/20080118075455/http://www.mathworks.comlaccess/helpdesk/help/toolbox/simevents/ref/scheduletimeout.html> [retrieved on 20091126] * |
DAX-2500X USER'S MANUAL, 22 August 2006 (2006-08-22), XP008144225, Retrieved from the Internet <URL:http:/lweb.archive.org/web/*/www.fiberbyte.com/PDF/DAQ2500XManual.pdf> [retrieved on 20091126] * |
See also references of EP2329333A4 * |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103684728B (en) * | 2012-09-04 | 2016-11-02 | 中国航空工业集团公司第六三一研究所 | FC network clocking synchronous error compensation method |
WO2015048986A1 (en) * | 2013-10-01 | 2015-04-09 | Telefonaktiebolaget L M Ericsson (Publ) | Synchronization module and method |
US10244491B2 (en) | 2013-10-01 | 2019-03-26 | Telefonaktiebolaget Lm Ericsson (Publ) | Synchronization module and method |
CN105342640A (en) * | 2015-11-26 | 2016-02-24 | 深圳市理邦精密仪器股份有限公司 | Synchronous calibration method and device of wireless probe ultrasonic signal transmission and monitoring apparatus |
CN112565554A (en) * | 2020-12-09 | 2021-03-26 | 威创集团股份有限公司 | Clock synchronization system based on FPGA |
CN112565554B (en) * | 2020-12-09 | 2022-03-18 | 威创集团股份有限公司 | Clock synchronization system based on FPGA |
Also Published As
Publication number | Publication date |
---|---|
EP2329333A1 (en) | 2011-06-08 |
CA2755750A1 (en) | 2010-02-25 |
CN102265237A (en) | 2011-11-30 |
AU2009284710A1 (en) | 2010-02-25 |
JP2012500430A (en) | 2012-01-05 |
US20120005517A1 (en) | 2012-01-05 |
EP2329333A4 (en) | 2014-12-03 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20120005517A1 (en) | Synchronisation and timing method and apparatus | |
AU2007215381B2 (en) | Distributed synchronization and timing system | |
US8943351B2 (en) | USB based synchronization and timing system | |
EP1901178B1 (en) | Synchronized multichannel universal serial bus | |
AU2013204446A1 (en) | Synchronisation and Timing Method and Apparatus | |
AU2013200979B2 (en) | Usb based synchronization and timing system | |
Foster et al. | Sub-nanosecond distributed synchronisation via the universal serial bus | |
AU2012216514A1 (en) | Distributed synchronization and timing system |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 200980141370.4 Country of ref document: CN |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 09807766 Country of ref document: EP Kind code of ref document: A1 |
|
ENP | Entry into the national phase |
Ref document number: 2011523269 Country of ref document: JP Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2755750 Country of ref document: CA |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2009284710 Country of ref document: AU |
|
WWE | Wipo information: entry into national phase |
Ref document number: 2009807766 Country of ref document: EP |
|
ENP | Entry into the national phase |
Ref document number: 2009284710 Country of ref document: AU Date of ref document: 20090821 Kind code of ref document: A |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1202/KOLNP/2011 Country of ref document: IN |
|
WWE | Wipo information: entry into national phase |
Ref document number: 13060181 Country of ref document: US |