WO2009081518A1 - 半導体装置および多層配線基板 - Google Patents
半導体装置および多層配線基板 Download PDFInfo
- Publication number
- WO2009081518A1 WO2009081518A1 PCT/JP2008/003248 JP2008003248W WO2009081518A1 WO 2009081518 A1 WO2009081518 A1 WO 2009081518A1 JP 2008003248 W JP2008003248 W JP 2008003248W WO 2009081518 A1 WO2009081518 A1 WO 2009081518A1
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- WO
- WIPO (PCT)
- Prior art keywords
- insulating layer
- heat insulating
- wiring board
- multilayer wiring
- semiconductor device
- Prior art date
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Classifications
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Definitions
- the heat insulating member is provided in the first insulating layer, and the heat insulating member is provided in the second opening formed at a position facing the semiconductor element of the first insulating layer. It may be configured to be filled with a low material.
- the heat insulating layer is formed on the outermost layer of the multilayer wiring board.
- a wiring pattern is formed on the outermost layer, and an electronic component such as a semiconductor element is connected to the wiring pattern.
- an electronic component is mounted by soldering or the like, a thermal and mechanical load is applied to the outermost layer. Therefore, it is not preferable to arrange a heat insulating layer having a low mechanical strength at this position.
- the 1st heat insulation layer 10a and the 2nd heat insulation layer 10b are comprised similarly to the above-mentioned heat insulation layer 10.
- FIG. also, vias 6 and interlayer electrodes 9 are formed in each of the first heat insulating layer 10a and the second heat insulating layer 10b. These vias 6 and interlayer electrodes 9 are formed of the insulating layer 3, the core substrate 1, and the insulating layer 4 respectively. Are electrically connected to the via 6 and the interlayer electrode 9.
- a via hole is formed by irradiating the via connection portion of the insulating layer 14 with laser light from above the separator. Thereafter, a conductor layer is formed on the wall surface of the via hole by copper plating, and a copper plating layer is formed on the surface of the insulating layer 14. Furthermore, the via hole is filled with an insulating resin by screen printing or the like. Then, after applying a photoresist on the copper plating layer by the same method as that for the core substrate 1, exposure and etching are performed to form a desired wiring pattern (interlayer electrode 9).
- the width of the heat insulating member 16 provided on the core substrate 1 is the same as the width L of the heat insulating member 15 provided on the insulating layer 14.
- the heat insulating material constituting the heat insulating member 16 is substantially the same as the heat insulating material constituting the heat insulating member 15. Since the process of forming the heat insulating member 16 on the core substrate 1 is basically the same as the process of forming the heat insulating member 15 on the insulating layer 14, the description thereof is omitted here.
- Embodiment 6 A semiconductor device according to Embodiment 6 of the present invention will be described with reference to FIG. As shown in FIG. 12, the semiconductor device SA6 according to the present embodiment is obtained by replacing the multilayer wiring board MB5 with the multilayer wiring board MB6 in the semiconductor device SA5 according to the fifth embodiment described above.
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Abstract
Description
相互に積層された、概ね平板状の少なくとも3つの絶縁層を含む多層配線基板と、前記多層配線基板の一方の主面に取り付けられた半導体素子を具備する半導体装置であって、
前記多層配線基板は、前記絶縁層よりも熱伝導性の低い材料で構成された断熱部材をさらに備え、前記断熱部材は、前記絶縁層の層間の少なくとも1箇所、もしくは前記絶縁層のうち少なくとも1つの絶縁層の一部に設けられているものである。
このビアは、隣接する前記絶縁層のそれぞれに設けられたビアと、層間電極を介して電気的に接続されていることが好ましい。
前記断熱部材は、前記第3の絶縁層のうち前記半導体素子に対向する箇所に形成された第1の開口部に、前記熱伝導性の低い材料が充填されて構成されることが好ましい。
前記断熱部材は、前記第1の絶縁層の前記半導体素子に対向する箇所に形成された第2の開口部に、前記熱伝導性の低い材料が充填されて構成されていてもよい。
前記断熱部材は、前記第3の絶縁層のうち前記半導体素子の取り付け位置に近接する箇所に形成された第1の複数のビア孔に前記熱伝導性の低い材料が充填されて構成されていてもよい。
前記断熱部材は、前記第1の絶縁層の前記半導体素子の取り付け位置に対向する箇所に形成された第2の複数のビア孔に前記熱伝導性の低い材料が充填されて構成されていてもよい。
図1および図2を参照して、本発明の実施の形態1にかかる半導体装置について説明する。図1に、本発明の実施の形態1にかかる半導体装置SA1の断面を示す。また図2に、図1の半導体装置SA1を構成する多層配線基板MB1の断面を示す。半導体装置SA1は、多層配線基板MB1の実装面に半導体素子SDがフリップチップ接続されて構成される。図中、従来の半導体装置SAPと同一の機能を有する部材には同一の符号を付し、また重複する説明は避ける。
図8を参照して、本発明の実施の形態2にかかる半導体装置について説明する。本実施の形態にかかる半導体装置SA2は、上述の実施の形態1の半導体装置SA1において、多層配線基板MB1が多層配線基板MB2に置き換えられたものである。
図9を参照して、本発明の実施の形態3にかかる半導体装置について説明する。図9に示すように、本実施の形態にかかる半導体装置SA3は前述の第1の実施の形態にかかる半導体装置SA1において、多層配線基板MB1が多層配線基板MB3に置き換えられたものである。
図10を参照して、本発明の実施の形態4にかかる半導体装置について説明する。図10に示すように、本実施の形態にかかる半導体装置SA4は上述の第3の実施の形態にかかる半導体装置SA3において、多層配線基板MB3が多層配線基板MB4に置き換えられたものである。
図11を参照して、本発明の実施の形態5にかかる半導体装置について説明する。図11に示すように、本実施の形態にかかる半導体装置SA4は前述の第3の実施の形態にかかる半導体装置SA3において、多層配線基板MB3が多層配線基板MB5に置き換えられたものである。
図12を参照して、本発明の実施の形態6にかかる半導体装置について説明する。図12に示すように、本実施の形態にかかる半導体装置SA6は上述の第5の実施の形態にかかる半導体装置SA5において、多層配線基板MB5が多層配線基板MB6に置き換えられたものである。
Claims (17)
- 相互に積層された、概ね平板状の少なくとも3つの絶縁層を含む多層配線基板と、前記多層配線基板の一方の主面に取り付けられた半導体素子を具備する半導体装置であって、
前記多層配線基板は、前記絶縁層よりも熱伝導性の低い材料で構成された断熱部材をさらに備え、前記断熱部材は、前記絶縁層の層間の少なくとも1箇所、もしくは前記絶縁層のうち少なくとも1つの絶縁層の一部に設けられている半導体装置。 - 前記多層配線基板は、前記絶縁層の1つからなるコア基板と、前記コア基板の一方の主面に積層された少なくとも1つの絶縁層と、前記コア基板の他方の主面に積層された少なくとも1つの絶縁層とを含む、請求項1記載の半導体装置。
- 前記断熱部材は、前記絶縁層の層間の少なくとも1箇所に配された、概ね平板上の断熱層である、請求項2記載の半導体装置。
- 前記断熱層は1つであり、かつ前記コア基板である第1の絶縁層と前記半導体素子実装側の最外の第2の絶縁層との間に配されている、請求項3記載の半導体装置。
- 前記断熱層には、その2つの主面をつなぐビアが設けられ、かつ
このビアは、隣接する前記絶縁層のそれぞれに設けられたビアと、層間電極を介して電気的に接続されている、請求項3記載の半導体装置。 - 前記断熱部材は、最外の2層を除いた前記絶縁層のうち少なくとも1層の、前記半導体素子の取り付け位置に近接する箇所に設けられている、請求項2記載の半導体装置。
- 前記断熱部材は、前記コア基板である第1の絶縁層と前記半導体素子実装側の最外の第2の絶縁層との間に配された第3の絶縁層に設けられ、かつ
前記断熱部材は、前記第3の絶縁層のうち前記半導体素子に対向する箇所に形成された第1の開口部に、前記熱伝導性の低い材料が充填されて構成される、請求項6記載の半導体装置。 - 前記断熱部材は前記第1の絶縁層に設けられ、かつ
前記断熱部材は、前記第1の絶縁層の前記半導体素子に対向する箇所に形成された第2の開口部に、前記熱伝導性の低い材料が充填されて構成される、請求項7記載の半導体装置。 - 前記断熱部材は、前記コア基板である第1の絶縁層と前記半導体素子実装側の最外の第2の絶縁層との間に配された第3の絶縁層に設けられ、かつ
前記断熱部材は、前記第3の絶縁層のうち前記半導体素子の取り付け位置に近接する箇所に形成された第1の複数のビア孔に前記熱伝導性の低い材料が充填されて構成される、請求項6記載の半導体装置。 - 前記断熱部材は前記第1の絶縁層に設けられ、かつ
前記断熱部材は、前記第1の絶縁層の前記半導体素子の取り付け位置に対向する箇所に形成された第2の複数のビア孔に前記熱伝導性の低い材料が充填されて構成される、請求項9記載の半導体装置。 - 前記絶縁層よりも熱伝導性の低い材料は、絶縁性の樹脂に無機の発泡体が混入されたものである、請求項1記載の半導体装置。
- 前記無機の発泡体は、多孔質シリカ、発泡ガラス、シリカバルーン、ガラスマイクロバルーン、シラスバルーン、およびクォーツマイクロスフィアーから選ばれた少なくとも1つからなる、請求項11記載の半導体装置。
- 前記無機の発泡体はセラミック中空粒子である、請求項11記載の半導体装置。
- 相互に接続された、概ね平板状の少なくとも3つの絶縁層を含み、かつ一方の主面に半導体素子に接続される配線が形成された多層配線基板であって、
前記絶縁層よりも熱伝導性の低い材料で構成された断熱部材をさらに備え、前記断熱部材は、前記絶縁層の層間の少なくとも1箇所、もしくは前記絶縁層のうち少なくとも1つの絶縁層の一部に設けられている多層配線基板。 - 前記多層配線基板は、前記絶縁層の1つからなるコア基板と、前記コア基板の一方の主面に積層された少なくとも1つの絶縁層と、前記コア基板の他方の主面に積層された少なくとも1つの絶縁層とを含む、請求項14記載の多層配線基板。
- 前記断熱部材は、前記絶縁層の層間の少なくとも一箇所に配された、概ね平板状の断熱層である、請求項15記載の多層配線基板。
- 前記断熱部材は、最外の2層を除いた前記絶縁層のうち少なくとも1層の、前記半導体素子の取り付け位置に近接する箇所に設けられている、請求項15記載の多層配線基板。
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CN2008801176507A CN101869008B (zh) | 2007-12-26 | 2008-11-11 | 半导体装置和多层配线基板 |
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